1 /*- 2 * Support the ENSONIQ AudioPCI board and Creative Labs SoundBlaster PCI 3 * boards based on the ES1370, ES1371 and ES1373 chips. 4 * 5 * Copyright (c) 1999 Russell Cattelan <cattelan@thebarn.com> 6 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 7 * Copyright (c) 1998 by Joachim Kuebart. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 21 * 3. All advertising materials mentioning features or use of this 22 * software must display the following acknowledgement: 23 * This product includes software developed by Joachim Kuebart. 24 * 25 * 4. The name of the author may not be used to endorse or promote 26 * products derived from this software without specific prior 27 * written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 31 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 32 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 39 * OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * Part of this code was heavily inspired by the linux driver from 44 * Thomas Sailer (sailer@ife.ee.ethz.ch) 45 * Just about everything has been touched and reworked in some way but 46 * the all the underlying sequences/timing/register values are from 47 * Thomas' code. 48 * 49 */ 50 51 #include <dev/sound/pcm/sound.h> 52 #include <dev/sound/pcm/ac97.h> 53 #include <dev/sound/pci/es137x.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 58 #include <sys/sysctl.h> 59 60 #include "mixer_if.h" 61 62 SND_DECLARE_FILE("$FreeBSD$"); 63 64 #define MEM_MAP_REG 0x14 65 66 /* PCI IDs of supported chips */ 67 #define ES1370_PCI_ID 0x50001274 68 #define ES1371_PCI_ID 0x13711274 69 #define ES1371_PCI_ID2 0x13713274 70 #define CT5880_PCI_ID 0x58801274 71 #define CT4730_PCI_ID 0x89381102 72 73 #define ES1371REV_ES1371_A 0x02 74 #define ES1371REV_ES1371_B 0x09 75 76 #define ES1371REV_ES1373_8 0x08 77 #define ES1371REV_ES1373_A 0x04 78 #define ES1371REV_ES1373_B 0x06 79 80 #define ES1371REV_CT5880_A 0x07 81 82 #define CT5880REV_CT5880_C 0x02 83 #define CT5880REV_CT5880_D 0x03 84 #define CT5880REV_CT5880_E 0x04 85 86 #define CT4730REV_CT4730_A 0x00 87 88 #define ES_DEFAULT_BUFSZ 4096 89 90 /* 2 DAC for playback, 1 ADC for record */ 91 #define ES_DAC1 0 92 #define ES_DAC2 1 93 #define ES_ADC 2 94 #define ES_NCHANS 3 95 96 #define ES1370_DAC1_MINSPEED 5512 97 #define ES1370_DAC1_MAXSPEED 44100 98 99 /* device private data */ 100 struct es_info; 101 102 struct es_chinfo { 103 struct es_info *parent; 104 struct pcm_channel *channel; 105 struct snd_dbuf *buffer; 106 struct pcmchan_caps caps; 107 int dir, num, index; 108 u_int32_t fmt, blksz, bufsz; 109 }; 110 111 /* 112 * 32bit Ensoniq Configuration (es->escfg). 113 * ---------------------------------------- 114 * 115 * +-------+--------+------+------+---------+--------+---------+---------+ 116 * len | 16 | 1 | 1 | 1 | 2 | 2 | 1 | 8 | 117 * +-------+--------+------+------+---------+--------+---------+---------+ 118 * | fixed | single | | | | | is | general | 119 * | rate | pcm | DACx | DACy | numplay | numrec | es1370? | purpose | 120 * | | mixer | | | | | | | 121 * +-------+--------+------+------+---------+--------+---------+---------+ 122 */ 123 #define ES_FIXED_RATE(cfgv) \ 124 (((cfgv) & 0xffff0000) >> 16) 125 #define ES_SET_FIXED_RATE(cfgv, nv) \ 126 (((cfgv) & ~0xffff0000) | (((nv) & 0xffff) << 16)) 127 #define ES_SINGLE_PCM_MIX(cfgv) \ 128 (((cfgv) & 0x8000) >> 15) 129 #define ES_SET_SINGLE_PCM_MIX(cfgv, nv) \ 130 (((cfgv) & ~0x8000) | (((nv) ? 1 : 0) << 15)) 131 #define ES_DAC_FIRST(cfgv) \ 132 (((cfgv) & 0x4000) >> 14) 133 #define ES_SET_DAC_FIRST(cfgv, nv) \ 134 (((cfgv) & ~0x4000) | (((nv) & 0x1) << 14)) 135 #define ES_DAC_SECOND(cfgv) \ 136 (((cfgv) & 0x2000) >> 13) 137 #define ES_SET_DAC_SECOND(cfgv, nv) \ 138 (((cfgv) & ~0x2000) | (((nv) & 0x1) << 13)) 139 #define ES_NUMPLAY(cfgv) \ 140 (((cfgv) & 0x1800) >> 11) 141 #define ES_SET_NUMPLAY(cfgv, nv) \ 142 (((cfgv) & ~0x1800) | (((nv) & 0x3) << 11)) 143 #define ES_NUMREC(cfgv) \ 144 (((cfgv) & 0x600) >> 9) 145 #define ES_SET_NUMREC(cfgv, nv) \ 146 (((cfgv) & ~0x600) | (((nv) & 0x3) << 9)) 147 #define ES_IS_ES1370(cfgv) \ 148 (((cfgv) & 0x100) >> 8) 149 #define ES_SET_IS_ES1370(cfgv, nv) \ 150 (((cfgv) & ~0x100) | (((nv) ? 1 : 0) << 8)) 151 #define ES_GP(cfgv) \ 152 ((cfgv) & 0xff) 153 #define ES_SET_GP(cfgv, nv) \ 154 (((cfgv) & ~0xff) | ((nv) & 0xff)) 155 156 #define ES_DAC1_ENABLED(cfgv) \ 157 (ES_NUMPLAY(cfgv) > 1 || \ 158 (ES_NUMPLAY(cfgv) == 1 && ES_DAC_FIRST(cfgv) == ES_DAC1)) 159 #define ES_DAC2_ENABLED(cfgv) \ 160 (ES_NUMPLAY(cfgv) > 1 || \ 161 (ES_NUMPLAY(cfgv) == 1 && ES_DAC_FIRST(cfgv) == ES_DAC2)) 162 163 /* 164 * DAC 1/2 configuration through kernel hint - hint.pcm.<unit>.dac="val" 165 * 166 * 0 = Enable both DACs - Default 167 * 1 = Enable single DAC (DAC1) 168 * 2 = Enable single DAC (DAC2) 169 * 3 = Enable both DACs, swap position (DAC2 comes first instead of DAC1) 170 */ 171 #define ES_DEFAULT_DAC_CFG 0 172 173 struct es_info { 174 bus_space_tag_t st; 175 bus_space_handle_t sh; 176 bus_dma_tag_t parent_dmat; 177 178 struct resource *reg, *irq; 179 int regtype, regid, irqid; 180 void *ih; 181 182 device_t dev; 183 int num; 184 unsigned int bufsz; 185 186 /* Contents of board's registers */ 187 uint32_t ctrl; 188 uint32_t sctrl; 189 uint32_t escfg; 190 struct es_chinfo ch[ES_NCHANS]; 191 struct mtx *lock; 192 }; 193 194 #define ES_LOCK(sc) snd_mtxlock((sc)->lock) 195 #define ES_UNLOCK(sc) snd_mtxunlock((sc)->lock) 196 #define ES_LOCK_ASSERT(sc) snd_mtxassert((sc)->lock) 197 198 /* prototypes */ 199 static void es_intr(void *); 200 static uint32_t es1371_wait_src_ready(struct es_info *); 201 static void es1371_src_write(struct es_info *, u_short, unsigned short); 202 static u_int es1371_adc_rate(struct es_info *, u_int, int); 203 static u_int es1371_dac_rate(struct es_info *, u_int, int); 204 static int es1371_init(struct es_info *); 205 static int es1370_init(struct es_info *); 206 static int es1370_wrcodec(struct es_info *, u_char, u_char); 207 208 static u_int32_t es_fmt[] = { 209 AFMT_U8, 210 AFMT_STEREO | AFMT_U8, 211 AFMT_S16_LE, 212 AFMT_STEREO | AFMT_S16_LE, 213 0 214 }; 215 static struct pcmchan_caps es_caps = {4000, 48000, es_fmt, 0}; 216 217 static const struct { 218 unsigned volidx:4; 219 unsigned left:4; 220 unsigned right:4; 221 unsigned stereo:1; 222 unsigned recmask:13; 223 unsigned avail:1; 224 } mixtable[SOUND_MIXER_NRDEVICES] = { 225 [SOUND_MIXER_VOLUME] = { 0, 0x0, 0x1, 1, 0x1f7f, 1 }, 226 [SOUND_MIXER_PCM] = { 1, 0x2, 0x3, 1, 0x0400, 1 }, 227 [SOUND_MIXER_SYNTH] = { 2, 0x4, 0x5, 1, 0x0060, 1 }, 228 [SOUND_MIXER_CD] = { 3, 0x6, 0x7, 1, 0x0006, 1 }, 229 [SOUND_MIXER_LINE] = { 4, 0x8, 0x9, 1, 0x0018, 1 }, 230 [SOUND_MIXER_LINE1] = { 5, 0xa, 0xb, 1, 0x1800, 1 }, 231 [SOUND_MIXER_LINE2] = { 6, 0xc, 0x0, 0, 0x0100, 1 }, 232 [SOUND_MIXER_LINE3] = { 7, 0xd, 0x0, 0, 0x0200, 1 }, 233 [SOUND_MIXER_MIC] = { 8, 0xe, 0x0, 0, 0x0001, 1 }, 234 [SOUND_MIXER_OGAIN] = { 9, 0xf, 0x0, 0, 0x0000, 1 } 235 }; 236 237 static __inline u_int32_t 238 es_rd(struct es_info *es, int regno, int size) 239 { 240 switch (size) { 241 case 1: 242 return bus_space_read_1(es->st, es->sh, regno); 243 case 2: 244 return bus_space_read_2(es->st, es->sh, regno); 245 case 4: 246 return bus_space_read_4(es->st, es->sh, regno); 247 default: 248 return 0xFFFFFFFF; 249 } 250 } 251 252 static __inline void 253 es_wr(struct es_info *es, int regno, u_int32_t data, int size) 254 { 255 256 switch (size) { 257 case 1: 258 bus_space_write_1(es->st, es->sh, regno, data); 259 break; 260 case 2: 261 bus_space_write_2(es->st, es->sh, regno, data); 262 break; 263 case 4: 264 bus_space_write_4(es->st, es->sh, regno, data); 265 break; 266 } 267 } 268 269 /* -------------------------------------------------------------------- */ 270 /* The es1370 mixer interface */ 271 272 static int 273 es1370_mixinit(struct snd_mixer *m) 274 { 275 struct es_info *es; 276 int i; 277 u_int32_t v; 278 279 es = mix_getdevinfo(m); 280 v = 0; 281 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 282 if (mixtable[i].avail) v |= (1 << i); 283 /* 284 * Each DAC1/2 for ES1370 can be controlled independently 285 * DAC1 = controlled by synth 286 * DAC2 = controlled by pcm 287 * This is indeed can confuse user if DAC1 become primary playback 288 * channel. Try to be smart and combine both if necessary. 289 */ 290 if (ES_SINGLE_PCM_MIX(es->escfg)) 291 v &= ~(1 << SOUND_MIXER_SYNTH); 292 mix_setdevs(m, v); 293 v = 0; 294 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 295 if (mixtable[i].recmask) v |= (1 << i); 296 if (ES_SINGLE_PCM_MIX(es->escfg)) /* ditto */ 297 v &= ~(1 << SOUND_MIXER_SYNTH); 298 mix_setrecdevs(m, v); 299 return 0; 300 } 301 302 static int 303 es1370_mixset(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 304 { 305 struct es_info *es; 306 int l, r, rl, rr, set_dac1; 307 308 if (!mixtable[dev].avail) return -1; 309 l = left; 310 r = mixtable[dev].stereo? right : l; 311 if (mixtable[dev].left == 0xf) { 312 rl = (l < 2)? 0x80 : 7 - (l - 2) / 14; 313 } else { 314 rl = (l < 10)? 0x80 : 15 - (l - 10) / 6; 315 } 316 es = mix_getdevinfo(m); 317 ES_LOCK(es); 318 if (dev == SOUND_MIXER_PCM && (ES_SINGLE_PCM_MIX(es->escfg)) && 319 ES_DAC1_ENABLED(es->escfg)) { 320 set_dac1 = 1; 321 } else { 322 set_dac1 = 0; 323 } 324 if (mixtable[dev].stereo) { 325 rr = (r < 10)? 0x80 : 15 - (r - 10) / 6; 326 es1370_wrcodec(es, mixtable[dev].right, rr); 327 if (set_dac1 && mixtable[SOUND_MIXER_SYNTH].stereo) 328 es1370_wrcodec(es, mixtable[SOUND_MIXER_SYNTH].right, rr); 329 } 330 es1370_wrcodec(es, mixtable[dev].left, rl); 331 if (set_dac1) 332 es1370_wrcodec(es, mixtable[SOUND_MIXER_SYNTH].left, rl); 333 ES_UNLOCK(es); 334 335 return l | (r << 8); 336 } 337 338 static int 339 es1370_mixsetrecsrc(struct snd_mixer *m, u_int32_t src) 340 { 341 struct es_info *es; 342 int i, j = 0; 343 344 es = mix_getdevinfo(m); 345 if (src == 0) src = 1 << SOUND_MIXER_MIC; 346 src &= mix_getrecdevs(m); 347 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) 348 if ((src & (1 << i)) != 0) j |= mixtable[i].recmask; 349 350 ES_LOCK(es); 351 if ((src & (1 << SOUND_MIXER_PCM)) && ES_SINGLE_PCM_MIX(es->escfg) && 352 ES_DAC1_ENABLED(es->escfg)) { 353 j |= mixtable[SOUND_MIXER_SYNTH].recmask; 354 } 355 es1370_wrcodec(es, CODEC_LIMIX1, j & 0x55); 356 es1370_wrcodec(es, CODEC_RIMIX1, j & 0xaa); 357 es1370_wrcodec(es, CODEC_LIMIX2, (j >> 8) & 0x17); 358 es1370_wrcodec(es, CODEC_RIMIX2, (j >> 8) & 0x0f); 359 es1370_wrcodec(es, CODEC_OMIX1, 0x7f); 360 es1370_wrcodec(es, CODEC_OMIX2, 0x3f); 361 ES_UNLOCK(es); 362 363 return src; 364 } 365 366 static kobj_method_t es1370_mixer_methods[] = { 367 KOBJMETHOD(mixer_init, es1370_mixinit), 368 KOBJMETHOD(mixer_set, es1370_mixset), 369 KOBJMETHOD(mixer_setrecsrc, es1370_mixsetrecsrc), 370 { 0, 0 } 371 }; 372 MIXER_DECLARE(es1370_mixer); 373 374 /* -------------------------------------------------------------------- */ 375 376 static int 377 es1370_wrcodec(struct es_info *es, u_char i, u_char data) 378 { 379 u_int t; 380 381 ES_LOCK_ASSERT(es); 382 383 for (t = 0; t < 0x1000; t++) { 384 if ((es_rd(es, ES1370_REG_STATUS, 4) & 385 STAT_CSTAT) == 0) { 386 es_wr(es, ES1370_REG_CODEC, 387 ((u_short)i << CODEC_INDEX_SHIFT) | data, 2); 388 return 0; 389 } 390 DELAY(1); 391 } 392 device_printf(es->dev, "%s: timed out\n", __func__); 393 return -1; 394 } 395 396 /* -------------------------------------------------------------------- */ 397 398 /* channel interface */ 399 static void * 400 eschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 401 { 402 struct es_info *es = devinfo; 403 struct es_chinfo *ch; 404 uint32_t index; 405 406 ES_LOCK(es); 407 408 if (dir == PCMDIR_PLAY) { 409 index = ES_GP(es->escfg); 410 es->escfg = ES_SET_GP(es->escfg, index + 1); 411 if (index == 0) { 412 index = ES_DAC_FIRST(es->escfg); 413 } else if (index == 1) { 414 index = ES_DAC_SECOND(es->escfg); 415 } else { 416 device_printf(es->dev, "Invalid ES_GP index: %d\n", index); 417 ES_UNLOCK(es); 418 return NULL; 419 } 420 if (!(index == ES_DAC1 || index == ES_DAC2)) { 421 device_printf(es->dev, "Unknown DAC: %d\n", 422 index + 1); 423 ES_UNLOCK(es); 424 return NULL; 425 } 426 if (es->ch[index].channel != NULL) { 427 device_printf(es->dev, "DAC%d already initialized!\n", 428 index + 1); 429 ES_UNLOCK(es); 430 return NULL; 431 } 432 } else 433 index = ES_ADC; 434 435 ch = &es->ch[index]; 436 ch->index = index; 437 ch->num = es->num++; 438 ch->caps = es_caps; 439 if (ES_IS_ES1370(es->escfg)) { 440 if (ch->index == ES_DAC1) { 441 ch->caps.maxspeed = ES1370_DAC1_MAXSPEED; 442 ch->caps.minspeed = ES1370_DAC1_MINSPEED; 443 } else { 444 uint32_t fixed_rate = ES_FIXED_RATE(es->escfg); 445 if (!(fixed_rate < es_caps.minspeed || 446 fixed_rate > es_caps.maxspeed)) { 447 ch->caps.maxspeed = fixed_rate; 448 ch->caps.minspeed = fixed_rate; 449 } 450 } 451 } 452 ch->parent = es; 453 ch->channel = c; 454 ch->buffer = b; 455 ch->bufsz = es->bufsz; 456 ch->blksz = ch->bufsz / 2; 457 ch->dir = dir; 458 ES_UNLOCK(es); 459 if (sndbuf_alloc(ch->buffer, es->parent_dmat, ch->bufsz) != 0) 460 return NULL; 461 ES_LOCK(es); 462 if (dir == PCMDIR_PLAY) { 463 if (ch->index == ES_DAC1) { 464 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_DAC1_FRAMEADR >> 8, 1); 465 es_wr(es, ES1370_REG_DAC1_FRAMEADR & 0xff, sndbuf_getbufaddr(ch->buffer), 4); 466 es_wr(es, ES1370_REG_DAC1_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 467 } else { 468 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_DAC2_FRAMEADR >> 8, 1); 469 es_wr(es, ES1370_REG_DAC2_FRAMEADR & 0xff, sndbuf_getbufaddr(ch->buffer), 4); 470 es_wr(es, ES1370_REG_DAC2_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 471 } 472 } else { 473 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_ADC_FRAMEADR >> 8, 1); 474 es_wr(es, ES1370_REG_ADC_FRAMEADR & 0xff, sndbuf_getbufaddr(ch->buffer), 4); 475 es_wr(es, ES1370_REG_ADC_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 476 } 477 ES_UNLOCK(es); 478 return ch; 479 } 480 481 static int 482 eschan_setformat(kobj_t obj, void *data, u_int32_t format) 483 { 484 struct es_chinfo *ch = data; 485 struct es_info *es = ch->parent; 486 487 ES_LOCK(es); 488 if (ch->dir == PCMDIR_PLAY) { 489 if (ch->index == ES_DAC1) { 490 es->sctrl &= ~SCTRL_P1FMT; 491 if (format & AFMT_S16_LE) es->sctrl |= SCTRL_P1SEB; 492 if (format & AFMT_STEREO) es->sctrl |= SCTRL_P1SMB; 493 } else { 494 es->sctrl &= ~SCTRL_P2FMT; 495 if (format & AFMT_S16_LE) es->sctrl |= SCTRL_P2SEB; 496 if (format & AFMT_STEREO) es->sctrl |= SCTRL_P2SMB; 497 } 498 } else { 499 es->sctrl &= ~SCTRL_R1FMT; 500 if (format & AFMT_S16_LE) es->sctrl |= SCTRL_R1SEB; 501 if (format & AFMT_STEREO) es->sctrl |= SCTRL_R1SMB; 502 } 503 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 504 ES_UNLOCK(es); 505 ch->fmt = format; 506 return 0; 507 } 508 509 static int 510 eschan1370_setspeed(kobj_t obj, void *data, u_int32_t speed) 511 { 512 struct es_chinfo *ch = data; 513 struct es_info *es = ch->parent; 514 515 /* Fixed rate , do nothing. */ 516 if (ch->caps.minspeed == ch->caps.maxspeed) 517 return ch->caps.maxspeed; 518 if (speed < ch->caps.minspeed) 519 speed = ch->caps.minspeed; 520 if (speed > ch->caps.maxspeed) 521 speed = ch->caps.maxspeed; 522 ES_LOCK(es); 523 if (ch->index == ES_DAC1) { 524 /* 525 * DAC1 does not support continuous rate settings. 526 * Pick the nearest and use it since FEEDER_RATE will 527 * do the the proper conversion for us. 528 */ 529 es->ctrl &= ~CTRL_WTSRSEL; 530 if (speed < 8268) { 531 speed = 5512; 532 es->ctrl |= 0 << CTRL_SH_WTSRSEL; 533 } else if (speed < 16537) { 534 speed = 11025; 535 es->ctrl |= 1 << CTRL_SH_WTSRSEL; 536 } else if (speed < 33075) { 537 speed = 22050; 538 es->ctrl |= 2 << CTRL_SH_WTSRSEL; 539 } else { 540 speed = 44100; 541 es->ctrl |= 3 << CTRL_SH_WTSRSEL; 542 } 543 } else { 544 es->ctrl &= ~CTRL_PCLKDIV; 545 es->ctrl |= DAC2_SRTODIV(speed) << CTRL_SH_PCLKDIV; 546 } 547 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 548 ES_UNLOCK(es); 549 return speed; 550 } 551 552 static int 553 eschan1371_setspeed(kobj_t obj, void *data, u_int32_t speed) 554 { 555 struct es_chinfo *ch = data; 556 struct es_info *es = ch->parent; 557 uint32_t i; 558 int delta; 559 560 ES_LOCK(es); 561 if (ch->dir == PCMDIR_PLAY) 562 i = es1371_dac_rate(es, speed, ch->index); /* play */ 563 else 564 i = es1371_adc_rate(es, speed, ch->index); /* record */ 565 ES_UNLOCK(es); 566 delta = (speed > i) ? speed - i : i - speed; 567 if (delta < 2) 568 return speed; 569 return i; 570 } 571 572 static int 573 eschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 574 { 575 struct es_info *es; 576 struct es_chinfo *ch = data; 577 uint32_t oblksz, obufsz; 578 int error; 579 580 oblksz = ch->blksz; 581 obufsz = ch->bufsz; 582 ch->blksz = blocksize; 583 ch->bufsz = ch->blksz * 2; 584 error = sndbuf_resize(ch->buffer, 2, ch->blksz); 585 if (error != 0) { 586 ch->blksz = oblksz; 587 ch->bufsz = obufsz; 588 es = ch->parent; 589 device_printf(es->dev, "unable to set block size, blksz = %d, " 590 "error = %d", blocksize, error); 591 } 592 return ch->blksz; 593 } 594 595 static int 596 eschan_trigger(kobj_t obj, void *data, int go) 597 { 598 struct es_chinfo *ch = data; 599 struct es_info *es = ch->parent; 600 uint32_t cnt, b = 0; 601 602 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 603 return 0; 604 605 cnt = (ch->blksz / sndbuf_getbps(ch->buffer)) - 1; 606 if (ch->fmt & AFMT_16BIT) 607 b |= 0x02; 608 if (ch->fmt & AFMT_STEREO) 609 b |= 0x01; 610 ES_LOCK(es); 611 if (ch->dir == PCMDIR_PLAY) { 612 if (go == PCMTRIG_START) { 613 if (ch->index == ES_DAC1) { 614 es->ctrl |= CTRL_DAC1_EN; 615 es->sctrl &= ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD); 616 es->sctrl |= SCTRL_P1INTEN | b; 617 es_wr(es, ES1370_REG_DAC1_SCOUNT, cnt, 4); 618 /* start at beginning of buffer */ 619 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_DAC1_FRAMECNT >> 8, 4); 620 es_wr(es, ES1370_REG_DAC1_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 621 } else { 622 es->ctrl |= CTRL_DAC2_EN; 623 es->sctrl &= ~(SCTRL_P2ENDINC | SCTRL_P2STINC | SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN); 624 es->sctrl |= SCTRL_P2INTEN | (b << 2) | 625 (((b & 2) ? : 1) << SCTRL_SH_P2ENDINC); 626 es_wr(es, ES1370_REG_DAC2_SCOUNT, cnt, 4); 627 /* start at beginning of buffer */ 628 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_DAC2_FRAMECNT >> 8, 4); 629 es_wr(es, ES1370_REG_DAC2_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 630 } 631 } else es->ctrl &= ~(ch->index == ES_DAC1 ? CTRL_DAC1_EN : CTRL_DAC2_EN); 632 } else { 633 if (go == PCMTRIG_START) { 634 es->ctrl |= CTRL_ADC_EN; 635 es->sctrl &= ~SCTRL_R1LOOPSEL; 636 es->sctrl |= SCTRL_R1INTEN | (b << 4); 637 es_wr(es, ES1370_REG_ADC_SCOUNT, cnt, 4); 638 /* start at beginning of buffer */ 639 es_wr(es, ES1370_REG_MEMPAGE, ES1370_REG_ADC_FRAMECNT >> 8, 4); 640 es_wr(es, ES1370_REG_ADC_FRAMECNT & 0xff, (ch->bufsz >> 2) - 1, 4); 641 } else es->ctrl &= ~CTRL_ADC_EN; 642 } 643 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 644 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 645 ES_UNLOCK(es); 646 return 0; 647 } 648 649 static int 650 eschan_getptr(kobj_t obj, void *data) 651 { 652 struct es_chinfo *ch = data; 653 struct es_info *es = ch->parent; 654 u_int32_t reg, cnt; 655 656 if (ch->dir == PCMDIR_PLAY) { 657 if (ch->index == ES_DAC1) 658 reg = ES1370_REG_DAC1_FRAMECNT; 659 else 660 reg = ES1370_REG_DAC2_FRAMECNT; 661 } else 662 reg = ES1370_REG_ADC_FRAMECNT; 663 ES_LOCK(es); 664 es_wr(es, ES1370_REG_MEMPAGE, reg >> 8, 4); 665 cnt = es_rd(es, reg & 0x000000ff, 4) >> 16; 666 ES_UNLOCK(es); 667 /* cnt is longwords */ 668 return cnt << 2; 669 } 670 671 static struct pcmchan_caps * 672 eschan_getcaps(kobj_t obj, void *data) 673 { 674 struct es_chinfo *ch = data; 675 676 return &ch->caps; 677 } 678 679 static kobj_method_t eschan1370_methods[] = { 680 KOBJMETHOD(channel_init, eschan_init), 681 KOBJMETHOD(channel_setformat, eschan_setformat), 682 KOBJMETHOD(channel_setspeed, eschan1370_setspeed), 683 KOBJMETHOD(channel_setblocksize, eschan_setblocksize), 684 KOBJMETHOD(channel_trigger, eschan_trigger), 685 KOBJMETHOD(channel_getptr, eschan_getptr), 686 KOBJMETHOD(channel_getcaps, eschan_getcaps), 687 { 0, 0 } 688 }; 689 CHANNEL_DECLARE(eschan1370); 690 691 static kobj_method_t eschan1371_methods[] = { 692 KOBJMETHOD(channel_init, eschan_init), 693 KOBJMETHOD(channel_setformat, eschan_setformat), 694 KOBJMETHOD(channel_setspeed, eschan1371_setspeed), 695 KOBJMETHOD(channel_setblocksize, eschan_setblocksize), 696 KOBJMETHOD(channel_trigger, eschan_trigger), 697 KOBJMETHOD(channel_getptr, eschan_getptr), 698 KOBJMETHOD(channel_getcaps, eschan_getcaps), 699 { 0, 0 } 700 }; 701 CHANNEL_DECLARE(eschan1371); 702 703 /* -------------------------------------------------------------------- */ 704 /* The interrupt handler */ 705 static void 706 es_intr(void *p) 707 { 708 struct es_info *es = p; 709 uint32_t intsrc, sctrl; 710 711 ES_LOCK(es); 712 intsrc = es_rd(es, ES1370_REG_STATUS, 4); 713 if ((intsrc & STAT_INTR) == 0) { 714 ES_UNLOCK(es); 715 return; 716 } 717 718 sctrl = es->sctrl; 719 if (intsrc & STAT_ADC) sctrl &= ~SCTRL_R1INTEN; 720 if (intsrc & STAT_DAC1) sctrl &= ~SCTRL_P1INTEN; 721 if (intsrc & STAT_DAC2) sctrl &= ~SCTRL_P2INTEN; 722 723 es_wr(es, ES1370_REG_SERIAL_CONTROL, sctrl, 4); 724 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 725 ES_UNLOCK(es); 726 727 if (intsrc & STAT_ADC) chn_intr(es->ch[ES_ADC].channel); 728 if (intsrc & STAT_DAC1) chn_intr(es->ch[ES_DAC1].channel); 729 if (intsrc & STAT_DAC2) chn_intr(es->ch[ES_DAC2].channel); 730 } 731 732 /* ES1370 specific */ 733 static int 734 es1370_init(struct es_info *es) 735 { 736 uint32_t fixed_rate; 737 int r, single_pcm; 738 739 /* ES1370 default to fixed rate operation */ 740 if (resource_int_value(device_get_name(es->dev), 741 device_get_unit(es->dev), "fixed_rate", &r) == 0) { 742 fixed_rate = r; 743 if (fixed_rate) { 744 if (fixed_rate < es_caps.minspeed) 745 fixed_rate = es_caps.minspeed; 746 if (fixed_rate > es_caps.maxspeed) 747 fixed_rate = es_caps.maxspeed; 748 } 749 } else 750 fixed_rate = es_caps.maxspeed; 751 752 if (resource_int_value(device_get_name(es->dev), 753 device_get_unit(es->dev), "single_pcm_mixer", &r) == 0) 754 single_pcm = (r) ? 1 : 0; 755 else 756 single_pcm = 1; 757 758 ES_LOCK(es); 759 if (ES_NUMPLAY(es->escfg) == 1) 760 single_pcm = 1; 761 /* This is ES1370 */ 762 es->escfg = ES_SET_IS_ES1370(es->escfg, 1); 763 if (fixed_rate) { 764 es->escfg = ES_SET_FIXED_RATE(es->escfg, fixed_rate); 765 } else { 766 es->escfg = ES_SET_FIXED_RATE(es->escfg, 0); 767 fixed_rate = DSP_DEFAULT_SPEED; 768 } 769 if (single_pcm) { 770 es->escfg = ES_SET_SINGLE_PCM_MIX(es->escfg, 1); 771 } else { 772 es->escfg = ES_SET_SINGLE_PCM_MIX(es->escfg, 0); 773 } 774 es->ctrl = CTRL_CDC_EN | CTRL_JYSTK_EN | CTRL_SERR_DIS | 775 (DAC2_SRTODIV(fixed_rate) << CTRL_SH_PCLKDIV); 776 es->ctrl |= 3 << CTRL_SH_WTSRSEL; 777 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 778 779 es->sctrl = 0; 780 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 781 782 es1370_wrcodec(es, CODEC_RES_PD, 3);/* No RST, PD */ 783 es1370_wrcodec(es, CODEC_CSEL, 0); /* CODEC ADC and CODEC DAC use 784 * {LR,B}CLK2 and run off the LRCLK2 785 * PLL; program DAC_SYNC=0! */ 786 es1370_wrcodec(es, CODEC_ADSEL, 0);/* Recording source is mixer */ 787 es1370_wrcodec(es, CODEC_MGAIN, 0);/* MIC amp is 0db */ 788 ES_UNLOCK(es); 789 790 return 0; 791 } 792 793 /* ES1371 specific */ 794 int 795 es1371_init(struct es_info *es) 796 { 797 uint32_t cssr, devid, revid, subdev; 798 int idx; 799 800 ES_LOCK(es); 801 /* This is NOT ES1370 */ 802 es->escfg = ES_SET_IS_ES1370(es->escfg, 0); 803 es->num = 0; 804 es->sctrl = 0; 805 cssr = 0; 806 devid = pci_get_devid(es->dev); 807 revid = pci_get_revid(es->dev); 808 subdev = (pci_get_subdevice(es->dev) << 16) | pci_get_subvendor(es->dev); 809 /* 810 * Joyport blacklist. Either we're facing with broken hardware 811 * or because this hardware need special (unknown) initialization 812 * procedures. 813 */ 814 switch (subdev) { 815 case 0x20001274: /* old Ensoniq */ 816 es->ctrl = 0; 817 break; 818 default: 819 es->ctrl = CTRL_JYSTK_EN; 820 break; 821 } 822 if (devid == CT4730_PCI_ID) { 823 /* XXX amplifier hack? */ 824 es->ctrl |= (1 << 16); 825 } 826 /* initialize the chips */ 827 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 828 es_wr(es, ES1370_REG_SERIAL_CONTROL, es->sctrl, 4); 829 es_wr(es, ES1371_REG_LEGACY, 0, 4); 830 if ((devid == ES1371_PCI_ID && revid == ES1371REV_ES1373_8) || 831 (devid == ES1371_PCI_ID && revid == ES1371REV_CT5880_A) || 832 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_C) || 833 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_D) || 834 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_E)) { 835 cssr = 1 << 29; 836 es_wr(es, ES1370_REG_STATUS, cssr, 4); 837 DELAY(20000); 838 } 839 /* AC'97 warm reset to start the bitclk */ 840 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 841 es_wr(es, ES1371_REG_LEGACY, ES1371_SYNC_RES, 4); 842 DELAY(2000); 843 es_wr(es, ES1370_REG_CONTROL, es->sctrl, 4); 844 es1371_wait_src_ready(es); 845 /* Init the sample rate converter */ 846 es_wr(es, ES1371_REG_SMPRATE, ES1371_DIS_SRC, 4); 847 for (idx = 0; idx < 0x80; idx++) 848 es1371_src_write(es, idx, 0); 849 es1371_src_write(es, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 850 es1371_src_write(es, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 851 es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 852 es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 853 es1371_src_write(es, ES_SMPREG_VOL_ADC, 1 << 12); 854 es1371_src_write(es, ES_SMPREG_VOL_ADC + 1, 1 << 12); 855 es1371_src_write(es, ES_SMPREG_VOL_DAC1, 1 << 12); 856 es1371_src_write(es, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 857 es1371_src_write(es, ES_SMPREG_VOL_DAC2, 1 << 12); 858 es1371_src_write(es, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 859 es1371_adc_rate(es, 22050, ES_ADC); 860 es1371_dac_rate(es, 22050, ES_DAC1); 861 es1371_dac_rate(es, 22050, ES_DAC2); 862 /* WARNING: 863 * enabling the sample rate converter without properly programming 864 * its parameters causes the chip to lock up (the SRC busy bit will 865 * be stuck high, and I've found no way to rectify this other than 866 * power cycle) 867 */ 868 es1371_wait_src_ready(es); 869 es_wr(es, ES1371_REG_SMPRATE, 0, 4); 870 /* try to reset codec directly */ 871 es_wr(es, ES1371_REG_CODEC, 0, 4); 872 es_wr(es, ES1370_REG_STATUS, cssr, 4); 873 ES_UNLOCK(es); 874 875 return (0); 876 } 877 878 /* -------------------------------------------------------------------- */ 879 880 static int 881 es1371_wrcd(kobj_t obj, void *s, int addr, u_int32_t data) 882 { 883 uint32_t t, x, orig; 884 struct es_info *es = (struct es_info*)s; 885 886 for (t = 0; t < 0x1000; t++) 887 if (!es_rd(es, ES1371_REG_CODEC & CODEC_WIP, 4)) 888 break; 889 /* save the current state for later */ 890 x = orig = es_rd(es, ES1371_REG_SMPRATE, 4); 891 /* enable SRC state data in SRC mux */ 892 es_wr(es, ES1371_REG_SMPRATE, 893 (x & 894 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1)) | 895 0x00010000, 4); 896 /* busy wait */ 897 for (t = 0; t < 0x1000; t++) 898 if ((es_rd(es, ES1371_REG_SMPRATE, 4) & 0x00870000) == 0x00000000) 899 break; 900 /* wait for a SAFE time to write addr/data and then do it, dammit */ 901 for (t = 0; t < 0x1000; t++) 902 if ((es_rd(es, ES1371_REG_SMPRATE, 4) & 0x00870000) == 0x00010000) 903 break; 904 905 es_wr(es, ES1371_REG_CODEC, 906 ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | 907 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), 4); 908 /* restore SRC reg */ 909 es1371_wait_src_ready(s); 910 es_wr(es, ES1371_REG_SMPRATE, orig, 4); 911 912 return 0; 913 } 914 915 static int 916 es1371_rdcd(kobj_t obj, void *s, int addr) 917 { 918 uint32_t t, x, orig; 919 struct es_info *es = (struct es_info *)s; 920 921 for (t = 0; t < 0x1000; t++) 922 if (!(x = es_rd(es, ES1371_REG_CODEC, 4) & CODEC_WIP)) 923 break; 924 925 /* save the current state for later */ 926 x = orig = es_rd(es, ES1371_REG_SMPRATE, 4); 927 /* enable SRC state data in SRC mux */ 928 es_wr(es, ES1371_REG_SMPRATE, 929 (x & 930 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1)) | 931 0x00010000, 4); 932 /* busy wait */ 933 for (t = 0; t < 0x1000; t++) 934 if ((x = es_rd(es, ES1371_REG_SMPRATE, 4) & 0x00870000) == 0x00000000) 935 break; 936 /* wait for a SAFE time to write addr/data and then do it, dammit */ 937 for (t = 0; t < 0x1000; t++) 938 if ((x = es_rd(es, ES1371_REG_SMPRATE, 4) & 0x00870000) == 0x00010000) 939 break; 940 941 es_wr(es, ES1371_REG_CODEC, 942 ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | 943 CODEC_PORD, 4); 944 945 /* restore SRC reg */ 946 es1371_wait_src_ready(s); 947 es_wr(es, ES1371_REG_SMPRATE, orig, 4); 948 949 /* now wait for the stinkin' data (RDY) */ 950 for (t = 0; t < 0x1000; t++) 951 if ((x = es_rd(es, ES1371_REG_CODEC, 4)) & CODEC_RDY) 952 break; 953 954 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT); 955 } 956 957 static kobj_method_t es1371_ac97_methods[] = { 958 KOBJMETHOD(ac97_read, es1371_rdcd), 959 KOBJMETHOD(ac97_write, es1371_wrcd), 960 { 0, 0 } 961 }; 962 AC97_DECLARE(es1371_ac97); 963 964 /* -------------------------------------------------------------------- */ 965 966 static u_int 967 es1371_src_read(struct es_info *es, u_short reg) 968 { 969 uint32_t r; 970 971 r = es1371_wait_src_ready(es) & 972 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1); 973 r |= ES1371_SRC_RAM_ADDRO(reg); 974 es_wr(es, ES1371_REG_SMPRATE, r, 4); 975 return ES1371_SRC_RAM_DATAI(es1371_wait_src_ready(es)); 976 } 977 978 static void 979 es1371_src_write(struct es_info *es, u_short reg, u_short data) 980 { 981 uint32_t r; 982 983 r = es1371_wait_src_ready(es) & 984 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1); 985 r |= ES1371_SRC_RAM_ADDRO(reg) | ES1371_SRC_RAM_DATAO(data); 986 es_wr(es, ES1371_REG_SMPRATE, r | ES1371_SRC_RAM_WE, 4); 987 } 988 989 static u_int 990 es1371_adc_rate(struct es_info *es, u_int rate, int set) 991 { 992 u_int n, truncm, freq, result; 993 994 ES_LOCK_ASSERT(es); 995 996 if (rate > 48000) rate = 48000; 997 if (rate < 4000) rate = 4000; 998 n = rate / 3000; 999 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 1000 n--; 1001 truncm = (21 * n - 1) | 1; 1002 freq = ((48000UL << 15) / rate) * n; 1003 result = (48000UL << 15) / (freq / n); 1004 if (set) { 1005 if (rate >= 24000) { 1006 if (truncm > 239) truncm = 239; 1007 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 1008 (((239 - truncm) >> 1) << 9) | (n << 4)); 1009 } else { 1010 if (truncm > 119) truncm = 119; 1011 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 1012 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 1013 } 1014 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 1015 (es1371_src_read(es, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 1016 0x00ff) | ((freq >> 5) & 0xfc00)); 1017 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 1018 es1371_src_write(es, ES_SMPREG_VOL_ADC, n << 8); 1019 es1371_src_write(es, ES_SMPREG_VOL_ADC + 1, n << 8); 1020 } 1021 return result; 1022 } 1023 1024 static u_int 1025 es1371_dac_rate(struct es_info *es, u_int rate, int set) 1026 { 1027 u_int freq, r, result, dac, dis; 1028 1029 ES_LOCK_ASSERT(es); 1030 1031 if (rate > 48000) rate = 48000; 1032 if (rate < 4000) rate = 4000; 1033 freq = ((rate << 15) + 1500) / 3000; 1034 result = (freq * 3000) >> 15; 1035 1036 dac = (set == ES_DAC1) ? ES_SMPREG_DAC1 : ES_SMPREG_DAC2; 1037 dis = (set == ES_DAC1) ? ES1371_DIS_P2 : ES1371_DIS_P1; 1038 r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1)); 1039 es_wr(es, ES1371_REG_SMPRATE, r, 4); 1040 es1371_src_write(es, dac + ES_SMPREG_INT_REGS, 1041 (es1371_src_read(es, dac + ES_SMPREG_INT_REGS) & 0x00ff) | ((freq >> 5) & 0xfc00)); 1042 es1371_src_write(es, dac + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 1043 r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | dis | ES1371_DIS_R1)); 1044 es_wr(es, ES1371_REG_SMPRATE, r, 4); 1045 return result; 1046 } 1047 1048 static uint32_t 1049 es1371_wait_src_ready(struct es_info *es) 1050 { 1051 uint32_t t, r; 1052 1053 for (t = 0; t < 0x1000; t++) { 1054 if (!((r = es_rd(es, ES1371_REG_SMPRATE, 4)) & ES1371_SRC_RAM_BUSY)) 1055 return r; 1056 DELAY(1); 1057 } 1058 device_printf(es->dev, "%s: timed out 0x%x [0x%x]\n", __func__, 1059 ES1371_REG_SMPRATE, r); 1060 return 0; 1061 } 1062 1063 /* -------------------------------------------------------------------- */ 1064 1065 /* 1066 * Probe and attach the card 1067 */ 1068 1069 static int 1070 es_pci_probe(device_t dev) 1071 { 1072 switch(pci_get_devid(dev)) { 1073 case ES1370_PCI_ID: 1074 device_set_desc(dev, "AudioPCI ES1370"); 1075 return BUS_PROBE_DEFAULT; 1076 1077 case ES1371_PCI_ID: 1078 switch(pci_get_revid(dev)) { 1079 case ES1371REV_ES1371_A: 1080 device_set_desc(dev, "AudioPCI ES1371-A"); 1081 return BUS_PROBE_DEFAULT; 1082 1083 case ES1371REV_ES1371_B: 1084 device_set_desc(dev, "AudioPCI ES1371-B"); 1085 return BUS_PROBE_DEFAULT; 1086 1087 case ES1371REV_ES1373_A: 1088 device_set_desc(dev, "AudioPCI ES1373-A"); 1089 return BUS_PROBE_DEFAULT; 1090 1091 case ES1371REV_ES1373_B: 1092 device_set_desc(dev, "AudioPCI ES1373-B"); 1093 return BUS_PROBE_DEFAULT; 1094 1095 case ES1371REV_ES1373_8: 1096 device_set_desc(dev, "AudioPCI ES1373-8"); 1097 return BUS_PROBE_DEFAULT; 1098 1099 case ES1371REV_CT5880_A: 1100 device_set_desc(dev, "Creative CT5880-A"); 1101 return BUS_PROBE_DEFAULT; 1102 1103 default: 1104 device_set_desc(dev, "AudioPCI ES1371-?"); 1105 device_printf(dev, "unknown revision %d -- please report to cg@freebsd.org\n", pci_get_revid(dev)); 1106 return BUS_PROBE_DEFAULT; 1107 } 1108 1109 case ES1371_PCI_ID2: 1110 device_set_desc(dev, "Strange AudioPCI ES1371-? (vid=3274)"); 1111 device_printf(dev, "unknown revision %d -- please report to cg@freebsd.org\n", pci_get_revid(dev)); 1112 return BUS_PROBE_DEFAULT; 1113 1114 case CT4730_PCI_ID: 1115 switch(pci_get_revid(dev)) { 1116 case CT4730REV_CT4730_A: 1117 device_set_desc(dev, "Creative SB AudioPCI CT4730/EV1938"); 1118 return BUS_PROBE_DEFAULT; 1119 default: 1120 device_set_desc(dev, "Creative SB AudioPCI CT4730-?"); 1121 device_printf(dev, "unknown revision %d -- please report to cg@freebsd.org\n", pci_get_revid(dev)); 1122 return BUS_PROBE_DEFAULT; 1123 } 1124 1125 case CT5880_PCI_ID: 1126 switch(pci_get_revid(dev)) { 1127 case CT5880REV_CT5880_C: 1128 device_set_desc(dev, "Creative CT5880-C"); 1129 return BUS_PROBE_DEFAULT; 1130 1131 case CT5880REV_CT5880_D: 1132 device_set_desc(dev, "Creative CT5880-D"); 1133 return BUS_PROBE_DEFAULT; 1134 1135 case CT5880REV_CT5880_E: 1136 device_set_desc(dev, "Creative CT5880-E"); 1137 return BUS_PROBE_DEFAULT; 1138 1139 default: 1140 device_set_desc(dev, "Creative CT5880-?"); 1141 device_printf(dev, "unknown revision %d -- please report to cg@freebsd.org\n", pci_get_revid(dev)); 1142 return BUS_PROBE_DEFAULT; 1143 } 1144 1145 default: 1146 return ENXIO; 1147 } 1148 } 1149 1150 #ifdef SND_DYNSYSCTL 1151 static int 1152 sysctl_es137x_spdif_enable(SYSCTL_HANDLER_ARGS) 1153 { 1154 struct es_info *es; 1155 device_t dev; 1156 uint32_t r; 1157 int err, new_en; 1158 1159 dev = oidp->oid_arg1; 1160 es = pcm_getdevinfo(dev); 1161 ES_LOCK(es); 1162 r = es_rd(es, ES1370_REG_STATUS, 4); 1163 ES_UNLOCK(es); 1164 new_en = (r & ENABLE_SPDIF) ? 1 : 0; 1165 err = sysctl_handle_int(oidp, &new_en, sizeof(new_en), req); 1166 1167 if (err || req->newptr == NULL) 1168 return (err); 1169 if (new_en < 0 || new_en > 1) 1170 return (EINVAL); 1171 1172 ES_LOCK(es); 1173 if (new_en) { 1174 r |= ENABLE_SPDIF; 1175 es->ctrl |= SPDIFEN_B; 1176 es->ctrl |= RECEN_B; 1177 } else { 1178 r &= ~ENABLE_SPDIF; 1179 es->ctrl &= ~SPDIFEN_B; 1180 es->ctrl &= ~RECEN_B; 1181 } 1182 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 1183 es_wr(es, ES1370_REG_STATUS, r, 4); 1184 ES_UNLOCK(es); 1185 1186 return (0); 1187 } 1188 1189 static int 1190 sysctl_es137x_latency_timer(SYSCTL_HANDLER_ARGS) 1191 { 1192 struct es_info *es; 1193 device_t dev; 1194 uint32_t val; 1195 int err; 1196 1197 dev = oidp->oid_arg1; 1198 es = pcm_getdevinfo(dev); 1199 ES_LOCK(es); 1200 val = pci_read_config(dev, PCIR_LATTIMER, 1); 1201 ES_UNLOCK(es); 1202 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 1203 1204 if (err || req->newptr == NULL) 1205 return (err); 1206 if (val > 255) 1207 return (EINVAL); 1208 1209 ES_LOCK(es); 1210 pci_write_config(dev, PCIR_LATTIMER, val, 1); 1211 ES_UNLOCK(es); 1212 1213 return (0); 1214 } 1215 1216 static int 1217 sysctl_es137x_fixed_rate(SYSCTL_HANDLER_ARGS) 1218 { 1219 struct es_info *es; 1220 device_t dev; 1221 uint32_t val; 1222 int err; 1223 1224 dev = oidp->oid_arg1; 1225 es = pcm_getdevinfo(dev); 1226 ES_LOCK(es); 1227 val = ES_FIXED_RATE(es->escfg); 1228 if (val < es_caps.minspeed) 1229 val = 0; 1230 ES_UNLOCK(es); 1231 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 1232 1233 if (err || req->newptr == NULL) 1234 return (err); 1235 if (val != 0 && (val < es_caps.minspeed || val > es_caps.maxspeed)) 1236 return (EINVAL); 1237 1238 ES_LOCK(es); 1239 if (es->ctrl & (CTRL_DAC2_EN|CTRL_ADC_EN)) { 1240 ES_UNLOCK(es); 1241 return (EBUSY); 1242 } 1243 if (val) { 1244 if (val != ES_FIXED_RATE(es->escfg)) { 1245 es->escfg = ES_SET_FIXED_RATE(es->escfg, val); 1246 es->ch[ES_DAC2].caps.maxspeed = val; 1247 es->ch[ES_DAC2].caps.minspeed = val; 1248 es->ch[ES_ADC].caps.maxspeed = val; 1249 es->ch[ES_ADC].caps.minspeed = val; 1250 es->ctrl &= ~CTRL_PCLKDIV; 1251 es->ctrl |= DAC2_SRTODIV(val) << CTRL_SH_PCLKDIV; 1252 es_wr(es, ES1370_REG_CONTROL, es->ctrl, 4); 1253 } 1254 } else { 1255 es->escfg = ES_SET_FIXED_RATE(es->escfg, 0); 1256 es->ch[ES_DAC2].caps = es_caps; 1257 es->ch[ES_ADC].caps = es_caps; 1258 } 1259 ES_UNLOCK(es); 1260 1261 return (0); 1262 } 1263 1264 static int 1265 sysctl_es137x_single_pcm_mixer(SYSCTL_HANDLER_ARGS) 1266 { 1267 struct es_info *es; 1268 struct snddev_info *d; 1269 struct snd_mixer *m; 1270 struct cdev *i_dev; 1271 device_t dev; 1272 uint32_t val, set; 1273 int recsrc, level, err; 1274 1275 dev = oidp->oid_arg1; 1276 d = device_get_softc(dev); 1277 if (d == NULL || d->mixer_dev == NULL || d->mixer_dev->si_drv1 == NULL) 1278 return (EINVAL); 1279 es = d->devinfo; 1280 if (es == NULL) 1281 return (EINVAL); 1282 ES_LOCK(es); 1283 set = ES_SINGLE_PCM_MIX(es->escfg); 1284 val = set; 1285 ES_UNLOCK(es); 1286 err = sysctl_handle_int(oidp, &val, sizeof(val), req); 1287 1288 if (err || req->newptr == NULL) 1289 return (err); 1290 if (!(val == 0 || val == 1)) 1291 return (EINVAL); 1292 if (val == set) 1293 return (0); 1294 i_dev = d->mixer_dev; 1295 if (mixer_ioctl(i_dev, 0, (caddr_t)&recsrc, 0, NULL) != EBADF) 1296 return (EBUSY); 1297 err = mixer_ioctl(i_dev, MIXER_READ(SOUND_MIXER_PCM), 1298 (caddr_t)&level, -1, NULL); 1299 if (!err) 1300 err = mixer_ioctl(i_dev, MIXER_READ(SOUND_MIXER_RECSRC), 1301 (caddr_t)&recsrc, -1, NULL); 1302 if (err) 1303 return (err); 1304 if (level < 0) 1305 return (EINVAL); 1306 1307 ES_LOCK(es); 1308 if (es->ctrl & (CTRL_ADC_EN | CTRL_DAC1_EN | CTRL_DAC2_EN)) { 1309 ES_UNLOCK(es); 1310 return (EBUSY); 1311 } 1312 if (val) { 1313 es->escfg = ES_SET_SINGLE_PCM_MIX(es->escfg, 1); 1314 } else { 1315 es->escfg = ES_SET_SINGLE_PCM_MIX(es->escfg, 0); 1316 } 1317 ES_UNLOCK(es); 1318 m = i_dev->si_drv1; 1319 if (!val) { 1320 mix_setdevs(m, mix_getdevs(d->mixer_dev->si_drv1) | 1321 (1 << SOUND_MIXER_SYNTH)); 1322 mix_setrecdevs(m, mix_getrecdevs(d->mixer_dev->si_drv1) | 1323 (1 << SOUND_MIXER_SYNTH)); 1324 err = mixer_ioctl(i_dev, MIXER_WRITE(SOUND_MIXER_SYNTH), 1325 (caddr_t)&level, -1, NULL); 1326 } else { 1327 err = mixer_ioctl(i_dev, MIXER_WRITE(SOUND_MIXER_SYNTH), 1328 (caddr_t)&level, -1, NULL); 1329 mix_setdevs(m, mix_getdevs(d->mixer_dev->si_drv1) & 1330 ~(1 << SOUND_MIXER_SYNTH)); 1331 mix_setrecdevs(m, mix_getrecdevs(d->mixer_dev->si_drv1) & 1332 ~(1 << SOUND_MIXER_SYNTH)); 1333 } 1334 if (!err) { 1335 level = recsrc; 1336 if (recsrc & (1 << SOUND_MIXER_PCM)) 1337 recsrc |= 1 << SOUND_MIXER_SYNTH; 1338 else if (recsrc & (1 << SOUND_MIXER_SYNTH)) 1339 recsrc |= 1 << SOUND_MIXER_PCM; 1340 if (level != recsrc) 1341 err = mixer_ioctl(i_dev, MIXER_WRITE(SOUND_MIXER_RECSRC), 1342 (caddr_t)&recsrc, -1, NULL); 1343 } 1344 return (err); 1345 } 1346 #endif /* SND_DYNSYSCTL */ 1347 1348 static void 1349 es_init_sysctls(device_t dev) 1350 { 1351 #ifdef SND_DYNSYSCTL 1352 struct es_info *es; 1353 int r, devid, revid; 1354 1355 devid = pci_get_devid(dev); 1356 revid = pci_get_revid(dev); 1357 es = pcm_getdevinfo(dev); 1358 if ((devid == ES1371_PCI_ID && revid == ES1371REV_ES1373_8) || 1359 (devid == ES1371_PCI_ID && revid == ES1371REV_CT5880_A) || 1360 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_C) || 1361 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_D) || 1362 (devid == CT5880_PCI_ID && revid == CT5880REV_CT5880_E)) { 1363 /* XXX: an user should be able to set this with a control tool, 1364 if not done before 7.0-RELEASE, this needs to be converted 1365 to a device specific sysctl "dev.pcm.X.yyy" via 1366 device_get_sysctl_*() as discussed on multimedia@ in msg-id 1367 <861wujij2q.fsf@xps.des.no> */ 1368 SYSCTL_ADD_PROC(snd_sysctl_tree(dev), 1369 SYSCTL_CHILDREN(snd_sysctl_tree_top(dev)), 1370 OID_AUTO, "_spdif_enabled", 1371 CTLTYPE_INT | CTLFLAG_RW, dev, sizeof(dev), 1372 sysctl_es137x_spdif_enable, "I", 1373 "Enable S/PDIF output on primary playback channel"); 1374 } else if (devid == ES1370_PCI_ID) { 1375 /* 1376 * Enable fixed rate sysctl if both DAC2 / ADC enabled. 1377 */ 1378 if (es->ch[ES_DAC2].channel != NULL && es->ch[ES_ADC].channel != NULL) { 1379 /* XXX: an user should be able to set this with a control tool, 1380 if not done before 7.0-RELEASE, this needs to be converted 1381 to a device specific sysctl "dev.pcm.X.yyy" via 1382 device_get_sysctl_*() as discussed on multimedia@ in msg-id 1383 <861wujij2q.fsf@xps.des.no> */ 1384 SYSCTL_ADD_PROC(snd_sysctl_tree(dev), 1385 SYSCTL_CHILDREN(snd_sysctl_tree_top(dev)), 1386 OID_AUTO, "_fixed_rate", 1387 CTLTYPE_INT | CTLFLAG_RW, dev, sizeof(dev), 1388 sysctl_es137x_fixed_rate, "I", 1389 "Enable fixed rate playback/recording"); 1390 } 1391 /* 1392 * Enable single pcm mixer sysctl if both DAC1/2 enabled. 1393 */ 1394 if (es->ch[ES_DAC1].channel != NULL && es->ch[ES_DAC2].channel != NULL) { 1395 /* XXX: an user should be able to set this with a control tool, 1396 if not done before 7.0-RELEASE, this needs to be converted 1397 to a device specific sysctl "dev.pcm.X.yyy" via 1398 device_get_sysctl_*() as discussed on multimedia@ in msg-id 1399 <861wujij2q.fsf@xps.des.no> */ 1400 SYSCTL_ADD_PROC(snd_sysctl_tree(dev), 1401 SYSCTL_CHILDREN(snd_sysctl_tree_top(dev)), 1402 OID_AUTO, "_single_pcm_mixer", 1403 CTLTYPE_INT | CTLFLAG_RW, dev, sizeof(dev), 1404 sysctl_es137x_single_pcm_mixer, "I", 1405 "Single PCM mixer controller for both DAC1/DAC2"); 1406 } 1407 } 1408 if (resource_int_value(device_get_name(dev), 1409 device_get_unit(dev), "latency_timer", &r) == 0 && 1410 !(r < 0 || r > 255)) 1411 pci_write_config(dev, PCIR_LATTIMER, r, 1); 1412 /* XXX: this needs to be converted to a device specific sysctl 1413 "dev.pcm.X.yyy" via device_get_sysctl_*() as discussed on 1414 multimedia@ in msg-id <861wujij2q.fsf@xps.des.no> */ 1415 SYSCTL_ADD_PROC(snd_sysctl_tree(dev), 1416 SYSCTL_CHILDREN(snd_sysctl_tree_top(dev)), 1417 OID_AUTO, "latency_timer", 1418 CTLTYPE_INT | CTLFLAG_RW, dev, sizeof(dev), 1419 sysctl_es137x_latency_timer, "I", 1420 "PCI Latency Timer configuration"); 1421 #endif /* SND_DYNSYSCTL */ 1422 } 1423 1424 static int 1425 es_pci_attach(device_t dev) 1426 { 1427 u_int32_t data; 1428 struct es_info *es = NULL; 1429 int mapped, i, numplay, dac_cfg; 1430 char status[SND_STATUSLEN]; 1431 struct ac97_info *codec = NULL; 1432 kobj_class_t ct = NULL; 1433 uint32_t devid; 1434 1435 if ((es = malloc(sizeof *es, M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1436 device_printf(dev, "cannot allocate softc\n"); 1437 return ENXIO; 1438 } 1439 es->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 1440 es->dev = dev; 1441 es->escfg = 0; 1442 mapped = 0; 1443 1444 pci_enable_busmaster(dev); 1445 data = pci_read_config(dev, PCIR_COMMAND, 2); 1446 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN); 1447 pci_write_config(dev, PCIR_COMMAND, data, 2); 1448 data = pci_read_config(dev, PCIR_COMMAND, 2); 1449 if (mapped == 0 && (data & PCIM_CMD_MEMEN)) { 1450 es->regid = MEM_MAP_REG; 1451 es->regtype = SYS_RES_MEMORY; 1452 es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid, 1453 RF_ACTIVE); 1454 if (es->reg) 1455 mapped++; 1456 } 1457 if (mapped == 0 && (data & PCIM_CMD_PORTEN)) { 1458 es->regid = PCIR_BAR(0); 1459 es->regtype = SYS_RES_IOPORT; 1460 es->reg = bus_alloc_resource_any(dev, es->regtype, &es->regid, 1461 RF_ACTIVE); 1462 if (es->reg) 1463 mapped++; 1464 } 1465 if (mapped == 0) { 1466 device_printf(dev, "unable to map register space\n"); 1467 goto bad; 1468 } 1469 1470 es->st = rman_get_bustag(es->reg); 1471 es->sh = rman_get_bushandle(es->reg); 1472 es->bufsz = pcm_getbuffersize(dev, 4096, ES_DEFAULT_BUFSZ, 65536); 1473 1474 if (resource_int_value(device_get_name(dev), 1475 device_get_unit(dev), "dac", &dac_cfg) == 0) { 1476 if (dac_cfg < 0 || dac_cfg > 3) 1477 dac_cfg = ES_DEFAULT_DAC_CFG; 1478 } else 1479 dac_cfg = ES_DEFAULT_DAC_CFG; 1480 1481 switch (dac_cfg) { 1482 case 0: /* Enable all DAC: DAC1, DAC2 */ 1483 numplay = 2; 1484 es->escfg = ES_SET_DAC_FIRST(es->escfg, ES_DAC1); 1485 es->escfg = ES_SET_DAC_SECOND(es->escfg, ES_DAC2); 1486 break; 1487 case 1: /* Only DAC1 */ 1488 numplay = 1; 1489 es->escfg = ES_SET_DAC_FIRST(es->escfg, ES_DAC1); 1490 break; 1491 case 3: /* Enable all DAC / swap position: DAC2, DAC1 */ 1492 numplay = 2; 1493 es->escfg = ES_SET_DAC_FIRST(es->escfg, ES_DAC2); 1494 es->escfg = ES_SET_DAC_SECOND(es->escfg, ES_DAC1); 1495 break; 1496 case 2: /* Only DAC2 */ 1497 default: 1498 numplay = 1; 1499 es->escfg = ES_SET_DAC_FIRST(es->escfg, ES_DAC2); 1500 break; 1501 } 1502 es->escfg = ES_SET_NUMPLAY(es->escfg, numplay); 1503 es->escfg = ES_SET_NUMREC(es->escfg, 1); 1504 1505 devid = pci_get_devid(dev); 1506 switch (devid) { 1507 case ES1371_PCI_ID: 1508 case ES1371_PCI_ID2: 1509 case CT5880_PCI_ID: 1510 case CT4730_PCI_ID: 1511 es1371_init(es); 1512 codec = AC97_CREATE(dev, es, es1371_ac97); 1513 if (codec == NULL) 1514 goto bad; 1515 /* our init routine does everything for us */ 1516 /* set to NULL; flag mixer_init not to run the ac97_init */ 1517 /* ac97_mixer.init = NULL; */ 1518 if (mixer_init(dev, ac97_getmixerclass(), codec)) 1519 goto bad; 1520 ct = &eschan1371_class; 1521 break; 1522 case ES1370_PCI_ID: 1523 es1370_init(es); 1524 /* 1525 * Disable fixed rate operation if DAC2 disabled. 1526 * This is a special case for es1370 only, where the 1527 * speed of both ADC and DAC2 locked together. 1528 */ 1529 if (!ES_DAC2_ENABLED(es->escfg)) { 1530 es->escfg = ES_SET_FIXED_RATE(es->escfg, 0); 1531 } 1532 if (mixer_init(dev, &es1370_mixer_class, es)) 1533 goto bad; 1534 ct = &eschan1370_class; 1535 break; 1536 default: 1537 goto bad; 1538 /* NOTREACHED */ 1539 } 1540 1541 es->irqid = 0; 1542 es->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &es->irqid, 1543 RF_ACTIVE | RF_SHAREABLE); 1544 if (!es->irq || snd_setup_intr(dev, es->irq, INTR_MPSAFE, es_intr, es, &es->ih)) { 1545 device_printf(dev, "unable to map interrupt\n"); 1546 goto bad; 1547 } 1548 1549 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 1550 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 1551 /*highaddr*/BUS_SPACE_MAXADDR, 1552 /*filter*/NULL, /*filterarg*/NULL, 1553 /*maxsize*/es->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 1554 /*flags*/0, /*lockfunc*/NULL, 1555 /*lockarg*/NULL, &es->parent_dmat) != 0) { 1556 device_printf(dev, "unable to create dma tag\n"); 1557 goto bad; 1558 } 1559 1560 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s", 1561 (es->regtype == SYS_RES_IOPORT)? "io" : "memory", 1562 rman_get_start(es->reg), rman_get_start(es->irq),PCM_KLDSTRING(snd_es137x)); 1563 1564 if (pcm_register(dev, es, numplay, 1)) 1565 goto bad; 1566 for (i = 0; i < numplay; i++) 1567 pcm_addchan(dev, PCMDIR_PLAY, ct, es); 1568 pcm_addchan(dev, PCMDIR_REC, ct, es); 1569 es_init_sysctls(dev); 1570 pcm_setstatus(dev, status); 1571 es->escfg = ES_SET_GP(es->escfg, 0); 1572 if (numplay == 1) { 1573 device_printf(dev, "<Playback: DAC%d / Record: ADC>\n", 1574 ES_DAC_FIRST(es->escfg) + 1); 1575 } else if (numplay == 2) { 1576 device_printf(dev, "<Playback: DAC%d,DAC%d / Record: ADC>\n", 1577 ES_DAC_FIRST(es->escfg) + 1, 1578 ES_DAC_SECOND(es->escfg) + 1); 1579 } 1580 return 0; 1581 1582 bad: 1583 if (es->parent_dmat) bus_dma_tag_destroy(es->parent_dmat); 1584 if (es->ih) bus_teardown_intr(dev, es->irq, es->ih); 1585 if (es->irq) bus_release_resource(dev, SYS_RES_IRQ, es->irqid, es->irq); 1586 if (codec) ac97_destroy(codec); 1587 if (es->reg) bus_release_resource(dev, es->regtype, es->regid, es->reg); 1588 if (es->lock) snd_mtxfree(es->lock); 1589 if (es) free(es, M_DEVBUF); 1590 return ENXIO; 1591 } 1592 1593 static int 1594 es_pci_detach(device_t dev) 1595 { 1596 int r; 1597 struct es_info *es; 1598 1599 r = pcm_unregister(dev); 1600 if (r) return r; 1601 1602 es = pcm_getdevinfo(dev); 1603 bus_teardown_intr(dev, es->irq, es->ih); 1604 bus_release_resource(dev, SYS_RES_IRQ, es->irqid, es->irq); 1605 bus_release_resource(dev, es->regtype, es->regid, es->reg); 1606 bus_dma_tag_destroy(es->parent_dmat); 1607 snd_mtxfree(es->lock); 1608 free(es, M_DEVBUF); 1609 1610 return 0; 1611 } 1612 1613 static device_method_t es_methods[] = { 1614 /* Device interface */ 1615 DEVMETHOD(device_probe, es_pci_probe), 1616 DEVMETHOD(device_attach, es_pci_attach), 1617 DEVMETHOD(device_detach, es_pci_detach), 1618 1619 { 0, 0 } 1620 }; 1621 1622 static driver_t es_driver = { 1623 "pcm", 1624 es_methods, 1625 PCM_SOFTC_SIZE, 1626 }; 1627 1628 DRIVER_MODULE(snd_es137x, pci, es_driver, pcm_devclass, 0, 0); 1629 MODULE_DEPEND(snd_es137x, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1630 MODULE_VERSION(snd_es137x, 1); 1631