1 /*- 2 * Copyright (c) 2006 Konstantin Dimitrov <kosio.dimitrov@gmail.com> 3 * Copyright (c) 2001 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 31 /* -------------------------------------------------------------------- */ 32 33 /* PCI device ID */ 34 #define PCIV_ENVY24 0x1412 35 #define PCID_ENVY24HT 0x1724 36 37 #define PCIR_CCS 0x10 /* Controller I/O Base Address */ 38 #define ENVY24HT_PCIR_MT 0x14 /* Multi-Track I/O Base Address */ 39 40 /* Controller Registers */ 41 42 #define ENVY24HT_CCS_CTL 0x00 /* Control/Status Register */ 43 #define ENVY24HT_CCS_CTL_RESET 0x80 /* Entire Chip soft reset */ 44 45 #define ENVY24HT_CCS_IMASK 0x01 /* Interrupt Mask Register */ 46 #define ENVY24HT_CCS_IMASK_PMT 0x10 /* Professional Multi-track */ 47 48 #define ENVY24HT_CCS_I2CDEV 0x10 /* I2C Port Device Address Register */ 49 #define ENVY24HT_CCS_I2CDEV_ADDR 0xfe /* I2C device address */ 50 #define ENVY24HT_CCS_I2CDEV_ROM 0xa0 /* reserved for the external I2C E2PROM */ 51 #define ENVY24HT_CCS_I2CDEV_WR 0x01 /* write */ 52 #define ENVY24HT_CCS_I2CDEV_RD 0x00 /* read */ 53 54 #define ENVY24HT_CCS_I2CADDR 0x11 /* I2C Port Byte Address Register */ 55 #define ENVY24HT_CCS_I2CDATA 0x12 /* I2C Port Read/Write Data Register */ 56 57 #define ENVY24HT_CCS_I2CSTAT 0x13 /* I2C Port Control and Status Register */ 58 #define ENVY24HT_CCS_I2CSTAT_ROM 0x80 /* external E2PROM exists */ 59 #define ENVY24HT_CCS_I2CSTAT_BSY 0x01 /* I2C port read/write status busy */ 60 61 #define ENVY24HT_CCS_SCFG 0x04 /* System Configuration Register */ 62 #define ENVY24HT_CCSM_SCFG_XIN2 0xc0 /* XIN2 Clock Source Configuration */ 63 /* 00: 24.576MHz(96kHz*256) */ 64 /* 01: 49.152MHz(192kHz*256) */ 65 /* 1x: Reserved */ 66 #define ENVY24HT_CCSM_SCFG_MPU 0x20 /* 0(not implemented)/1(1) MPU-401 UART */ 67 #define ENVY24HT_CCSM_SCFG_ADC 0x0c /* 1-2 stereo ADC connected, S/PDIF receiver connected */ 68 #define ENVY24HT_CCSM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */ 69 70 #define ENVY24HT_CCS_ACL 0x05 /* AC-Link Configuration Register */ 71 #define ENVY24HT_CCSM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */ 72 #define ENVY24HT_CCSM_ACL_OMODE 0x02 /* AC 97 codec SDATA_OUT 0:split 1:packed */ 73 74 #define ENVY24HT_CCS_I2S 0x06 /* I2S Converters Features Register */ 75 #define ENVY24HT_CCSM_I2S_VOL 0x80 /* I2S codec Volume and mute */ 76 #define ENVY24HT_CCSM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */ 77 #define ENVY24HT_CCSM_I2S_192KHZ 0x08 /* I2S converter 192kHz sampling rate support */ 78 #define ENVY24HT_CCSM_I2S_RES 0x30 /* Converter resolution */ 79 #define ENVY24HT_CCSM_I2S_16BIT 0x00 /* 16bit */ 80 #define ENVY24HT_CCSM_I2S_18BIT 0x10 /* 18bit */ 81 #define ENVY24HT_CCSM_I2S_20BIT 0x20 /* 20bit */ 82 #define ENVY24HT_CCSM_I2S_24BIT 0x30 /* 24bit */ 83 #define ENVY24HT_CCSM_I2S_ID 0x07 /* Other I2S IDs */ 84 85 #define ENVY24HT_CCS_SPDIF 0x07 /* S/PDIF Configuration Register */ 86 #define ENVY24HT_CCSM_SPDIF_INT_EN 0x80 /* Enable integrated S/PDIF transmitter */ 87 #define ENVY24HT_CCSM_SPDIF_INT_OUT 0x40 /* Internal S/PDIF Out implemented */ 88 #define ENVY24HT_CCSM_SPDIF_ID 0x3c /* S/PDIF chip ID */ 89 #define ENVY24HT_CCSM_SPDIF_IN 0x02 /* S/PDIF Stereo In is present */ 90 #define ENVY24HT_CCSM_SPDIF_OUT 0x01 /* External S/PDIF Out implemented */ 91 92 /* Professional Multi-Track Control Registers */ 93 94 #define ENVY24HT_MT_INT_STAT 0x00 /* DMA Interrupt Mask and Status Register */ 95 #define ENVY24HT_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */ 96 #define ENVY24HT_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */ 97 #define ENVY24HT_MT_INT_MASK 0x03 98 #define ENVY24HT_MT_INT_RMASK 0x02 /* Multi-track record interrupt mask */ 99 #define ENVY24HT_MT_INT_PMASK 0x01 /* Multi-track playback interrupt mask */ 100 101 #define ENVY24HT_MT_RATE 0x01 /* Sampling Rate Select Register */ 102 #define ENVY24HT_MT_RATE_SPDIF 0x10 /* S/PDIF input clock as the master */ 103 #define ENVY24HT_MT_RATE_48000 0x00 104 #define ENVY24HT_MT_RATE_24000 0x01 105 #define ENVY24HT_MT_RATE_12000 0x02 106 #define ENVY24HT_MT_RATE_9600 0x03 107 #define ENVY24HT_MT_RATE_32000 0x04 108 #define ENVY24HT_MT_RATE_16000 0x05 109 #define ENVY24HT_MT_RATE_8000 0x06 110 #define ENVY24HT_MT_RATE_96000 0x07 111 #define ENVY24HT_MT_RATE_192000 0x0e 112 #define ENVY24HT_MT_RATE_64000 0x0f 113 #define ENVY24HT_MT_RATE_44100 0x08 114 #define ENVY24HT_MT_RATE_22050 0x09 115 #define ENVY24HT_MT_RATE_11025 0x0a 116 #define ENVY24HT_MT_RATE_88200 0x0b 117 #define ENVY24HT_MT_RATE_176400 0x0c 118 #define ENVY24HT_MT_RATE_MASK 0x0f 119 120 #define ENVY24HT_MT_I2S 0x02 /* I2S Data Format Register */ 121 #define ENVY24HT_MT_I2S_MLR128 0x08 /* MCLK/LRCLK ratio 128x (or 256x) */ 122 123 #define ENVY24HT_MT_PADDR 0x10 /* Playback DMA Current/Base Address Register */ 124 #define ENVY24HT_MT_PCNT 0x14 /* Playback DMA Current/Base Count Register */ 125 #define ENVY24HT_MT_PTERM 0x1C /* Playback Current/Base Terminal Count Register */ 126 127 #define ENVY24HT_MT_PCTL 0x18 /* Global Playback and Record DMA Start/Stop Register */ 128 #define ENVY24HT_MT_PCTL_RSTART 0x02 /* 1: Record start; 0: Record stop */ 129 #define ENVY24HT_MT_PCTL_PSTART 0x01 /* 1: Playback start; 0: Playback stop */ 130 131 #define ENVY24HT_MT_RADDR 0x20 /* Record DMA Current/Base Address Register */ 132 #define ENVY24HT_MT_RCNT 0x24 /* Record DMA Current/Base Count Register */ 133 #define ENVY24HT_MT_RTERM 0x26 /* Record Current/Base Terminal Count Register */ 134 135 /* 136 These map values are refferd from ALSA sound driver. 137 */ 138 /* ENVY24 configuration E2PROM map */ 139 #define ENVY24HT_E2PROM_SUBVENDOR 0x02 140 #define ENVY24HT_E2PROM_SUBDEVICE 0x00 141 #define ENVY24HT_E2PROM_SIZE 0x04 142 #define ENVY24HT_E2PROM_VERSION 0x05 143 #define ENVY24HT_E2PROM_SCFG 0x06 144 #define ENVY24HT_E2PROM_ACL 0x07 145 #define ENVY24HT_E2PROM_I2S 0x08 146 #define ENVY24HT_E2PROM_SPDIF 0x09 147 #define ENVY24HT_E2PROM_GPIOMASK 0x0d 148 #define ENVY24HT_E2PROM_GPIOSTATE 0x10 149 #define ENVY24HT_E2PROM_GPIODIR 0x0a 150 151 /* ENVY24 mixer channel defines */ 152 /* 153 ENVY24 mixer has original line matrix. So, general mixer command is not 154 able to use for this. If system has consumer AC'97 output, AC'97 line is 155 used as master mixer, and it is able to control. 156 */ 157 #define ENVY24HT_CHAN_NUM 11 /* Play * 5 + Record * 5 + Mix * 1 */ 158 159 #define ENVY24HT_CHAN_PLAY_DAC1 0 160 #define ENVY24HT_CHAN_PLAY_DAC2 1 161 #define ENVY24HT_CHAN_PLAY_DAC3 2 162 #define ENVY24HT_CHAN_PLAY_DAC4 3 163 #define ENVY24HT_CHAN_PLAY_SPDIF 4 164 #define ENVY24HT_CHAN_REC_ADC1 5 165 #define ENVY24HT_CHAN_REC_ADC2 6 166 #define ENVY24HT_CHAN_REC_ADC3 7 167 #define ENVY24HT_CHAN_REC_ADC4 8 168 #define ENVY24HT_CHAN_REC_SPDIF 9 169 #define ENVY24HT_CHAN_REC_MIX 10 170 171 #define ENVY24HT_MIX_MASK 0x3fd 172 #define ENVY24HT_MIX_REC_MASK 0x3e0 173 174 /* volume value constants */ 175 #define ENVY24HT_VOL_MAX 0 /* 0db(negate) */ 176 #define ENVY24HT_VOL_MIN 96 /* -144db(negate) */ 177 #define ENVY24HT_VOL_MUTE 127 /* mute */ 178 179 #define BUS_SPACE_MAXADDR_ENVY24 0x0fffffff /* Address space beyond 256MB is not 180 supported */ 181 #define BUS_SPACE_MAXSIZE_ENVY24 0x3fffc /* 64k x 4byte(1dword) */ 182 183 #define ENVY24HT_CCS_GPIO_HDATA 0x1E 184 #define ENVY24HT_CCS_GPIO_LDATA 0x14 185 #define ENVY24HT_CCS_GPIO_LMASK 0x16 186 #define ENVY24HT_CCS_GPIO_HMASK 0x1F 187 #define ENVY24HT_CCS_GPIO_CTLDIR 0x18 188 189