1 /*- 2 * Copyright (c) 2001 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 30 /* -------------------------------------------------------------------- */ 31 32 /* PCI device ID */ 33 #define PCIV_ENVY24 0x1412 34 #define PCID_ENVY24 0x1712 35 36 /* PCI Registers */ 37 38 #define PCIR_CCS 0x10 /* Controller I/O Base Address */ 39 #define PCIR_DDMA 0x14 /* DDMA I/O Base Address */ 40 #define PCIR_DS 0x18 /* DMA Path Registers I/O Base Address */ 41 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */ 42 43 #define PCIR_LAC 0x40 /* Legacy Audio Control */ 44 #define PCIM_LAC_DISABLE 0x8000 /* Legacy Audio Hardware disabled */ 45 #define PCIM_LAC_SBDMA0 0x0000 /* SB DMA Channel Select: 0 */ 46 #define PCIM_LAC_SBDMA1 0x0040 /* SB DMA Channel Select: 1 */ 47 #define PCIM_LAC_SBDMA3 0x00c0 /* SB DMA Channel Select: 3 */ 48 #define PCIM_LAC_IOADDR10 0x0020 /* I/O Address Alias Control */ 49 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */ 50 #define PCIM_LAC_GAME 0x0004 /* Game Port enable (200h) */ 51 #define PCIM_LAC_FM 0x0002 /* FM I/O enable (AdLib 388h base) */ 52 #define PCIM_LAC_SB 0x0001 /* SB I/O enable */ 53 54 #define PCIR_LCC 0x42 /* Legacy Configuration Control */ 55 #define PCIM_LCC_VINT 0xff00 /* Interrupt vector to be snooped */ 56 #define PCIM_LCC_SVIDRW 0x0080 /* SVID read/write enable */ 57 #define PCIM_LCC_SNPSB 0x0040 /* snoop SB 22C/24Ch I/O write cycle */ 58 #define PCIM_LCC_SNPPIC 0x0020 /* snoop PIC I/O R/W cycle */ 59 #define PCIM_LCC_SNPPCI 0x0010 /* snoop PCI bus interrupt acknowledge cycle */ 60 #define PCIM_LCC_SBBASE 0x0008 /* SB base 240h(1)/220h(0) */ 61 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */ 62 #define PCIM_LCC_LDMA 0x0001 /* Legacy DMA enable */ 63 64 #define PCIR_SCFG 0x60 /* System Configuration Register */ 65 #define PCIM_SCFG_XIN2 0xc0 /* XIN2 Clock Source Configuration */ 66 /* 00: 22.5792MHz(44.1kHz*512) */ 67 /* 01: 16.9344MHz(44.1kHz*384) */ 68 /* 10: from external clock synthesizer chip */ 69 #define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */ 70 #define PCIM_SCFG_AC97 0x10 /* 0: AC'97 codec exist */ 71 /* 1: AC'97 codec not exist */ 72 #define PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */ 73 #define PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */ 74 75 #define PCIR_ACL 0x61 /* AC-Link Configuration Register */ 76 #define PCIM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */ 77 #define PCIM_ACL_OMODE 0x02 /* AC 97 codec SDATA_OUT 0:split 1:packed */ 78 #define PCIM_ACL_IMODE 0x01 /* AC 97 codec SDATA_IN 0:split 1:packed */ 79 80 #define PCIR_I2S 0x62 /* I2S Converters Features Register */ 81 #define PCIM_I2S_VOL 0x80 /* I2S codec Volume and mute */ 82 #define PCIM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */ 83 #define PCIM_I2S_RES 0x30 /* Converter resolution */ 84 #define PCIM_I2S_16BIT 0x00 /* 16bit */ 85 #define PCIM_I2S_18BIT 0x10 /* 18bit */ 86 #define PCIM_I2S_20BIT 0x20 /* 20bit */ 87 #define PCIM_I2S_24BIT 0x30 /* 24bit */ 88 #define PCIM_I2S_ID 0x0f /* Other I2S IDs */ 89 90 #define PCIR_SPDIF 0x63 /* S/PDIF Configuration Register */ 91 #define PCIM_SPDIF_ID 0xfc /* S/PDIF chip ID */ 92 #define PCIM_SPDIF_IN 0x02 /* S/PDIF Stereo In is present */ 93 #define PCIM_SPDIF_OUT 0x01 /* S/PDIF Stereo Out is present */ 94 95 #define PCIR_POWER_STAT 0x84 /* Power Management Control and Status */ 96 97 /* Controller Registers */ 98 99 #define ENVY24_CCS_CTL 0x00 /* Control/Status Register */ 100 #define ENVY24_CCS_CTL_RESET 0x80 /* Entire Chip soft reset */ 101 #define ENVY24_CCS_CTL_DMAINT 0x40 /* DS DMA Channel-C interrupt */ 102 #define ENVY24_CCS_CTL_DOSVOL 0x10 /* set the DOS WT volume control */ 103 #define ENVY24_CCS_CTL_EDGE 0x08 /* SERR# edge (only one PCI clock width) */ 104 #define ENVY24_CCS_CTL_SBINT 0x02 /* SERR# assertion for SB interrupt */ 105 #define ENVY24_CCS_CTL_NATIVE 0x01 /* Mode select: 0:SB mode 1:native mode */ 106 107 #define ENVY24_CCS_IMASK 0x01 /* Interrupt Mask Register */ 108 #define ENVY24_CCS_IMASK_PMIDI 0x80 /* Primary MIDI */ 109 #define ENVY24_CCS_IMASK_TIMER 0x40 /* Timer */ 110 #define ENVY24_CCS_IMASK_SMIDI 0x20 /* Secondary MIDI */ 111 #define ENVY24_CCS_IMASK_PMT 0x10 /* Professional Multi-track */ 112 #define ENVY24_CCS_IMASK_FM 0x08 /* FM/MIDI trapping */ 113 #define ENVY24_CCS_IMASK_PDMA 0x04 /* Playback DS DMA */ 114 #define ENVY24_CCS_IMASK_RDMA 0x02 /* Consumer record DMA */ 115 #define ENVY24_CCS_IMASK_SB 0x01 /* Consumer/SB mode playback */ 116 117 #define ENVY24_CCS_ISTAT 0x02 /* Interrupt Status Register */ 118 #define ENVY24_CCS_ISTAT_PMIDI 0x80 /* Primary MIDI */ 119 #define ENVY24_CCS_ISTAT_TIMER 0x40 /* Timer */ 120 #define ENVY24_CCS_ISTAT_SMIDI 0x20 /* Secondary MIDI */ 121 #define ENVY24_CCS_ISTAT_PMT 0x10 /* Professional Multi-track */ 122 #define ENVY24_CCS_ISTAT_FM 0x08 /* FM/MIDI trapping */ 123 #define ENVY24_CCS_ISTAT_PDMA 0x04 /* Playback DS DMA */ 124 #define ENVY24_CCS_ISTAT_RDMA 0x02 /* Consumer record DMA */ 125 #define ENVY24_CCS_ISTAT_SB 0x01 /* Consumer/SB mode playback */ 126 127 #define ENVY24_CCS_INDEX 0x03 /* Envy24 Index Register */ 128 #define ENVY24_CCS_DATA 0x04 /* Envy24 Data Register */ 129 130 #define ENVY24_CCS_NMI1 0x05 /* NMI Status Register 1 */ 131 #define ENVY24_CCS_NMI1_PCI 0x80 /* PCI I/O read/write cycle */ 132 #define ENVY24_CCS_NMI1_SB 0x40 /* SB 22C/24C write */ 133 #define ENVY24_CCS_NMI1_SBDMA 0x10 /* SB interrupt (SB DMA/SB F2 command) */ 134 #define ENVY24_CCS_NMI1_DSDMA 0x08 /* DS channel C DMA interrupt */ 135 #define ENVY24_CCS_NMI1_MIDI 0x04 /* MIDI 330h or [PCI_10]h+Ch write */ 136 #define ENVY24_CCS_NMI1_FM 0x01 /* FM data register write */ 137 138 #define ENVY24_CCS_NMIDAT 0x06 /* NMI Data Register */ 139 #define ENVY24_CCS_NMIIDX 0x07 /* NMI Index Register */ 140 #define ENVY24_CCS_AC97IDX 0x08 /* Consumer AC'97 Index Register */ 141 142 #define ENVY24_CCS_AC97CMD 0x09 /* Consumer AC'97 Command/Status Register */ 143 #define ENVY24_CCS_AC97CMD_COLD 0x80 /* Cold reset */ 144 #define ENVY24_CCS_AC97CMD_WARM 0x40 /* Warm reset */ 145 #define ENVY24_CCS_AC97CMD_WRCODEC 0x20 /* Write to AC'97 codec registers */ 146 #define ENVY24_CCS_AC97CMD_RDCODEC 0x10 /* Read from AC'97 codec registers */ 147 #define ENVY24_CCS_AC97CMD_READY 0x08 /* AC'97 codec ready status bit */ 148 #define ENVY24_CCS_AC97CMD_PVSR 0x02 /* VSR for Playback */ 149 #define ENVY24_CCS_AC97CMD_RVSR 0x01 /* VSR for Record */ 150 151 #define ENVY24_CCS_AC97DAT 0x0a /* Consumer AC'97 Data Port Register */ 152 #define ENVY24_CCS_PMIDIDAT 0x0c /* Primary MIDI UART Data Register */ 153 #define ENVY24_CCS_PMIDICMD 0x0d /* Primary MIDI UART Command/Status Register */ 154 155 #define ENVY24_CCS_NMI2 0x0e /* NMI Status Register 2 */ 156 #define ENVY24_CCS_NMI2_FMBANK 0x30 /* FM bank indicator */ 157 #define ENVY24_CCS_NMI2_FM0 0x10 /* FM bank 0 (388h/220h/228h) */ 158 #define ENVY24_CCS_NMI2_FM1 0x20 /* FM bank 1 (38ah/222h) */ 159 #define ENVY24_CCS_NMI2_PICIO 0x0f /* PIC I/O cycle */ 160 #define ENVY24_CCS_NMI2_PIC20W 0x01 /* 20h write */ 161 #define ENVY24_CCS_NMI2_PICA0W 0x02 /* a0h write */ 162 #define ENVY24_CCS_NMI2_PIC21W 0x05 /* 21h write */ 163 #define ENVY24_CCS_NMI2_PICA1W 0x06 /* a1h write */ 164 #define ENVY24_CCS_NMI2_PIC20R 0x09 /* 20h read */ 165 #define ENVY24_CCS_NMI2_PICA0R 0x0a /* a0h read */ 166 #define ENVY24_CCS_NMI2_PIC21R 0x0d /* 21h read */ 167 #define ENVY24_CCS_NMI2_PICA1R 0x0e /* a1h read */ 168 169 #define ENVY24_CCS_JOY 0x0f /* Game port register */ 170 171 #define ENVY24_CCS_I2CDEV 0x10 /* I2C Port Device Address Register */ 172 #define ENVY24_CCS_I2CDEV_ADDR 0xfe /* I2C device address */ 173 #define ENVY24_CCS_I2CDEV_ROM 0xa0 /* reserved for the external I2C E2PROM */ 174 #define ENVY24_CCS_I2CDEV_WR 0x01 /* write */ 175 #define ENVY24_CCS_I2CDEV_RD 0x00 /* read */ 176 177 #define ENVY24_CCS_I2CADDR 0x11 /* I2C Port Byte Address Register */ 178 #define ENVY24_CCS_I2CDATA 0x12 /* I2C Port Read/Write Data Register */ 179 180 #define ENVY24_CCS_I2CSTAT 0x13 /* I2C Port Control and Status Register */ 181 #define ENVY24_CCS_I2CSTAT_ROM 0x80 /* external E2PROM exists */ 182 #define ENVY24_CCS_I2CSTAT_BSY 0x01 /* I2C port read/write status busy */ 183 184 #define ENVY24_CCS_CDMABASE 0x14 /* Consumer Record DMA Current/Base Address Register */ 185 #define ENVY24_CCS_CDMACNT 0x18 /* Consumer Record DMA Current/Base Count Register */ 186 #define ENVY24_CCS_SERR 0x1b /* PCI Configuration SERR# Shadow Register */ 187 #define ENVY24_CCS_SMIDIDAT 0x1c /* Secondary MIDI UART Data Register */ 188 #define ENVY24_CCS_SMIDICMD 0x1d /* Secondary MIDI UART Command/Status Register */ 189 190 #define ENVY24_CCS_TIMER 0x1e /* Timer Register */ 191 #define ENVY24_CCS_TIMER_EN 0x8000 /* Timer count enable */ 192 #define ENVY24_CCS_TIMER_MASK 0x7fff /* Timer counter mask */ 193 194 /* Controller Indexed Registers */ 195 196 #define ENVY24_CCI_PTCHIGH 0x00 /* Playback Terminal Count Register (High Byte) */ 197 #define ENVY24_CCI_PTCLOW 0x01 /* Playback Terminal Count Register (Low Byte) */ 198 199 #define ENVY24_CCI_PCTL 0x02 /* Playback Control Register */ 200 #define ENVY24_CCI_PCTL_TURBO 0x80 /* 4x up sampling in the host by software */ 201 #define ENVY24_CCI_PCTL_U8 0x10 /* 8 bits unsigned */ 202 #define ENVY24_CCI_PCTL_S16 0x00 /* 16 bits signed */ 203 #define ENVY24_CCI_PCTL_STEREO 0x08 /* stereo */ 204 #define ENVY24_CCI_PCTL_MONO 0x00 /* mono */ 205 #define ENVY24_CCI_PCTL_FLUSH 0x04 /* FIFO flush (sticky bit. Requires toggling) */ 206 #define ENVY24_CCI_PCTL_PAUSE 0x02 /* Pause */ 207 #define ENVY24_CCI_PCTL_ENABLE 0x01 /* Playback enable */ 208 209 #define ENVY24_CCI_PLVOL 0x03 /* Playback Left Volume/Pan Register */ 210 #define ENVY24_CCI_PRVOL 0x04 /* Playback Right Volume/Pan Register */ 211 #define ENVY24_CCI_VOL_MASK 0x3f /* Volume value mask */ 212 213 #define ENVY24_CCI_SOFTVOL 0x05 /* Soft Volume/Mute Control Register */ 214 #define ENVY24_CCI_PSRLOW 0x06 /* Playback Sampling Rate Register (Low Byte) */ 215 #define ENVY24_CCI_PSRMID 0x07 /* Playback Sampling Rate Register (Middle Byte) */ 216 #define ENVY24_CCI_PSRHIGH 0x08 /* Playback Sampling Rate Register (High Byte) */ 217 #define ENVY24_CCI_RTCHIGH 0x10 /* Record Terminal Count Register (High Byte) */ 218 #define ENVY24_CCI_RTCLOW 0x11 /* Record Terminal Count Register (Low Byte) */ 219 220 #define ENVY24_CCI_RCTL 0x12 /* Record Control Register */ 221 #define ENVY24_CCI_RCTL_DRTN 0x80 /* Digital return enable */ 222 #define ENVY24_CCI_RCTL_U8 0x04 /* 8 bits unsigned */ 223 #define ENVY24_CCI_RCTL_S16 0x00 /* 16 bits signed */ 224 #define ENVY24_CCI_RCTL_STEREO 0x00 /* stereo */ 225 #define ENVY24_CCI_RCTL_MONO 0x02 /* mono */ 226 #define ENVY24_CCI_RCTL_ENABLE 0x01 /* Record enable */ 227 228 #define ENVY24_CCI_GPIODAT 0x20 /* GPIO Data Register */ 229 #define ENVY24_CCI_GPIOMASK 0x21 /* GPIO Write Mask Register */ 230 231 #define ENVY24_CCI_GPIOCTL 0x22 /* GPIO Direction Control Register */ 232 #define ENVY24_CCI_GPIO_OUT 1 /* output */ 233 #define ENVY24_CCI_GPIO_IN 0 /* input */ 234 235 #define ENVY24_CCI_CPDWN 0x30 /* Consumer Section Power Down Register */ 236 #define ENVY24_CCI_CPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_1 */ 237 #define ENVY24_CCI_CPDWN_GAME 0x40 /* Game port analog power down */ 238 #define ENVY24_CCI_CPDWN_I2C 0x10 /* I2C port clock */ 239 #define ENVY24_CCI_CPDWN_MIDI 0x08 /* MIDI clock */ 240 #define ENVY24_CCI_CPDWN_AC97 0x04 /* AC'97 clock */ 241 #define ENVY24_CCI_CPDWN_DS 0x02 /* DS Block clock */ 242 #define ENVY24_CCI_CPDWN_PCI 0x01 /* PCI clock for SB, DMA controller */ 243 244 #define ENVY24_CCI_MTPDWN 0x31 /* Multi-Track Section Power Down Register */ 245 #define ENVY24_CCI_MTPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_2 */ 246 #define ENVY24_CCI_MTPDWN_SPDIF 0x04 /* S/PDIF clock */ 247 #define ENVY24_CCI_MTPDWN_MIX 0x02 /* Professional digital mixer clock */ 248 #define ENVY24_CCI_MTPDWN_I2S 0x01 /* Multi-track I2S serial interface clock */ 249 250 /* DDMA Registers */ 251 252 #define ENVY24_DDMA_ADDR0 0x00 /* DMA Base and Current Address bit 0-7 */ 253 #define ENVY24_DDMA_ADDR8 0x01 /* DMA Base and Current Address bit 8-15 */ 254 #define ENVY24_DDMA_ADDR16 0x02 /* DMA Base and Current Address bit 16-23 */ 255 #define ENVY24_DDMA_ADDR24 0x03 /* DMA Base and Current Address bit 24-31 */ 256 #define ENVY24_DDMA_CNT0 0x04 /* DMA Base and Current Count 0-7 */ 257 #define ENVY24_DDMA_CNT8 0x05 /* DMA Base and Current Count 8-15 */ 258 #define ENVY24_DDMA_CNT16 0x06 /* (not supported) */ 259 #define ENVY24_DDMA_CMD 0x08 /* Status and Command */ 260 #define ENVY24_DDMA_MODE 0x0b /* Mode */ 261 #define ENVY24_DDMA_RESET 0x0c /* Master reset */ 262 #define ENVY24_DDMA_CHAN 0x0f /* Channel Mask */ 263 264 /* Consumer Section DMA Channel Registers */ 265 266 #define ENVY24_CS_INTMASK 0x00 /* DirectSound DMA Interrupt Mask Register */ 267 #define ENVY24_CS_INTSTAT 0x02 /* DirectSound DMA Interrupt Status Register */ 268 #define ENVY24_CS_CHDAT 0x04 /* Channel Data register */ 269 270 #define ENVY24_CS_CHIDX 0x08 /* Channel Index Register */ 271 #define ENVY24_CS_CHIDX_NUM 0xf0 /* Channel number */ 272 #define ENVY24_CS_CHIDX_ADDR0 0x00 /* Buffer_0 DMA base address */ 273 #define ENVY24_CS_CHIDX_CNT0 0x01 /* Buffer_0 DMA base count */ 274 #define ENVY24_CS_CHIDX_ADDR1 0x02 /* Buffer_1 DMA base address */ 275 #define ENVY24_CS_CHIDX_CNT1 0x03 /* Buffer_1 DMA base count */ 276 #define ENVY24_CS_CHIDX_CTL 0x04 /* Channel Control and Status register */ 277 #define ENVY24_CS_CHIDX_RATE 0x05 /* Channel Sampling Rate */ 278 #define ENVY24_CS_CHIDX_VOL 0x06 /* Channel left and right volume/pan control */ 279 /* Channel Control and Status Register at Index 4h */ 280 #define ENVY24_CS_CTL_BUF 0x80 /* indicating that the current active buffer */ 281 #define ENVY24_CS_CTL_AUTO1 0x40 /* Buffer_1 auto init. enable */ 282 #define ENVY24_CS_CTL_AUTO0 0x20 /* Buffer_0 auto init. enable */ 283 #define ENVY24_CS_CTL_FLUSH 0x10 /* Flush FIFO */ 284 #define ENVY24_CS_CTL_STEREO 0x08 /* stereo(or mono) */ 285 #define ENVY24_CS_CTL_U8 0x04 /* 8-bit unsigned(or 16-bit signed) */ 286 #define ENVY24_CS_CTL_PAUSE 0x02 /* DMA request 1:pause */ 287 #define ENVY24_CS_CTL_START 0x01 /* DMA request 1: start, 0:stop */ 288 /* Consumer mode Left/Right Volume Register at Index 06h */ 289 #define ENVY24_CS_VOL_RIGHT 0x3f00 290 #define ENVY24_CS_VOL_LEFT 0x003f 291 292 /* Professional Multi-Track Control Registers */ 293 294 #define ENVY24_MT_INT 0x00 /* DMA Interrupt Mask and Status Register */ 295 #define ENVY24_MT_INT_RMASK 0x80 /* Multi-track record interrupt mask */ 296 #define ENVY24_MT_INT_PMASK 0x40 /* Multi-track playback interrupt mask */ 297 #define ENVY24_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */ 298 #define ENVY24_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */ 299 300 #define ENVY24_MT_RATE 0x01 /* Sampling Rate Select Register */ 301 #define ENVY24_MT_RATE_SPDIF 0x10 /* S/PDIF input clock as the master */ 302 #define ENVY24_MT_RATE_48000 0x00 303 #define ENVY24_MT_RATE_24000 0x01 304 #define ENVY24_MT_RATE_12000 0x02 305 #define ENVY24_MT_RATE_9600 0x03 306 #define ENVY24_MT_RATE_32000 0x04 307 #define ENVY24_MT_RATE_16000 0x05 308 #define ENVY24_MT_RATE_8000 0x06 309 #define ENVY24_MT_RATE_96000 0x07 310 #define ENVY24_MT_RATE_64000 0x0f 311 #define ENVY24_MT_RATE_44100 0x08 312 #define ENVY24_MT_RATE_22050 0x09 313 #define ENVY24_MT_RATE_11025 0x0a 314 #define ENVY24_MT_RATE_88200 0x0b 315 #define ENVY24_MT_RATE_MASK 0x0f 316 317 #define ENVY24_MT_I2S 0x02 /* I2S Data Format Register */ 318 #define ENVY24_MT_I2S_MLR128 0x08 /* MCLK/LRCLK ratio 128x(or 256x) */ 319 #define ENVY24_MT_I2S_SLR48 0x04 /* SCLK/LRCLK ratio 48bpf(or 64bpf) */ 320 #define ENVY24_MT_I2S_FORM 0x00 /* I2S data format */ 321 322 #define ENVY24_MT_AC97IDX 0x04 /* Index Register for AC'97 Codecs */ 323 324 #define ENVY24_MT_AC97CMD 0x05 /* Command and Status Register for AC'97 Codecs */ 325 #define ENVY24_MT_AC97CMD_CLD 0x80 /* Cold reset */ 326 #define ENVY24_MT_AC97CMD_WRM 0x40 /* Warm reset */ 327 #define ENVY24_MT_AC97CMD_WR 0x20 /* write to AC'97 codec register */ 328 #define ENVY24_MT_AC97CMD_RD 0x10 /* read AC'97 CODEC register */ 329 #define ENVY24_MT_AC97CMD_RDY 0x08 /* AC'97 codec ready status bit */ 330 #define ENVY24_MT_AC97CMD_ID 0x03 /* ID(0-3) for external AC 97 registers */ 331 332 #define ENVY24_MT_AC97DLO 0x06 /* AC'97 codec register data low byte */ 333 #define ENVY24_MT_AC97DHI 0x07 /* AC'97 codec register data high byte */ 334 #define ENVY24_MT_PADDR 0x10 /* Playback DMA Current/Base Address Register */ 335 #define ENVY24_MT_PCNT 0x14 /* Playback DMA Current/Base Count Register */ 336 #define ENVY24_MT_PTERM 0x16 /* Playback Current/Base Terminal Count Register */ 337 #define ENVY24_MT_PCTL 0x18 /* Playback and Record Control Register */ 338 #define ENVY24_MT_PCTL_RSTART 0x04 /* 1: Record start; 0: Record stop */ 339 #define ENVY24_MT_PCTL_PAUSE 0x02 /* 1: Pause; 0: Resume */ 340 #define ENVY24_MT_PCTL_PSTART 0x01 /* 1: Playback start; 0: Playback stop */ 341 342 #define ENVY24_MT_RADDR 0x20 /* Record DMA Current/Base Address Register */ 343 #define ENVY24_MT_RCNT 0x24 /* Record DMA Current/Base Count Register */ 344 #define ENVY24_MT_RTERM 0x26 /* Record Current/Base Terminal Count Register */ 345 #define ENVY24_MT_RCTL 0x28 /* Record Control Register */ 346 #define ENVY24_MT_RCTL_RSTART 0x01 /* 1: Record start; 0: Record stop */ 347 348 #define ENVY24_MT_PSDOUT 0x30 /* Routing Control Register for Data to PSDOUT[0:3] */ 349 #define ENVY24_MT_SPDOUT 0x32 /* Routing Control Register for SPDOUT */ 350 #define ENVY24_MT_RECORD 0x34 /* Captured (Recorded) data Routing Selection Register */ 351 352 #define BUS_SPACE_MAXADDR_ENVY24 0x0fffffff /* Address space beyond 256MB is not supported */ 353 #define BUS_SPACE_MAXSIZE_ENVY24 0x3fffc /* 64k x 4byte(1dword) */ 354 355 #define ENVY24_MT_VOLUME 0x38 /* Left/Right Volume Control Data Register */ 356 #define ENVY24_MT_VOLUME_L 0x007f /* Left Volume Mask */ 357 #define ENVY24_MT_VOLUME_R 0x7f00 /* Right Volume Mask */ 358 359 #define ENVY24_MT_VOLIDX 0x3a /* Volume Control Stream Index Register */ 360 #define ENVY24_MT_VOLRATE 0x3b /* Volume Control Rate Register */ 361 #define ENVY24_MT_MONAC97 0x3c /* Digital Mixer Monitor Routing Control Register */ 362 #define ENVY24_MT_PEAKIDX 0x3e /* Peak Meter Index Register */ 363 #define ENVY24_MT_PEAKDAT 0x3f /* Peak Meter Data Register */ 364 365 /* -------------------------------------------------------------------- */ 366 367 /* ENVY24 mixer channel defines */ 368 /* 369 ENVY24 mixer has original line matrix. So, general mixer command is not 370 able to use for this. If system has consumer AC'97 output, AC'97 line is 371 used as master mixer, and it is able to control. 372 */ 373 #define ENVY24_CHAN_NUM 11 /* Play * 5 + Record * 5 + Mix * 1 */ 374 375 #define ENVY24_CHAN_PLAY_DAC1 0 376 #define ENVY24_CHAN_PLAY_DAC2 1 377 #define ENVY24_CHAN_PLAY_DAC3 2 378 #define ENVY24_CHAN_PLAY_DAC4 3 379 #define ENVY24_CHAN_PLAY_SPDIF 4 380 #define ENVY24_CHAN_REC_ADC1 5 381 #define ENVY24_CHAN_REC_ADC2 6 382 #define ENVY24_CHAN_REC_ADC3 7 383 #define ENVY24_CHAN_REC_ADC4 8 384 #define ENVY24_CHAN_REC_SPDIF 9 385 #define ENVY24_CHAN_REC_MIX 10 386 387 #define ENVY24_MIX_MASK 0x3ff 388 #define ENVY24_MIX_REC_MASK 0x3e0 389 390 /* volume value constants */ 391 #define ENVY24_VOL_MAX 0 /* 0db(negate) */ 392 #define ENVY24_VOL_MIN 96 /* -144db(negate) */ 393 #define ENVY24_VOL_MUTE 127 /* mute */ 394 395 /* -------------------------------------------------------------------- */ 396 397 /* ENVY24 routing control defines */ 398 /* 399 ENVY24 has input->output data routing matrix switch. But original ENVY24 400 matrix control is so complex. So, in this driver, matrix control is 401 defined 4 parameters. 402 403 1: output DAC channels (include S/PDIF output) 404 2: output data classes 405 a. direct output from DMA 406 b. MIXER output which mixed the DMA outputs and input channels 407 (NOTICE: this class is able to set only DAC-1 and S/PDIF output) 408 c. direct input from ADC 409 d. direct input from S/PDIF 410 3: input ADC channel selection(when 2:c. is selected) 411 4: left/right reverse 412 413 These parameters matrix is bit reduced from original ENVY24 matrix 414 pattern(ex. route different ADC input to one DAC). But almost case 415 this is enough to use. 416 */ 417 #define ENVY24_ROUTE_DAC_1 0 418 #define ENVY24_ROUTE_DAC_2 1 419 #define ENVY24_ROUTE_DAC_3 2 420 #define ENVY24_ROUTE_DAC_4 3 421 #define ENVY24_ROUTE_DAC_SPDIF 4 422 423 #define ENVY24_ROUTE_CLASS_DMA 0 424 #define ENVY24_ROUTE_CLASS_MIX 1 425 #define ENVY24_ROUTE_CLASS_ADC 2 426 #define ENVY24_ROUTE_CLASS_SPDIF 3 427 428 #define ENVY24_ROUTE_ADC_1 0 429 #define ENVY24_ROUTE_ADC_2 1 430 #define ENVY24_ROUTE_ADC_3 2 431 #define ENVY24_ROUTE_ADC_4 3 432 433 #define ENVY24_ROUTE_NORMAL 0 434 #define ENVY24_ROUTE_REVERSE 1 435 #define ENVY24_ROUTE_LEFT 0 436 #define ENVY24_ROUTE_RIGHT 1 437 438 /* -------------------------------------------------------------------- */ 439 440 /* 441 These map values are refferd from ALSA sound driver. 442 */ 443 /* ENVY24 configuration E2PROM map */ 444 #define ENVY24_E2PROM_SUBVENDOR 0x00 445 #define ENVY24_E2PROM_SUBDEVICE 0x02 446 #define ENVY24_E2PROM_SIZE 0x04 447 #define ENVY24_E2PROM_VERSION 0x05 448 #define ENVY24_E2PROM_SCFG 0x06 449 #define ENVY24_E2PROM_ACL 0x07 450 #define ENVY24_E2PROM_I2S 0x08 451 #define ENVY24_E2PROM_SPDIF 0x09 452 #define ENVY24_E2PROM_GPIOMASK 0x0a 453 #define ENVY24_E2PROM_GPIOSTATE 0x0b 454 #define ENVY24_E2PROM_GPIODIR 0x0c 455 #define ENVY24_E2PROM_AC97MAIN 0x0d 456 #define ENVY24_E2PROM_AC97PCM 0x0f 457 #define ENVY24_E2PROM_AC97REC 0x11 458 #define ENVY24_E2PROM_AC97RECSRC 0x13 459 #define ENVY24_E2PROM_DACID 0x14 460 #define ENVY24_E2PROM_ADCID 0x18 461 #define ENVY24_E2PROM_EXTRA 0x1c 462 463 /* GPIO connect map of M-Audio Delta series */ 464 #define ENVY24_GPIO_CS84X4_PRO 0x01 465 #define ENVY24_GPIO_CS8414_STATUS 0x02 466 #define ENVY24_GPIO_CS84X4_CLK 0x04 467 #define ENVY24_GPIO_CS84X4_DATA 0x08 468 #define ENVY24_GPIO_AK4524_CDTI 0x10 /* this value is duplicated to input select */ 469 #define ENVY24_GPIO_AK4524_CCLK 0x20 470 #define ENVY24_GPIO_AK4524_CS0 0x40 471 #define ENVY24_GPIO_AK4524_CS1 0x80 472 473 /* M-Audio Delta series S/PDIF(CS84[01]4) control pin values */ 474 #define ENVY24_CS8404_PRO_RATE 0x18 475 #define ENVY24_CS8404_PRO_RATE32 0x00 476 #define ENVY24_CS8404_PRO_RATE441 0x10 477 #define ENVY24_CS8404_PRO_RATE48 0x08 478 479 /* M-Audio Delta series parameter */ 480 #define ENVY24_DELTA_AK4524_CIF 0 481 482 #define I2C_DELAY 1000 483 484 /* PCA9554 registers */ 485 #define PCA9554_I2CDEV 0x40 /* I2C device address */ 486 #define PCA9554_IN 0x00 /* input port */ 487 #define PCA9554_OUT 0x01 /* output port */ 488 #define PCA9554_INVERT 0x02 /* polarity invert */ 489 #define PCA9554_DIR 0x03 /* port directions */ 490 491 /* PCF8574 registers */ 492 #define PCF8574_I2CDEV_DAC 0x48 493 #define PCF8574_SENSE_MASK 0x40 494 495 /* end of file */ 496