1 /*- 2 * Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org> 3 * Copyright (c) 2003 Orlando Bassotto <orlando.bassotto@ieo-research.it> 4 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <dev/sound/pcm/sound.h> 30 #include <dev/sound/pcm/ac97.h> 31 #include <gnu/dev/sound/pci/emu10k1.h> 32 #include "emu10k1-alsa%diked.h" 33 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 #include <sys/queue.h> 37 38 #include <dev/sound/midi/mpu401.h> 39 #include "mpufoi_if.h" 40 41 SND_DECLARE_FILE("$FreeBSD$"); 42 43 /* -------------------------------------------------------------------- */ 44 45 #define NUM_G 64 /* use all channels */ 46 #define WAVEOUT_MAXBUFSIZE 32768 47 #define EMUPAGESIZE 4096 /* don't change */ 48 #define EMUMAXPAGES (WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE) 49 #define EMU10K1_PCI_ID 0x00021102 /* 1102 => Creative Labs Vendor ID */ 50 #define EMU10K2_PCI_ID 0x00041102 51 #define EMU10K3_PCI_ID 0x00081102 52 #define EMU_DEFAULT_BUFSZ 4096 53 #define EMU_MAX_CHANS 8 54 #define EMU_CHANS 4 55 56 #define MAXREQVOICES 8 57 #define RESERVED 0 58 #define NUM_MIDI 16 59 #define NUM_FXSENDS 4 60 61 #define TMEMSIZE 256*1024 62 #define TMEMSIZEREG 4 63 64 #define ENABLE 0xffffffff 65 #define DISABLE 0x00000000 66 #define ENV_ON DCYSUSV_CHANNELENABLE_MASK 67 #define ENV_OFF 0x00 /* XXX: should this be 1? */ 68 69 #define A_IOCFG_GPOUT_A 0x40 /* Analog Output */ 70 #define A_IOCFG_GPOUT_D 0x04 /* Digital Output */ 71 #define A_IOCFG_GPOUT_AD (A_IOCFG_GPOUT_A|A_IOCFG_GPOUT_D) /* A_IOCFG_GPOUT0 */ 72 73 struct emu_memblk { 74 SLIST_ENTRY(emu_memblk) link; 75 void *buf; 76 bus_addr_t buf_addr; 77 u_int32_t pte_start, pte_size; 78 }; 79 80 struct emu_mem { 81 u_int8_t bmap[EMUMAXPAGES / 8]; 82 u_int32_t *ptb_pages; 83 void *silent_page; 84 bus_addr_t silent_page_addr; 85 bus_addr_t ptb_pages_addr; 86 SLIST_HEAD(, emu_memblk) blocks; 87 }; 88 89 struct emu_voice { 90 int vnum; 91 int b16:1, stereo:1, busy:1, running:1, ismaster:1; 92 int speed; 93 int start, end, vol; 94 int fxrt1; /* FX routing */ 95 int fxrt2; /* FX routing (only for audigy) */ 96 u_int32_t buf; 97 struct emu_voice *slave; 98 struct pcm_channel *channel; 99 }; 100 101 struct sc_info; 102 103 /* channel registers */ 104 struct sc_pchinfo { 105 int spd, fmt, blksz, run; 106 struct emu_voice *master, *slave; 107 struct snd_dbuf *buffer; 108 struct pcm_channel *channel; 109 struct sc_info *parent; 110 }; 111 112 struct sc_rchinfo { 113 int spd, fmt, run, blksz, num; 114 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask; 115 struct snd_dbuf *buffer; 116 struct pcm_channel *channel; 117 struct sc_info *parent; 118 }; 119 120 /* device private data */ 121 struct sc_info { 122 device_t dev; 123 u_int32_t type, rev; 124 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1; 125 u_int32_t addrmask; /* wider if audigy */ 126 127 bus_space_tag_t st; 128 bus_space_handle_t sh; 129 bus_dma_tag_t parent_dmat; 130 131 struct resource *reg, *irq; 132 void *ih; 133 struct mtx *lock; 134 135 unsigned int bufsz; 136 int timer, timerinterval; 137 int pnum, rnum; 138 int nchans; 139 struct emu_mem mem; 140 struct emu_voice voice[64]; 141 struct sc_pchinfo pch[EMU_MAX_CHANS]; 142 struct sc_rchinfo rch[3]; 143 struct mpu401 *mpu; 144 mpu401_intr_t *mpu_intr; 145 int mputx; 146 }; 147 148 /* -------------------------------------------------------------------- */ 149 150 /* 151 * prototypes 152 */ 153 154 /* stuff */ 155 static int emu_init(struct sc_info *); 156 static void emu_intr(void *); 157 static void *emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr); 158 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr); 159 static int emu_memfree(struct sc_info *sc, void *buf); 160 static int emu_memstart(struct sc_info *sc, void *buf); 161 #ifdef EMUDEBUG 162 static void emu_vdump(struct sc_info *sc, struct emu_voice *v); 163 #endif 164 165 /* talk to the card */ 166 static u_int32_t emu_rd(struct sc_info *, int, int); 167 static void emu_wr(struct sc_info *, int, u_int32_t, int); 168 169 /* -------------------------------------------------------------------- */ 170 171 static u_int32_t emu_rfmt_ac97[] = { 172 AFMT_S16_LE, 173 AFMT_STEREO | AFMT_S16_LE, 174 0 175 }; 176 177 static u_int32_t emu_rfmt_mic[] = { 178 AFMT_U8, 179 0 180 }; 181 182 static u_int32_t emu_rfmt_efx[] = { 183 AFMT_STEREO | AFMT_S16_LE, 184 0 185 }; 186 187 static struct pcmchan_caps emu_reccaps[3] = { 188 {8000, 48000, emu_rfmt_ac97, 0}, 189 {8000, 8000, emu_rfmt_mic, 0}, 190 {48000, 48000, emu_rfmt_efx, 0}, 191 }; 192 193 static u_int32_t emu_pfmt[] = { 194 AFMT_U8, 195 AFMT_STEREO | AFMT_U8, 196 AFMT_S16_LE, 197 AFMT_STEREO | AFMT_S16_LE, 198 0 199 }; 200 201 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0}; 202 203 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000}; 204 /* audigy supports 12kHz. */ 205 static int audigy_adcspeed[9] = { 206 48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000 207 }; 208 209 /* -------------------------------------------------------------------- */ 210 /* Hardware */ 211 static u_int32_t 212 emu_rd(struct sc_info *sc, int regno, int size) 213 { 214 switch (size) { 215 case 1: 216 return bus_space_read_1(sc->st, sc->sh, regno); 217 case 2: 218 return bus_space_read_2(sc->st, sc->sh, regno); 219 case 4: 220 return bus_space_read_4(sc->st, sc->sh, regno); 221 default: 222 return 0xffffffff; 223 } 224 } 225 226 static void 227 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 228 { 229 switch (size) { 230 case 1: 231 bus_space_write_1(sc->st, sc->sh, regno, data); 232 break; 233 case 2: 234 bus_space_write_2(sc->st, sc->sh, regno, data); 235 break; 236 case 4: 237 bus_space_write_4(sc->st, sc->sh, regno, data); 238 break; 239 } 240 } 241 242 static u_int32_t 243 emu_rdptr(struct sc_info *sc, int chn, int reg) 244 { 245 u_int32_t ptr, val, mask, size, offset; 246 247 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK); 248 emu_wr(sc, PTR, ptr, 4); 249 val = emu_rd(sc, DATA, 4); 250 if (reg & 0xff000000) { 251 size = (reg >> 24) & 0x3f; 252 offset = (reg >> 16) & 0x1f; 253 mask = ((1 << size) - 1) << offset; 254 val &= mask; 255 val >>= offset; 256 } 257 return val; 258 } 259 260 static void 261 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data) 262 { 263 u_int32_t ptr, mask, size, offset; 264 265 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK); 266 emu_wr(sc, PTR, ptr, 4); 267 if (reg & 0xff000000) { 268 size = (reg >> 24) & 0x3f; 269 offset = (reg >> 16) & 0x1f; 270 mask = ((1 << size) - 1) << offset; 271 data <<= offset; 272 data &= mask; 273 data |= emu_rd(sc, DATA, 4) & ~mask; 274 } 275 emu_wr(sc, DATA, data, 4); 276 } 277 278 static void 279 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data) 280 { 281 pc += sc->audigy ? AUDIGY_CODEBASE : MICROCODEBASE; 282 emu_wrptr(sc, 0, pc, data); 283 } 284 285 /* -------------------------------------------------------------------- */ 286 /* ac97 codec */ 287 /* no locking needed */ 288 289 static int 290 emu_rdcd(kobj_t obj, void *devinfo, int regno) 291 { 292 struct sc_info *sc = (struct sc_info *)devinfo; 293 294 emu_wr(sc, AC97ADDRESS, regno, 1); 295 return emu_rd(sc, AC97DATA, 2); 296 } 297 298 static int 299 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 300 { 301 struct sc_info *sc = (struct sc_info *)devinfo; 302 303 emu_wr(sc, AC97ADDRESS, regno, 1); 304 emu_wr(sc, AC97DATA, data, 2); 305 return 0; 306 } 307 308 static kobj_method_t emu_ac97_methods[] = { 309 KOBJMETHOD(ac97_read, emu_rdcd), 310 KOBJMETHOD(ac97_write, emu_wrcd), 311 { 0, 0 } 312 }; 313 AC97_DECLARE(emu_ac97); 314 315 /* -------------------------------------------------------------------- */ 316 /* stuff */ 317 static int 318 emu_settimer(struct sc_info *sc) 319 { 320 struct sc_pchinfo *pch; 321 struct sc_rchinfo *rch; 322 int i, tmp, rate; 323 324 rate = 0; 325 for (i = 0; i < sc->nchans; i++) { 326 pch = &sc->pch[i]; 327 if (pch->buffer) { 328 tmp = (pch->spd * sndbuf_getbps(pch->buffer)) 329 / pch->blksz; 330 if (tmp > rate) 331 rate = tmp; 332 } 333 } 334 335 for (i = 0; i < 3; i++) { 336 rch = &sc->rch[i]; 337 if (rch->buffer) { 338 tmp = (rch->spd * sndbuf_getbps(rch->buffer)) 339 / rch->blksz; 340 if (tmp > rate) 341 rate = tmp; 342 } 343 } 344 RANGE(rate, 48, 9600); 345 sc->timerinterval = 48000 / rate; 346 emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2); 347 348 return sc->timerinterval; 349 } 350 351 static int 352 emu_enatimer(struct sc_info *sc, int go) 353 { 354 u_int32_t x; 355 if (go) { 356 if (sc->timer++ == 0) { 357 x = emu_rd(sc, INTE, 4); 358 x |= INTE_INTERVALTIMERENB; 359 emu_wr(sc, INTE, x, 4); 360 } 361 } else { 362 sc->timer = 0; 363 x = emu_rd(sc, INTE, 4); 364 x &= ~INTE_INTERVALTIMERENB; 365 emu_wr(sc, INTE, x, 4); 366 } 367 return 0; 368 } 369 370 static void 371 emu_enastop(struct sc_info *sc, char channel, int enable) 372 { 373 int reg = (channel & 0x20) ? SOLEH : SOLEL; 374 channel &= 0x1f; 375 reg |= 1 << 24; 376 reg |= channel << 16; 377 emu_wrptr(sc, 0, reg, enable); 378 } 379 380 static int 381 emu_recval(int speed) { 382 int val; 383 384 val = 0; 385 while (val < 7 && speed < adcspeed[val]) 386 val++; 387 return val; 388 } 389 390 static int 391 audigy_recval(int speed) { 392 int val; 393 394 val = 0; 395 while (val < 8 && speed < audigy_adcspeed[val]) 396 val++; 397 return val; 398 } 399 400 static u_int32_t 401 emu_rate_to_pitch(u_int32_t rate) 402 { 403 static u_int32_t logMagTable[128] = { 404 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2, 405 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5, 406 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081, 407 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191, 408 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7, 409 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829, 410 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e, 411 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26, 412 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d, 413 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885, 414 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899, 415 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c, 416 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3, 417 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3, 418 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83, 419 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df 420 }; 421 static char logSlopeTable[128] = { 422 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58, 423 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53, 424 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f, 425 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b, 426 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47, 427 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44, 428 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41, 429 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e, 430 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c, 431 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 432 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37, 433 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35, 434 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34, 435 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32, 436 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30, 437 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f 438 }; 439 int i; 440 441 if (rate == 0) 442 return 0; /* Bail out if no leading "1" */ 443 rate *= 11185; /* Scale 48000 to 0x20002380 */ 444 for (i = 31; i > 0; i--) { 445 if (rate & 0x80000000) { /* Detect leading "1" */ 446 return (((u_int32_t) (i - 15) << 20) + 447 logMagTable[0x7f & (rate >> 24)] + 448 (0x7f & (rate >> 17)) * 449 logSlopeTable[0x7f & (rate >> 24)]); 450 } 451 rate <<= 1; 452 } 453 454 return 0; /* Should never reach this point */ 455 } 456 457 static u_int32_t 458 emu_rate_to_linearpitch(u_int32_t rate) 459 { 460 rate = (rate << 8) / 375; 461 return (rate >> 1) + (rate & 1); 462 } 463 464 static struct emu_voice * 465 emu_valloc(struct sc_info *sc) 466 { 467 struct emu_voice *v; 468 int i; 469 470 v = NULL; 471 for (i = 0; i < 64 && sc->voice[i].busy; i++); 472 if (i < 64) { 473 v = &sc->voice[i]; 474 v->busy = 1; 475 } 476 return v; 477 } 478 479 static int 480 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s, 481 u_int32_t sz, struct snd_dbuf *b) 482 { 483 void *buf; 484 bus_addr_t tmp_addr; 485 486 buf = emu_memalloc(sc, sz, &tmp_addr); 487 if (buf == NULL) 488 return -1; 489 if (b != NULL) 490 sndbuf_setup(b, buf, sz); 491 m->start = emu_memstart(sc, buf) * EMUPAGESIZE; 492 m->end = m->start + sz; 493 m->channel = NULL; 494 m->speed = 0; 495 m->b16 = 0; 496 m->stereo = 0; 497 m->running = 0; 498 m->ismaster = 1; 499 m->vol = 0xff; 500 m->buf = tmp_addr; 501 m->slave = s; 502 if (sc->audigy) { 503 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 8 | 504 FXBUS_PCM_LEFT << 16 | FXBUS_MIDI_REVERB << 24; 505 m->fxrt2 = 0x3f3f3f3f; /* No effects on second route */ 506 } else { 507 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 4 | 508 FXBUS_PCM_LEFT << 8 | FXBUS_MIDI_REVERB << 12; 509 m->fxrt2 = 0; 510 } 511 512 if (s != NULL) { 513 s->start = m->start; 514 s->end = m->end; 515 s->channel = NULL; 516 s->speed = 0; 517 s->b16 = 0; 518 s->stereo = 0; 519 s->running = 0; 520 s->ismaster = 0; 521 s->vol = m->vol; 522 s->buf = m->buf; 523 s->fxrt1 = m->fxrt1; 524 s->fxrt2 = m->fxrt2; 525 s->slave = NULL; 526 } 527 return 0; 528 } 529 530 static void 531 emu_vsetup(struct sc_pchinfo *ch) 532 { 533 struct emu_voice *v = ch->master; 534 535 if (ch->fmt) { 536 v->b16 = (ch->fmt & AFMT_16BIT) ? 1 : 0; 537 v->stereo = (ch->fmt & AFMT_STEREO) ? 1 : 0; 538 if (v->slave != NULL) { 539 v->slave->b16 = v->b16; 540 v->slave->stereo = v->stereo; 541 } 542 } 543 if (ch->spd) { 544 v->speed = ch->spd; 545 if (v->slave != NULL) 546 v->slave->speed = v->speed; 547 } 548 } 549 550 static void 551 emu_vwrite(struct sc_info *sc, struct emu_voice *v) 552 { 553 int s; 554 int l, r, x, y; 555 u_int32_t sa, ea, start, val, silent_page; 556 557 s = (v->stereo ? 1 : 0) + (v->b16 ? 1 : 0); 558 559 sa = v->start >> s; 560 ea = v->end >> s; 561 562 l = r = x = y = v->vol; 563 if (v->stereo) { 564 l = v->ismaster ? l : 0; 565 r = v->ismaster ? 0 : r; 566 } 567 568 emu_wrptr(sc, v->vnum, CPF, v->stereo ? CPF_STEREO_MASK : 0); 569 val = v->stereo ? 28 : 30; 570 val *= v->b16 ? 1 : 2; 571 start = sa + val; 572 573 if (sc->audigy) { 574 emu_wrptr(sc, v->vnum, A_FXRT1, v->fxrt1); 575 emu_wrptr(sc, v->vnum, A_FXRT2, v->fxrt2); 576 emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, 0); 577 } 578 else 579 emu_wrptr(sc, v->vnum, FXRT, v->fxrt1 << 16); 580 581 emu_wrptr(sc, v->vnum, PTRX, (x << 8) | r); 582 emu_wrptr(sc, v->vnum, DSL, ea | (y << 24)); 583 emu_wrptr(sc, v->vnum, PSST, sa | (l << 24)); 584 emu_wrptr(sc, v->vnum, CCCA, start | (v->b16 ? 0 : CCCA_8BITSELECT)); 585 586 emu_wrptr(sc, v->vnum, Z1, 0); 587 emu_wrptr(sc, v->vnum, Z2, 0); 588 589 silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1) 590 | MAP_PTI_MASK; 591 emu_wrptr(sc, v->vnum, MAPA, silent_page); 592 emu_wrptr(sc, v->vnum, MAPB, silent_page); 593 594 emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK); 595 emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK); 596 emu_wrptr(sc, v->vnum, ATKHLDM, 0); 597 emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK); 598 emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000); 599 emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000); 600 emu_wrptr(sc, v->vnum, FMMOD, 0); 601 emu_wrptr(sc, v->vnum, TREMFRQ, 0); 602 emu_wrptr(sc, v->vnum, FM2FRQ2, 0); 603 emu_wrptr(sc, v->vnum, ENVVAL, 0x8000); 604 605 emu_wrptr(sc, v->vnum, ATKHLDV, 606 ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK); 607 emu_wrptr(sc, v->vnum, ENVVOL, 0x8000); 608 609 emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f); 610 emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0); 611 612 if (v->slave != NULL) 613 emu_vwrite(sc, v->slave); 614 } 615 616 static void 617 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go) 618 { 619 u_int32_t pitch_target, initial_pitch; 620 u_int32_t cra, cs, ccis; 621 u_int32_t sample, i; 622 623 if (go) { 624 cra = 64; 625 cs = v->stereo ? 4 : 2; 626 ccis = v->stereo ? 28 : 30; 627 ccis *= v->b16 ? 1 : 2; 628 sample = v->b16 ? 0x00000000 : 0x80808080; 629 630 for (i = 0; i < cs; i++) 631 emu_wrptr(sc, v->vnum, CD0 + i, sample); 632 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0); 633 emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra); 634 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis); 635 636 emu_wrptr(sc, v->vnum, IFATN, 0xff00); 637 emu_wrptr(sc, v->vnum, VTFT, 0xffffffff); 638 emu_wrptr(sc, v->vnum, CVCF, 0xffffffff); 639 emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f); 640 emu_enastop(sc, v->vnum, 0); 641 642 pitch_target = emu_rate_to_linearpitch(v->speed); 643 initial_pitch = emu_rate_to_pitch(v->speed) >> 8; 644 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target); 645 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target); 646 emu_wrptr(sc, v->vnum, IP, initial_pitch); 647 } else { 648 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0); 649 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0); 650 emu_wrptr(sc, v->vnum, IFATN, 0xffff); 651 emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff); 652 emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff); 653 emu_wrptr(sc, v->vnum, IP, 0); 654 emu_enastop(sc, v->vnum, 1); 655 } 656 if (v->slave != NULL) 657 emu_vtrigger(sc, v->slave, go); 658 } 659 660 static int 661 emu_vpos(struct sc_info *sc, struct emu_voice *v) 662 { 663 int s, ptr; 664 665 s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0); 666 ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s; 667 return ptr & ~0x0000001f; 668 } 669 670 #ifdef EMUDEBUG 671 static void 672 emu_vdump(struct sc_info *sc, struct emu_voice *v) 673 { 674 char *regname[] = { 675 "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl", 676 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL, 677 "envvol", "atkhldv", "dcysusv", "lfoval1", 678 "envval", "atkhldm", "dcysusm", "lfoval2", 679 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2", 680 "tempenv" 681 }; 682 char *regname2[] = { 683 "mudata1", "mustat1", "mudata2", "mustat2", 684 "fxwc1", "fxwc2", "spdrate", NULL, NULL, 685 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1", 686 NULL, NULL 687 }; 688 int i, x; 689 690 printf("voice number %d\n", v->vnum); 691 for (i = 0, x = 0; i <= 0x1e; i++) { 692 if (regname[i] == NULL) 693 continue; 694 printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i)); 695 printf("%s", (x == 2) ? "\n" : "\t"); 696 x++; 697 if (x > 2) 698 x = 0; 699 } 700 701 /* Print out audigy extra registers */ 702 if (sc->audigy) { 703 for (i = 0; i <= 0xe; i++) { 704 if (regname2[i] == NULL) 705 continue; 706 printf("%s\t[%08x]", regname2[i], 707 emu_rdptr(sc, v->vnum, i + 0x70)); 708 printf("%s", (x == 2)? "\n" : "\t"); 709 x++; 710 if (x > 2) 711 x = 0; 712 } 713 } 714 printf("\n\n"); 715 } 716 #endif 717 718 /* channel interface */ 719 static void * 720 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 721 struct pcm_channel *c, int dir) 722 { 723 struct sc_info *sc = devinfo; 724 struct sc_pchinfo *ch; 725 void *r; 726 727 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction")); 728 ch = &sc->pch[sc->pnum++]; 729 ch->buffer = b; 730 ch->parent = sc; 731 ch->channel = c; 732 ch->blksz = sc->bufsz / 2; 733 ch->fmt = AFMT_U8; 734 ch->spd = 8000; 735 snd_mtxlock(sc->lock); 736 ch->master = emu_valloc(sc); 737 ch->slave = emu_valloc(sc); 738 snd_mtxunlock(sc->lock); 739 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer)) 740 ? NULL : ch; 741 742 return r; 743 } 744 745 static int 746 emupchan_free(kobj_t obj, void *data) 747 { 748 struct sc_pchinfo *ch = data; 749 struct sc_info *sc = ch->parent; 750 int r; 751 752 snd_mtxlock(sc->lock); 753 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer)); 754 snd_mtxunlock(sc->lock); 755 756 return r; 757 } 758 759 static int 760 emupchan_setformat(kobj_t obj, void *data, u_int32_t format) 761 { 762 struct sc_pchinfo *ch = data; 763 764 ch->fmt = format; 765 return 0; 766 } 767 768 static int 769 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 770 { 771 struct sc_pchinfo *ch = data; 772 773 ch->spd = speed; 774 return ch->spd; 775 } 776 777 static int 778 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 779 { 780 struct sc_pchinfo *ch = data; 781 struct sc_info *sc = ch->parent; 782 int irqrate, blksz; 783 784 ch->blksz = blocksize; 785 snd_mtxlock(sc->lock); 786 emu_settimer(sc); 787 irqrate = 48000 / sc->timerinterval; 788 snd_mtxunlock(sc->lock); 789 blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate; 790 return blocksize; 791 } 792 793 static int 794 emupchan_trigger(kobj_t obj, void *data, int go) 795 { 796 struct sc_pchinfo *ch = data; 797 struct sc_info *sc = ch->parent; 798 799 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 800 return 0; 801 802 snd_mtxlock(sc->lock); 803 if (go == PCMTRIG_START) { 804 emu_vsetup(ch); 805 emu_vwrite(sc, ch->master); 806 emu_settimer(sc); 807 emu_enatimer(sc, 1); 808 #ifdef EMUDEBUG 809 printf("start [%d bit, %s, %d hz]\n", 810 ch->master->b16 ? 16 : 8, 811 ch->master->stereo ? "stereo" : "mono", 812 ch->master->speed); 813 emu_vdump(sc, ch->master); 814 emu_vdump(sc, ch->slave); 815 #endif 816 } 817 ch->run = (go == PCMTRIG_START) ? 1 : 0; 818 emu_vtrigger(sc, ch->master, ch->run); 819 snd_mtxunlock(sc->lock); 820 return 0; 821 } 822 823 static int 824 emupchan_getptr(kobj_t obj, void *data) 825 { 826 struct sc_pchinfo *ch = data; 827 struct sc_info *sc = ch->parent; 828 int r; 829 830 snd_mtxlock(sc->lock); 831 r = emu_vpos(sc, ch->master); 832 snd_mtxunlock(sc->lock); 833 834 return r; 835 } 836 837 static struct pcmchan_caps * 838 emupchan_getcaps(kobj_t obj, void *data) 839 { 840 return &emu_playcaps; 841 } 842 843 static kobj_method_t emupchan_methods[] = { 844 KOBJMETHOD(channel_init, emupchan_init), 845 KOBJMETHOD(channel_free, emupchan_free), 846 KOBJMETHOD(channel_setformat, emupchan_setformat), 847 KOBJMETHOD(channel_setspeed, emupchan_setspeed), 848 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize), 849 KOBJMETHOD(channel_trigger, emupchan_trigger), 850 KOBJMETHOD(channel_getptr, emupchan_getptr), 851 KOBJMETHOD(channel_getcaps, emupchan_getcaps), 852 { 0, 0 } 853 }; 854 CHANNEL_DECLARE(emupchan); 855 856 /* channel interface */ 857 static void * 858 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 859 struct pcm_channel *c, int dir) 860 { 861 struct sc_info *sc = devinfo; 862 struct sc_rchinfo *ch; 863 864 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction")); 865 ch = &sc->rch[sc->rnum]; 866 ch->buffer = b; 867 ch->parent = sc; 868 ch->channel = c; 869 ch->blksz = sc->bufsz / 2; 870 ch->fmt = AFMT_U8; 871 ch->spd = 8000; 872 ch->num = sc->rnum; 873 switch(sc->rnum) { 874 case 0: 875 ch->idxreg = sc->audigy ? A_ADCIDX : ADCIDX; 876 ch->basereg = ADCBA; 877 ch->sizereg = ADCBS; 878 ch->setupreg = ADCCR; 879 ch->irqmask = INTE_ADCBUFENABLE; 880 break; 881 882 case 1: 883 ch->idxreg = FXIDX; 884 ch->basereg = FXBA; 885 ch->sizereg = FXBS; 886 ch->setupreg = FXWC; 887 ch->irqmask = INTE_EFXBUFENABLE; 888 break; 889 890 case 2: 891 ch->idxreg = MICIDX; 892 ch->basereg = MICBA; 893 ch->sizereg = MICBS; 894 ch->setupreg = 0; 895 ch->irqmask = INTE_MICBUFENABLE; 896 break; 897 } 898 sc->rnum++; 899 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) 900 return NULL; 901 else { 902 snd_mtxlock(sc->lock); 903 emu_wrptr(sc, 0, ch->basereg, sndbuf_getbufaddr(ch->buffer)); 904 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */ 905 snd_mtxunlock(sc->lock); 906 return ch; 907 } 908 } 909 910 static int 911 emurchan_setformat(kobj_t obj, void *data, u_int32_t format) 912 { 913 struct sc_rchinfo *ch = data; 914 915 ch->fmt = format; 916 return 0; 917 } 918 919 static int 920 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 921 { 922 struct sc_rchinfo *ch = data; 923 924 if (ch->num == 0) { 925 if (ch->parent->audigy) 926 speed = audigy_adcspeed[audigy_recval(speed)]; 927 else 928 speed = adcspeed[emu_recval(speed)]; 929 } 930 if (ch->num == 1) 931 speed = 48000; 932 if (ch->num == 2) 933 speed = 8000; 934 ch->spd = speed; 935 return ch->spd; 936 } 937 938 static int 939 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 940 { 941 struct sc_rchinfo *ch = data; 942 struct sc_info *sc = ch->parent; 943 int irqrate, blksz; 944 945 ch->blksz = blocksize; 946 snd_mtxlock(sc->lock); 947 emu_settimer(sc); 948 irqrate = 48000 / sc->timerinterval; 949 snd_mtxunlock(sc->lock); 950 blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate; 951 return blocksize; 952 } 953 954 /* semantic note: must start at beginning of buffer */ 955 static int 956 emurchan_trigger(kobj_t obj, void *data, int go) 957 { 958 struct sc_rchinfo *ch = data; 959 struct sc_info *sc = ch->parent; 960 u_int32_t val, sz; 961 962 switch(sc->bufsz) { 963 case 4096: 964 sz = ADCBS_BUFSIZE_4096; 965 break; 966 967 case 8192: 968 sz = ADCBS_BUFSIZE_8192; 969 break; 970 971 case 16384: 972 sz = ADCBS_BUFSIZE_16384; 973 break; 974 975 case 32768: 976 sz = ADCBS_BUFSIZE_32768; 977 break; 978 979 case 65536: 980 sz = ADCBS_BUFSIZE_65536; 981 break; 982 983 default: 984 sz = ADCBS_BUFSIZE_4096; 985 } 986 987 snd_mtxlock(sc->lock); 988 switch(go) { 989 case PCMTRIG_START: 990 ch->run = 1; 991 emu_wrptr(sc, 0, ch->sizereg, sz); 992 if (ch->num == 0) { 993 if (sc->audigy) { 994 val = A_ADCCR_LCHANENABLE; 995 if (ch->fmt & AFMT_STEREO) 996 val |= A_ADCCR_RCHANENABLE; 997 val |= audigy_recval(ch->spd); 998 } else { 999 val = ADCCR_LCHANENABLE; 1000 if (ch->fmt & AFMT_STEREO) 1001 val |= ADCCR_RCHANENABLE; 1002 val |= emu_recval(ch->spd); 1003 } 1004 1005 emu_wrptr(sc, 0, ch->setupreg, 0); 1006 emu_wrptr(sc, 0, ch->setupreg, val); 1007 } 1008 val = emu_rd(sc, INTE, 4); 1009 val |= ch->irqmask; 1010 emu_wr(sc, INTE, val, 4); 1011 break; 1012 1013 case PCMTRIG_STOP: 1014 case PCMTRIG_ABORT: 1015 ch->run = 0; 1016 emu_wrptr(sc, 0, ch->sizereg, 0); 1017 if (ch->setupreg) 1018 emu_wrptr(sc, 0, ch->setupreg, 0); 1019 val = emu_rd(sc, INTE, 4); 1020 val &= ~ch->irqmask; 1021 emu_wr(sc, INTE, val, 4); 1022 break; 1023 1024 case PCMTRIG_EMLDMAWR: 1025 case PCMTRIG_EMLDMARD: 1026 default: 1027 break; 1028 } 1029 snd_mtxunlock(sc->lock); 1030 1031 return 0; 1032 } 1033 1034 static int 1035 emurchan_getptr(kobj_t obj, void *data) 1036 { 1037 struct sc_rchinfo *ch = data; 1038 struct sc_info *sc = ch->parent; 1039 int r; 1040 1041 snd_mtxlock(sc->lock); 1042 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff; 1043 snd_mtxunlock(sc->lock); 1044 1045 return r; 1046 } 1047 1048 static struct pcmchan_caps * 1049 emurchan_getcaps(kobj_t obj, void *data) 1050 { 1051 struct sc_rchinfo *ch = data; 1052 1053 return &emu_reccaps[ch->num]; 1054 } 1055 1056 static kobj_method_t emurchan_methods[] = { 1057 KOBJMETHOD(channel_init, emurchan_init), 1058 KOBJMETHOD(channel_setformat, emurchan_setformat), 1059 KOBJMETHOD(channel_setspeed, emurchan_setspeed), 1060 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize), 1061 KOBJMETHOD(channel_trigger, emurchan_trigger), 1062 KOBJMETHOD(channel_getptr, emurchan_getptr), 1063 KOBJMETHOD(channel_getcaps, emurchan_getcaps), 1064 { 0, 0 } 1065 }; 1066 CHANNEL_DECLARE(emurchan); 1067 1068 static unsigned char 1069 emu_mread(void *arg, struct sc_info *sc, int reg) 1070 { 1071 unsigned int d; 1072 1073 d = emu_rd(sc, 0x18 + reg, 1); 1074 return d; 1075 } 1076 1077 static void 1078 emu_mwrite(void *arg, struct sc_info *sc, int reg, unsigned char b) 1079 { 1080 1081 emu_wr(sc, 0x18 + reg, b, 1); 1082 } 1083 1084 static int 1085 emu_muninit(void *arg, struct sc_info *sc) 1086 { 1087 1088 snd_mtxlock(sc->lock); 1089 sc->mpu_intr = 0; 1090 snd_mtxunlock(sc->lock); 1091 1092 return 0; 1093 } 1094 1095 static kobj_method_t emu_mpu_methods[] = { 1096 KOBJMETHOD(mpufoi_read, emu_mread), 1097 KOBJMETHOD(mpufoi_write, emu_mwrite), 1098 KOBJMETHOD(mpufoi_uninit, emu_muninit), 1099 { 0, 0 } 1100 }; 1101 1102 DEFINE_CLASS(emu_mpu, emu_mpu_methods, 0); 1103 1104 static void 1105 emu_intr2(void *p) 1106 { 1107 struct sc_info *sc = (struct sc_info *)p; 1108 1109 if (sc->mpu_intr) 1110 (sc->mpu_intr)(sc->mpu); 1111 } 1112 1113 static void 1114 emu_midiattach(struct sc_info *sc) 1115 { 1116 int i; 1117 1118 i = emu_rd(sc, INTE, 4); 1119 i |= INTE_MIDIRXENABLE; 1120 emu_wr(sc, INTE, i, 4); 1121 1122 sc->mpu = mpu401_init(&emu_mpu_class, sc, emu_intr2, &sc->mpu_intr); 1123 } 1124 /* -------------------------------------------------------------------- */ 1125 /* The interrupt handler */ 1126 1127 static void 1128 emu_intr(void *data) 1129 { 1130 struct sc_info *sc = data; 1131 u_int32_t stat, ack, i, x; 1132 1133 snd_mtxlock(sc->lock); 1134 while (1) { 1135 stat = emu_rd(sc, IPR, 4); 1136 if (stat == 0) 1137 break; 1138 ack = 0; 1139 1140 /* process irq */ 1141 if (stat & IPR_INTERVALTIMER) 1142 ack |= IPR_INTERVALTIMER; 1143 1144 if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) 1145 ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL); 1146 1147 if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) 1148 ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL); 1149 1150 if (stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) 1151 ack |= stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL); 1152 1153 if (stat & IPR_PCIERROR) { 1154 ack |= IPR_PCIERROR; 1155 device_printf(sc->dev, "pci error\n"); 1156 /* we still get an nmi with ecc ram even if we ack this */ 1157 } 1158 if (stat & IPR_SAMPLERATETRACKER) { 1159 ack |= IPR_SAMPLERATETRACKER; 1160 #ifdef EMUDEBUG 1161 device_printf(sc->dev, 1162 "sample rate tracker lock status change\n"); 1163 #endif 1164 } 1165 1166 if (stat & IPR_MIDIRECVBUFEMPTY) 1167 if (sc->mpu_intr) { 1168 (sc->mpu_intr)(sc->mpu); 1169 ack |= IPR_MIDIRECVBUFEMPTY | IPR_MIDITRANSBUFEMPTY; 1170 } 1171 if (stat & ~ack) 1172 device_printf(sc->dev, "dodgy irq: %x (harmless)\n", 1173 stat & ~ack); 1174 1175 emu_wr(sc, IPR, stat, 4); 1176 1177 if (ack) { 1178 snd_mtxunlock(sc->lock); 1179 1180 if (ack & IPR_INTERVALTIMER) { 1181 x = 0; 1182 for (i = 0; i < sc->nchans; i++) { 1183 if (sc->pch[i].run) { 1184 x = 1; 1185 chn_intr(sc->pch[i].channel); 1186 } 1187 } 1188 if (x == 0) 1189 emu_enatimer(sc, 0); 1190 } 1191 1192 1193 if (ack & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) { 1194 if (sc->rch[0].channel) 1195 chn_intr(sc->rch[0].channel); 1196 } 1197 if (ack & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) { 1198 if (sc->rch[1].channel) 1199 chn_intr(sc->rch[1].channel); 1200 } 1201 if (ack & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) { 1202 if (sc->rch[2].channel) 1203 chn_intr(sc->rch[2].channel); 1204 } 1205 1206 snd_mtxlock(sc->lock); 1207 } 1208 } 1209 snd_mtxunlock(sc->lock); 1210 } 1211 1212 /* -------------------------------------------------------------------- */ 1213 1214 static void 1215 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1216 { 1217 bus_addr_t *phys = arg; 1218 1219 *phys = error ? 0 : (bus_addr_t)segs->ds_addr; 1220 1221 if (bootverbose) { 1222 printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n", 1223 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len, 1224 nseg, error); 1225 } 1226 } 1227 1228 static void * 1229 emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr) 1230 { 1231 void *buf; 1232 bus_dmamap_t map; 1233 1234 *addr = 0; 1235 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map)) 1236 return NULL; 1237 if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, emu_setmap, addr, 0) 1238 || !*addr) 1239 return NULL; 1240 return buf; 1241 } 1242 1243 static void 1244 emu_free(struct sc_info *sc, void *buf) 1245 { 1246 bus_dmamem_free(sc->parent_dmat, buf, NULL); 1247 } 1248 1249 static void * 1250 emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr) 1251 { 1252 u_int32_t blksz, start, idx, ofs, tmp, found; 1253 struct emu_mem *mem = &sc->mem; 1254 struct emu_memblk *blk; 1255 void *buf; 1256 1257 blksz = sz / EMUPAGESIZE; 1258 if (sz > (blksz * EMUPAGESIZE)) 1259 blksz++; 1260 /* find a free block in the bitmap */ 1261 found = 0; 1262 start = 1; 1263 while (!found && start + blksz < EMUMAXPAGES) { 1264 found = 1; 1265 for (idx = start; idx < start + blksz; idx++) 1266 if (mem->bmap[idx >> 3] & (1 << (idx & 7))) 1267 found = 0; 1268 if (!found) 1269 start++; 1270 } 1271 if (!found) 1272 return NULL; 1273 blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT); 1274 if (blk == NULL) 1275 return NULL; 1276 buf = emu_malloc(sc, sz, &blk->buf_addr); 1277 *addr = blk->buf_addr; 1278 if (buf == NULL) { 1279 free(blk, M_DEVBUF); 1280 return NULL; 1281 } 1282 blk->buf = buf; 1283 blk->pte_start = start; 1284 blk->pte_size = blksz; 1285 #ifdef EMUDEBUG 1286 printf("buf %p, pte_start %d, pte_size %d\n", blk->buf, 1287 blk->pte_start, blk->pte_size); 1288 #endif 1289 ofs = 0; 1290 for (idx = start; idx < start + blksz; idx++) { 1291 mem->bmap[idx >> 3] |= 1 << (idx & 7); 1292 tmp = (u_int32_t)(u_long)((u_int8_t *)blk->buf_addr + ofs); 1293 #ifdef EMUDEBUG 1294 printf("pte[%d] -> %x phys, %x virt\n", idx, tmp, 1295 ((u_int32_t)buf) + ofs); 1296 #endif 1297 mem->ptb_pages[idx] = (tmp << 1) | idx; 1298 ofs += EMUPAGESIZE; 1299 } 1300 SLIST_INSERT_HEAD(&mem->blocks, blk, link); 1301 return buf; 1302 } 1303 1304 static int 1305 emu_memfree(struct sc_info *sc, void *buf) 1306 { 1307 u_int32_t idx, tmp; 1308 struct emu_mem *mem = &sc->mem; 1309 struct emu_memblk *blk, *i; 1310 1311 blk = NULL; 1312 SLIST_FOREACH(i, &mem->blocks, link) { 1313 if (i->buf == buf) 1314 blk = i; 1315 } 1316 if (blk == NULL) 1317 return EINVAL; 1318 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link); 1319 emu_free(sc, buf); 1320 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1321 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) { 1322 mem->bmap[idx >> 3] &= ~(1 << (idx & 7)); 1323 mem->ptb_pages[idx] = tmp | idx; 1324 } 1325 free(blk, M_DEVBUF); 1326 return 0; 1327 } 1328 1329 static int 1330 emu_memstart(struct sc_info *sc, void *buf) 1331 { 1332 struct emu_mem *mem = &sc->mem; 1333 struct emu_memblk *blk, *i; 1334 1335 blk = NULL; 1336 SLIST_FOREACH(i, &mem->blocks, link) { 1337 if (i->buf == buf) 1338 blk = i; 1339 } 1340 if (blk == NULL) 1341 return -EINVAL; 1342 return blk->pte_start; 1343 } 1344 1345 static void 1346 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1347 u_int32_t *pc) 1348 { 1349 emu_wrefx(sc, (*pc) * 2, (x << 10) | y); 1350 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w); 1351 (*pc)++; 1352 } 1353 1354 static void 1355 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1356 u_int32_t *pc) 1357 { 1358 emu_wrefx(sc, (*pc) * 2, (x << 12) | y); 1359 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w); 1360 (*pc)++; 1361 } 1362 1363 static void 1364 audigy_initefx(struct sc_info *sc) 1365 { 1366 int i; 1367 u_int32_t pc = 0; 1368 1369 /* skip 0, 0, -1, 0 - NOPs */ 1370 for (i = 0; i < 512; i++) 1371 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc); 1372 1373 for (i = 0; i < 512; i++) 1374 emu_wrptr(sc, 0, A_FXGPREGBASE + i, 0x0); 1375 1376 pc = 16; 1377 1378 /* stop fx processor */ 1379 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP); 1380 1381 /* Audigy 2 (EMU10K2) DSP Registers: 1382 FX Bus 1383 0x000-0x00f : 16 registers (?) 1384 Input 1385 0x040/0x041 : AC97 Codec (l/r) 1386 0x042/0x043 : ADC, S/PDIF (l/r) 1387 0x044/0x045 : Optical S/PDIF in (l/r) 1388 0x046/0x047 : ? 1389 0x048/0x049 : Line/Mic 2 (l/r) 1390 0x04a/0x04b : RCA S/PDIF (l/r) 1391 0x04c/0x04d : Aux 2 (l/r) 1392 Output 1393 0x060/0x061 : Digital Front (l/r) 1394 0x062/0x063 : Digital Center/LFE 1395 0x064/0x065 : AudigyDrive Heaphone (l/r) 1396 0x066/0x067 : Digital Rear (l/r) 1397 0x068/0x069 : Analog Front (l/r) 1398 0x06a/0x06b : Analog Center/LFE 1399 0x06c/0x06d : ? 1400 0x06e/0x06f : Analog Rear (l/r) 1401 0x070/0x071 : AC97 Output (l/r) 1402 0x072/0x073 : ? 1403 0x074/0x075 : ? 1404 0x076/0x077 : ADC Recording Buffer (l/r) 1405 Constants 1406 0x0c0 - 0x0c4 = 0 - 4 1407 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20 1408 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000 1409 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000 1410 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff 1411 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc 1412 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (?) 1413 Temporary Values 1414 0x0d6 : Accumulator (?) 1415 0x0d7 : Condition Register 1416 0x0d8 : Noise source 1417 0x0d9 : Noise source 1418 Tank Memory Data Registers 1419 0x200 - 0x2ff 1420 Tank Memory Address Registers 1421 0x300 - 0x3ff 1422 General Purpose Registers 1423 0x400 - 0x5ff 1424 */ 1425 1426 /* AC97Output[l/r] = FXBus PCM[l/r] */ 1427 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000, 1428 A_C_00000000, A_FXBUS(FXBUS_PCM_LEFT), &pc); 1429 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000, 1430 A_C_00000000, A_FXBUS(FXBUS_PCM_RIGHT), &pc); 1431 1432 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */ 1433 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000, 1434 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_L), &pc); 1435 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000, 1436 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_R), &pc); 1437 1438 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1439 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1), 1440 A_C_40000000, A_GPR(0), &pc); 1441 1442 /* Headphones[l/r] = GPR[0/1] */ 1443 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L), 1444 A_C_00000000, A_C_00000000, A_GPR(0), &pc); 1445 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R), 1446 A_C_00000000, A_C_00000000, A_GPR(1), &pc); 1447 1448 /* Analog Front[l/r] = GPR[0/1] */ 1449 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000, 1450 A_C_00000000, A_GPR(0), &pc); 1451 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000, 1452 A_C_00000000, A_GPR(1), &pc); 1453 1454 /* Digital Front[l/r] = GPR[0/1] */ 1455 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000, 1456 A_C_00000000, A_GPR(0), &pc); 1457 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000, 1458 A_C_00000000, A_GPR(1), &pc); 1459 1460 /* Center and Subwoofer configuration */ 1461 /* Analog Center = GPR[0] + GPR[2] */ 1462 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000, 1463 A_GPR(0), A_GPR(2), &pc); 1464 /* Analog Sub = GPR[1] + GPR[2] */ 1465 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000, 1466 A_GPR(1), A_GPR(2), &pc); 1467 1468 /* Digital Center = GPR[0] + GPR[2] */ 1469 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000, 1470 A_GPR(0), A_GPR(2), &pc); 1471 /* Digital Sub = GPR[1] + GPR[2] */ 1472 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000, 1473 A_GPR(1), A_GPR(2), &pc); 1474 1475 #if 0 1476 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1477 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1478 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1479 A_GPR(16), A_GPR(0), &pc); 1480 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1481 A_GPR(17), A_GPR(1), &pc); 1482 1483 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1484 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1485 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1486 A_GPR(16), A_GPR(0), &pc); 1487 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1488 A_GPR(17), A_GPR(1), &pc); 1489 #else 1490 /* XXX This is just a copy to the channel, since we do not have 1491 * a patch manager, it is useful for have another output enabled. 1492 */ 1493 1494 /* Analog Rear[l/r] = GPR[0/1] */ 1495 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1496 A_C_00000000, A_GPR(0), &pc); 1497 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1498 A_C_00000000, A_GPR(1), &pc); 1499 1500 /* Digital Rear[l/r] = GPR[0/1] */ 1501 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1502 A_C_00000000, A_GPR(0), &pc); 1503 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1504 A_C_00000000, A_GPR(1), &pc); 1505 #endif 1506 1507 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1508 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000, 1509 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc); 1510 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000, 1511 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc); 1512 1513 /* resume normal operations */ 1514 emu_wrptr(sc, 0, A_DBG, 0); 1515 } 1516 1517 static void 1518 emu_initefx(struct sc_info *sc) 1519 { 1520 int i; 1521 u_int32_t pc = 16; 1522 1523 /* acc3 0,0,0,0 - NOPs */ 1524 for (i = 0; i < 512; i++) { 1525 emu_wrefx(sc, i * 2, 0x10040); 1526 emu_wrefx(sc, i * 2 + 1, 0x610040); 1527 } 1528 1529 for (i = 0; i < 256; i++) 1530 emu_wrptr(sc, 0, FXGPREGBASE + i, 0); 1531 1532 /* FX-8010 DSP Registers: 1533 FX Bus 1534 0x000-0x00f : 16 registers 1535 Input 1536 0x010/0x011 : AC97 Codec (l/r) 1537 0x012/0x013 : ADC, S/PDIF (l/r) 1538 0x014/0x015 : Mic(left), Zoom (l/r) 1539 0x016/0x017 : TOS link in (l/r) 1540 0x018/0x019 : Line/Mic 1 (l/r) 1541 0x01a/0x01b : COAX S/PDIF (l/r) 1542 0x01c/0x01d : Line/Mic 2 (l/r) 1543 Output 1544 0x020/0x021 : AC97 Output (l/r) 1545 0x022/0x023 : TOS link out (l/r) 1546 0x024/0x025 : Center/LFE 1547 0x026/0x027 : LiveDrive Headphone (l/r) 1548 0x028/0x029 : Rear Channel (l/r) 1549 0x02a/0x02b : ADC Recording Buffer (l/r) 1550 0x02c : Mic Recording Buffer 1551 0x031/0x032 : Analog Center/LFE 1552 Constants 1553 0x040 - 0x044 = 0 - 4 1554 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20 1555 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000 1556 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000 1557 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff 1558 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc 1559 0x054 = 0x5a7ef9db, 0x055 = 0x00100000 1560 Temporary Values 1561 0x056 : Accumulator 1562 0x057 : Condition Register 1563 0x058 : Noise source 1564 0x059 : Noise source 1565 0x05a : IRQ Register 1566 0x05b : TRAM Delay Base Address Count 1567 General Purpose Registers 1568 0x100 - 0x1ff 1569 Tank Memory Data Registers 1570 0x200 - 0x2ff 1571 Tank Memory Address Registers 1572 0x300 - 0x3ff 1573 */ 1574 1575 /* Routing - this will be configurable in later version */ 1576 1577 /* GPR[0/1] = FX * 4 + SPDIF-in */ 1578 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L), 1579 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc); 1580 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R), 1581 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc); 1582 1583 /* GPR[0/1] += APS-input */ 1584 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000, 1585 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc); 1586 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000, 1587 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc); 1588 1589 /* FrontOut (AC97) = GPR[0/1] */ 1590 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000, 1591 C_00000000, GPR(0), &pc); 1592 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000, 1593 C_00000001, GPR(1), &pc); 1594 1595 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1596 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc); 1597 1598 #if 0 1599 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */ 1600 /* RearVolume = GPR[0x10/0x11] */ 1601 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000, 1602 GPR(16), GPR(0), &pc); 1603 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000, 1604 GPR(17), GPR(1), &pc); 1605 #else 1606 /* XXX This is just a copy to the channel, since we do not have 1607 * a patch manager, it is useful for have another output enabled. 1608 */ 1609 1610 /* Rear[l/r] = GPR[0/1] */ 1611 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000, 1612 C_00000000, GPR(0), &pc); 1613 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000, 1614 C_00000000, GPR(1), &pc); 1615 #endif 1616 1617 /* TOS out[l/r] = GPR[0/1] */ 1618 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000, 1619 C_00000000, GPR(0), &pc); 1620 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000, 1621 C_00000000, GPR(1), &pc); 1622 1623 /* Center and Subwoofer configuration */ 1624 /* Analog Center = GPR[0] + GPR[2] */ 1625 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000, 1626 GPR(0), GPR(2), &pc); 1627 /* Analog Sub = GPR[1] + GPR[2] */ 1628 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000, 1629 GPR(1), GPR(2), &pc); 1630 /* Digital Center = GPR[0] + GPR[2] */ 1631 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_CENTER), C_00000000, 1632 GPR(0), GPR(2), &pc); 1633 /* Digital Sub = GPR[1] + GPR[2] */ 1634 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_LFE), C_00000000, 1635 GPR(1), GPR(2), &pc); 1636 1637 /* Headphones[l/r] = GPR[0/1] */ 1638 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000, 1639 C_00000000, GPR(0), &pc); 1640 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000, 1641 C_00000000, GPR(1), &pc); 1642 1643 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1644 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000, 1645 C_00000000, EXTIN(EXTIN_AC97_L), &pc); 1646 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000, 1647 C_00000000, EXTIN(EXTIN_AC97_R), &pc); 1648 1649 /* resume normal operations */ 1650 emu_wrptr(sc, 0, DBG, 0); 1651 } 1652 1653 /* Probe and attach the card */ 1654 static int 1655 emu_init(struct sc_info *sc) 1656 { 1657 u_int32_t spcs, ch, tmp, i; 1658 1659 if (sc->audigy) { 1660 /* enable additional AC97 slots */ 1661 emu_wrptr(sc, 0, AC97SLOT, AC97SLOT_CNTR | AC97SLOT_LFE); 1662 } 1663 1664 /* disable audio and lock cache */ 1665 emu_wr(sc, HCFG, 1666 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, 1667 4); 1668 1669 /* reset recording buffers */ 1670 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE); 1671 emu_wrptr(sc, 0, MICBA, 0); 1672 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE); 1673 emu_wrptr(sc, 0, FXBA, 0); 1674 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE); 1675 emu_wrptr(sc, 0, ADCBA, 0); 1676 1677 /* disable channel interrupt */ 1678 emu_wr(sc, INTE, 1679 INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE, 1680 4); 1681 emu_wrptr(sc, 0, CLIEL, 0); 1682 emu_wrptr(sc, 0, CLIEH, 0); 1683 emu_wrptr(sc, 0, SOLEL, 0); 1684 emu_wrptr(sc, 0, SOLEH, 0); 1685 1686 /* wonder what these do... */ 1687 if (sc->audigy) { 1688 emu_wrptr(sc, 0, SPBYPASS, 0xf00); 1689 emu_wrptr(sc, 0, AC97SLOT, 0x3); 1690 } 1691 1692 /* init envelope engine */ 1693 for (ch = 0; ch < NUM_G; ch++) { 1694 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF); 1695 emu_wrptr(sc, ch, IP, 0); 1696 emu_wrptr(sc, ch, VTFT, 0xffff); 1697 emu_wrptr(sc, ch, CVCF, 0xffff); 1698 emu_wrptr(sc, ch, PTRX, 0); 1699 emu_wrptr(sc, ch, CPF, 0); 1700 emu_wrptr(sc, ch, CCR, 0); 1701 1702 emu_wrptr(sc, ch, PSST, 0); 1703 emu_wrptr(sc, ch, DSL, 0x10); 1704 emu_wrptr(sc, ch, CCCA, 0); 1705 emu_wrptr(sc, ch, Z1, 0); 1706 emu_wrptr(sc, ch, Z2, 0); 1707 emu_wrptr(sc, ch, FXRT, 0xd01c0000); 1708 1709 emu_wrptr(sc, ch, ATKHLDM, 0); 1710 emu_wrptr(sc, ch, DCYSUSM, 0); 1711 emu_wrptr(sc, ch, IFATN, 0xffff); 1712 emu_wrptr(sc, ch, PEFE, 0); 1713 emu_wrptr(sc, ch, FMMOD, 0); 1714 emu_wrptr(sc, ch, TREMFRQ, 24); /* 1 Hz */ 1715 emu_wrptr(sc, ch, FM2FRQ2, 24); /* 1 Hz */ 1716 emu_wrptr(sc, ch, TEMPENV, 0); 1717 1718 /*** these are last so OFF prevents writing ***/ 1719 emu_wrptr(sc, ch, LFOVAL2, 0); 1720 emu_wrptr(sc, ch, LFOVAL1, 0); 1721 emu_wrptr(sc, ch, ATKHLDV, 0); 1722 emu_wrptr(sc, ch, ENVVOL, 0); 1723 emu_wrptr(sc, ch, ENVVAL, 0); 1724 1725 if (sc->audigy) { 1726 /* audigy cards need this to initialize correctly */ 1727 emu_wrptr(sc, ch, 0x4c, 0); 1728 emu_wrptr(sc, ch, 0x4d, 0); 1729 emu_wrptr(sc, ch, 0x4e, 0); 1730 emu_wrptr(sc, ch, 0x4f, 0); 1731 /* set default routing */ 1732 emu_wrptr(sc, ch, A_FXRT1, 0x03020100); 1733 emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f); 1734 emu_wrptr(sc, ch, A_SENDAMOUNTS, 0); 1735 } 1736 1737 sc->voice[ch].vnum = ch; 1738 sc->voice[ch].slave = NULL; 1739 sc->voice[ch].busy = 0; 1740 sc->voice[ch].ismaster = 0; 1741 sc->voice[ch].running = 0; 1742 sc->voice[ch].b16 = 0; 1743 sc->voice[ch].stereo = 0; 1744 sc->voice[ch].speed = 0; 1745 sc->voice[ch].start = 0; 1746 sc->voice[ch].end = 0; 1747 sc->voice[ch].channel = NULL; 1748 } 1749 sc->pnum = sc->rnum = 0; 1750 1751 /* 1752 * Init to 0x02109204 : 1753 * Clock accuracy = 0 (1000ppm) 1754 * Sample Rate = 2 (48kHz) 1755 * Audio Channel = 1 (Left of 2) 1756 * Source Number = 0 (Unspecified) 1757 * Generation Status = 1 (Original for Cat Code 12) 1758 * Cat Code = 12 (Digital Signal Mixer) 1759 * Mode = 0 (Mode 0) 1760 * Emphasis = 0 (None) 1761 * CP = 1 (Copyright unasserted) 1762 * AN = 0 (Audio data) 1763 * P = 0 (Consumer) 1764 */ 1765 spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 | 1766 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | 1767 SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 | 1768 SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT; 1769 emu_wrptr(sc, 0, SPCS0, spcs); 1770 emu_wrptr(sc, 0, SPCS1, spcs); 1771 emu_wrptr(sc, 0, SPCS2, spcs); 1772 1773 if (!sc->audigy) 1774 emu_initefx(sc); 1775 else if (sc->audigy2) { /* Audigy 2 */ 1776 /* from ALSA initialization code: */ 1777 1778 /* Hack for Alice3 to work independent of haP16V driver */ 1779 u_int32_t tmp; 1780 1781 /* Setup SRCMulti_I2S SamplingRate */ 1782 tmp = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE) & 0xfffff1ff; 1783 emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, tmp | 0x400); 1784 1785 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */ 1786 emu_wr(sc, 0x20, 0x00600000, 4); 1787 emu_wr(sc, 0x24, 0x00000014, 4); 1788 1789 /* Setup SRCMulti Input Audio Enable */ 1790 emu_wr(sc, 0x20, 0x006e0000, 4); 1791 emu_wr(sc, 0x24, 0xff00ff00, 4); 1792 } 1793 1794 SLIST_INIT(&sc->mem.blocks); 1795 sc->mem.ptb_pages = emu_malloc(sc, EMUMAXPAGES * sizeof(u_int32_t), 1796 &sc->mem.ptb_pages_addr); 1797 if (sc->mem.ptb_pages == NULL) 1798 return -1; 1799 1800 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE, 1801 &sc->mem.silent_page_addr); 1802 if (sc->mem.silent_page == NULL) { 1803 emu_free(sc, sc->mem.ptb_pages); 1804 return -1; 1805 } 1806 /* Clear page with silence & setup all pointers to this page */ 1807 bzero(sc->mem.silent_page, EMUPAGESIZE); 1808 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1809 for (i = 0; i < EMUMAXPAGES; i++) 1810 sc->mem.ptb_pages[i] = tmp | i; 1811 1812 emu_wrptr(sc, 0, PTB, (sc->mem.ptb_pages_addr)); 1813 emu_wrptr(sc, 0, TCB, 0); /* taken from original driver */ 1814 emu_wrptr(sc, 0, TCBS, 0); /* taken from original driver */ 1815 1816 for (ch = 0; ch < NUM_G; ch++) { 1817 emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK); 1818 emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK); 1819 } 1820 1821 /* emu_memalloc(sc, EMUPAGESIZE); */ 1822 /* 1823 * Hokay, now enable the AUD bit 1824 * 1825 * Audigy 1826 * Enable Audio = 0 (enabled after fx processor initialization) 1827 * Mute Disable Audio = 0 1828 * Joystick = 1 1829 * 1830 * Audigy 2 1831 * Enable Audio = 1 1832 * Mute Disable Audio = 0 1833 * Joystick = 1 1834 * GP S/PDIF AC3 Enable = 1 1835 * CD S/PDIF AC3 Enable = 1 1836 * 1837 * EMU10K1 1838 * Enable Audio = 1 1839 * Mute Disable Audio = 0 1840 * Lock Tank Memory = 1 1841 * Lock Sound Memory = 0 1842 * Auto Mute = 1 1843 */ 1844 1845 if (sc->audigy) { 1846 tmp = HCFG_AUTOMUTE | HCFG_JOYENABLE; 1847 if (sc->audigy2) /* Audigy 2 */ 1848 tmp = HCFG_AUDIOENABLE | HCFG_AC3ENABLE_CDSPDIF | 1849 HCFG_AC3ENABLE_GPSPDIF; 1850 emu_wr(sc, HCFG, tmp, 4); 1851 1852 audigy_initefx(sc); 1853 1854 /* from ALSA initialization code: */ 1855 1856 /* enable audio and disable both audio/digital outputs */ 1857 emu_wr(sc, HCFG, emu_rd(sc, HCFG, 4) | HCFG_AUDIOENABLE, 4); 1858 emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) & ~A_IOCFG_GPOUT_AD, 1859 4); 1860 if (sc->audigy2) { /* Audigy 2 */ 1861 /* Unmute Analog. 1862 * Set GPO6 to 1 for Apollo. This has to be done after 1863 * init Alice3 I2SOut beyond 48kHz. 1864 * So, sequence is important. 1865 */ 1866 emu_wr(sc, A_IOCFG, 1867 emu_rd(sc, A_IOCFG, 4) | A_IOCFG_GPOUT_A, 4); 1868 } 1869 } else { 1870 /* EMU10K1 initialization code */ 1871 tmp = HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK 1872 | HCFG_AUTOMUTE; 1873 if (sc->rev >= 6) 1874 tmp |= HCFG_JOYENABLE; 1875 1876 emu_wr(sc, HCFG, tmp, 4); 1877 1878 /* TOSLink detection */ 1879 sc->tos_link = 0; 1880 tmp = emu_rd(sc, HCFG, 4); 1881 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) { 1882 emu_wr(sc, HCFG, tmp | HCFG_GPOUT1, 4); 1883 DELAY(50); 1884 if (tmp != (emu_rd(sc, HCFG, 4) & ~HCFG_GPOUT1)) { 1885 sc->tos_link = 1; 1886 emu_wr(sc, HCFG, tmp, 4); 1887 } 1888 } 1889 } 1890 1891 return 0; 1892 } 1893 1894 static int 1895 emu_uninit(struct sc_info *sc) 1896 { 1897 u_int32_t ch; 1898 1899 emu_wr(sc, INTE, 0, 4); 1900 for (ch = 0; ch < NUM_G; ch++) 1901 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF); 1902 for (ch = 0; ch < NUM_G; ch++) { 1903 emu_wrptr(sc, ch, VTFT, 0); 1904 emu_wrptr(sc, ch, CVCF, 0); 1905 emu_wrptr(sc, ch, PTRX, 0); 1906 emu_wrptr(sc, ch, CPF, 0); 1907 } 1908 1909 if (sc->audigy) { /* stop fx processor */ 1910 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP); 1911 } 1912 1913 /* disable audio and lock cache */ 1914 emu_wr(sc, HCFG, 1915 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, 1916 4); 1917 1918 emu_wrptr(sc, 0, PTB, 0); 1919 /* reset recording buffers */ 1920 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE); 1921 emu_wrptr(sc, 0, MICBA, 0); 1922 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE); 1923 emu_wrptr(sc, 0, FXBA, 0); 1924 emu_wrptr(sc, 0, FXWC, 0); 1925 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE); 1926 emu_wrptr(sc, 0, ADCBA, 0); 1927 emu_wrptr(sc, 0, TCB, 0); 1928 emu_wrptr(sc, 0, TCBS, 0); 1929 1930 /* disable channel interrupt */ 1931 emu_wrptr(sc, 0, CLIEL, 0); 1932 emu_wrptr(sc, 0, CLIEH, 0); 1933 emu_wrptr(sc, 0, SOLEL, 0); 1934 emu_wrptr(sc, 0, SOLEH, 0); 1935 1936 /* init envelope engine */ 1937 if (!SLIST_EMPTY(&sc->mem.blocks)) 1938 device_printf(sc->dev, "warning: memblock list not empty\n"); 1939 emu_free(sc, sc->mem.ptb_pages); 1940 emu_free(sc, sc->mem.silent_page); 1941 1942 if(sc->mpu) 1943 mpu401_uninit(sc->mpu); 1944 return 0; 1945 } 1946 1947 static int 1948 emu_pci_probe(device_t dev) 1949 { 1950 char *s = NULL; 1951 1952 switch (pci_get_devid(dev)) { 1953 case EMU10K1_PCI_ID: 1954 s = "Creative EMU10K1"; 1955 break; 1956 1957 case EMU10K2_PCI_ID: 1958 if (pci_get_revid(dev) == 0x04) 1959 s = "Creative Audigy 2 (EMU10K2)"; 1960 else 1961 s = "Creative Audigy (EMU10K2)"; 1962 break; 1963 1964 case EMU10K3_PCI_ID: 1965 s = "Creative Audigy 2 (EMU10K3)"; 1966 break; 1967 1968 default: 1969 return ENXIO; 1970 } 1971 1972 device_set_desc(dev, s); 1973 return BUS_PROBE_DEFAULT; 1974 } 1975 1976 static int 1977 emu_pci_attach(device_t dev) 1978 { 1979 struct ac97_info *codec = NULL; 1980 struct sc_info *sc; 1981 u_int32_t data; 1982 int i, gotmic; 1983 char status[SND_STATUSLEN]; 1984 1985 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO)) == NULL) { 1986 device_printf(dev, "cannot allocate softc\n"); 1987 return ENXIO; 1988 } 1989 1990 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 1991 sc->dev = dev; 1992 sc->type = pci_get_devid(dev); 1993 sc->rev = pci_get_revid(dev); 1994 sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID; 1995 sc->audigy2 = (sc->audigy && sc->rev == 0x04); 1996 sc->nchans = sc->audigy ? 8 : 4; 1997 sc->addrmask = sc->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK; 1998 1999 data = pci_read_config(dev, PCIR_COMMAND, 2); 2000 data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN); 2001 pci_write_config(dev, PCIR_COMMAND, data, 2); 2002 data = pci_read_config(dev, PCIR_COMMAND, 2); 2003 2004 i = PCIR_BAR(0); 2005 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE); 2006 if (sc->reg == NULL) { 2007 device_printf(dev, "unable to map register space\n"); 2008 goto bad; 2009 } 2010 sc->st = rman_get_bustag(sc->reg); 2011 sc->sh = rman_get_bushandle(sc->reg); 2012 2013 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536); 2014 2015 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 2016 /*lowaddr*/1 << 31, /* can only access 0-2gb */ 2017 /*highaddr*/BUS_SPACE_MAXADDR, 2018 /*filter*/NULL, /*filterarg*/NULL, 2019 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 2020 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 2021 /*lockarg*/&Giant, &sc->parent_dmat) != 0) { 2022 device_printf(dev, "unable to create dma tag\n"); 2023 goto bad; 2024 } 2025 2026 if (emu_init(sc) == -1) { 2027 device_printf(dev, "unable to initialize the card\n"); 2028 goto bad; 2029 } 2030 2031 codec = AC97_CREATE(dev, sc, emu_ac97); 2032 if (codec == NULL) goto bad; 2033 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL) ? 1 : 0; 2034 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 2035 2036 emu_midiattach(sc); 2037 2038 i = 0; 2039 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, 2040 RF_ACTIVE | RF_SHAREABLE); 2041 if (!sc->irq || 2042 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) { 2043 device_printf(dev, "unable to map interrupt\n"); 2044 goto bad; 2045 } 2046 2047 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 2048 rman_get_start(sc->reg), rman_get_start(sc->irq), 2049 PCM_KLDSTRING(snd_emu10k1)); 2050 2051 if (pcm_register(dev, sc, sc->nchans, gotmic ? 3 : 2)) goto bad; 2052 for (i = 0; i < sc->nchans; i++) 2053 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc); 2054 for (i = 0; i < (gotmic ? 3 : 2); i++) 2055 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc); 2056 2057 pcm_setstatus(dev, status); 2058 2059 return 0; 2060 2061 bad: 2062 if (codec) ac97_destroy(codec); 2063 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2064 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih); 2065 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2066 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat); 2067 if (sc->lock) snd_mtxfree(sc->lock); 2068 free(sc, M_DEVBUF); 2069 return ENXIO; 2070 } 2071 2072 static int 2073 emu_pci_detach(device_t dev) 2074 { 2075 int r; 2076 struct sc_info *sc; 2077 2078 r = pcm_unregister(dev); 2079 if (r) 2080 return r; 2081 2082 sc = pcm_getdevinfo(dev); 2083 /* shutdown chip */ 2084 emu_uninit(sc); 2085 2086 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2087 bus_teardown_intr(dev, sc->irq, sc->ih); 2088 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2089 bus_dma_tag_destroy(sc->parent_dmat); 2090 snd_mtxfree(sc->lock); 2091 free(sc, M_DEVBUF); 2092 2093 return 0; 2094 } 2095 2096 /* add suspend, resume */ 2097 static device_method_t emu_methods[] = { 2098 /* Device interface */ 2099 DEVMETHOD(device_probe, emu_pci_probe), 2100 DEVMETHOD(device_attach, emu_pci_attach), 2101 DEVMETHOD(device_detach, emu_pci_detach), 2102 2103 { 0, 0 } 2104 }; 2105 2106 static driver_t emu_driver = { 2107 "pcm", 2108 emu_methods, 2109 PCM_SOFTC_SIZE, 2110 }; 2111 2112 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, 0, 0); 2113 DRIVER_MODULE(snd_emu10k1, cardbus, emu_driver, pcm_devclass, 0, 0); 2114 MODULE_DEPEND(snd_emu10k1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 2115 MODULE_VERSION(snd_emu10k1, 1); 2116 MODULE_DEPEND(snd_emu10k1, midi, 1, 1, 1); 2117 2118 /* dummy driver to silence the joystick device */ 2119 static int 2120 emujoy_pci_probe(device_t dev) 2121 { 2122 char *s = NULL; 2123 2124 switch (pci_get_devid(dev)) { 2125 case 0x70021102: 2126 s = "Creative EMU10K1 Joystick"; 2127 device_quiet(dev); 2128 break; 2129 case 0x70031102: 2130 s = "Creative EMU10K2 Joystick"; 2131 device_quiet(dev); 2132 break; 2133 } 2134 2135 if (s) device_set_desc(dev, s); 2136 return s ? -1000 : ENXIO; 2137 } 2138 2139 static int 2140 emujoy_pci_attach(device_t dev) 2141 { 2142 return 0; 2143 } 2144 2145 static int 2146 emujoy_pci_detach(device_t dev) 2147 { 2148 return 0; 2149 } 2150 2151 static device_method_t emujoy_methods[] = { 2152 DEVMETHOD(device_probe, emujoy_pci_probe), 2153 DEVMETHOD(device_attach, emujoy_pci_attach), 2154 DEVMETHOD(device_detach, emujoy_pci_detach), 2155 2156 { 0, 0 } 2157 }; 2158 2159 static driver_t emujoy_driver = { 2160 "emujoy", 2161 emujoy_methods, 2162 8, 2163 }; 2164 2165 static devclass_t emujoy_devclass; 2166 2167 DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, 0, 0); 2168 2169