1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org> 5 * Copyright (c) 2003 Orlando Bassotto <orlando.bassotto@ieo-research.it> 6 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifdef HAVE_KERNEL_OPTION_HEADERS 32 #include "opt_snd.h" 33 #endif 34 35 #include <dev/sound/pcm/sound.h> 36 #include <dev/sound/pcm/ac97.h> 37 #include <dev/sound/pci/emuxkireg.h> 38 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 #include <sys/queue.h> 42 43 #include <dev/sound/midi/mpu401.h> 44 #include "mpufoi_if.h" 45 46 /* -------------------------------------------------------------------- */ 47 48 #define NUM_G 64 /* use all channels */ 49 #define WAVEOUT_MAXBUFSIZE 32768 50 #define EMUPAGESIZE 4096 /* don't change */ 51 #define EMUMAXPAGES (WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE) 52 #define EMU10K1_PCI_ID 0x00021102 /* 1102 => Creative Labs Vendor ID */ 53 #define EMU10K2_PCI_ID 0x00041102 54 #define EMU10K3_PCI_ID 0x00081102 55 #define EMU_DEFAULT_BUFSZ 4096 56 #define EMU_MAX_CHANS 8 57 #define EMU_CHANS 4 58 59 #define MAXREQVOICES 8 60 #define RESERVED 0 61 #define NUM_MIDI 16 62 #define NUM_FXSENDS 4 63 64 #define TMEMSIZE 256*1024 65 #define TMEMSIZEREG 4 66 67 #define ENABLE 0xffffffff 68 #define DISABLE 0x00000000 69 #define ENV_ON EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK 70 #define ENV_OFF 0x00 /* XXX: should this be 1? */ 71 72 #define EMU_A_IOCFG_GPOUT_A 0x40 73 #define EMU_A_IOCFG_GPOUT_D 0x04 74 #define EMU_A_IOCFG_GPOUT_AD (EMU_A_IOCFG_GPOUT_A|EMU_A_IOCFG_GPOUT_D) /* EMU_A_IOCFG_GPOUT0 */ 75 76 #define EMU_HCFG_GPOUT1 0x00000800 77 78 /* instruction set */ 79 #define iACC3 0x06 80 #define iMACINT0 0x04 81 #define iINTERP 0x0e 82 83 #define C_00000000 0x40 84 #define C_00000001 0x41 85 #define C_00000004 0x44 86 #define C_40000000 0x4d 87 /* Audigy constants */ 88 #define A_C_00000000 0xc0 89 #define A_C_40000000 0xcd 90 91 /* GPRs */ 92 #define FXBUS(x) (0x00 + (x)) 93 #define EXTIN(x) (0x10 + (x)) 94 #define EXTOUT(x) (0x20 + (x)) 95 96 #define GPR(x) (EMU_FXGPREGBASE + (x)) 97 #define A_EXTIN(x) (0x40 + (x)) 98 #define A_FXBUS(x) (0x00 + (x)) 99 #define A_EXTOUT(x) (0x60 + (x)) 100 #define A_GPR(x) (EMU_A_FXGPREGBASE + (x)) 101 102 /* FX buses */ 103 #define FXBUS_PCM_LEFT 0x00 104 #define FXBUS_PCM_RIGHT 0x01 105 #define FXBUS_MIDI_LEFT 0x04 106 #define FXBUS_MIDI_RIGHT 0x05 107 #define FXBUS_MIDI_REVERB 0x0c 108 #define FXBUS_MIDI_CHORUS 0x0d 109 110 /* Inputs */ 111 #define EXTIN_AC97_L 0x00 112 #define EXTIN_AC97_R 0x01 113 #define EXTIN_SPDIF_CD_L 0x02 114 #define EXTIN_SPDIF_CD_R 0x03 115 #define EXTIN_TOSLINK_L 0x06 116 #define EXTIN_TOSLINK_R 0x07 117 #define EXTIN_COAX_SPDIF_L 0x0a 118 #define EXTIN_COAX_SPDIF_R 0x0b 119 /* Audigy Inputs */ 120 #define A_EXTIN_AC97_L 0x00 121 #define A_EXTIN_AC97_R 0x01 122 123 /* Outputs */ 124 #define EXTOUT_AC97_L 0x00 125 #define EXTOUT_AC97_R 0x01 126 #define EXTOUT_TOSLINK_L 0x02 127 #define EXTOUT_TOSLINK_R 0x03 128 #define EXTOUT_AC97_CENTER 0x04 129 #define EXTOUT_AC97_LFE 0x05 130 #define EXTOUT_HEADPHONE_L 0x06 131 #define EXTOUT_HEADPHONE_R 0x07 132 #define EXTOUT_REAR_L 0x08 133 #define EXTOUT_REAR_R 0x09 134 #define EXTOUT_ADC_CAP_L 0x0a 135 #define EXTOUT_ADC_CAP_R 0x0b 136 #define EXTOUT_ACENTER 0x11 137 #define EXTOUT_ALFE 0x12 138 /* Audigy Outputs */ 139 #define A_EXTOUT_FRONT_L 0x00 140 #define A_EXTOUT_FRONT_R 0x01 141 #define A_EXTOUT_CENTER 0x02 142 #define A_EXTOUT_LFE 0x03 143 #define A_EXTOUT_HEADPHONE_L 0x04 144 #define A_EXTOUT_HEADPHONE_R 0x05 145 #define A_EXTOUT_REAR_L 0x06 146 #define A_EXTOUT_REAR_R 0x07 147 #define A_EXTOUT_AFRONT_L 0x08 148 #define A_EXTOUT_AFRONT_R 0x09 149 #define A_EXTOUT_ACENTER 0x0a 150 #define A_EXTOUT_ALFE 0x0b 151 #define A_EXTOUT_AREAR_L 0x0e 152 #define A_EXTOUT_AREAR_R 0x0f 153 #define A_EXTOUT_AC97_L 0x10 154 #define A_EXTOUT_AC97_R 0x11 155 #define A_EXTOUT_ADC_CAP_L 0x16 156 #define A_EXTOUT_ADC_CAP_R 0x17 157 158 struct emu_memblk { 159 SLIST_ENTRY(emu_memblk) link; 160 void *buf; 161 bus_addr_t buf_addr; 162 u_int32_t pte_start, pte_size; 163 bus_dmamap_t buf_map; 164 }; 165 166 struct emu_mem { 167 u_int8_t bmap[EMUMAXPAGES / 8]; 168 u_int32_t *ptb_pages; 169 void *silent_page; 170 bus_addr_t silent_page_addr; 171 bus_addr_t ptb_pages_addr; 172 bus_dmamap_t ptb_map; 173 bus_dmamap_t silent_map; 174 SLIST_HEAD(, emu_memblk) blocks; 175 }; 176 177 struct emu_voice { 178 int vnum; 179 unsigned int b16:1, stereo:1, busy:1, running:1, ismaster:1; 180 int speed; 181 int start, end, vol; 182 int fxrt1; /* FX routing */ 183 int fxrt2; /* FX routing (only for audigy) */ 184 u_int32_t buf; 185 struct emu_voice *slave; 186 struct pcm_channel *channel; 187 }; 188 189 struct sc_info; 190 191 /* channel registers */ 192 struct sc_pchinfo { 193 int spd, fmt, blksz, run; 194 struct emu_voice *master, *slave; 195 struct snd_dbuf *buffer; 196 struct pcm_channel *channel; 197 struct sc_info *parent; 198 }; 199 200 struct sc_rchinfo { 201 int spd, fmt, run, blksz, num; 202 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask; 203 struct snd_dbuf *buffer; 204 struct pcm_channel *channel; 205 struct sc_info *parent; 206 }; 207 208 /* device private data */ 209 struct sc_info { 210 device_t dev; 211 u_int32_t type, rev; 212 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1; 213 u_int32_t addrmask; /* wider if audigy */ 214 215 bus_space_tag_t st; 216 bus_space_handle_t sh; 217 bus_dma_tag_t parent_dmat; 218 219 struct resource *reg, *irq; 220 void *ih; 221 struct mtx *lock; 222 223 unsigned int bufsz; 224 int timer, timerinterval; 225 int pnum, rnum; 226 int nchans; 227 struct emu_mem mem; 228 struct emu_voice voice[64]; 229 struct sc_pchinfo pch[EMU_MAX_CHANS]; 230 struct sc_rchinfo rch[3]; 231 struct mpu401 *mpu; 232 mpu401_intr_t *mpu_intr; 233 int mputx; 234 }; 235 236 /* -------------------------------------------------------------------- */ 237 238 /* 239 * prototypes 240 */ 241 242 /* stuff */ 243 static int emu_init(struct sc_info *); 244 static void emu_intr(void *); 245 static void *emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr, bus_dmamap_t *map); 246 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr); 247 static int emu_memfree(struct sc_info *sc, void *buf); 248 static int emu_memstart(struct sc_info *sc, void *buf); 249 #ifdef EMUDEBUG 250 static void emu_vdump(struct sc_info *sc, struct emu_voice *v); 251 #endif 252 253 /* talk to the card */ 254 static u_int32_t emu_rd(struct sc_info *, int, int); 255 static void emu_wr(struct sc_info *, int, u_int32_t, int); 256 257 /* -------------------------------------------------------------------- */ 258 259 static u_int32_t emu_rfmt_ac97[] = { 260 SND_FORMAT(AFMT_S16_LE, 1, 0), 261 SND_FORMAT(AFMT_S16_LE, 2, 0), 262 0 263 }; 264 265 static u_int32_t emu_rfmt_mic[] = { 266 SND_FORMAT(AFMT_U8, 1, 0), 267 0 268 }; 269 270 static u_int32_t emu_rfmt_efx[] = { 271 SND_FORMAT(AFMT_S16_LE, 2, 0), 272 0 273 }; 274 275 static struct pcmchan_caps emu_reccaps[3] = { 276 {8000, 48000, emu_rfmt_ac97, 0}, 277 {8000, 8000, emu_rfmt_mic, 0}, 278 {48000, 48000, emu_rfmt_efx, 0}, 279 }; 280 281 static u_int32_t emu_pfmt[] = { 282 SND_FORMAT(AFMT_U8, 1, 0), 283 SND_FORMAT(AFMT_U8, 2, 0), 284 SND_FORMAT(AFMT_S16_LE, 1, 0), 285 SND_FORMAT(AFMT_S16_LE, 2, 0), 286 0 287 }; 288 289 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0}; 290 291 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000}; 292 /* audigy supports 12kHz. */ 293 static int audigy_adcspeed[9] = { 294 48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000 295 }; 296 297 /* -------------------------------------------------------------------- */ 298 /* Hardware */ 299 static u_int32_t 300 emu_rd(struct sc_info *sc, int regno, int size) 301 { 302 switch (size) { 303 case 1: 304 return bus_space_read_1(sc->st, sc->sh, regno); 305 case 2: 306 return bus_space_read_2(sc->st, sc->sh, regno); 307 case 4: 308 return bus_space_read_4(sc->st, sc->sh, regno); 309 default: 310 return 0xffffffff; 311 } 312 } 313 314 static void 315 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 316 { 317 switch (size) { 318 case 1: 319 bus_space_write_1(sc->st, sc->sh, regno, data); 320 break; 321 case 2: 322 bus_space_write_2(sc->st, sc->sh, regno, data); 323 break; 324 case 4: 325 bus_space_write_4(sc->st, sc->sh, regno, data); 326 break; 327 } 328 } 329 330 static u_int32_t 331 emu_rdptr(struct sc_info *sc, int chn, int reg) 332 { 333 u_int32_t ptr, val, mask, size, offset; 334 335 ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK); 336 emu_wr(sc, EMU_PTR, ptr, 4); 337 val = emu_rd(sc, EMU_DATA, 4); 338 if (reg & 0xff000000) { 339 size = (reg >> 24) & 0x3f; 340 offset = (reg >> 16) & 0x1f; 341 mask = ((1 << size) - 1) << offset; 342 val &= mask; 343 val >>= offset; 344 } 345 return val; 346 } 347 348 static void 349 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data) 350 { 351 u_int32_t ptr, mask, size, offset; 352 353 ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK); 354 emu_wr(sc, EMU_PTR, ptr, 4); 355 if (reg & 0xff000000) { 356 size = (reg >> 24) & 0x3f; 357 offset = (reg >> 16) & 0x1f; 358 mask = ((1 << size) - 1) << offset; 359 data <<= offset; 360 data &= mask; 361 data |= emu_rd(sc, EMU_DATA, 4) & ~mask; 362 } 363 emu_wr(sc, EMU_DATA, data, 4); 364 } 365 366 static void 367 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data) 368 { 369 pc += sc->audigy ? EMU_A_MICROCODEBASE : EMU_MICROCODEBASE; 370 emu_wrptr(sc, 0, pc, data); 371 } 372 373 /* -------------------------------------------------------------------- */ 374 /* ac97 codec */ 375 /* no locking needed */ 376 377 static int 378 emu_rdcd(kobj_t obj, void *devinfo, int regno) 379 { 380 struct sc_info *sc = (struct sc_info *)devinfo; 381 382 emu_wr(sc, EMU_AC97ADDR, regno, 1); 383 return emu_rd(sc, EMU_AC97DATA, 2); 384 } 385 386 static int 387 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 388 { 389 struct sc_info *sc = (struct sc_info *)devinfo; 390 391 emu_wr(sc, EMU_AC97ADDR, regno, 1); 392 emu_wr(sc, EMU_AC97DATA, data, 2); 393 return 0; 394 } 395 396 static kobj_method_t emu_ac97_methods[] = { 397 KOBJMETHOD(ac97_read, emu_rdcd), 398 KOBJMETHOD(ac97_write, emu_wrcd), 399 KOBJMETHOD_END 400 }; 401 AC97_DECLARE(emu_ac97); 402 403 /* -------------------------------------------------------------------- */ 404 /* stuff */ 405 static int 406 emu_settimer(struct sc_info *sc) 407 { 408 struct sc_pchinfo *pch; 409 struct sc_rchinfo *rch; 410 int i, tmp, rate; 411 412 rate = 0; 413 for (i = 0; i < sc->nchans; i++) { 414 pch = &sc->pch[i]; 415 if (pch->buffer) { 416 tmp = (pch->spd * sndbuf_getalign(pch->buffer)) 417 / pch->blksz; 418 if (tmp > rate) 419 rate = tmp; 420 } 421 } 422 423 for (i = 0; i < 3; i++) { 424 rch = &sc->rch[i]; 425 if (rch->buffer) { 426 tmp = (rch->spd * sndbuf_getalign(rch->buffer)) 427 / rch->blksz; 428 if (tmp > rate) 429 rate = tmp; 430 } 431 } 432 RANGE(rate, 48, 9600); 433 sc->timerinterval = 48000 / rate; 434 emu_wr(sc, EMU_TIMER, sc->timerinterval & 0x03ff, 2); 435 436 return sc->timerinterval; 437 } 438 439 static int 440 emu_enatimer(struct sc_info *sc, int go) 441 { 442 u_int32_t x; 443 if (go) { 444 if (sc->timer++ == 0) { 445 x = emu_rd(sc, EMU_INTE, 4); 446 x |= EMU_INTE_INTERTIMERENB; 447 emu_wr(sc, EMU_INTE, x, 4); 448 } 449 } else { 450 sc->timer = 0; 451 x = emu_rd(sc, EMU_INTE, 4); 452 x &= ~EMU_INTE_INTERTIMERENB; 453 emu_wr(sc, EMU_INTE, x, 4); 454 } 455 return 0; 456 } 457 458 static void 459 emu_enastop(struct sc_info *sc, char channel, int enable) 460 { 461 int reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL; 462 channel &= 0x1f; 463 reg |= 1 << 24; 464 reg |= channel << 16; 465 emu_wrptr(sc, 0, reg, enable); 466 } 467 468 static int 469 emu_recval(int speed) { 470 int val; 471 472 val = 0; 473 while (val < 7 && speed < adcspeed[val]) 474 val++; 475 return val; 476 } 477 478 static int 479 audigy_recval(int speed) { 480 int val; 481 482 val = 0; 483 while (val < 8 && speed < audigy_adcspeed[val]) 484 val++; 485 return val; 486 } 487 488 static u_int32_t 489 emu_rate_to_pitch(u_int32_t rate) 490 { 491 static u_int32_t logMagTable[128] = { 492 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2, 493 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5, 494 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081, 495 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191, 496 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7, 497 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829, 498 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e, 499 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26, 500 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d, 501 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885, 502 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899, 503 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c, 504 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3, 505 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3, 506 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83, 507 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df 508 }; 509 static char logSlopeTable[128] = { 510 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58, 511 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53, 512 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f, 513 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b, 514 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47, 515 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44, 516 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41, 517 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e, 518 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c, 519 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 520 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37, 521 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35, 522 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34, 523 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32, 524 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30, 525 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f 526 }; 527 int i; 528 529 if (rate == 0) 530 return 0; /* Bail out if no leading "1" */ 531 rate *= 11185; /* Scale 48000 to 0x20002380 */ 532 for (i = 31; i > 0; i--) { 533 if (rate & 0x80000000) { /* Detect leading "1" */ 534 return (((u_int32_t) (i - 15) << 20) + 535 logMagTable[0x7f & (rate >> 24)] + 536 (0x7f & (rate >> 17)) * 537 logSlopeTable[0x7f & (rate >> 24)]); 538 } 539 rate <<= 1; 540 } 541 542 return 0; /* Should never reach this point */ 543 } 544 545 static u_int32_t 546 emu_rate_to_linearpitch(u_int32_t rate) 547 { 548 rate = (rate << 8) / 375; 549 return (rate >> 1) + (rate & 1); 550 } 551 552 static struct emu_voice * 553 emu_valloc(struct sc_info *sc) 554 { 555 struct emu_voice *v; 556 int i; 557 558 v = NULL; 559 for (i = 0; i < 64 && sc->voice[i].busy; i++); 560 if (i < 64) { 561 v = &sc->voice[i]; 562 v->busy = 1; 563 } 564 return v; 565 } 566 567 static int 568 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s, 569 u_int32_t sz, struct snd_dbuf *b) 570 { 571 void *buf; 572 bus_addr_t tmp_addr; 573 574 buf = emu_memalloc(sc, sz, &tmp_addr); 575 if (buf == NULL) 576 return -1; 577 if (b != NULL) 578 sndbuf_setup(b, buf, sz); 579 m->start = emu_memstart(sc, buf) * EMUPAGESIZE; 580 m->end = m->start + sz; 581 m->channel = NULL; 582 m->speed = 0; 583 m->b16 = 0; 584 m->stereo = 0; 585 m->running = 0; 586 m->ismaster = 1; 587 m->vol = 0xff; 588 m->buf = tmp_addr; 589 m->slave = s; 590 if (sc->audigy) { 591 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 8 | 592 FXBUS_PCM_LEFT << 16 | FXBUS_MIDI_REVERB << 24; 593 m->fxrt2 = 0x3f3f3f3f; /* No effects on second route */ 594 } else { 595 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 4 | 596 FXBUS_PCM_LEFT << 8 | FXBUS_MIDI_REVERB << 12; 597 m->fxrt2 = 0; 598 } 599 600 if (s != NULL) { 601 s->start = m->start; 602 s->end = m->end; 603 s->channel = NULL; 604 s->speed = 0; 605 s->b16 = 0; 606 s->stereo = 0; 607 s->running = 0; 608 s->ismaster = 0; 609 s->vol = m->vol; 610 s->buf = m->buf; 611 s->fxrt1 = m->fxrt1; 612 s->fxrt2 = m->fxrt2; 613 s->slave = NULL; 614 } 615 return 0; 616 } 617 618 static void 619 emu_vsetup(struct sc_pchinfo *ch) 620 { 621 struct emu_voice *v = ch->master; 622 623 if (ch->fmt) { 624 v->b16 = (ch->fmt & AFMT_16BIT) ? 1 : 0; 625 v->stereo = (AFMT_CHANNEL(ch->fmt) > 1) ? 1 : 0; 626 if (v->slave != NULL) { 627 v->slave->b16 = v->b16; 628 v->slave->stereo = v->stereo; 629 } 630 } 631 if (ch->spd) { 632 v->speed = ch->spd; 633 if (v->slave != NULL) 634 v->slave->speed = v->speed; 635 } 636 } 637 638 static void 639 emu_vwrite(struct sc_info *sc, struct emu_voice *v) 640 { 641 int s; 642 int l, r, x, y; 643 u_int32_t sa, ea, start, val, silent_page; 644 645 s = (v->stereo ? 1 : 0) + (v->b16 ? 1 : 0); 646 647 sa = v->start >> s; 648 ea = v->end >> s; 649 650 l = r = x = y = v->vol; 651 if (v->stereo) { 652 l = v->ismaster ? l : 0; 653 r = v->ismaster ? 0 : r; 654 } 655 656 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF, v->stereo ? EMU_CHAN_CPF_STEREO_MASK : 0); 657 val = v->stereo ? 28 : 30; 658 val *= v->b16 ? 1 : 2; 659 start = sa + val; 660 661 if (sc->audigy) { 662 emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT1, v->fxrt1); 663 emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT2, v->fxrt2); 664 emu_wrptr(sc, v->vnum, EMU_A_CHAN_SENDAMOUNTS, 0); 665 } 666 else 667 emu_wrptr(sc, v->vnum, EMU_CHAN_FXRT, v->fxrt1 << 16); 668 669 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX, (x << 8) | r); 670 emu_wrptr(sc, v->vnum, EMU_CHAN_DSL, ea | (y << 24)); 671 emu_wrptr(sc, v->vnum, EMU_CHAN_PSST, sa | (l << 24)); 672 emu_wrptr(sc, v->vnum, EMU_CHAN_CCCA, start | (v->b16 ? 0 : EMU_CHAN_CCCA_8BITSELECT)); 673 674 emu_wrptr(sc, v->vnum, EMU_CHAN_Z1, 0); 675 emu_wrptr(sc, v->vnum, EMU_CHAN_Z2, 0); 676 677 silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1) 678 | EMU_CHAN_MAP_PTI_MASK; 679 emu_wrptr(sc, v->vnum, EMU_CHAN_MAPA, silent_page); 680 emu_wrptr(sc, v->vnum, EMU_CHAN_MAPB, silent_page); 681 682 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, EMU_CHAN_CVCF_CURRFILTER_MASK); 683 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, EMU_CHAN_VTFT_FILTERTARGET_MASK); 684 emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDM, 0); 685 emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSM, EMU_CHAN_DCYSUSM_DECAYTIME_MASK); 686 emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL1, 0x8000); 687 emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL2, 0x8000); 688 emu_wrptr(sc, v->vnum, EMU_CHAN_FMMOD, 0); 689 emu_wrptr(sc, v->vnum, EMU_CHAN_TREMFRQ, 0); 690 emu_wrptr(sc, v->vnum, EMU_CHAN_FM2FRQ2, 0); 691 emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVAL, 0x8000); 692 693 emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDV, 694 EMU_CHAN_ATKHLDV_HOLDTIME_MASK | EMU_CHAN_ATKHLDV_ATTACKTIME_MASK); 695 emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVOL, 0x8000); 696 697 emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_FILTERAMOUNT, 0x7f); 698 emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_PITCHAMOUNT, 0); 699 700 if (v->slave != NULL) 701 emu_vwrite(sc, v->slave); 702 } 703 704 static void 705 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go) 706 { 707 u_int32_t pitch_target, initial_pitch; 708 u_int32_t cra, cs, ccis; 709 u_int32_t sample, i; 710 711 if (go) { 712 cra = 64; 713 cs = v->stereo ? 4 : 2; 714 ccis = v->stereo ? 28 : 30; 715 ccis *= v->b16 ? 1 : 2; 716 sample = v->b16 ? 0x00000000 : 0x80808080; 717 718 for (i = 0; i < cs; i++) 719 emu_wrptr(sc, v->vnum, EMU_CHAN_CD0 + i, sample); 720 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, 0); 721 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_READADDRESS, cra); 722 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, ccis); 723 724 emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xff00); 725 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0xffffffff); 726 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0xffffffff); 727 emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSV, 0x00007f7f); 728 emu_enastop(sc, v->vnum, 0); 729 730 pitch_target = emu_rate_to_linearpitch(v->speed); 731 initial_pitch = emu_rate_to_pitch(v->speed) >> 8; 732 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, pitch_target); 733 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, pitch_target); 734 emu_wrptr(sc, v->vnum, EMU_CHAN_IP, initial_pitch); 735 } else { 736 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, 0); 737 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, 0); 738 emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xffff); 739 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0x0000ffff); 740 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0x0000ffff); 741 emu_wrptr(sc, v->vnum, EMU_CHAN_IP, 0); 742 emu_enastop(sc, v->vnum, 1); 743 } 744 if (v->slave != NULL) 745 emu_vtrigger(sc, v->slave, go); 746 } 747 748 static int 749 emu_vpos(struct sc_info *sc, struct emu_voice *v) 750 { 751 int s, ptr; 752 753 s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0); 754 ptr = (emu_rdptr(sc, v->vnum, EMU_CHAN_CCCA_CURRADDR) - (v->start >> s)) << s; 755 return ptr & ~0x0000001f; 756 } 757 758 #ifdef EMUDEBUG 759 static void 760 emu_vdump(struct sc_info *sc, struct emu_voice *v) 761 { 762 char *regname[] = { 763 "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl", 764 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL, 765 "envvol", "atkhldv", "dcysusv", "lfoval1", 766 "envval", "atkhldm", "dcysusm", "lfoval2", 767 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2", 768 "tempenv" 769 }; 770 char *regname2[] = { 771 "mudata1", "mustat1", "mudata2", "mustat2", 772 "fxwc1", "fxwc2", "spdrate", NULL, NULL, 773 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1", 774 NULL, NULL 775 }; 776 int i, x; 777 778 printf("voice number %d\n", v->vnum); 779 for (i = 0, x = 0; i <= 0x1e; i++) { 780 if (regname[i] == NULL) 781 continue; 782 printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i)); 783 printf("%s", (x == 2) ? "\n" : "\t"); 784 x++; 785 if (x > 2) 786 x = 0; 787 } 788 789 /* Print out audigy extra registers */ 790 if (sc->audigy) { 791 for (i = 0; i <= 0xe; i++) { 792 if (regname2[i] == NULL) 793 continue; 794 printf("%s\t[%08x]", regname2[i], 795 emu_rdptr(sc, v->vnum, i + 0x70)); 796 printf("%s", (x == 2)? "\n" : "\t"); 797 x++; 798 if (x > 2) 799 x = 0; 800 } 801 } 802 printf("\n\n"); 803 } 804 #endif 805 806 /* channel interface */ 807 static void * 808 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 809 struct pcm_channel *c, int dir) 810 { 811 struct sc_info *sc = devinfo; 812 struct sc_pchinfo *ch; 813 void *r; 814 815 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction")); 816 ch = &sc->pch[sc->pnum++]; 817 ch->buffer = b; 818 ch->parent = sc; 819 ch->channel = c; 820 ch->blksz = sc->bufsz / 2; 821 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 822 ch->spd = 8000; 823 snd_mtxlock(sc->lock); 824 ch->master = emu_valloc(sc); 825 ch->slave = emu_valloc(sc); 826 snd_mtxunlock(sc->lock); 827 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer)) 828 ? NULL : ch; 829 830 return r; 831 } 832 833 static int 834 emupchan_free(kobj_t obj, void *data) 835 { 836 struct sc_pchinfo *ch = data; 837 struct sc_info *sc = ch->parent; 838 int r; 839 840 snd_mtxlock(sc->lock); 841 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer)); 842 snd_mtxunlock(sc->lock); 843 844 return r; 845 } 846 847 static int 848 emupchan_setformat(kobj_t obj, void *data, u_int32_t format) 849 { 850 struct sc_pchinfo *ch = data; 851 852 ch->fmt = format; 853 return 0; 854 } 855 856 static u_int32_t 857 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 858 { 859 struct sc_pchinfo *ch = data; 860 861 ch->spd = speed; 862 return ch->spd; 863 } 864 865 static u_int32_t 866 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 867 { 868 struct sc_pchinfo *ch = data; 869 struct sc_info *sc = ch->parent; 870 871 ch->blksz = blocksize; 872 snd_mtxlock(sc->lock); 873 emu_settimer(sc); 874 snd_mtxunlock(sc->lock); 875 return blocksize; 876 } 877 878 static int 879 emupchan_trigger(kobj_t obj, void *data, int go) 880 { 881 struct sc_pchinfo *ch = data; 882 struct sc_info *sc = ch->parent; 883 884 if (!PCMTRIG_COMMON(go)) 885 return 0; 886 887 snd_mtxlock(sc->lock); 888 if (go == PCMTRIG_START) { 889 emu_vsetup(ch); 890 emu_vwrite(sc, ch->master); 891 emu_settimer(sc); 892 emu_enatimer(sc, 1); 893 #ifdef EMUDEBUG 894 printf("start [%d bit, %s, %d hz]\n", 895 ch->master->b16 ? 16 : 8, 896 ch->master->stereo ? "stereo" : "mono", 897 ch->master->speed); 898 emu_vdump(sc, ch->master); 899 emu_vdump(sc, ch->slave); 900 #endif 901 } 902 ch->run = (go == PCMTRIG_START) ? 1 : 0; 903 emu_vtrigger(sc, ch->master, ch->run); 904 snd_mtxunlock(sc->lock); 905 return 0; 906 } 907 908 static u_int32_t 909 emupchan_getptr(kobj_t obj, void *data) 910 { 911 struct sc_pchinfo *ch = data; 912 struct sc_info *sc = ch->parent; 913 int r; 914 915 snd_mtxlock(sc->lock); 916 r = emu_vpos(sc, ch->master); 917 snd_mtxunlock(sc->lock); 918 919 return r; 920 } 921 922 static struct pcmchan_caps * 923 emupchan_getcaps(kobj_t obj, void *data) 924 { 925 return &emu_playcaps; 926 } 927 928 static kobj_method_t emupchan_methods[] = { 929 KOBJMETHOD(channel_init, emupchan_init), 930 KOBJMETHOD(channel_free, emupchan_free), 931 KOBJMETHOD(channel_setformat, emupchan_setformat), 932 KOBJMETHOD(channel_setspeed, emupchan_setspeed), 933 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize), 934 KOBJMETHOD(channel_trigger, emupchan_trigger), 935 KOBJMETHOD(channel_getptr, emupchan_getptr), 936 KOBJMETHOD(channel_getcaps, emupchan_getcaps), 937 KOBJMETHOD_END 938 }; 939 CHANNEL_DECLARE(emupchan); 940 941 /* channel interface */ 942 static void * 943 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 944 struct pcm_channel *c, int dir) 945 { 946 struct sc_info *sc = devinfo; 947 struct sc_rchinfo *ch; 948 949 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction")); 950 ch = &sc->rch[sc->rnum]; 951 ch->buffer = b; 952 ch->parent = sc; 953 ch->channel = c; 954 ch->blksz = sc->bufsz / 2; 955 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 956 ch->spd = 8000; 957 ch->num = sc->rnum; 958 switch(sc->rnum) { 959 case 0: 960 ch->idxreg = sc->audigy ? EMU_A_ADCIDX : EMU_ADCIDX; 961 ch->basereg = EMU_ADCBA; 962 ch->sizereg = EMU_ADCBS; 963 ch->setupreg = EMU_ADCCR; 964 ch->irqmask = EMU_INTE_ADCBUFENABLE; 965 break; 966 967 case 1: 968 ch->idxreg = EMU_FXIDX; 969 ch->basereg = EMU_FXBA; 970 ch->sizereg = EMU_FXBS; 971 ch->setupreg = EMU_FXWC; 972 ch->irqmask = EMU_INTE_EFXBUFENABLE; 973 break; 974 975 case 2: 976 ch->idxreg = EMU_MICIDX; 977 ch->basereg = EMU_MICBA; 978 ch->sizereg = EMU_MICBS; 979 ch->setupreg = 0; 980 ch->irqmask = EMU_INTE_MICBUFENABLE; 981 break; 982 } 983 sc->rnum++; 984 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) 985 return NULL; 986 else { 987 snd_mtxlock(sc->lock); 988 emu_wrptr(sc, 0, ch->basereg, sndbuf_getbufaddr(ch->buffer)); 989 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */ 990 snd_mtxunlock(sc->lock); 991 return ch; 992 } 993 } 994 995 static int 996 emurchan_setformat(kobj_t obj, void *data, u_int32_t format) 997 { 998 struct sc_rchinfo *ch = data; 999 1000 ch->fmt = format; 1001 return 0; 1002 } 1003 1004 static u_int32_t 1005 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 1006 { 1007 struct sc_rchinfo *ch = data; 1008 1009 if (ch->num == 0) { 1010 if (ch->parent->audigy) 1011 speed = audigy_adcspeed[audigy_recval(speed)]; 1012 else 1013 speed = adcspeed[emu_recval(speed)]; 1014 } 1015 if (ch->num == 1) 1016 speed = 48000; 1017 if (ch->num == 2) 1018 speed = 8000; 1019 ch->spd = speed; 1020 return ch->spd; 1021 } 1022 1023 static u_int32_t 1024 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 1025 { 1026 struct sc_rchinfo *ch = data; 1027 struct sc_info *sc = ch->parent; 1028 1029 ch->blksz = blocksize; 1030 snd_mtxlock(sc->lock); 1031 emu_settimer(sc); 1032 snd_mtxunlock(sc->lock); 1033 return blocksize; 1034 } 1035 1036 /* semantic note: must start at beginning of buffer */ 1037 static int 1038 emurchan_trigger(kobj_t obj, void *data, int go) 1039 { 1040 struct sc_rchinfo *ch = data; 1041 struct sc_info *sc = ch->parent; 1042 u_int32_t val, sz; 1043 1044 if (!PCMTRIG_COMMON(go)) 1045 return 0; 1046 1047 switch(sc->bufsz) { 1048 case 4096: 1049 sz = EMU_RECBS_BUFSIZE_4096; 1050 break; 1051 1052 case 8192: 1053 sz = EMU_RECBS_BUFSIZE_8192; 1054 break; 1055 1056 case 16384: 1057 sz = EMU_RECBS_BUFSIZE_16384; 1058 break; 1059 1060 case 32768: 1061 sz = EMU_RECBS_BUFSIZE_32768; 1062 break; 1063 1064 case 65536: 1065 sz = EMU_RECBS_BUFSIZE_65536; 1066 break; 1067 1068 default: 1069 sz = EMU_RECBS_BUFSIZE_4096; 1070 } 1071 1072 snd_mtxlock(sc->lock); 1073 switch(go) { 1074 case PCMTRIG_START: 1075 ch->run = 1; 1076 emu_wrptr(sc, 0, ch->sizereg, sz); 1077 if (ch->num == 0) { 1078 if (sc->audigy) { 1079 val = EMU_A_ADCCR_LCHANENABLE; 1080 if (AFMT_CHANNEL(ch->fmt) > 1) 1081 val |= EMU_A_ADCCR_RCHANENABLE; 1082 val |= audigy_recval(ch->spd); 1083 } else { 1084 val = EMU_ADCCR_LCHANENABLE; 1085 if (AFMT_CHANNEL(ch->fmt) > 1) 1086 val |= EMU_ADCCR_RCHANENABLE; 1087 val |= emu_recval(ch->spd); 1088 } 1089 1090 emu_wrptr(sc, 0, ch->setupreg, 0); 1091 emu_wrptr(sc, 0, ch->setupreg, val); 1092 } 1093 val = emu_rd(sc, EMU_INTE, 4); 1094 val |= ch->irqmask; 1095 emu_wr(sc, EMU_INTE, val, 4); 1096 break; 1097 1098 case PCMTRIG_STOP: 1099 case PCMTRIG_ABORT: 1100 ch->run = 0; 1101 emu_wrptr(sc, 0, ch->sizereg, 0); 1102 if (ch->setupreg) 1103 emu_wrptr(sc, 0, ch->setupreg, 0); 1104 val = emu_rd(sc, EMU_INTE, 4); 1105 val &= ~ch->irqmask; 1106 emu_wr(sc, EMU_INTE, val, 4); 1107 break; 1108 1109 case PCMTRIG_EMLDMAWR: 1110 case PCMTRIG_EMLDMARD: 1111 default: 1112 break; 1113 } 1114 snd_mtxunlock(sc->lock); 1115 1116 return 0; 1117 } 1118 1119 static u_int32_t 1120 emurchan_getptr(kobj_t obj, void *data) 1121 { 1122 struct sc_rchinfo *ch = data; 1123 struct sc_info *sc = ch->parent; 1124 int r; 1125 1126 snd_mtxlock(sc->lock); 1127 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff; 1128 snd_mtxunlock(sc->lock); 1129 1130 return r; 1131 } 1132 1133 static struct pcmchan_caps * 1134 emurchan_getcaps(kobj_t obj, void *data) 1135 { 1136 struct sc_rchinfo *ch = data; 1137 1138 return &emu_reccaps[ch->num]; 1139 } 1140 1141 static kobj_method_t emurchan_methods[] = { 1142 KOBJMETHOD(channel_init, emurchan_init), 1143 KOBJMETHOD(channel_setformat, emurchan_setformat), 1144 KOBJMETHOD(channel_setspeed, emurchan_setspeed), 1145 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize), 1146 KOBJMETHOD(channel_trigger, emurchan_trigger), 1147 KOBJMETHOD(channel_getptr, emurchan_getptr), 1148 KOBJMETHOD(channel_getcaps, emurchan_getcaps), 1149 KOBJMETHOD_END 1150 }; 1151 CHANNEL_DECLARE(emurchan); 1152 1153 static unsigned char 1154 emu_mread(struct mpu401 *arg, void *sc, int reg) 1155 { 1156 unsigned int d; 1157 1158 d = emu_rd((struct sc_info *)sc, 0x18 + reg, 1); 1159 return d; 1160 } 1161 1162 static void 1163 emu_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b) 1164 { 1165 1166 emu_wr((struct sc_info *)sc, 0x18 + reg, b, 1); 1167 } 1168 1169 static int 1170 emu_muninit(struct mpu401 *arg, void *cookie) 1171 { 1172 struct sc_info *sc = cookie; 1173 1174 snd_mtxlock(sc->lock); 1175 sc->mpu_intr = NULL; 1176 snd_mtxunlock(sc->lock); 1177 1178 return 0; 1179 } 1180 1181 static kobj_method_t emu_mpu_methods[] = { 1182 KOBJMETHOD(mpufoi_read, emu_mread), 1183 KOBJMETHOD(mpufoi_write, emu_mwrite), 1184 KOBJMETHOD(mpufoi_uninit, emu_muninit), 1185 KOBJMETHOD_END 1186 }; 1187 1188 static DEFINE_CLASS(emu_mpu, emu_mpu_methods, 0); 1189 1190 static void 1191 emu_intr2(void *p) 1192 { 1193 struct sc_info *sc = (struct sc_info *)p; 1194 1195 if (sc->mpu_intr) 1196 (sc->mpu_intr)(sc->mpu); 1197 } 1198 1199 static void 1200 emu_midiattach(struct sc_info *sc) 1201 { 1202 int i; 1203 1204 i = emu_rd(sc, EMU_INTE, 4); 1205 i |= EMU_INTE_MIDIRXENABLE; 1206 emu_wr(sc, EMU_INTE, i, 4); 1207 1208 sc->mpu = mpu401_init(&emu_mpu_class, sc, emu_intr2, &sc->mpu_intr); 1209 } 1210 /* -------------------------------------------------------------------- */ 1211 /* The interrupt handler */ 1212 1213 static void 1214 emu_intr(void *data) 1215 { 1216 struct sc_info *sc = data; 1217 u_int32_t stat, ack, i, x; 1218 1219 snd_mtxlock(sc->lock); 1220 while (1) { 1221 stat = emu_rd(sc, EMU_IPR, 4); 1222 if (stat == 0) 1223 break; 1224 ack = 0; 1225 1226 /* process irq */ 1227 if (stat & EMU_IPR_INTERVALTIMER) 1228 ack |= EMU_IPR_INTERVALTIMER; 1229 1230 if (stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL)) 1231 ack |= stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL); 1232 1233 if (stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL)) 1234 ack |= stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL); 1235 1236 if (stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL)) 1237 ack |= stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL); 1238 1239 if (stat & EMU_PCIERROR) { 1240 ack |= EMU_PCIERROR; 1241 device_printf(sc->dev, "pci error\n"); 1242 /* we still get an nmi with ecc ram even if we ack this */ 1243 } 1244 if (stat & EMU_IPR_RATETRCHANGE) { 1245 ack |= EMU_IPR_RATETRCHANGE; 1246 #ifdef EMUDEBUG 1247 device_printf(sc->dev, 1248 "sample rate tracker lock status change\n"); 1249 #endif 1250 } 1251 1252 if (stat & EMU_IPR_MIDIRECVBUFE) { 1253 if (sc->mpu_intr) { 1254 (sc->mpu_intr)(sc->mpu); 1255 ack |= EMU_IPR_MIDIRECVBUFE | EMU_IPR_MIDITRANSBUFE; 1256 } 1257 } 1258 if (stat & ~ack) 1259 device_printf(sc->dev, "dodgy irq: %x (harmless)\n", 1260 stat & ~ack); 1261 1262 emu_wr(sc, EMU_IPR, stat, 4); 1263 1264 if (ack) { 1265 snd_mtxunlock(sc->lock); 1266 1267 if (ack & EMU_IPR_INTERVALTIMER) { 1268 x = 0; 1269 for (i = 0; i < sc->nchans; i++) { 1270 if (sc->pch[i].run) { 1271 x = 1; 1272 chn_intr(sc->pch[i].channel); 1273 } 1274 } 1275 if (x == 0) 1276 emu_enatimer(sc, 0); 1277 } 1278 1279 if (ack & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL)) { 1280 if (sc->rch[0].channel) 1281 chn_intr(sc->rch[0].channel); 1282 } 1283 if (ack & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL)) { 1284 if (sc->rch[1].channel) 1285 chn_intr(sc->rch[1].channel); 1286 } 1287 if (ack & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL)) { 1288 if (sc->rch[2].channel) 1289 chn_intr(sc->rch[2].channel); 1290 } 1291 1292 snd_mtxlock(sc->lock); 1293 } 1294 } 1295 snd_mtxunlock(sc->lock); 1296 } 1297 1298 /* -------------------------------------------------------------------- */ 1299 1300 static void 1301 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1302 { 1303 bus_addr_t *phys = arg; 1304 1305 *phys = error ? 0 : (bus_addr_t)segs->ds_addr; 1306 1307 if (bootverbose) { 1308 printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n", 1309 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len, 1310 nseg, error); 1311 } 1312 } 1313 1314 static void * 1315 emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr, 1316 bus_dmamap_t *map) 1317 { 1318 void *buf; 1319 1320 *addr = 0; 1321 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, map)) 1322 return NULL; 1323 if (bus_dmamap_load(sc->parent_dmat, *map, buf, sz, emu_setmap, addr, 1324 BUS_DMA_NOWAIT) || !*addr) { 1325 bus_dmamem_free(sc->parent_dmat, buf, *map); 1326 return NULL; 1327 } 1328 return buf; 1329 } 1330 1331 static void 1332 emu_free(struct sc_info *sc, void *buf, bus_dmamap_t map) 1333 { 1334 bus_dmamap_unload(sc->parent_dmat, map); 1335 bus_dmamem_free(sc->parent_dmat, buf, map); 1336 } 1337 1338 static void * 1339 emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr) 1340 { 1341 u_int32_t blksz, start, idx, ofs, tmp, found; 1342 struct emu_mem *mem = &sc->mem; 1343 struct emu_memblk *blk; 1344 void *buf; 1345 1346 blksz = sz / EMUPAGESIZE; 1347 if (sz > (blksz * EMUPAGESIZE)) 1348 blksz++; 1349 /* find a free block in the bitmap */ 1350 found = 0; 1351 start = 1; 1352 while (!found && start + blksz < EMUMAXPAGES) { 1353 found = 1; 1354 for (idx = start; idx < start + blksz; idx++) 1355 if (mem->bmap[idx >> 3] & (1 << (idx & 7))) 1356 found = 0; 1357 if (!found) 1358 start++; 1359 } 1360 if (!found) 1361 return NULL; 1362 blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT); 1363 if (blk == NULL) 1364 return NULL; 1365 buf = emu_malloc(sc, sz, &blk->buf_addr, &blk->buf_map); 1366 *addr = blk->buf_addr; 1367 if (buf == NULL) { 1368 free(blk, M_DEVBUF); 1369 return NULL; 1370 } 1371 blk->buf = buf; 1372 blk->pte_start = start; 1373 blk->pte_size = blksz; 1374 #ifdef EMUDEBUG 1375 printf("buf %p, pte_start %d, pte_size %d\n", blk->buf, 1376 blk->pte_start, blk->pte_size); 1377 #endif 1378 ofs = 0; 1379 for (idx = start; idx < start + blksz; idx++) { 1380 mem->bmap[idx >> 3] |= 1 << (idx & 7); 1381 tmp = (uint32_t)(blk->buf_addr + ofs); 1382 #ifdef EMUDEBUG 1383 printf("pte[%d] -> %x phys, %x virt\n", idx, tmp, 1384 ((u_int32_t)buf) + ofs); 1385 #endif 1386 mem->ptb_pages[idx] = (tmp << 1) | idx; 1387 ofs += EMUPAGESIZE; 1388 } 1389 SLIST_INSERT_HEAD(&mem->blocks, blk, link); 1390 return buf; 1391 } 1392 1393 static int 1394 emu_memfree(struct sc_info *sc, void *buf) 1395 { 1396 u_int32_t idx, tmp; 1397 struct emu_mem *mem = &sc->mem; 1398 struct emu_memblk *blk, *i; 1399 1400 blk = NULL; 1401 SLIST_FOREACH(i, &mem->blocks, link) { 1402 if (i->buf == buf) 1403 blk = i; 1404 } 1405 if (blk == NULL) 1406 return EINVAL; 1407 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link); 1408 emu_free(sc, buf, blk->buf_map); 1409 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1410 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) { 1411 mem->bmap[idx >> 3] &= ~(1 << (idx & 7)); 1412 mem->ptb_pages[idx] = tmp | idx; 1413 } 1414 free(blk, M_DEVBUF); 1415 return 0; 1416 } 1417 1418 static int 1419 emu_memstart(struct sc_info *sc, void *buf) 1420 { 1421 struct emu_mem *mem = &sc->mem; 1422 struct emu_memblk *blk, *i; 1423 1424 blk = NULL; 1425 SLIST_FOREACH(i, &mem->blocks, link) { 1426 if (i->buf == buf) 1427 blk = i; 1428 } 1429 if (blk == NULL) 1430 return -EINVAL; 1431 return blk->pte_start; 1432 } 1433 1434 static void 1435 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1436 u_int32_t *pc) 1437 { 1438 emu_wrefx(sc, (*pc) * 2, (x << 10) | y); 1439 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w); 1440 (*pc)++; 1441 } 1442 1443 static void 1444 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1445 u_int32_t *pc) 1446 { 1447 emu_wrefx(sc, (*pc) * 2, (x << 12) | y); 1448 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w); 1449 (*pc)++; 1450 } 1451 1452 static void 1453 audigy_initefx(struct sc_info *sc) 1454 { 1455 int i; 1456 u_int32_t pc = 0; 1457 1458 /* skip 0, 0, -1, 0 - NOPs */ 1459 for (i = 0; i < 512; i++) 1460 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc); 1461 1462 for (i = 0; i < 512; i++) 1463 emu_wrptr(sc, 0, EMU_A_FXGPREGBASE + i, 0x0); 1464 1465 pc = 16; 1466 1467 /* stop fx processor */ 1468 emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP); 1469 1470 /* Audigy 2 (EMU10K2) DSP Registers: 1471 FX Bus 1472 0x000-0x00f : 16 registers (?) 1473 Input 1474 0x040/0x041 : AC97 Codec (l/r) 1475 0x042/0x043 : ADC, S/PDIF (l/r) 1476 0x044/0x045 : Optical S/PDIF in (l/r) 1477 0x046/0x047 : ? 1478 0x048/0x049 : Line/Mic 2 (l/r) 1479 0x04a/0x04b : RCA S/PDIF (l/r) 1480 0x04c/0x04d : Aux 2 (l/r) 1481 Output 1482 0x060/0x061 : Digital Front (l/r) 1483 0x062/0x063 : Digital Center/LFE 1484 0x064/0x065 : AudigyDrive Heaphone (l/r) 1485 0x066/0x067 : Digital Rear (l/r) 1486 0x068/0x069 : Analog Front (l/r) 1487 0x06a/0x06b : Analog Center/LFE 1488 0x06c/0x06d : ? 1489 0x06e/0x06f : Analog Rear (l/r) 1490 0x070/0x071 : AC97 Output (l/r) 1491 0x072/0x073 : ? 1492 0x074/0x075 : ? 1493 0x076/0x077 : ADC Recording Buffer (l/r) 1494 Constants 1495 0x0c0 - 0x0c4 = 0 - 4 1496 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20 1497 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000 1498 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000 1499 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff 1500 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc 1501 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (?) 1502 Temporary Values 1503 0x0d6 : Accumulator (?) 1504 0x0d7 : Condition Register 1505 0x0d8 : Noise source 1506 0x0d9 : Noise source 1507 Tank Memory Data Registers 1508 0x200 - 0x2ff 1509 Tank Memory Address Registers 1510 0x300 - 0x3ff 1511 General Purpose Registers 1512 0x400 - 0x5ff 1513 */ 1514 1515 /* AC97Output[l/r] = FXBus PCM[l/r] */ 1516 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000, 1517 A_C_00000000, A_FXBUS(FXBUS_PCM_LEFT), &pc); 1518 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000, 1519 A_C_00000000, A_FXBUS(FXBUS_PCM_RIGHT), &pc); 1520 1521 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */ 1522 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000, 1523 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_L), &pc); 1524 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000, 1525 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_R), &pc); 1526 1527 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1528 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1), 1529 A_C_40000000, A_GPR(0), &pc); 1530 1531 /* Headphones[l/r] = GPR[0/1] */ 1532 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L), 1533 A_C_00000000, A_C_00000000, A_GPR(0), &pc); 1534 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R), 1535 A_C_00000000, A_C_00000000, A_GPR(1), &pc); 1536 1537 /* Analog Front[l/r] = GPR[0/1] */ 1538 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000, 1539 A_C_00000000, A_GPR(0), &pc); 1540 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000, 1541 A_C_00000000, A_GPR(1), &pc); 1542 1543 /* Digital Front[l/r] = GPR[0/1] */ 1544 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000, 1545 A_C_00000000, A_GPR(0), &pc); 1546 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000, 1547 A_C_00000000, A_GPR(1), &pc); 1548 1549 /* Center and Subwoofer configuration */ 1550 /* Analog Center = GPR[0] + GPR[2] */ 1551 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000, 1552 A_GPR(0), A_GPR(2), &pc); 1553 /* Analog Sub = GPR[1] + GPR[2] */ 1554 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000, 1555 A_GPR(1), A_GPR(2), &pc); 1556 1557 /* Digital Center = GPR[0] + GPR[2] */ 1558 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000, 1559 A_GPR(0), A_GPR(2), &pc); 1560 /* Digital Sub = GPR[1] + GPR[2] */ 1561 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000, 1562 A_GPR(1), A_GPR(2), &pc); 1563 1564 #if 0 1565 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1566 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1567 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1568 A_GPR(16), A_GPR(0), &pc); 1569 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1570 A_GPR(17), A_GPR(1), &pc); 1571 1572 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1573 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1574 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1575 A_GPR(16), A_GPR(0), &pc); 1576 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1577 A_GPR(17), A_GPR(1), &pc); 1578 #else 1579 /* XXX This is just a copy to the channel, since we do not have 1580 * a patch manager, it is useful for have another output enabled. 1581 */ 1582 1583 /* Analog Rear[l/r] = GPR[0/1] */ 1584 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1585 A_C_00000000, A_GPR(0), &pc); 1586 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1587 A_C_00000000, A_GPR(1), &pc); 1588 1589 /* Digital Rear[l/r] = GPR[0/1] */ 1590 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1591 A_C_00000000, A_GPR(0), &pc); 1592 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1593 A_C_00000000, A_GPR(1), &pc); 1594 #endif 1595 1596 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1597 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000, 1598 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc); 1599 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000, 1600 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc); 1601 1602 /* resume normal operations */ 1603 emu_wrptr(sc, 0, EMU_A_DBG, 0); 1604 } 1605 1606 static void 1607 emu_initefx(struct sc_info *sc) 1608 { 1609 int i; 1610 u_int32_t pc = 16; 1611 1612 /* acc3 0,0,0,0 - NOPs */ 1613 for (i = 0; i < 512; i++) { 1614 emu_wrefx(sc, i * 2, 0x10040); 1615 emu_wrefx(sc, i * 2 + 1, 0x610040); 1616 } 1617 1618 for (i = 0; i < 256; i++) 1619 emu_wrptr(sc, 0, EMU_FXGPREGBASE + i, 0); 1620 1621 /* FX-8010 DSP Registers: 1622 FX Bus 1623 0x000-0x00f : 16 registers 1624 Input 1625 0x010/0x011 : AC97 Codec (l/r) 1626 0x012/0x013 : ADC, S/PDIF (l/r) 1627 0x014/0x015 : Mic(left), Zoom (l/r) 1628 0x016/0x017 : TOS link in (l/r) 1629 0x018/0x019 : Line/Mic 1 (l/r) 1630 0x01a/0x01b : COAX S/PDIF (l/r) 1631 0x01c/0x01d : Line/Mic 2 (l/r) 1632 Output 1633 0x020/0x021 : AC97 Output (l/r) 1634 0x022/0x023 : TOS link out (l/r) 1635 0x024/0x025 : Center/LFE 1636 0x026/0x027 : LiveDrive Headphone (l/r) 1637 0x028/0x029 : Rear Channel (l/r) 1638 0x02a/0x02b : ADC Recording Buffer (l/r) 1639 0x02c : Mic Recording Buffer 1640 0x031/0x032 : Analog Center/LFE 1641 Constants 1642 0x040 - 0x044 = 0 - 4 1643 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20 1644 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000 1645 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000 1646 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff 1647 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc 1648 0x054 = 0x5a7ef9db, 0x055 = 0x00100000 1649 Temporary Values 1650 0x056 : Accumulator 1651 0x057 : Condition Register 1652 0x058 : Noise source 1653 0x059 : Noise source 1654 0x05a : IRQ Register 1655 0x05b : TRAM Delay Base Address Count 1656 General Purpose Registers 1657 0x100 - 0x1ff 1658 Tank Memory Data Registers 1659 0x200 - 0x2ff 1660 Tank Memory Address Registers 1661 0x300 - 0x3ff 1662 */ 1663 1664 /* Routing - this will be configurable in later version */ 1665 1666 /* GPR[0/1] = FX * 4 + SPDIF-in */ 1667 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L), 1668 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc); 1669 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R), 1670 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc); 1671 1672 /* GPR[0/1] += APS-input */ 1673 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000, 1674 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc); 1675 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000, 1676 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc); 1677 1678 /* FrontOut (AC97) = GPR[0/1] */ 1679 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000, 1680 C_00000000, GPR(0), &pc); 1681 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000, 1682 C_00000001, GPR(1), &pc); 1683 1684 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1685 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc); 1686 1687 #if 0 1688 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */ 1689 /* RearVolume = GPR[0x10/0x11] */ 1690 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000, 1691 GPR(16), GPR(0), &pc); 1692 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000, 1693 GPR(17), GPR(1), &pc); 1694 #else 1695 /* XXX This is just a copy to the channel, since we do not have 1696 * a patch manager, it is useful for have another output enabled. 1697 */ 1698 1699 /* Rear[l/r] = GPR[0/1] */ 1700 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000, 1701 C_00000000, GPR(0), &pc); 1702 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000, 1703 C_00000000, GPR(1), &pc); 1704 #endif 1705 1706 /* TOS out[l/r] = GPR[0/1] */ 1707 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000, 1708 C_00000000, GPR(0), &pc); 1709 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000, 1710 C_00000000, GPR(1), &pc); 1711 1712 /* Center and Subwoofer configuration */ 1713 /* Analog Center = GPR[0] + GPR[2] */ 1714 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000, 1715 GPR(0), GPR(2), &pc); 1716 /* Analog Sub = GPR[1] + GPR[2] */ 1717 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000, 1718 GPR(1), GPR(2), &pc); 1719 /* Digital Center = GPR[0] + GPR[2] */ 1720 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_CENTER), C_00000000, 1721 GPR(0), GPR(2), &pc); 1722 /* Digital Sub = GPR[1] + GPR[2] */ 1723 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_LFE), C_00000000, 1724 GPR(1), GPR(2), &pc); 1725 1726 /* Headphones[l/r] = GPR[0/1] */ 1727 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000, 1728 C_00000000, GPR(0), &pc); 1729 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000, 1730 C_00000000, GPR(1), &pc); 1731 1732 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1733 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000, 1734 C_00000000, EXTIN(EXTIN_AC97_L), &pc); 1735 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000, 1736 C_00000000, EXTIN(EXTIN_AC97_R), &pc); 1737 1738 /* resume normal operations */ 1739 emu_wrptr(sc, 0, EMU_DBG, 0); 1740 } 1741 1742 /* Probe and attach the card */ 1743 static int 1744 emu_init(struct sc_info *sc) 1745 { 1746 u_int32_t spcs, ch, tmp, i; 1747 1748 if (sc->audigy) { 1749 /* enable additional AC97 slots */ 1750 emu_wrptr(sc, 0, EMU_AC97SLOT, EMU_AC97SLOT_CENTER | EMU_AC97SLOT_LFE); 1751 } 1752 1753 /* disable audio and lock cache */ 1754 emu_wr(sc, EMU_HCFG, 1755 EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE, 1756 4); 1757 1758 /* reset recording buffers */ 1759 emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE); 1760 emu_wrptr(sc, 0, EMU_MICBA, 0); 1761 emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE); 1762 emu_wrptr(sc, 0, EMU_FXBA, 0); 1763 emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE); 1764 emu_wrptr(sc, 0, EMU_ADCBA, 0); 1765 1766 /* disable channel interrupt */ 1767 emu_wr(sc, EMU_INTE, 1768 EMU_INTE_INTERTIMERENB | EMU_INTE_SAMPLERATER | EMU_INTE_PCIERRENABLE, 1769 4); 1770 emu_wrptr(sc, 0, EMU_CLIEL, 0); 1771 emu_wrptr(sc, 0, EMU_CLIEH, 0); 1772 emu_wrptr(sc, 0, EMU_SOLEL, 0); 1773 emu_wrptr(sc, 0, EMU_SOLEH, 0); 1774 1775 /* wonder what these do... */ 1776 if (sc->audigy) { 1777 emu_wrptr(sc, 0, EMU_SPBYPASS, 0xf00); 1778 emu_wrptr(sc, 0, EMU_AC97SLOT, 0x3); 1779 } 1780 1781 /* init envelope engine */ 1782 for (ch = 0; ch < NUM_G; ch++) { 1783 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF); 1784 emu_wrptr(sc, ch, EMU_CHAN_IP, 0); 1785 emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0xffff); 1786 emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0xffff); 1787 emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0); 1788 emu_wrptr(sc, ch, EMU_CHAN_CPF, 0); 1789 emu_wrptr(sc, ch, EMU_CHAN_CCR, 0); 1790 1791 emu_wrptr(sc, ch, EMU_CHAN_PSST, 0); 1792 emu_wrptr(sc, ch, EMU_CHAN_DSL, 0x10); 1793 emu_wrptr(sc, ch, EMU_CHAN_CCCA, 0); 1794 emu_wrptr(sc, ch, EMU_CHAN_Z1, 0); 1795 emu_wrptr(sc, ch, EMU_CHAN_Z2, 0); 1796 emu_wrptr(sc, ch, EMU_CHAN_FXRT, 0xd01c0000); 1797 1798 emu_wrptr(sc, ch, EMU_CHAN_ATKHLDM, 0); 1799 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSM, 0); 1800 emu_wrptr(sc, ch, EMU_CHAN_IFATN, 0xffff); 1801 emu_wrptr(sc, ch, EMU_CHAN_PEFE, 0); 1802 emu_wrptr(sc, ch, EMU_CHAN_FMMOD, 0); 1803 emu_wrptr(sc, ch, EMU_CHAN_TREMFRQ, 24); /* 1 Hz */ 1804 emu_wrptr(sc, ch, EMU_CHAN_FM2FRQ2, 24); /* 1 Hz */ 1805 emu_wrptr(sc, ch, EMU_CHAN_TEMPENV, 0); 1806 1807 /*** these are last so OFF prevents writing ***/ 1808 emu_wrptr(sc, ch, EMU_CHAN_LFOVAL2, 0); 1809 emu_wrptr(sc, ch, EMU_CHAN_LFOVAL1, 0); 1810 emu_wrptr(sc, ch, EMU_CHAN_ATKHLDV, 0); 1811 emu_wrptr(sc, ch, EMU_CHAN_ENVVOL, 0); 1812 emu_wrptr(sc, ch, EMU_CHAN_ENVVAL, 0); 1813 1814 if (sc->audigy) { 1815 /* audigy cards need this to initialize correctly */ 1816 emu_wrptr(sc, ch, 0x4c, 0); 1817 emu_wrptr(sc, ch, 0x4d, 0); 1818 emu_wrptr(sc, ch, 0x4e, 0); 1819 emu_wrptr(sc, ch, 0x4f, 0); 1820 /* set default routing */ 1821 emu_wrptr(sc, ch, EMU_A_CHAN_FXRT1, 0x03020100); 1822 emu_wrptr(sc, ch, EMU_A_CHAN_FXRT2, 0x3f3f3f3f); 1823 emu_wrptr(sc, ch, EMU_A_CHAN_SENDAMOUNTS, 0); 1824 } 1825 1826 sc->voice[ch].vnum = ch; 1827 sc->voice[ch].slave = NULL; 1828 sc->voice[ch].busy = 0; 1829 sc->voice[ch].ismaster = 0; 1830 sc->voice[ch].running = 0; 1831 sc->voice[ch].b16 = 0; 1832 sc->voice[ch].stereo = 0; 1833 sc->voice[ch].speed = 0; 1834 sc->voice[ch].start = 0; 1835 sc->voice[ch].end = 0; 1836 sc->voice[ch].channel = NULL; 1837 } 1838 sc->pnum = sc->rnum = 0; 1839 1840 /* 1841 * Init to 0x02109204 : 1842 * Clock accuracy = 0 (1000ppm) 1843 * Sample Rate = 2 (48kHz) 1844 * Audio Channel = 1 (Left of 2) 1845 * Source Number = 0 (Unspecified) 1846 * Generation Status = 1 (Original for Cat Code 12) 1847 * Cat Code = 12 (Digital Signal Mixer) 1848 * Mode = 0 (Mode 0) 1849 * Emphasis = 0 (None) 1850 * CP = 1 (Copyright unasserted) 1851 * AN = 0 (Audio data) 1852 * P = 0 (Consumer) 1853 */ 1854 spcs = EMU_SPCS_CLKACCY_1000PPM | EMU_SPCS_SAMPLERATE_48 | 1855 EMU_SPCS_CHANNELNUM_LEFT | EMU_SPCS_SOURCENUM_UNSPEC | 1856 EMU_SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 | 1857 EMU_SPCS_EMPHASIS_NONE | EMU_SPCS_COPYRIGHT; 1858 emu_wrptr(sc, 0, EMU_SPCS0, spcs); 1859 emu_wrptr(sc, 0, EMU_SPCS1, spcs); 1860 emu_wrptr(sc, 0, EMU_SPCS2, spcs); 1861 1862 if (!sc->audigy) 1863 emu_initefx(sc); 1864 else if (sc->audigy2) { /* Audigy 2 */ 1865 /* from ALSA initialization code: */ 1866 1867 /* Hack for Alice3 to work independent of haP16V driver */ 1868 u_int32_t tmp; 1869 1870 /* Setup SRCMulti_I2S SamplingRate */ 1871 tmp = emu_rdptr(sc, 0, EMU_A_SPDIF_SAMPLERATE) & 0xfffff1ff; 1872 emu_wrptr(sc, 0, EMU_A_SPDIF_SAMPLERATE, tmp | 0x400); 1873 1874 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */ 1875 emu_wr(sc, 0x20, 0x00600000, 4); 1876 emu_wr(sc, 0x24, 0x00000014, 4); 1877 1878 /* Setup SRCMulti Input Audio Enable */ 1879 emu_wr(sc, 0x20, 0x006e0000, 4); 1880 emu_wr(sc, 0x24, 0xff00ff00, 4); 1881 } 1882 1883 SLIST_INIT(&sc->mem.blocks); 1884 sc->mem.ptb_pages = emu_malloc(sc, EMUMAXPAGES * sizeof(u_int32_t), 1885 &sc->mem.ptb_pages_addr, &sc->mem.ptb_map); 1886 if (sc->mem.ptb_pages == NULL) 1887 return -1; 1888 1889 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE, 1890 &sc->mem.silent_page_addr, &sc->mem.silent_map); 1891 if (sc->mem.silent_page == NULL) { 1892 emu_free(sc, sc->mem.ptb_pages, sc->mem.ptb_map); 1893 return -1; 1894 } 1895 /* Clear page with silence & setup all pointers to this page */ 1896 bzero(sc->mem.silent_page, EMUPAGESIZE); 1897 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1898 for (i = 0; i < EMUMAXPAGES; i++) 1899 sc->mem.ptb_pages[i] = tmp | i; 1900 1901 emu_wrptr(sc, 0, EMU_PTB, (sc->mem.ptb_pages_addr)); 1902 emu_wrptr(sc, 0, EMU_TCB, 0); /* taken from original driver */ 1903 emu_wrptr(sc, 0, EMU_TCBS, 0); /* taken from original driver */ 1904 1905 for (ch = 0; ch < NUM_G; ch++) { 1906 emu_wrptr(sc, ch, EMU_CHAN_MAPA, tmp | EMU_CHAN_MAP_PTI_MASK); 1907 emu_wrptr(sc, ch, EMU_CHAN_MAPB, tmp | EMU_CHAN_MAP_PTI_MASK); 1908 } 1909 1910 /* emu_memalloc(sc, EMUPAGESIZE); */ 1911 /* 1912 * Hokay, now enable the AUD bit 1913 * 1914 * Audigy 1915 * Enable Audio = 0 (enabled after fx processor initialization) 1916 * Mute Disable Audio = 0 1917 * Joystick = 1 1918 * 1919 * Audigy 2 1920 * Enable Audio = 1 1921 * Mute Disable Audio = 0 1922 * Joystick = 1 1923 * GP S/PDIF AC3 Enable = 1 1924 * CD S/PDIF AC3 Enable = 1 1925 * 1926 * EMU10K1 1927 * Enable Audio = 1 1928 * Mute Disable Audio = 0 1929 * Lock Tank Memory = 1 1930 * Lock Sound Memory = 0 1931 * Auto Mute = 1 1932 */ 1933 1934 if (sc->audigy) { 1935 tmp = EMU_HCFG_AUTOMUTE | EMU_HCFG_JOYENABLE; 1936 if (sc->audigy2) /* Audigy 2 */ 1937 tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_AC3ENABLE_CDSPDIF | 1938 EMU_HCFG_AC3ENABLE_GPSPDIF; 1939 emu_wr(sc, EMU_HCFG, tmp, 4); 1940 1941 audigy_initefx(sc); 1942 1943 /* from ALSA initialization code: */ 1944 1945 /* enable audio and disable both audio/digital outputs */ 1946 emu_wr(sc, EMU_HCFG, emu_rd(sc, EMU_HCFG, 4) | EMU_HCFG_AUDIOENABLE, 4); 1947 emu_wr(sc, EMU_A_IOCFG, emu_rd(sc, EMU_A_IOCFG, 4) & ~EMU_A_IOCFG_GPOUT_AD, 1948 4); 1949 if (sc->audigy2) { /* Audigy 2 */ 1950 /* Unmute Analog. 1951 * Set GPO6 to 1 for Apollo. This has to be done after 1952 * init Alice3 I2SOut beyond 48kHz. 1953 * So, sequence is important. 1954 */ 1955 emu_wr(sc, EMU_A_IOCFG, 1956 emu_rd(sc, EMU_A_IOCFG, 4) | EMU_A_IOCFG_GPOUT_A, 4); 1957 } 1958 } else { 1959 /* EMU10K1 initialization code */ 1960 tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_LOCKTANKCACHE_MASK 1961 | EMU_HCFG_AUTOMUTE; 1962 if (sc->rev >= 6) 1963 tmp |= EMU_HCFG_JOYENABLE; 1964 1965 emu_wr(sc, EMU_HCFG, tmp, 4); 1966 1967 /* TOSLink detection */ 1968 sc->tos_link = 0; 1969 tmp = emu_rd(sc, EMU_HCFG, 4); 1970 if (tmp & (EMU_HCFG_GPINPUT0 | EMU_HCFG_GPINPUT1)) { 1971 emu_wr(sc, EMU_HCFG, tmp | EMU_HCFG_GPOUT1, 4); 1972 DELAY(50); 1973 if (tmp != (emu_rd(sc, EMU_HCFG, 4) & ~EMU_HCFG_GPOUT1)) { 1974 sc->tos_link = 1; 1975 emu_wr(sc, EMU_HCFG, tmp, 4); 1976 } 1977 } 1978 } 1979 1980 return 0; 1981 } 1982 1983 static int 1984 emu_uninit(struct sc_info *sc) 1985 { 1986 u_int32_t ch; 1987 1988 emu_wr(sc, EMU_INTE, 0, 4); 1989 for (ch = 0; ch < NUM_G; ch++) 1990 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF); 1991 for (ch = 0; ch < NUM_G; ch++) { 1992 emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0); 1993 emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0); 1994 emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0); 1995 emu_wrptr(sc, ch, EMU_CHAN_CPF, 0); 1996 } 1997 1998 if (sc->audigy) { /* stop fx processor */ 1999 emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP); 2000 } 2001 2002 /* disable audio and lock cache */ 2003 emu_wr(sc, EMU_HCFG, 2004 EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE, 2005 4); 2006 2007 emu_wrptr(sc, 0, EMU_PTB, 0); 2008 /* reset recording buffers */ 2009 emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE); 2010 emu_wrptr(sc, 0, EMU_MICBA, 0); 2011 emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE); 2012 emu_wrptr(sc, 0, EMU_FXBA, 0); 2013 emu_wrptr(sc, 0, EMU_FXWC, 0); 2014 emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE); 2015 emu_wrptr(sc, 0, EMU_ADCBA, 0); 2016 emu_wrptr(sc, 0, EMU_TCB, 0); 2017 emu_wrptr(sc, 0, EMU_TCBS, 0); 2018 2019 /* disable channel interrupt */ 2020 emu_wrptr(sc, 0, EMU_CLIEL, 0); 2021 emu_wrptr(sc, 0, EMU_CLIEH, 0); 2022 emu_wrptr(sc, 0, EMU_SOLEL, 0); 2023 emu_wrptr(sc, 0, EMU_SOLEH, 0); 2024 2025 /* init envelope engine */ 2026 if (!SLIST_EMPTY(&sc->mem.blocks)) 2027 device_printf(sc->dev, "warning: memblock list not empty\n"); 2028 emu_free(sc, sc->mem.ptb_pages, sc->mem.ptb_map); 2029 emu_free(sc, sc->mem.silent_page, sc->mem.silent_map); 2030 2031 if(sc->mpu) 2032 mpu401_uninit(sc->mpu); 2033 return 0; 2034 } 2035 2036 static int 2037 emu_pci_probe(device_t dev) 2038 { 2039 char *s = NULL; 2040 2041 switch (pci_get_devid(dev)) { 2042 case EMU10K1_PCI_ID: 2043 s = "Creative EMU10K1"; 2044 break; 2045 2046 case EMU10K2_PCI_ID: 2047 if (pci_get_revid(dev) == 0x04) 2048 s = "Creative Audigy 2 (EMU10K2)"; 2049 else 2050 s = "Creative Audigy (EMU10K2)"; 2051 break; 2052 2053 case EMU10K3_PCI_ID: 2054 s = "Creative Audigy 2 (EMU10K3)"; 2055 break; 2056 2057 default: 2058 return ENXIO; 2059 } 2060 2061 device_set_desc(dev, s); 2062 return BUS_PROBE_LOW_PRIORITY; 2063 } 2064 2065 static int 2066 emu_pci_attach(device_t dev) 2067 { 2068 struct ac97_info *codec = NULL; 2069 struct sc_info *sc; 2070 int i, gotmic; 2071 char status[SND_STATUSLEN]; 2072 2073 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 2074 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_emu10k1 softc"); 2075 sc->dev = dev; 2076 sc->type = pci_get_devid(dev); 2077 sc->rev = pci_get_revid(dev); 2078 sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID; 2079 sc->audigy2 = (sc->audigy && sc->rev == 0x04); 2080 sc->nchans = sc->audigy ? 8 : 4; 2081 sc->addrmask = sc->audigy ? EMU_A_PTR_ADDR_MASK : EMU_PTR_ADDR_MASK; 2082 2083 pci_enable_busmaster(dev); 2084 2085 i = PCIR_BAR(0); 2086 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE); 2087 if (sc->reg == NULL) { 2088 device_printf(dev, "unable to map register space\n"); 2089 goto bad; 2090 } 2091 sc->st = rman_get_bustag(sc->reg); 2092 sc->sh = rman_get_bushandle(sc->reg); 2093 2094 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536); 2095 2096 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 2097 /*boundary*/0, 2098 /*lowaddr*/(1U << 31) - 1, /* can only access 0-2gb */ 2099 /*highaddr*/BUS_SPACE_MAXADDR, 2100 /*filter*/NULL, /*filterarg*/NULL, 2101 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 2102 /*flags*/0, /*lockfunc*/NULL, /*lockarg*/NULL, 2103 &sc->parent_dmat) != 0) { 2104 device_printf(dev, "unable to create dma tag\n"); 2105 goto bad; 2106 } 2107 2108 if (emu_init(sc) == -1) { 2109 device_printf(dev, "unable to initialize the card\n"); 2110 goto bad; 2111 } 2112 2113 codec = AC97_CREATE(dev, sc, emu_ac97); 2114 if (codec == NULL) goto bad; 2115 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL) ? 1 : 0; 2116 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 2117 2118 emu_midiattach(sc); 2119 2120 i = 0; 2121 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, 2122 RF_ACTIVE | RF_SHAREABLE); 2123 if (!sc->irq || 2124 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) { 2125 device_printf(dev, "unable to map interrupt\n"); 2126 goto bad; 2127 } 2128 2129 snprintf(status, SND_STATUSLEN, "port 0x%jx irq %jd on %s", 2130 rman_get_start(sc->reg), rman_get_start(sc->irq), 2131 device_get_nameunit(device_get_parent(dev))); 2132 2133 if (pcm_register(dev, sc, sc->nchans, gotmic ? 3 : 2)) goto bad; 2134 for (i = 0; i < sc->nchans; i++) 2135 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc); 2136 for (i = 0; i < (gotmic ? 3 : 2); i++) 2137 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc); 2138 2139 pcm_setstatus(dev, status); 2140 2141 return 0; 2142 2143 bad: 2144 if (codec) ac97_destroy(codec); 2145 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2146 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih); 2147 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2148 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat); 2149 if (sc->lock) snd_mtxfree(sc->lock); 2150 free(sc, M_DEVBUF); 2151 return ENXIO; 2152 } 2153 2154 static int 2155 emu_pci_detach(device_t dev) 2156 { 2157 int r; 2158 struct sc_info *sc; 2159 2160 r = pcm_unregister(dev); 2161 if (r) 2162 return r; 2163 2164 sc = pcm_getdevinfo(dev); 2165 /* shutdown chip */ 2166 emu_uninit(sc); 2167 2168 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2169 bus_teardown_intr(dev, sc->irq, sc->ih); 2170 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2171 bus_dma_tag_destroy(sc->parent_dmat); 2172 snd_mtxfree(sc->lock); 2173 free(sc, M_DEVBUF); 2174 2175 return 0; 2176 } 2177 2178 /* add suspend, resume */ 2179 static device_method_t emu_methods[] = { 2180 /* Device interface */ 2181 DEVMETHOD(device_probe, emu_pci_probe), 2182 DEVMETHOD(device_attach, emu_pci_attach), 2183 DEVMETHOD(device_detach, emu_pci_detach), 2184 2185 DEVMETHOD_END 2186 }; 2187 2188 static driver_t emu_driver = { 2189 "pcm", 2190 emu_methods, 2191 PCM_SOFTC_SIZE, 2192 }; 2193 2194 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, NULL, NULL); 2195 MODULE_DEPEND(snd_emu10k1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 2196 MODULE_VERSION(snd_emu10k1, 1); 2197 MODULE_DEPEND(snd_emu10k1, midi, 1, 1, 1); 2198 2199 /* dummy driver to silence the joystick device */ 2200 static int 2201 emujoy_pci_probe(device_t dev) 2202 { 2203 char *s = NULL; 2204 2205 switch (pci_get_devid(dev)) { 2206 case 0x70021102: 2207 s = "Creative EMU10K1 Joystick"; 2208 device_quiet(dev); 2209 break; 2210 case 0x70031102: 2211 s = "Creative EMU10K2 Joystick"; 2212 device_quiet(dev); 2213 break; 2214 } 2215 2216 if (s) device_set_desc(dev, s); 2217 return s ? -1000 : ENXIO; 2218 } 2219 2220 static int 2221 emujoy_pci_attach(device_t dev) 2222 { 2223 2224 return 0; 2225 } 2226 2227 static int 2228 emujoy_pci_detach(device_t dev) 2229 { 2230 2231 return 0; 2232 } 2233 2234 static device_method_t emujoy_methods[] = { 2235 DEVMETHOD(device_probe, emujoy_pci_probe), 2236 DEVMETHOD(device_attach, emujoy_pci_attach), 2237 DEVMETHOD(device_detach, emujoy_pci_detach), 2238 2239 DEVMETHOD_END 2240 }; 2241 2242 static driver_t emujoy_driver = { 2243 "emujoy", 2244 emujoy_methods, 2245 1 /* no softc */ 2246 }; 2247 2248 DRIVER_MODULE(emujoy, pci, emujoy_driver, NULL, NULL); 2249