1 /*- 2 * Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org> 3 * Copyright (c) 2003 Orlando Bassotto <orlando.bassotto@ieo-research.it> 4 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifdef HAVE_KERNEL_OPTION_HEADERS 30 #include "opt_snd.h" 31 #endif 32 33 #include <dev/sound/pcm/sound.h> 34 #include <dev/sound/pcm/ac97.h> 35 #include <dev/sound/pci/emuxkireg.h> 36 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 #include <sys/queue.h> 40 41 #include <dev/sound/midi/mpu401.h> 42 #include "mpufoi_if.h" 43 44 SND_DECLARE_FILE("$FreeBSD$"); 45 46 /* -------------------------------------------------------------------- */ 47 48 #define NUM_G 64 /* use all channels */ 49 #define WAVEOUT_MAXBUFSIZE 32768 50 #define EMUPAGESIZE 4096 /* don't change */ 51 #define EMUMAXPAGES (WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE) 52 #define EMU10K1_PCI_ID 0x00021102 /* 1102 => Creative Labs Vendor ID */ 53 #define EMU10K2_PCI_ID 0x00041102 54 #define EMU10K3_PCI_ID 0x00081102 55 #define EMU_DEFAULT_BUFSZ 4096 56 #define EMU_MAX_CHANS 8 57 #define EMU_CHANS 4 58 59 #define MAXREQVOICES 8 60 #define RESERVED 0 61 #define NUM_MIDI 16 62 #define NUM_FXSENDS 4 63 64 #define TMEMSIZE 256*1024 65 #define TMEMSIZEREG 4 66 67 #define ENABLE 0xffffffff 68 #define DISABLE 0x00000000 69 #define ENV_ON EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK 70 #define ENV_OFF 0x00 /* XXX: should this be 1? */ 71 72 #define EMU_A_IOCFG_GPOUT_A 0x40 73 #define EMU_A_IOCFG_GPOUT_D 0x04 74 #define EMU_A_IOCFG_GPOUT_AD (EMU_A_IOCFG_GPOUT_A|EMU_A_IOCFG_GPOUT_D) /* EMU_A_IOCFG_GPOUT0 */ 75 76 #define EMU_HCFG_GPOUT1 0x00000800 77 78 /* instruction set */ 79 #define iACC3 0x06 80 #define iMACINT0 0x04 81 #define iINTERP 0x0e 82 83 #define C_00000000 0x40 84 #define C_00000001 0x41 85 #define C_00000004 0x44 86 #define C_40000000 0x4d 87 /* Audigy constants */ 88 #define A_C_00000000 0xc0 89 #define A_C_40000000 0xcd 90 91 /* GPRs */ 92 #define FXBUS(x) (0x00 + (x)) 93 #define EXTIN(x) (0x10 + (x)) 94 #define EXTOUT(x) (0x20 + (x)) 95 96 #define GPR(x) (EMU_FXGPREGBASE + (x)) 97 #define A_EXTIN(x) (0x40 + (x)) 98 #define A_FXBUS(x) (0x00 + (x)) 99 #define A_EXTOUT(x) (0x60 + (x)) 100 #define A_GPR(x) (EMU_A_FXGPREGBASE + (x)) 101 102 /* FX buses */ 103 #define FXBUS_PCM_LEFT 0x00 104 #define FXBUS_PCM_RIGHT 0x01 105 #define FXBUS_MIDI_LEFT 0x04 106 #define FXBUS_MIDI_RIGHT 0x05 107 #define FXBUS_MIDI_REVERB 0x0c 108 #define FXBUS_MIDI_CHORUS 0x0d 109 110 /* Inputs */ 111 #define EXTIN_AC97_L 0x00 112 #define EXTIN_AC97_R 0x01 113 #define EXTIN_SPDIF_CD_L 0x02 114 #define EXTIN_SPDIF_CD_R 0x03 115 #define EXTIN_TOSLINK_L 0x06 116 #define EXTIN_TOSLINK_R 0x07 117 #define EXTIN_COAX_SPDIF_L 0x0a 118 #define EXTIN_COAX_SPDIF_R 0x0b 119 /* Audigy Inputs */ 120 #define A_EXTIN_AC97_L 0x00 121 #define A_EXTIN_AC97_R 0x01 122 123 /* Outputs */ 124 #define EXTOUT_AC97_L 0x00 125 #define EXTOUT_AC97_R 0x01 126 #define EXTOUT_TOSLINK_L 0x02 127 #define EXTOUT_TOSLINK_R 0x03 128 #define EXTOUT_AC97_CENTER 0x04 129 #define EXTOUT_AC97_LFE 0x05 130 #define EXTOUT_HEADPHONE_L 0x06 131 #define EXTOUT_HEADPHONE_R 0x07 132 #define EXTOUT_REAR_L 0x08 133 #define EXTOUT_REAR_R 0x09 134 #define EXTOUT_ADC_CAP_L 0x0a 135 #define EXTOUT_ADC_CAP_R 0x0b 136 #define EXTOUT_ACENTER 0x11 137 #define EXTOUT_ALFE 0x12 138 /* Audigy Outputs */ 139 #define A_EXTOUT_FRONT_L 0x00 140 #define A_EXTOUT_FRONT_R 0x01 141 #define A_EXTOUT_CENTER 0x02 142 #define A_EXTOUT_LFE 0x03 143 #define A_EXTOUT_HEADPHONE_L 0x04 144 #define A_EXTOUT_HEADPHONE_R 0x05 145 #define A_EXTOUT_REAR_L 0x06 146 #define A_EXTOUT_REAR_R 0x07 147 #define A_EXTOUT_AFRONT_L 0x08 148 #define A_EXTOUT_AFRONT_R 0x09 149 #define A_EXTOUT_ACENTER 0x0a 150 #define A_EXTOUT_ALFE 0x0b 151 #define A_EXTOUT_AREAR_L 0x0e 152 #define A_EXTOUT_AREAR_R 0x0f 153 #define A_EXTOUT_AC97_L 0x10 154 #define A_EXTOUT_AC97_R 0x11 155 #define A_EXTOUT_ADC_CAP_L 0x16 156 #define A_EXTOUT_ADC_CAP_R 0x17 157 158 struct emu_memblk { 159 SLIST_ENTRY(emu_memblk) link; 160 void *buf; 161 bus_addr_t buf_addr; 162 u_int32_t pte_start, pte_size; 163 }; 164 165 struct emu_mem { 166 u_int8_t bmap[EMUMAXPAGES / 8]; 167 u_int32_t *ptb_pages; 168 void *silent_page; 169 bus_addr_t silent_page_addr; 170 bus_addr_t ptb_pages_addr; 171 SLIST_HEAD(, emu_memblk) blocks; 172 }; 173 174 struct emu_voice { 175 int vnum; 176 unsigned int b16:1, stereo:1, busy:1, running:1, ismaster:1; 177 int speed; 178 int start, end, vol; 179 int fxrt1; /* FX routing */ 180 int fxrt2; /* FX routing (only for audigy) */ 181 u_int32_t buf; 182 struct emu_voice *slave; 183 struct pcm_channel *channel; 184 }; 185 186 struct sc_info; 187 188 /* channel registers */ 189 struct sc_pchinfo { 190 int spd, fmt, blksz, run; 191 struct emu_voice *master, *slave; 192 struct snd_dbuf *buffer; 193 struct pcm_channel *channel; 194 struct sc_info *parent; 195 }; 196 197 struct sc_rchinfo { 198 int spd, fmt, run, blksz, num; 199 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask; 200 struct snd_dbuf *buffer; 201 struct pcm_channel *channel; 202 struct sc_info *parent; 203 }; 204 205 /* device private data */ 206 struct sc_info { 207 device_t dev; 208 u_int32_t type, rev; 209 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1; 210 u_int32_t addrmask; /* wider if audigy */ 211 212 bus_space_tag_t st; 213 bus_space_handle_t sh; 214 bus_dma_tag_t parent_dmat; 215 216 struct resource *reg, *irq; 217 void *ih; 218 struct mtx *lock; 219 220 unsigned int bufsz; 221 int timer, timerinterval; 222 int pnum, rnum; 223 int nchans; 224 struct emu_mem mem; 225 struct emu_voice voice[64]; 226 struct sc_pchinfo pch[EMU_MAX_CHANS]; 227 struct sc_rchinfo rch[3]; 228 struct mpu401 *mpu; 229 mpu401_intr_t *mpu_intr; 230 int mputx; 231 }; 232 233 /* -------------------------------------------------------------------- */ 234 235 /* 236 * prototypes 237 */ 238 239 /* stuff */ 240 static int emu_init(struct sc_info *); 241 static void emu_intr(void *); 242 static void *emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr); 243 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr); 244 static int emu_memfree(struct sc_info *sc, void *buf); 245 static int emu_memstart(struct sc_info *sc, void *buf); 246 #ifdef EMUDEBUG 247 static void emu_vdump(struct sc_info *sc, struct emu_voice *v); 248 #endif 249 250 /* talk to the card */ 251 static u_int32_t emu_rd(struct sc_info *, int, int); 252 static void emu_wr(struct sc_info *, int, u_int32_t, int); 253 254 /* -------------------------------------------------------------------- */ 255 256 static u_int32_t emu_rfmt_ac97[] = { 257 SND_FORMAT(AFMT_S16_LE, 1, 0), 258 SND_FORMAT(AFMT_S16_LE, 2, 0), 259 0 260 }; 261 262 static u_int32_t emu_rfmt_mic[] = { 263 SND_FORMAT(AFMT_U8, 1, 0), 264 0 265 }; 266 267 static u_int32_t emu_rfmt_efx[] = { 268 SND_FORMAT(AFMT_S16_LE, 2, 0), 269 0 270 }; 271 272 static struct pcmchan_caps emu_reccaps[3] = { 273 {8000, 48000, emu_rfmt_ac97, 0}, 274 {8000, 8000, emu_rfmt_mic, 0}, 275 {48000, 48000, emu_rfmt_efx, 0}, 276 }; 277 278 static u_int32_t emu_pfmt[] = { 279 SND_FORMAT(AFMT_U8, 1, 0), 280 SND_FORMAT(AFMT_U8, 2, 0), 281 SND_FORMAT(AFMT_S16_LE, 1, 0), 282 SND_FORMAT(AFMT_S16_LE, 2, 0), 283 0 284 }; 285 286 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0}; 287 288 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000}; 289 /* audigy supports 12kHz. */ 290 static int audigy_adcspeed[9] = { 291 48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000 292 }; 293 294 /* -------------------------------------------------------------------- */ 295 /* Hardware */ 296 static u_int32_t 297 emu_rd(struct sc_info *sc, int regno, int size) 298 { 299 switch (size) { 300 case 1: 301 return bus_space_read_1(sc->st, sc->sh, regno); 302 case 2: 303 return bus_space_read_2(sc->st, sc->sh, regno); 304 case 4: 305 return bus_space_read_4(sc->st, sc->sh, regno); 306 default: 307 return 0xffffffff; 308 } 309 } 310 311 static void 312 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 313 { 314 switch (size) { 315 case 1: 316 bus_space_write_1(sc->st, sc->sh, regno, data); 317 break; 318 case 2: 319 bus_space_write_2(sc->st, sc->sh, regno, data); 320 break; 321 case 4: 322 bus_space_write_4(sc->st, sc->sh, regno, data); 323 break; 324 } 325 } 326 327 static u_int32_t 328 emu_rdptr(struct sc_info *sc, int chn, int reg) 329 { 330 u_int32_t ptr, val, mask, size, offset; 331 332 ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK); 333 emu_wr(sc, EMU_PTR, ptr, 4); 334 val = emu_rd(sc, EMU_DATA, 4); 335 if (reg & 0xff000000) { 336 size = (reg >> 24) & 0x3f; 337 offset = (reg >> 16) & 0x1f; 338 mask = ((1 << size) - 1) << offset; 339 val &= mask; 340 val >>= offset; 341 } 342 return val; 343 } 344 345 static void 346 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data) 347 { 348 u_int32_t ptr, mask, size, offset; 349 350 ptr = ((reg << 16) & sc->addrmask) | (chn & EMU_PTR_CHNO_MASK); 351 emu_wr(sc, EMU_PTR, ptr, 4); 352 if (reg & 0xff000000) { 353 size = (reg >> 24) & 0x3f; 354 offset = (reg >> 16) & 0x1f; 355 mask = ((1 << size) - 1) << offset; 356 data <<= offset; 357 data &= mask; 358 data |= emu_rd(sc, EMU_DATA, 4) & ~mask; 359 } 360 emu_wr(sc, EMU_DATA, data, 4); 361 } 362 363 static void 364 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data) 365 { 366 pc += sc->audigy ? EMU_A_MICROCODEBASE : EMU_MICROCODEBASE; 367 emu_wrptr(sc, 0, pc, data); 368 } 369 370 /* -------------------------------------------------------------------- */ 371 /* ac97 codec */ 372 /* no locking needed */ 373 374 static int 375 emu_rdcd(kobj_t obj, void *devinfo, int regno) 376 { 377 struct sc_info *sc = (struct sc_info *)devinfo; 378 379 emu_wr(sc, EMU_AC97ADDR, regno, 1); 380 return emu_rd(sc, EMU_AC97DATA, 2); 381 } 382 383 static int 384 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 385 { 386 struct sc_info *sc = (struct sc_info *)devinfo; 387 388 emu_wr(sc, EMU_AC97ADDR, regno, 1); 389 emu_wr(sc, EMU_AC97DATA, data, 2); 390 return 0; 391 } 392 393 static kobj_method_t emu_ac97_methods[] = { 394 KOBJMETHOD(ac97_read, emu_rdcd), 395 KOBJMETHOD(ac97_write, emu_wrcd), 396 KOBJMETHOD_END 397 }; 398 AC97_DECLARE(emu_ac97); 399 400 /* -------------------------------------------------------------------- */ 401 /* stuff */ 402 static int 403 emu_settimer(struct sc_info *sc) 404 { 405 struct sc_pchinfo *pch; 406 struct sc_rchinfo *rch; 407 int i, tmp, rate; 408 409 rate = 0; 410 for (i = 0; i < sc->nchans; i++) { 411 pch = &sc->pch[i]; 412 if (pch->buffer) { 413 tmp = (pch->spd * sndbuf_getalign(pch->buffer)) 414 / pch->blksz; 415 if (tmp > rate) 416 rate = tmp; 417 } 418 } 419 420 for (i = 0; i < 3; i++) { 421 rch = &sc->rch[i]; 422 if (rch->buffer) { 423 tmp = (rch->spd * sndbuf_getalign(rch->buffer)) 424 / rch->blksz; 425 if (tmp > rate) 426 rate = tmp; 427 } 428 } 429 RANGE(rate, 48, 9600); 430 sc->timerinterval = 48000 / rate; 431 emu_wr(sc, EMU_TIMER, sc->timerinterval & 0x03ff, 2); 432 433 return sc->timerinterval; 434 } 435 436 static int 437 emu_enatimer(struct sc_info *sc, int go) 438 { 439 u_int32_t x; 440 if (go) { 441 if (sc->timer++ == 0) { 442 x = emu_rd(sc, EMU_INTE, 4); 443 x |= EMU_INTE_INTERTIMERENB; 444 emu_wr(sc, EMU_INTE, x, 4); 445 } 446 } else { 447 sc->timer = 0; 448 x = emu_rd(sc, EMU_INTE, 4); 449 x &= ~EMU_INTE_INTERTIMERENB; 450 emu_wr(sc, EMU_INTE, x, 4); 451 } 452 return 0; 453 } 454 455 static void 456 emu_enastop(struct sc_info *sc, char channel, int enable) 457 { 458 int reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL; 459 channel &= 0x1f; 460 reg |= 1 << 24; 461 reg |= channel << 16; 462 emu_wrptr(sc, 0, reg, enable); 463 } 464 465 static int 466 emu_recval(int speed) { 467 int val; 468 469 val = 0; 470 while (val < 7 && speed < adcspeed[val]) 471 val++; 472 return val; 473 } 474 475 static int 476 audigy_recval(int speed) { 477 int val; 478 479 val = 0; 480 while (val < 8 && speed < audigy_adcspeed[val]) 481 val++; 482 return val; 483 } 484 485 static u_int32_t 486 emu_rate_to_pitch(u_int32_t rate) 487 { 488 static u_int32_t logMagTable[128] = { 489 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2, 490 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5, 491 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081, 492 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191, 493 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7, 494 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829, 495 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e, 496 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26, 497 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d, 498 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885, 499 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899, 500 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c, 501 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3, 502 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3, 503 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83, 504 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df 505 }; 506 static char logSlopeTable[128] = { 507 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58, 508 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53, 509 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f, 510 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b, 511 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47, 512 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44, 513 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41, 514 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e, 515 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c, 516 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 517 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37, 518 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35, 519 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34, 520 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32, 521 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30, 522 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f 523 }; 524 int i; 525 526 if (rate == 0) 527 return 0; /* Bail out if no leading "1" */ 528 rate *= 11185; /* Scale 48000 to 0x20002380 */ 529 for (i = 31; i > 0; i--) { 530 if (rate & 0x80000000) { /* Detect leading "1" */ 531 return (((u_int32_t) (i - 15) << 20) + 532 logMagTable[0x7f & (rate >> 24)] + 533 (0x7f & (rate >> 17)) * 534 logSlopeTable[0x7f & (rate >> 24)]); 535 } 536 rate <<= 1; 537 } 538 539 return 0; /* Should never reach this point */ 540 } 541 542 static u_int32_t 543 emu_rate_to_linearpitch(u_int32_t rate) 544 { 545 rate = (rate << 8) / 375; 546 return (rate >> 1) + (rate & 1); 547 } 548 549 static struct emu_voice * 550 emu_valloc(struct sc_info *sc) 551 { 552 struct emu_voice *v; 553 int i; 554 555 v = NULL; 556 for (i = 0; i < 64 && sc->voice[i].busy; i++); 557 if (i < 64) { 558 v = &sc->voice[i]; 559 v->busy = 1; 560 } 561 return v; 562 } 563 564 static int 565 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s, 566 u_int32_t sz, struct snd_dbuf *b) 567 { 568 void *buf; 569 bus_addr_t tmp_addr; 570 571 buf = emu_memalloc(sc, sz, &tmp_addr); 572 if (buf == NULL) 573 return -1; 574 if (b != NULL) 575 sndbuf_setup(b, buf, sz); 576 m->start = emu_memstart(sc, buf) * EMUPAGESIZE; 577 m->end = m->start + sz; 578 m->channel = NULL; 579 m->speed = 0; 580 m->b16 = 0; 581 m->stereo = 0; 582 m->running = 0; 583 m->ismaster = 1; 584 m->vol = 0xff; 585 m->buf = tmp_addr; 586 m->slave = s; 587 if (sc->audigy) { 588 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 8 | 589 FXBUS_PCM_LEFT << 16 | FXBUS_MIDI_REVERB << 24; 590 m->fxrt2 = 0x3f3f3f3f; /* No effects on second route */ 591 } else { 592 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 4 | 593 FXBUS_PCM_LEFT << 8 | FXBUS_MIDI_REVERB << 12; 594 m->fxrt2 = 0; 595 } 596 597 if (s != NULL) { 598 s->start = m->start; 599 s->end = m->end; 600 s->channel = NULL; 601 s->speed = 0; 602 s->b16 = 0; 603 s->stereo = 0; 604 s->running = 0; 605 s->ismaster = 0; 606 s->vol = m->vol; 607 s->buf = m->buf; 608 s->fxrt1 = m->fxrt1; 609 s->fxrt2 = m->fxrt2; 610 s->slave = NULL; 611 } 612 return 0; 613 } 614 615 static void 616 emu_vsetup(struct sc_pchinfo *ch) 617 { 618 struct emu_voice *v = ch->master; 619 620 if (ch->fmt) { 621 v->b16 = (ch->fmt & AFMT_16BIT) ? 1 : 0; 622 v->stereo = (AFMT_CHANNEL(ch->fmt) > 1) ? 1 : 0; 623 if (v->slave != NULL) { 624 v->slave->b16 = v->b16; 625 v->slave->stereo = v->stereo; 626 } 627 } 628 if (ch->spd) { 629 v->speed = ch->spd; 630 if (v->slave != NULL) 631 v->slave->speed = v->speed; 632 } 633 } 634 635 static void 636 emu_vwrite(struct sc_info *sc, struct emu_voice *v) 637 { 638 int s; 639 int l, r, x, y; 640 u_int32_t sa, ea, start, val, silent_page; 641 642 s = (v->stereo ? 1 : 0) + (v->b16 ? 1 : 0); 643 644 sa = v->start >> s; 645 ea = v->end >> s; 646 647 l = r = x = y = v->vol; 648 if (v->stereo) { 649 l = v->ismaster ? l : 0; 650 r = v->ismaster ? 0 : r; 651 } 652 653 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF, v->stereo ? EMU_CHAN_CPF_STEREO_MASK : 0); 654 val = v->stereo ? 28 : 30; 655 val *= v->b16 ? 1 : 2; 656 start = sa + val; 657 658 if (sc->audigy) { 659 emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT1, v->fxrt1); 660 emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT2, v->fxrt2); 661 emu_wrptr(sc, v->vnum, EMU_A_CHAN_SENDAMOUNTS, 0); 662 } 663 else 664 emu_wrptr(sc, v->vnum, EMU_CHAN_FXRT, v->fxrt1 << 16); 665 666 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX, (x << 8) | r); 667 emu_wrptr(sc, v->vnum, EMU_CHAN_DSL, ea | (y << 24)); 668 emu_wrptr(sc, v->vnum, EMU_CHAN_PSST, sa | (l << 24)); 669 emu_wrptr(sc, v->vnum, EMU_CHAN_CCCA, start | (v->b16 ? 0 : EMU_CHAN_CCCA_8BITSELECT)); 670 671 emu_wrptr(sc, v->vnum, EMU_CHAN_Z1, 0); 672 emu_wrptr(sc, v->vnum, EMU_CHAN_Z2, 0); 673 674 silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1) 675 | EMU_CHAN_MAP_PTI_MASK; 676 emu_wrptr(sc, v->vnum, EMU_CHAN_MAPA, silent_page); 677 emu_wrptr(sc, v->vnum, EMU_CHAN_MAPB, silent_page); 678 679 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, EMU_CHAN_CVCF_CURRFILTER_MASK); 680 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, EMU_CHAN_VTFT_FILTERTARGET_MASK); 681 emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDM, 0); 682 emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSM, EMU_CHAN_DCYSUSM_DECAYTIME_MASK); 683 emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL1, 0x8000); 684 emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL2, 0x8000); 685 emu_wrptr(sc, v->vnum, EMU_CHAN_FMMOD, 0); 686 emu_wrptr(sc, v->vnum, EMU_CHAN_TREMFRQ, 0); 687 emu_wrptr(sc, v->vnum, EMU_CHAN_FM2FRQ2, 0); 688 emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVAL, 0x8000); 689 690 emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDV, 691 EMU_CHAN_ATKHLDV_HOLDTIME_MASK | EMU_CHAN_ATKHLDV_ATTACKTIME_MASK); 692 emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVOL, 0x8000); 693 694 emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_FILTERAMOUNT, 0x7f); 695 emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_PITCHAMOUNT, 0); 696 697 if (v->slave != NULL) 698 emu_vwrite(sc, v->slave); 699 } 700 701 static void 702 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go) 703 { 704 u_int32_t pitch_target, initial_pitch; 705 u_int32_t cra, cs, ccis; 706 u_int32_t sample, i; 707 708 if (go) { 709 cra = 64; 710 cs = v->stereo ? 4 : 2; 711 ccis = v->stereo ? 28 : 30; 712 ccis *= v->b16 ? 1 : 2; 713 sample = v->b16 ? 0x00000000 : 0x80808080; 714 715 for (i = 0; i < cs; i++) 716 emu_wrptr(sc, v->vnum, EMU_CHAN_CD0 + i, sample); 717 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, 0); 718 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_READADDRESS, cra); 719 emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, ccis); 720 721 emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xff00); 722 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0xffffffff); 723 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0xffffffff); 724 emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSV, 0x00007f7f); 725 emu_enastop(sc, v->vnum, 0); 726 727 pitch_target = emu_rate_to_linearpitch(v->speed); 728 initial_pitch = emu_rate_to_pitch(v->speed) >> 8; 729 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, pitch_target); 730 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, pitch_target); 731 emu_wrptr(sc, v->vnum, EMU_CHAN_IP, initial_pitch); 732 } else { 733 emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, 0); 734 emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, 0); 735 emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xffff); 736 emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0x0000ffff); 737 emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0x0000ffff); 738 emu_wrptr(sc, v->vnum, EMU_CHAN_IP, 0); 739 emu_enastop(sc, v->vnum, 1); 740 } 741 if (v->slave != NULL) 742 emu_vtrigger(sc, v->slave, go); 743 } 744 745 static int 746 emu_vpos(struct sc_info *sc, struct emu_voice *v) 747 { 748 int s, ptr; 749 750 s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0); 751 ptr = (emu_rdptr(sc, v->vnum, EMU_CHAN_CCCA_CURRADDR) - (v->start >> s)) << s; 752 return ptr & ~0x0000001f; 753 } 754 755 #ifdef EMUDEBUG 756 static void 757 emu_vdump(struct sc_info *sc, struct emu_voice *v) 758 { 759 char *regname[] = { 760 "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl", 761 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL, 762 "envvol", "atkhldv", "dcysusv", "lfoval1", 763 "envval", "atkhldm", "dcysusm", "lfoval2", 764 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2", 765 "tempenv" 766 }; 767 char *regname2[] = { 768 "mudata1", "mustat1", "mudata2", "mustat2", 769 "fxwc1", "fxwc2", "spdrate", NULL, NULL, 770 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1", 771 NULL, NULL 772 }; 773 int i, x; 774 775 printf("voice number %d\n", v->vnum); 776 for (i = 0, x = 0; i <= 0x1e; i++) { 777 if (regname[i] == NULL) 778 continue; 779 printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i)); 780 printf("%s", (x == 2) ? "\n" : "\t"); 781 x++; 782 if (x > 2) 783 x = 0; 784 } 785 786 /* Print out audigy extra registers */ 787 if (sc->audigy) { 788 for (i = 0; i <= 0xe; i++) { 789 if (regname2[i] == NULL) 790 continue; 791 printf("%s\t[%08x]", regname2[i], 792 emu_rdptr(sc, v->vnum, i + 0x70)); 793 printf("%s", (x == 2)? "\n" : "\t"); 794 x++; 795 if (x > 2) 796 x = 0; 797 } 798 } 799 printf("\n\n"); 800 } 801 #endif 802 803 /* channel interface */ 804 static void * 805 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 806 struct pcm_channel *c, int dir) 807 { 808 struct sc_info *sc = devinfo; 809 struct sc_pchinfo *ch; 810 void *r; 811 812 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction")); 813 ch = &sc->pch[sc->pnum++]; 814 ch->buffer = b; 815 ch->parent = sc; 816 ch->channel = c; 817 ch->blksz = sc->bufsz / 2; 818 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 819 ch->spd = 8000; 820 snd_mtxlock(sc->lock); 821 ch->master = emu_valloc(sc); 822 ch->slave = emu_valloc(sc); 823 snd_mtxunlock(sc->lock); 824 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer)) 825 ? NULL : ch; 826 827 return r; 828 } 829 830 static int 831 emupchan_free(kobj_t obj, void *data) 832 { 833 struct sc_pchinfo *ch = data; 834 struct sc_info *sc = ch->parent; 835 int r; 836 837 snd_mtxlock(sc->lock); 838 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer)); 839 snd_mtxunlock(sc->lock); 840 841 return r; 842 } 843 844 static int 845 emupchan_setformat(kobj_t obj, void *data, u_int32_t format) 846 { 847 struct sc_pchinfo *ch = data; 848 849 ch->fmt = format; 850 return 0; 851 } 852 853 static u_int32_t 854 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 855 { 856 struct sc_pchinfo *ch = data; 857 858 ch->spd = speed; 859 return ch->spd; 860 } 861 862 static u_int32_t 863 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 864 { 865 struct sc_pchinfo *ch = data; 866 struct sc_info *sc = ch->parent; 867 int irqrate, blksz; 868 869 ch->blksz = blocksize; 870 snd_mtxlock(sc->lock); 871 emu_settimer(sc); 872 irqrate = 48000 / sc->timerinterval; 873 snd_mtxunlock(sc->lock); 874 blksz = (ch->spd * sndbuf_getalign(ch->buffer)) / irqrate; 875 return blocksize; 876 } 877 878 static int 879 emupchan_trigger(kobj_t obj, void *data, int go) 880 { 881 struct sc_pchinfo *ch = data; 882 struct sc_info *sc = ch->parent; 883 884 if (!PCMTRIG_COMMON(go)) 885 return 0; 886 887 snd_mtxlock(sc->lock); 888 if (go == PCMTRIG_START) { 889 emu_vsetup(ch); 890 emu_vwrite(sc, ch->master); 891 emu_settimer(sc); 892 emu_enatimer(sc, 1); 893 #ifdef EMUDEBUG 894 printf("start [%d bit, %s, %d hz]\n", 895 ch->master->b16 ? 16 : 8, 896 ch->master->stereo ? "stereo" : "mono", 897 ch->master->speed); 898 emu_vdump(sc, ch->master); 899 emu_vdump(sc, ch->slave); 900 #endif 901 } 902 ch->run = (go == PCMTRIG_START) ? 1 : 0; 903 emu_vtrigger(sc, ch->master, ch->run); 904 snd_mtxunlock(sc->lock); 905 return 0; 906 } 907 908 static u_int32_t 909 emupchan_getptr(kobj_t obj, void *data) 910 { 911 struct sc_pchinfo *ch = data; 912 struct sc_info *sc = ch->parent; 913 int r; 914 915 snd_mtxlock(sc->lock); 916 r = emu_vpos(sc, ch->master); 917 snd_mtxunlock(sc->lock); 918 919 return r; 920 } 921 922 static struct pcmchan_caps * 923 emupchan_getcaps(kobj_t obj, void *data) 924 { 925 return &emu_playcaps; 926 } 927 928 static kobj_method_t emupchan_methods[] = { 929 KOBJMETHOD(channel_init, emupchan_init), 930 KOBJMETHOD(channel_free, emupchan_free), 931 KOBJMETHOD(channel_setformat, emupchan_setformat), 932 KOBJMETHOD(channel_setspeed, emupchan_setspeed), 933 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize), 934 KOBJMETHOD(channel_trigger, emupchan_trigger), 935 KOBJMETHOD(channel_getptr, emupchan_getptr), 936 KOBJMETHOD(channel_getcaps, emupchan_getcaps), 937 KOBJMETHOD_END 938 }; 939 CHANNEL_DECLARE(emupchan); 940 941 /* channel interface */ 942 static void * 943 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 944 struct pcm_channel *c, int dir) 945 { 946 struct sc_info *sc = devinfo; 947 struct sc_rchinfo *ch; 948 949 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction")); 950 ch = &sc->rch[sc->rnum]; 951 ch->buffer = b; 952 ch->parent = sc; 953 ch->channel = c; 954 ch->blksz = sc->bufsz / 2; 955 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 956 ch->spd = 8000; 957 ch->num = sc->rnum; 958 switch(sc->rnum) { 959 case 0: 960 ch->idxreg = sc->audigy ? EMU_A_ADCIDX : EMU_ADCIDX; 961 ch->basereg = EMU_ADCBA; 962 ch->sizereg = EMU_ADCBS; 963 ch->setupreg = EMU_ADCCR; 964 ch->irqmask = EMU_INTE_ADCBUFENABLE; 965 break; 966 967 case 1: 968 ch->idxreg = EMU_FXIDX; 969 ch->basereg = EMU_FXBA; 970 ch->sizereg = EMU_FXBS; 971 ch->setupreg = EMU_FXWC; 972 ch->irqmask = EMU_INTE_EFXBUFENABLE; 973 break; 974 975 case 2: 976 ch->idxreg = EMU_MICIDX; 977 ch->basereg = EMU_MICBA; 978 ch->sizereg = EMU_MICBS; 979 ch->setupreg = 0; 980 ch->irqmask = EMU_INTE_MICBUFENABLE; 981 break; 982 } 983 sc->rnum++; 984 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) 985 return NULL; 986 else { 987 snd_mtxlock(sc->lock); 988 emu_wrptr(sc, 0, ch->basereg, sndbuf_getbufaddr(ch->buffer)); 989 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */ 990 snd_mtxunlock(sc->lock); 991 return ch; 992 } 993 } 994 995 static int 996 emurchan_setformat(kobj_t obj, void *data, u_int32_t format) 997 { 998 struct sc_rchinfo *ch = data; 999 1000 ch->fmt = format; 1001 return 0; 1002 } 1003 1004 static u_int32_t 1005 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 1006 { 1007 struct sc_rchinfo *ch = data; 1008 1009 if (ch->num == 0) { 1010 if (ch->parent->audigy) 1011 speed = audigy_adcspeed[audigy_recval(speed)]; 1012 else 1013 speed = adcspeed[emu_recval(speed)]; 1014 } 1015 if (ch->num == 1) 1016 speed = 48000; 1017 if (ch->num == 2) 1018 speed = 8000; 1019 ch->spd = speed; 1020 return ch->spd; 1021 } 1022 1023 static u_int32_t 1024 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 1025 { 1026 struct sc_rchinfo *ch = data; 1027 struct sc_info *sc = ch->parent; 1028 int irqrate, blksz; 1029 1030 ch->blksz = blocksize; 1031 snd_mtxlock(sc->lock); 1032 emu_settimer(sc); 1033 irqrate = 48000 / sc->timerinterval; 1034 snd_mtxunlock(sc->lock); 1035 blksz = (ch->spd * sndbuf_getalign(ch->buffer)) / irqrate; 1036 return blocksize; 1037 } 1038 1039 /* semantic note: must start at beginning of buffer */ 1040 static int 1041 emurchan_trigger(kobj_t obj, void *data, int go) 1042 { 1043 struct sc_rchinfo *ch = data; 1044 struct sc_info *sc = ch->parent; 1045 u_int32_t val, sz; 1046 1047 if (!PCMTRIG_COMMON(go)) 1048 return 0; 1049 1050 switch(sc->bufsz) { 1051 case 4096: 1052 sz = EMU_RECBS_BUFSIZE_4096; 1053 break; 1054 1055 case 8192: 1056 sz = EMU_RECBS_BUFSIZE_8192; 1057 break; 1058 1059 case 16384: 1060 sz = EMU_RECBS_BUFSIZE_16384; 1061 break; 1062 1063 case 32768: 1064 sz = EMU_RECBS_BUFSIZE_32768; 1065 break; 1066 1067 case 65536: 1068 sz = EMU_RECBS_BUFSIZE_65536; 1069 break; 1070 1071 default: 1072 sz = EMU_RECBS_BUFSIZE_4096; 1073 } 1074 1075 snd_mtxlock(sc->lock); 1076 switch(go) { 1077 case PCMTRIG_START: 1078 ch->run = 1; 1079 emu_wrptr(sc, 0, ch->sizereg, sz); 1080 if (ch->num == 0) { 1081 if (sc->audigy) { 1082 val = EMU_A_ADCCR_LCHANENABLE; 1083 if (AFMT_CHANNEL(ch->fmt) > 1) 1084 val |= EMU_A_ADCCR_RCHANENABLE; 1085 val |= audigy_recval(ch->spd); 1086 } else { 1087 val = EMU_ADCCR_LCHANENABLE; 1088 if (AFMT_CHANNEL(ch->fmt) > 1) 1089 val |= EMU_ADCCR_RCHANENABLE; 1090 val |= emu_recval(ch->spd); 1091 } 1092 1093 emu_wrptr(sc, 0, ch->setupreg, 0); 1094 emu_wrptr(sc, 0, ch->setupreg, val); 1095 } 1096 val = emu_rd(sc, EMU_INTE, 4); 1097 val |= ch->irqmask; 1098 emu_wr(sc, EMU_INTE, val, 4); 1099 break; 1100 1101 case PCMTRIG_STOP: 1102 case PCMTRIG_ABORT: 1103 ch->run = 0; 1104 emu_wrptr(sc, 0, ch->sizereg, 0); 1105 if (ch->setupreg) 1106 emu_wrptr(sc, 0, ch->setupreg, 0); 1107 val = emu_rd(sc, EMU_INTE, 4); 1108 val &= ~ch->irqmask; 1109 emu_wr(sc, EMU_INTE, val, 4); 1110 break; 1111 1112 case PCMTRIG_EMLDMAWR: 1113 case PCMTRIG_EMLDMARD: 1114 default: 1115 break; 1116 } 1117 snd_mtxunlock(sc->lock); 1118 1119 return 0; 1120 } 1121 1122 static u_int32_t 1123 emurchan_getptr(kobj_t obj, void *data) 1124 { 1125 struct sc_rchinfo *ch = data; 1126 struct sc_info *sc = ch->parent; 1127 int r; 1128 1129 snd_mtxlock(sc->lock); 1130 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff; 1131 snd_mtxunlock(sc->lock); 1132 1133 return r; 1134 } 1135 1136 static struct pcmchan_caps * 1137 emurchan_getcaps(kobj_t obj, void *data) 1138 { 1139 struct sc_rchinfo *ch = data; 1140 1141 return &emu_reccaps[ch->num]; 1142 } 1143 1144 static kobj_method_t emurchan_methods[] = { 1145 KOBJMETHOD(channel_init, emurchan_init), 1146 KOBJMETHOD(channel_setformat, emurchan_setformat), 1147 KOBJMETHOD(channel_setspeed, emurchan_setspeed), 1148 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize), 1149 KOBJMETHOD(channel_trigger, emurchan_trigger), 1150 KOBJMETHOD(channel_getptr, emurchan_getptr), 1151 KOBJMETHOD(channel_getcaps, emurchan_getcaps), 1152 KOBJMETHOD_END 1153 }; 1154 CHANNEL_DECLARE(emurchan); 1155 1156 static unsigned char 1157 emu_mread(struct mpu401 *arg, void *sc, int reg) 1158 { 1159 unsigned int d; 1160 1161 d = emu_rd((struct sc_info *)sc, 0x18 + reg, 1); 1162 return d; 1163 } 1164 1165 static void 1166 emu_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b) 1167 { 1168 1169 emu_wr((struct sc_info *)sc, 0x18 + reg, b, 1); 1170 } 1171 1172 static int 1173 emu_muninit(struct mpu401 *arg, void *cookie) 1174 { 1175 struct sc_info *sc = cookie; 1176 1177 snd_mtxlock(sc->lock); 1178 sc->mpu_intr = 0; 1179 snd_mtxunlock(sc->lock); 1180 1181 return 0; 1182 } 1183 1184 static kobj_method_t emu_mpu_methods[] = { 1185 KOBJMETHOD(mpufoi_read, emu_mread), 1186 KOBJMETHOD(mpufoi_write, emu_mwrite), 1187 KOBJMETHOD(mpufoi_uninit, emu_muninit), 1188 KOBJMETHOD_END 1189 }; 1190 1191 static DEFINE_CLASS(emu_mpu, emu_mpu_methods, 0); 1192 1193 static void 1194 emu_intr2(void *p) 1195 { 1196 struct sc_info *sc = (struct sc_info *)p; 1197 1198 if (sc->mpu_intr) 1199 (sc->mpu_intr)(sc->mpu); 1200 } 1201 1202 static void 1203 emu_midiattach(struct sc_info *sc) 1204 { 1205 int i; 1206 1207 i = emu_rd(sc, EMU_INTE, 4); 1208 i |= EMU_INTE_MIDIRXENABLE; 1209 emu_wr(sc, EMU_INTE, i, 4); 1210 1211 sc->mpu = mpu401_init(&emu_mpu_class, sc, emu_intr2, &sc->mpu_intr); 1212 } 1213 /* -------------------------------------------------------------------- */ 1214 /* The interrupt handler */ 1215 1216 static void 1217 emu_intr(void *data) 1218 { 1219 struct sc_info *sc = data; 1220 u_int32_t stat, ack, i, x; 1221 1222 snd_mtxlock(sc->lock); 1223 while (1) { 1224 stat = emu_rd(sc, EMU_IPR, 4); 1225 if (stat == 0) 1226 break; 1227 ack = 0; 1228 1229 /* process irq */ 1230 if (stat & EMU_IPR_INTERVALTIMER) 1231 ack |= EMU_IPR_INTERVALTIMER; 1232 1233 if (stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL)) 1234 ack |= stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL); 1235 1236 if (stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL)) 1237 ack |= stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL); 1238 1239 if (stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL)) 1240 ack |= stat & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL); 1241 1242 if (stat & EMU_PCIERROR) { 1243 ack |= EMU_PCIERROR; 1244 device_printf(sc->dev, "pci error\n"); 1245 /* we still get an nmi with ecc ram even if we ack this */ 1246 } 1247 if (stat & EMU_IPR_RATETRCHANGE) { 1248 ack |= EMU_IPR_RATETRCHANGE; 1249 #ifdef EMUDEBUG 1250 device_printf(sc->dev, 1251 "sample rate tracker lock status change\n"); 1252 #endif 1253 } 1254 1255 if (stat & EMU_IPR_MIDIRECVBUFE) 1256 if (sc->mpu_intr) { 1257 (sc->mpu_intr)(sc->mpu); 1258 ack |= EMU_IPR_MIDIRECVBUFE | EMU_IPR_MIDITRANSBUFE; 1259 } 1260 if (stat & ~ack) 1261 device_printf(sc->dev, "dodgy irq: %x (harmless)\n", 1262 stat & ~ack); 1263 1264 emu_wr(sc, EMU_IPR, stat, 4); 1265 1266 if (ack) { 1267 snd_mtxunlock(sc->lock); 1268 1269 if (ack & EMU_IPR_INTERVALTIMER) { 1270 x = 0; 1271 for (i = 0; i < sc->nchans; i++) { 1272 if (sc->pch[i].run) { 1273 x = 1; 1274 chn_intr(sc->pch[i].channel); 1275 } 1276 } 1277 if (x == 0) 1278 emu_enatimer(sc, 0); 1279 } 1280 1281 1282 if (ack & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL)) { 1283 if (sc->rch[0].channel) 1284 chn_intr(sc->rch[0].channel); 1285 } 1286 if (ack & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL)) { 1287 if (sc->rch[1].channel) 1288 chn_intr(sc->rch[1].channel); 1289 } 1290 if (ack & (EMU_IPR_MICBUFFULL | EMU_IPR_MICBUFHALFFULL)) { 1291 if (sc->rch[2].channel) 1292 chn_intr(sc->rch[2].channel); 1293 } 1294 1295 snd_mtxlock(sc->lock); 1296 } 1297 } 1298 snd_mtxunlock(sc->lock); 1299 } 1300 1301 /* -------------------------------------------------------------------- */ 1302 1303 static void 1304 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1305 { 1306 bus_addr_t *phys = arg; 1307 1308 *phys = error ? 0 : (bus_addr_t)segs->ds_addr; 1309 1310 if (bootverbose) { 1311 printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n", 1312 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len, 1313 nseg, error); 1314 } 1315 } 1316 1317 static void * 1318 emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr) 1319 { 1320 void *buf; 1321 bus_dmamap_t map; 1322 1323 *addr = 0; 1324 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map)) 1325 return NULL; 1326 if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, emu_setmap, addr, 0) 1327 || !*addr) 1328 return NULL; 1329 return buf; 1330 } 1331 1332 static void 1333 emu_free(struct sc_info *sc, void *buf) 1334 { 1335 bus_dmamem_free(sc->parent_dmat, buf, NULL); 1336 } 1337 1338 static void * 1339 emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr) 1340 { 1341 u_int32_t blksz, start, idx, ofs, tmp, found; 1342 struct emu_mem *mem = &sc->mem; 1343 struct emu_memblk *blk; 1344 void *buf; 1345 1346 blksz = sz / EMUPAGESIZE; 1347 if (sz > (blksz * EMUPAGESIZE)) 1348 blksz++; 1349 /* find a free block in the bitmap */ 1350 found = 0; 1351 start = 1; 1352 while (!found && start + blksz < EMUMAXPAGES) { 1353 found = 1; 1354 for (idx = start; idx < start + blksz; idx++) 1355 if (mem->bmap[idx >> 3] & (1 << (idx & 7))) 1356 found = 0; 1357 if (!found) 1358 start++; 1359 } 1360 if (!found) 1361 return NULL; 1362 blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT); 1363 if (blk == NULL) 1364 return NULL; 1365 buf = emu_malloc(sc, sz, &blk->buf_addr); 1366 *addr = blk->buf_addr; 1367 if (buf == NULL) { 1368 free(blk, M_DEVBUF); 1369 return NULL; 1370 } 1371 blk->buf = buf; 1372 blk->pte_start = start; 1373 blk->pte_size = blksz; 1374 #ifdef EMUDEBUG 1375 printf("buf %p, pte_start %d, pte_size %d\n", blk->buf, 1376 blk->pte_start, blk->pte_size); 1377 #endif 1378 ofs = 0; 1379 for (idx = start; idx < start + blksz; idx++) { 1380 mem->bmap[idx >> 3] |= 1 << (idx & 7); 1381 tmp = (u_int32_t)(u_long)((u_int8_t *)blk->buf_addr + ofs); 1382 #ifdef EMUDEBUG 1383 printf("pte[%d] -> %x phys, %x virt\n", idx, tmp, 1384 ((u_int32_t)buf) + ofs); 1385 #endif 1386 mem->ptb_pages[idx] = (tmp << 1) | idx; 1387 ofs += EMUPAGESIZE; 1388 } 1389 SLIST_INSERT_HEAD(&mem->blocks, blk, link); 1390 return buf; 1391 } 1392 1393 static int 1394 emu_memfree(struct sc_info *sc, void *buf) 1395 { 1396 u_int32_t idx, tmp; 1397 struct emu_mem *mem = &sc->mem; 1398 struct emu_memblk *blk, *i; 1399 1400 blk = NULL; 1401 SLIST_FOREACH(i, &mem->blocks, link) { 1402 if (i->buf == buf) 1403 blk = i; 1404 } 1405 if (blk == NULL) 1406 return EINVAL; 1407 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link); 1408 emu_free(sc, buf); 1409 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1410 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) { 1411 mem->bmap[idx >> 3] &= ~(1 << (idx & 7)); 1412 mem->ptb_pages[idx] = tmp | idx; 1413 } 1414 free(blk, M_DEVBUF); 1415 return 0; 1416 } 1417 1418 static int 1419 emu_memstart(struct sc_info *sc, void *buf) 1420 { 1421 struct emu_mem *mem = &sc->mem; 1422 struct emu_memblk *blk, *i; 1423 1424 blk = NULL; 1425 SLIST_FOREACH(i, &mem->blocks, link) { 1426 if (i->buf == buf) 1427 blk = i; 1428 } 1429 if (blk == NULL) 1430 return -EINVAL; 1431 return blk->pte_start; 1432 } 1433 1434 static void 1435 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1436 u_int32_t *pc) 1437 { 1438 emu_wrefx(sc, (*pc) * 2, (x << 10) | y); 1439 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w); 1440 (*pc)++; 1441 } 1442 1443 static void 1444 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1445 u_int32_t *pc) 1446 { 1447 emu_wrefx(sc, (*pc) * 2, (x << 12) | y); 1448 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w); 1449 (*pc)++; 1450 } 1451 1452 static void 1453 audigy_initefx(struct sc_info *sc) 1454 { 1455 int i; 1456 u_int32_t pc = 0; 1457 1458 /* skip 0, 0, -1, 0 - NOPs */ 1459 for (i = 0; i < 512; i++) 1460 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc); 1461 1462 for (i = 0; i < 512; i++) 1463 emu_wrptr(sc, 0, EMU_A_FXGPREGBASE + i, 0x0); 1464 1465 pc = 16; 1466 1467 /* stop fx processor */ 1468 emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP); 1469 1470 /* Audigy 2 (EMU10K2) DSP Registers: 1471 FX Bus 1472 0x000-0x00f : 16 registers (?) 1473 Input 1474 0x040/0x041 : AC97 Codec (l/r) 1475 0x042/0x043 : ADC, S/PDIF (l/r) 1476 0x044/0x045 : Optical S/PDIF in (l/r) 1477 0x046/0x047 : ? 1478 0x048/0x049 : Line/Mic 2 (l/r) 1479 0x04a/0x04b : RCA S/PDIF (l/r) 1480 0x04c/0x04d : Aux 2 (l/r) 1481 Output 1482 0x060/0x061 : Digital Front (l/r) 1483 0x062/0x063 : Digital Center/LFE 1484 0x064/0x065 : AudigyDrive Heaphone (l/r) 1485 0x066/0x067 : Digital Rear (l/r) 1486 0x068/0x069 : Analog Front (l/r) 1487 0x06a/0x06b : Analog Center/LFE 1488 0x06c/0x06d : ? 1489 0x06e/0x06f : Analog Rear (l/r) 1490 0x070/0x071 : AC97 Output (l/r) 1491 0x072/0x073 : ? 1492 0x074/0x075 : ? 1493 0x076/0x077 : ADC Recording Buffer (l/r) 1494 Constants 1495 0x0c0 - 0x0c4 = 0 - 4 1496 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20 1497 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000 1498 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000 1499 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff 1500 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc 1501 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (?) 1502 Temporary Values 1503 0x0d6 : Accumulator (?) 1504 0x0d7 : Condition Register 1505 0x0d8 : Noise source 1506 0x0d9 : Noise source 1507 Tank Memory Data Registers 1508 0x200 - 0x2ff 1509 Tank Memory Address Registers 1510 0x300 - 0x3ff 1511 General Purpose Registers 1512 0x400 - 0x5ff 1513 */ 1514 1515 /* AC97Output[l/r] = FXBus PCM[l/r] */ 1516 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000, 1517 A_C_00000000, A_FXBUS(FXBUS_PCM_LEFT), &pc); 1518 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000, 1519 A_C_00000000, A_FXBUS(FXBUS_PCM_RIGHT), &pc); 1520 1521 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */ 1522 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000, 1523 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_L), &pc); 1524 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000, 1525 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_R), &pc); 1526 1527 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1528 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1), 1529 A_C_40000000, A_GPR(0), &pc); 1530 1531 /* Headphones[l/r] = GPR[0/1] */ 1532 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L), 1533 A_C_00000000, A_C_00000000, A_GPR(0), &pc); 1534 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R), 1535 A_C_00000000, A_C_00000000, A_GPR(1), &pc); 1536 1537 /* Analog Front[l/r] = GPR[0/1] */ 1538 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000, 1539 A_C_00000000, A_GPR(0), &pc); 1540 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000, 1541 A_C_00000000, A_GPR(1), &pc); 1542 1543 /* Digital Front[l/r] = GPR[0/1] */ 1544 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000, 1545 A_C_00000000, A_GPR(0), &pc); 1546 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000, 1547 A_C_00000000, A_GPR(1), &pc); 1548 1549 /* Center and Subwoofer configuration */ 1550 /* Analog Center = GPR[0] + GPR[2] */ 1551 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000, 1552 A_GPR(0), A_GPR(2), &pc); 1553 /* Analog Sub = GPR[1] + GPR[2] */ 1554 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000, 1555 A_GPR(1), A_GPR(2), &pc); 1556 1557 /* Digital Center = GPR[0] + GPR[2] */ 1558 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000, 1559 A_GPR(0), A_GPR(2), &pc); 1560 /* Digital Sub = GPR[1] + GPR[2] */ 1561 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000, 1562 A_GPR(1), A_GPR(2), &pc); 1563 1564 #if 0 1565 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1566 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1567 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1568 A_GPR(16), A_GPR(0), &pc); 1569 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1570 A_GPR(17), A_GPR(1), &pc); 1571 1572 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1573 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1574 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1575 A_GPR(16), A_GPR(0), &pc); 1576 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1577 A_GPR(17), A_GPR(1), &pc); 1578 #else 1579 /* XXX This is just a copy to the channel, since we do not have 1580 * a patch manager, it is useful for have another output enabled. 1581 */ 1582 1583 /* Analog Rear[l/r] = GPR[0/1] */ 1584 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1585 A_C_00000000, A_GPR(0), &pc); 1586 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1587 A_C_00000000, A_GPR(1), &pc); 1588 1589 /* Digital Rear[l/r] = GPR[0/1] */ 1590 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1591 A_C_00000000, A_GPR(0), &pc); 1592 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1593 A_C_00000000, A_GPR(1), &pc); 1594 #endif 1595 1596 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1597 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000, 1598 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc); 1599 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000, 1600 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc); 1601 1602 /* resume normal operations */ 1603 emu_wrptr(sc, 0, EMU_A_DBG, 0); 1604 } 1605 1606 static void 1607 emu_initefx(struct sc_info *sc) 1608 { 1609 int i; 1610 u_int32_t pc = 16; 1611 1612 /* acc3 0,0,0,0 - NOPs */ 1613 for (i = 0; i < 512; i++) { 1614 emu_wrefx(sc, i * 2, 0x10040); 1615 emu_wrefx(sc, i * 2 + 1, 0x610040); 1616 } 1617 1618 for (i = 0; i < 256; i++) 1619 emu_wrptr(sc, 0, EMU_FXGPREGBASE + i, 0); 1620 1621 /* FX-8010 DSP Registers: 1622 FX Bus 1623 0x000-0x00f : 16 registers 1624 Input 1625 0x010/0x011 : AC97 Codec (l/r) 1626 0x012/0x013 : ADC, S/PDIF (l/r) 1627 0x014/0x015 : Mic(left), Zoom (l/r) 1628 0x016/0x017 : TOS link in (l/r) 1629 0x018/0x019 : Line/Mic 1 (l/r) 1630 0x01a/0x01b : COAX S/PDIF (l/r) 1631 0x01c/0x01d : Line/Mic 2 (l/r) 1632 Output 1633 0x020/0x021 : AC97 Output (l/r) 1634 0x022/0x023 : TOS link out (l/r) 1635 0x024/0x025 : Center/LFE 1636 0x026/0x027 : LiveDrive Headphone (l/r) 1637 0x028/0x029 : Rear Channel (l/r) 1638 0x02a/0x02b : ADC Recording Buffer (l/r) 1639 0x02c : Mic Recording Buffer 1640 0x031/0x032 : Analog Center/LFE 1641 Constants 1642 0x040 - 0x044 = 0 - 4 1643 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20 1644 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000 1645 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000 1646 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff 1647 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc 1648 0x054 = 0x5a7ef9db, 0x055 = 0x00100000 1649 Temporary Values 1650 0x056 : Accumulator 1651 0x057 : Condition Register 1652 0x058 : Noise source 1653 0x059 : Noise source 1654 0x05a : IRQ Register 1655 0x05b : TRAM Delay Base Address Count 1656 General Purpose Registers 1657 0x100 - 0x1ff 1658 Tank Memory Data Registers 1659 0x200 - 0x2ff 1660 Tank Memory Address Registers 1661 0x300 - 0x3ff 1662 */ 1663 1664 /* Routing - this will be configurable in later version */ 1665 1666 /* GPR[0/1] = FX * 4 + SPDIF-in */ 1667 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L), 1668 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc); 1669 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R), 1670 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc); 1671 1672 /* GPR[0/1] += APS-input */ 1673 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000, 1674 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc); 1675 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000, 1676 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc); 1677 1678 /* FrontOut (AC97) = GPR[0/1] */ 1679 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000, 1680 C_00000000, GPR(0), &pc); 1681 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000, 1682 C_00000001, GPR(1), &pc); 1683 1684 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1685 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc); 1686 1687 #if 0 1688 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */ 1689 /* RearVolume = GPR[0x10/0x11] */ 1690 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000, 1691 GPR(16), GPR(0), &pc); 1692 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000, 1693 GPR(17), GPR(1), &pc); 1694 #else 1695 /* XXX This is just a copy to the channel, since we do not have 1696 * a patch manager, it is useful for have another output enabled. 1697 */ 1698 1699 /* Rear[l/r] = GPR[0/1] */ 1700 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000, 1701 C_00000000, GPR(0), &pc); 1702 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000, 1703 C_00000000, GPR(1), &pc); 1704 #endif 1705 1706 /* TOS out[l/r] = GPR[0/1] */ 1707 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000, 1708 C_00000000, GPR(0), &pc); 1709 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000, 1710 C_00000000, GPR(1), &pc); 1711 1712 /* Center and Subwoofer configuration */ 1713 /* Analog Center = GPR[0] + GPR[2] */ 1714 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000, 1715 GPR(0), GPR(2), &pc); 1716 /* Analog Sub = GPR[1] + GPR[2] */ 1717 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000, 1718 GPR(1), GPR(2), &pc); 1719 /* Digital Center = GPR[0] + GPR[2] */ 1720 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_CENTER), C_00000000, 1721 GPR(0), GPR(2), &pc); 1722 /* Digital Sub = GPR[1] + GPR[2] */ 1723 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_LFE), C_00000000, 1724 GPR(1), GPR(2), &pc); 1725 1726 /* Headphones[l/r] = GPR[0/1] */ 1727 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000, 1728 C_00000000, GPR(0), &pc); 1729 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000, 1730 C_00000000, GPR(1), &pc); 1731 1732 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1733 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000, 1734 C_00000000, EXTIN(EXTIN_AC97_L), &pc); 1735 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000, 1736 C_00000000, EXTIN(EXTIN_AC97_R), &pc); 1737 1738 /* resume normal operations */ 1739 emu_wrptr(sc, 0, EMU_DBG, 0); 1740 } 1741 1742 /* Probe and attach the card */ 1743 static int 1744 emu_init(struct sc_info *sc) 1745 { 1746 u_int32_t spcs, ch, tmp, i; 1747 1748 if (sc->audigy) { 1749 /* enable additional AC97 slots */ 1750 emu_wrptr(sc, 0, EMU_AC97SLOT, EMU_AC97SLOT_CENTER | EMU_AC97SLOT_LFE); 1751 } 1752 1753 /* disable audio and lock cache */ 1754 emu_wr(sc, EMU_HCFG, 1755 EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE, 1756 4); 1757 1758 /* reset recording buffers */ 1759 emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE); 1760 emu_wrptr(sc, 0, EMU_MICBA, 0); 1761 emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE); 1762 emu_wrptr(sc, 0, EMU_FXBA, 0); 1763 emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE); 1764 emu_wrptr(sc, 0, EMU_ADCBA, 0); 1765 1766 /* disable channel interrupt */ 1767 emu_wr(sc, EMU_INTE, 1768 EMU_INTE_INTERTIMERENB | EMU_INTE_SAMPLERATER | EMU_INTE_PCIERRENABLE, 1769 4); 1770 emu_wrptr(sc, 0, EMU_CLIEL, 0); 1771 emu_wrptr(sc, 0, EMU_CLIEH, 0); 1772 emu_wrptr(sc, 0, EMU_SOLEL, 0); 1773 emu_wrptr(sc, 0, EMU_SOLEH, 0); 1774 1775 /* wonder what these do... */ 1776 if (sc->audigy) { 1777 emu_wrptr(sc, 0, EMU_SPBYPASS, 0xf00); 1778 emu_wrptr(sc, 0, EMU_AC97SLOT, 0x3); 1779 } 1780 1781 /* init envelope engine */ 1782 for (ch = 0; ch < NUM_G; ch++) { 1783 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF); 1784 emu_wrptr(sc, ch, EMU_CHAN_IP, 0); 1785 emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0xffff); 1786 emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0xffff); 1787 emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0); 1788 emu_wrptr(sc, ch, EMU_CHAN_CPF, 0); 1789 emu_wrptr(sc, ch, EMU_CHAN_CCR, 0); 1790 1791 emu_wrptr(sc, ch, EMU_CHAN_PSST, 0); 1792 emu_wrptr(sc, ch, EMU_CHAN_DSL, 0x10); 1793 emu_wrptr(sc, ch, EMU_CHAN_CCCA, 0); 1794 emu_wrptr(sc, ch, EMU_CHAN_Z1, 0); 1795 emu_wrptr(sc, ch, EMU_CHAN_Z2, 0); 1796 emu_wrptr(sc, ch, EMU_CHAN_FXRT, 0xd01c0000); 1797 1798 emu_wrptr(sc, ch, EMU_CHAN_ATKHLDM, 0); 1799 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSM, 0); 1800 emu_wrptr(sc, ch, EMU_CHAN_IFATN, 0xffff); 1801 emu_wrptr(sc, ch, EMU_CHAN_PEFE, 0); 1802 emu_wrptr(sc, ch, EMU_CHAN_FMMOD, 0); 1803 emu_wrptr(sc, ch, EMU_CHAN_TREMFRQ, 24); /* 1 Hz */ 1804 emu_wrptr(sc, ch, EMU_CHAN_FM2FRQ2, 24); /* 1 Hz */ 1805 emu_wrptr(sc, ch, EMU_CHAN_TEMPENV, 0); 1806 1807 /*** these are last so OFF prevents writing ***/ 1808 emu_wrptr(sc, ch, EMU_CHAN_LFOVAL2, 0); 1809 emu_wrptr(sc, ch, EMU_CHAN_LFOVAL1, 0); 1810 emu_wrptr(sc, ch, EMU_CHAN_ATKHLDV, 0); 1811 emu_wrptr(sc, ch, EMU_CHAN_ENVVOL, 0); 1812 emu_wrptr(sc, ch, EMU_CHAN_ENVVAL, 0); 1813 1814 if (sc->audigy) { 1815 /* audigy cards need this to initialize correctly */ 1816 emu_wrptr(sc, ch, 0x4c, 0); 1817 emu_wrptr(sc, ch, 0x4d, 0); 1818 emu_wrptr(sc, ch, 0x4e, 0); 1819 emu_wrptr(sc, ch, 0x4f, 0); 1820 /* set default routing */ 1821 emu_wrptr(sc, ch, EMU_A_CHAN_FXRT1, 0x03020100); 1822 emu_wrptr(sc, ch, EMU_A_CHAN_FXRT2, 0x3f3f3f3f); 1823 emu_wrptr(sc, ch, EMU_A_CHAN_SENDAMOUNTS, 0); 1824 } 1825 1826 sc->voice[ch].vnum = ch; 1827 sc->voice[ch].slave = NULL; 1828 sc->voice[ch].busy = 0; 1829 sc->voice[ch].ismaster = 0; 1830 sc->voice[ch].running = 0; 1831 sc->voice[ch].b16 = 0; 1832 sc->voice[ch].stereo = 0; 1833 sc->voice[ch].speed = 0; 1834 sc->voice[ch].start = 0; 1835 sc->voice[ch].end = 0; 1836 sc->voice[ch].channel = NULL; 1837 } 1838 sc->pnum = sc->rnum = 0; 1839 1840 /* 1841 * Init to 0x02109204 : 1842 * Clock accuracy = 0 (1000ppm) 1843 * Sample Rate = 2 (48kHz) 1844 * Audio Channel = 1 (Left of 2) 1845 * Source Number = 0 (Unspecified) 1846 * Generation Status = 1 (Original for Cat Code 12) 1847 * Cat Code = 12 (Digital Signal Mixer) 1848 * Mode = 0 (Mode 0) 1849 * Emphasis = 0 (None) 1850 * CP = 1 (Copyright unasserted) 1851 * AN = 0 (Audio data) 1852 * P = 0 (Consumer) 1853 */ 1854 spcs = EMU_SPCS_CLKACCY_1000PPM | EMU_SPCS_SAMPLERATE_48 | 1855 EMU_SPCS_CHANNELNUM_LEFT | EMU_SPCS_SOURCENUM_UNSPEC | 1856 EMU_SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 | 1857 EMU_SPCS_EMPHASIS_NONE | EMU_SPCS_COPYRIGHT; 1858 emu_wrptr(sc, 0, EMU_SPCS0, spcs); 1859 emu_wrptr(sc, 0, EMU_SPCS1, spcs); 1860 emu_wrptr(sc, 0, EMU_SPCS2, spcs); 1861 1862 if (!sc->audigy) 1863 emu_initefx(sc); 1864 else if (sc->audigy2) { /* Audigy 2 */ 1865 /* from ALSA initialization code: */ 1866 1867 /* Hack for Alice3 to work independent of haP16V driver */ 1868 u_int32_t tmp; 1869 1870 /* Setup SRCMulti_I2S SamplingRate */ 1871 tmp = emu_rdptr(sc, 0, EMU_A_SPDIF_SAMPLERATE) & 0xfffff1ff; 1872 emu_wrptr(sc, 0, EMU_A_SPDIF_SAMPLERATE, tmp | 0x400); 1873 1874 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */ 1875 emu_wr(sc, 0x20, 0x00600000, 4); 1876 emu_wr(sc, 0x24, 0x00000014, 4); 1877 1878 /* Setup SRCMulti Input Audio Enable */ 1879 emu_wr(sc, 0x20, 0x006e0000, 4); 1880 emu_wr(sc, 0x24, 0xff00ff00, 4); 1881 } 1882 1883 SLIST_INIT(&sc->mem.blocks); 1884 sc->mem.ptb_pages = emu_malloc(sc, EMUMAXPAGES * sizeof(u_int32_t), 1885 &sc->mem.ptb_pages_addr); 1886 if (sc->mem.ptb_pages == NULL) 1887 return -1; 1888 1889 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE, 1890 &sc->mem.silent_page_addr); 1891 if (sc->mem.silent_page == NULL) { 1892 emu_free(sc, sc->mem.ptb_pages); 1893 return -1; 1894 } 1895 /* Clear page with silence & setup all pointers to this page */ 1896 bzero(sc->mem.silent_page, EMUPAGESIZE); 1897 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1898 for (i = 0; i < EMUMAXPAGES; i++) 1899 sc->mem.ptb_pages[i] = tmp | i; 1900 1901 emu_wrptr(sc, 0, EMU_PTB, (sc->mem.ptb_pages_addr)); 1902 emu_wrptr(sc, 0, EMU_TCB, 0); /* taken from original driver */ 1903 emu_wrptr(sc, 0, EMU_TCBS, 0); /* taken from original driver */ 1904 1905 for (ch = 0; ch < NUM_G; ch++) { 1906 emu_wrptr(sc, ch, EMU_CHAN_MAPA, tmp | EMU_CHAN_MAP_PTI_MASK); 1907 emu_wrptr(sc, ch, EMU_CHAN_MAPB, tmp | EMU_CHAN_MAP_PTI_MASK); 1908 } 1909 1910 /* emu_memalloc(sc, EMUPAGESIZE); */ 1911 /* 1912 * Hokay, now enable the AUD bit 1913 * 1914 * Audigy 1915 * Enable Audio = 0 (enabled after fx processor initialization) 1916 * Mute Disable Audio = 0 1917 * Joystick = 1 1918 * 1919 * Audigy 2 1920 * Enable Audio = 1 1921 * Mute Disable Audio = 0 1922 * Joystick = 1 1923 * GP S/PDIF AC3 Enable = 1 1924 * CD S/PDIF AC3 Enable = 1 1925 * 1926 * EMU10K1 1927 * Enable Audio = 1 1928 * Mute Disable Audio = 0 1929 * Lock Tank Memory = 1 1930 * Lock Sound Memory = 0 1931 * Auto Mute = 1 1932 */ 1933 1934 if (sc->audigy) { 1935 tmp = EMU_HCFG_AUTOMUTE | EMU_HCFG_JOYENABLE; 1936 if (sc->audigy2) /* Audigy 2 */ 1937 tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_AC3ENABLE_CDSPDIF | 1938 EMU_HCFG_AC3ENABLE_GPSPDIF; 1939 emu_wr(sc, EMU_HCFG, tmp, 4); 1940 1941 audigy_initefx(sc); 1942 1943 /* from ALSA initialization code: */ 1944 1945 /* enable audio and disable both audio/digital outputs */ 1946 emu_wr(sc, EMU_HCFG, emu_rd(sc, EMU_HCFG, 4) | EMU_HCFG_AUDIOENABLE, 4); 1947 emu_wr(sc, EMU_A_IOCFG, emu_rd(sc, EMU_A_IOCFG, 4) & ~EMU_A_IOCFG_GPOUT_AD, 1948 4); 1949 if (sc->audigy2) { /* Audigy 2 */ 1950 /* Unmute Analog. 1951 * Set GPO6 to 1 for Apollo. This has to be done after 1952 * init Alice3 I2SOut beyond 48kHz. 1953 * So, sequence is important. 1954 */ 1955 emu_wr(sc, EMU_A_IOCFG, 1956 emu_rd(sc, EMU_A_IOCFG, 4) | EMU_A_IOCFG_GPOUT_A, 4); 1957 } 1958 } else { 1959 /* EMU10K1 initialization code */ 1960 tmp = EMU_HCFG_AUDIOENABLE | EMU_HCFG_LOCKTANKCACHE_MASK 1961 | EMU_HCFG_AUTOMUTE; 1962 if (sc->rev >= 6) 1963 tmp |= EMU_HCFG_JOYENABLE; 1964 1965 emu_wr(sc, EMU_HCFG, tmp, 4); 1966 1967 /* TOSLink detection */ 1968 sc->tos_link = 0; 1969 tmp = emu_rd(sc, EMU_HCFG, 4); 1970 if (tmp & (EMU_HCFG_GPINPUT0 | EMU_HCFG_GPINPUT1)) { 1971 emu_wr(sc, EMU_HCFG, tmp | EMU_HCFG_GPOUT1, 4); 1972 DELAY(50); 1973 if (tmp != (emu_rd(sc, EMU_HCFG, 4) & ~EMU_HCFG_GPOUT1)) { 1974 sc->tos_link = 1; 1975 emu_wr(sc, EMU_HCFG, tmp, 4); 1976 } 1977 } 1978 } 1979 1980 return 0; 1981 } 1982 1983 static int 1984 emu_uninit(struct sc_info *sc) 1985 { 1986 u_int32_t ch; 1987 1988 emu_wr(sc, EMU_INTE, 0, 4); 1989 for (ch = 0; ch < NUM_G; ch++) 1990 emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, ENV_OFF); 1991 for (ch = 0; ch < NUM_G; ch++) { 1992 emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0); 1993 emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0); 1994 emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0); 1995 emu_wrptr(sc, ch, EMU_CHAN_CPF, 0); 1996 } 1997 1998 if (sc->audigy) { /* stop fx processor */ 1999 emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP); 2000 } 2001 2002 /* disable audio and lock cache */ 2003 emu_wr(sc, EMU_HCFG, 2004 EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE, 2005 4); 2006 2007 emu_wrptr(sc, 0, EMU_PTB, 0); 2008 /* reset recording buffers */ 2009 emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE); 2010 emu_wrptr(sc, 0, EMU_MICBA, 0); 2011 emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE); 2012 emu_wrptr(sc, 0, EMU_FXBA, 0); 2013 emu_wrptr(sc, 0, EMU_FXWC, 0); 2014 emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE); 2015 emu_wrptr(sc, 0, EMU_ADCBA, 0); 2016 emu_wrptr(sc, 0, EMU_TCB, 0); 2017 emu_wrptr(sc, 0, EMU_TCBS, 0); 2018 2019 /* disable channel interrupt */ 2020 emu_wrptr(sc, 0, EMU_CLIEL, 0); 2021 emu_wrptr(sc, 0, EMU_CLIEH, 0); 2022 emu_wrptr(sc, 0, EMU_SOLEL, 0); 2023 emu_wrptr(sc, 0, EMU_SOLEH, 0); 2024 2025 /* init envelope engine */ 2026 if (!SLIST_EMPTY(&sc->mem.blocks)) 2027 device_printf(sc->dev, "warning: memblock list not empty\n"); 2028 emu_free(sc, sc->mem.ptb_pages); 2029 emu_free(sc, sc->mem.silent_page); 2030 2031 if(sc->mpu) 2032 mpu401_uninit(sc->mpu); 2033 return 0; 2034 } 2035 2036 static int 2037 emu_pci_probe(device_t dev) 2038 { 2039 char *s = NULL; 2040 2041 switch (pci_get_devid(dev)) { 2042 case EMU10K1_PCI_ID: 2043 s = "Creative EMU10K1"; 2044 break; 2045 2046 case EMU10K2_PCI_ID: 2047 if (pci_get_revid(dev) == 0x04) 2048 s = "Creative Audigy 2 (EMU10K2)"; 2049 else 2050 s = "Creative Audigy (EMU10K2)"; 2051 break; 2052 2053 case EMU10K3_PCI_ID: 2054 s = "Creative Audigy 2 (EMU10K3)"; 2055 break; 2056 2057 default: 2058 return ENXIO; 2059 } 2060 2061 device_set_desc(dev, s); 2062 return BUS_PROBE_LOW_PRIORITY; 2063 } 2064 2065 static int 2066 emu_pci_attach(device_t dev) 2067 { 2068 struct ac97_info *codec = NULL; 2069 struct sc_info *sc; 2070 int i, gotmic; 2071 char status[SND_STATUSLEN]; 2072 2073 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 2074 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_emu10k1 softc"); 2075 sc->dev = dev; 2076 sc->type = pci_get_devid(dev); 2077 sc->rev = pci_get_revid(dev); 2078 sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID; 2079 sc->audigy2 = (sc->audigy && sc->rev == 0x04); 2080 sc->nchans = sc->audigy ? 8 : 4; 2081 sc->addrmask = sc->audigy ? EMU_A_PTR_ADDR_MASK : EMU_PTR_ADDR_MASK; 2082 2083 pci_enable_busmaster(dev); 2084 2085 i = PCIR_BAR(0); 2086 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE); 2087 if (sc->reg == NULL) { 2088 device_printf(dev, "unable to map register space\n"); 2089 goto bad; 2090 } 2091 sc->st = rman_get_bustag(sc->reg); 2092 sc->sh = rman_get_bushandle(sc->reg); 2093 2094 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536); 2095 2096 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 2097 /*boundary*/0, 2098 /*lowaddr*/(1U << 31) - 1, /* can only access 0-2gb */ 2099 /*highaddr*/BUS_SPACE_MAXADDR, 2100 /*filter*/NULL, /*filterarg*/NULL, 2101 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 2102 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 2103 /*lockarg*/&Giant, &sc->parent_dmat) != 0) { 2104 device_printf(dev, "unable to create dma tag\n"); 2105 goto bad; 2106 } 2107 2108 if (emu_init(sc) == -1) { 2109 device_printf(dev, "unable to initialize the card\n"); 2110 goto bad; 2111 } 2112 2113 codec = AC97_CREATE(dev, sc, emu_ac97); 2114 if (codec == NULL) goto bad; 2115 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL) ? 1 : 0; 2116 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 2117 2118 emu_midiattach(sc); 2119 2120 i = 0; 2121 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, 2122 RF_ACTIVE | RF_SHAREABLE); 2123 if (!sc->irq || 2124 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) { 2125 device_printf(dev, "unable to map interrupt\n"); 2126 goto bad; 2127 } 2128 2129 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 2130 rman_get_start(sc->reg), rman_get_start(sc->irq), 2131 PCM_KLDSTRING(snd_emu10k1)); 2132 2133 if (pcm_register(dev, sc, sc->nchans, gotmic ? 3 : 2)) goto bad; 2134 for (i = 0; i < sc->nchans; i++) 2135 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc); 2136 for (i = 0; i < (gotmic ? 3 : 2); i++) 2137 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc); 2138 2139 pcm_setstatus(dev, status); 2140 2141 return 0; 2142 2143 bad: 2144 if (codec) ac97_destroy(codec); 2145 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2146 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih); 2147 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2148 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat); 2149 if (sc->lock) snd_mtxfree(sc->lock); 2150 free(sc, M_DEVBUF); 2151 return ENXIO; 2152 } 2153 2154 static int 2155 emu_pci_detach(device_t dev) 2156 { 2157 int r; 2158 struct sc_info *sc; 2159 2160 r = pcm_unregister(dev); 2161 if (r) 2162 return r; 2163 2164 sc = pcm_getdevinfo(dev); 2165 /* shutdown chip */ 2166 emu_uninit(sc); 2167 2168 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2169 bus_teardown_intr(dev, sc->irq, sc->ih); 2170 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2171 bus_dma_tag_destroy(sc->parent_dmat); 2172 snd_mtxfree(sc->lock); 2173 free(sc, M_DEVBUF); 2174 2175 return 0; 2176 } 2177 2178 /* add suspend, resume */ 2179 static device_method_t emu_methods[] = { 2180 /* Device interface */ 2181 DEVMETHOD(device_probe, emu_pci_probe), 2182 DEVMETHOD(device_attach, emu_pci_attach), 2183 DEVMETHOD(device_detach, emu_pci_detach), 2184 2185 { 0, 0 } 2186 }; 2187 2188 static driver_t emu_driver = { 2189 "pcm", 2190 emu_methods, 2191 PCM_SOFTC_SIZE, 2192 }; 2193 2194 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, 0, 0); 2195 MODULE_DEPEND(snd_emu10k1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 2196 MODULE_VERSION(snd_emu10k1, 1); 2197 MODULE_DEPEND(snd_emu10k1, midi, 1, 1, 1); 2198 2199 /* dummy driver to silence the joystick device */ 2200 static int 2201 emujoy_pci_probe(device_t dev) 2202 { 2203 char *s = NULL; 2204 2205 switch (pci_get_devid(dev)) { 2206 case 0x70021102: 2207 s = "Creative EMU10K1 Joystick"; 2208 device_quiet(dev); 2209 break; 2210 case 0x70031102: 2211 s = "Creative EMU10K2 Joystick"; 2212 device_quiet(dev); 2213 break; 2214 } 2215 2216 if (s) device_set_desc(dev, s); 2217 return s ? -1000 : ENXIO; 2218 } 2219 2220 static int 2221 emujoy_pci_attach(device_t dev) 2222 { 2223 return 0; 2224 } 2225 2226 static int 2227 emujoy_pci_detach(device_t dev) 2228 { 2229 return 0; 2230 } 2231 2232 static device_method_t emujoy_methods[] = { 2233 DEVMETHOD(device_probe, emujoy_pci_probe), 2234 DEVMETHOD(device_attach, emujoy_pci_attach), 2235 DEVMETHOD(device_detach, emujoy_pci_detach), 2236 2237 { 0, 0 } 2238 }; 2239 2240 static driver_t emujoy_driver = { 2241 "emujoy", 2242 emujoy_methods, 2243 8, 2244 }; 2245 2246 static devclass_t emujoy_devclass; 2247 2248 DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, 0, 0); 2249 2250