xref: /freebsd/sys/dev/sound/pci/emu10k1.c (revision 282a3889ebf826db9839be296ff1dd903f6d6d6e)
1 /*-
2  * Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org>
3  * Copyright (c) 2003 Orlando Bassotto <orlando.bassotto@ieo-research.it>
4  * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <dev/sound/pcm/sound.h>
30 #include <dev/sound/pcm/ac97.h>
31 #include "emu10k1-alsa%diked.h"
32 
33 #include <dev/pci/pcireg.h>
34 #include <dev/pci/pcivar.h>
35 #include <sys/queue.h>
36 
37 #include <dev/sound/midi/mpu401.h>
38 #include "mpufoi_if.h"
39 
40 SND_DECLARE_FILE("$FreeBSD$");
41 
42 /* -------------------------------------------------------------------- */
43 
44 #define	NUM_G		64	/* use all channels */
45 #define	WAVEOUT_MAXBUFSIZE 32768
46 #define	EMUPAGESIZE	4096	/* don't change */
47 #define	EMUMAXPAGES	(WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE)
48 #define	EMU10K1_PCI_ID	0x00021102	/* 1102 => Creative Labs Vendor ID */
49 #define	EMU10K2_PCI_ID	0x00041102
50 #define	EMU10K3_PCI_ID	0x00081102
51 #define	EMU_DEFAULT_BUFSZ	4096
52 #define EMU_MAX_CHANS	8
53 #define	EMU_CHANS	4
54 
55 #define	MAXREQVOICES	8
56 #define	RESERVED	0
57 #define	NUM_MIDI	16
58 #define	NUM_FXSENDS	4
59 
60 #define	TMEMSIZE	256*1024
61 #define	TMEMSIZEREG	4
62 
63 #define	ENABLE		0xffffffff
64 #define	DISABLE		0x00000000
65 #define	ENV_ON		DCYSUSV_CHANNELENABLE_MASK
66 #define	ENV_OFF		0x00	/* XXX: should this be 1? */
67 
68 #define	A_IOCFG_GPOUT_A	0x40	/* Analog Output */
69 #define	A_IOCFG_GPOUT_D	0x04	/* Digital Output */
70 #define	A_IOCFG_GPOUT_AD (A_IOCFG_GPOUT_A|A_IOCFG_GPOUT_D)  /* A_IOCFG_GPOUT0 */
71 
72 struct emu_memblk {
73 	SLIST_ENTRY(emu_memblk) link;
74 	void *buf;
75 	bus_addr_t buf_addr;
76 	u_int32_t pte_start, pte_size;
77 };
78 
79 struct emu_mem {
80 	u_int8_t bmap[EMUMAXPAGES / 8];
81 	u_int32_t *ptb_pages;
82 	void *silent_page;
83 	bus_addr_t silent_page_addr;
84 	bus_addr_t ptb_pages_addr;
85 	SLIST_HEAD(, emu_memblk) blocks;
86 };
87 
88 struct emu_voice {
89 	int vnum;
90 	unsigned int b16:1, stereo:1, busy:1, running:1, ismaster:1;
91 	int speed;
92 	int start, end, vol;
93 	int fxrt1;	/* FX routing */
94 	int fxrt2;	/* FX routing (only for audigy) */
95 	u_int32_t buf;
96 	struct emu_voice *slave;
97 	struct pcm_channel *channel;
98 };
99 
100 struct sc_info;
101 
102 /* channel registers */
103 struct sc_pchinfo {
104 	int spd, fmt, blksz, run;
105 	struct emu_voice *master, *slave;
106 	struct snd_dbuf *buffer;
107 	struct pcm_channel *channel;
108 	struct sc_info *parent;
109 };
110 
111 struct sc_rchinfo {
112 	int spd, fmt, run, blksz, num;
113 	u_int32_t idxreg, basereg, sizereg, setupreg, irqmask;
114 	struct snd_dbuf *buffer;
115 	struct pcm_channel *channel;
116 	struct sc_info *parent;
117 };
118 
119 /* device private data */
120 struct sc_info {
121 	device_t	dev;
122 	u_int32_t	type, rev;
123 	u_int32_t	tos_link:1, APS:1, audigy:1, audigy2:1;
124 	u_int32_t	addrmask;	/* wider if audigy */
125 
126 	bus_space_tag_t st;
127 	bus_space_handle_t sh;
128 	bus_dma_tag_t parent_dmat;
129 
130 	struct resource *reg, *irq;
131 	void		*ih;
132 	struct mtx	*lock;
133 
134 	unsigned int bufsz;
135 	int timer, timerinterval;
136 	int pnum, rnum;
137 	int nchans;
138 	struct emu_mem mem;
139 	struct emu_voice voice[64];
140 	struct sc_pchinfo pch[EMU_MAX_CHANS];
141 	struct sc_rchinfo rch[3];
142 	struct mpu401   *mpu;
143 	mpu401_intr_t           *mpu_intr;
144 	int mputx;
145 };
146 
147 /* -------------------------------------------------------------------- */
148 
149 /*
150  * prototypes
151  */
152 
153 /* stuff */
154 static int emu_init(struct sc_info *);
155 static void emu_intr(void *);
156 static void *emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr);
157 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr);
158 static int emu_memfree(struct sc_info *sc, void *buf);
159 static int emu_memstart(struct sc_info *sc, void *buf);
160 #ifdef EMUDEBUG
161 static void emu_vdump(struct sc_info *sc, struct emu_voice *v);
162 #endif
163 
164 /* talk to the card */
165 static u_int32_t emu_rd(struct sc_info *, int, int);
166 static void emu_wr(struct sc_info *, int, u_int32_t, int);
167 
168 /* -------------------------------------------------------------------- */
169 
170 static u_int32_t emu_rfmt_ac97[] = {
171 	AFMT_S16_LE,
172 	AFMT_STEREO | AFMT_S16_LE,
173 	0
174 };
175 
176 static u_int32_t emu_rfmt_mic[] = {
177 	AFMT_U8,
178 	0
179 };
180 
181 static u_int32_t emu_rfmt_efx[] = {
182 	AFMT_STEREO | AFMT_S16_LE,
183 	0
184 };
185 
186 static struct pcmchan_caps emu_reccaps[3] = {
187 	{8000, 48000, emu_rfmt_ac97, 0},
188 	{8000, 8000, emu_rfmt_mic, 0},
189 	{48000, 48000, emu_rfmt_efx, 0},
190 };
191 
192 static u_int32_t emu_pfmt[] = {
193 	AFMT_U8,
194 	AFMT_STEREO | AFMT_U8,
195 	AFMT_S16_LE,
196 	AFMT_STEREO | AFMT_S16_LE,
197 	0
198 };
199 
200 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0};
201 
202 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000};
203 /* audigy supports 12kHz. */
204 static int audigy_adcspeed[9] = {
205 	48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000
206 };
207 
208 /* -------------------------------------------------------------------- */
209 /* Hardware */
210 static u_int32_t
211 emu_rd(struct sc_info *sc, int regno, int size)
212 {
213 	switch (size) {
214 	case 1:
215 		return bus_space_read_1(sc->st, sc->sh, regno);
216 	case 2:
217 		return bus_space_read_2(sc->st, sc->sh, regno);
218 	case 4:
219 		return bus_space_read_4(sc->st, sc->sh, regno);
220 	default:
221 		return 0xffffffff;
222 	}
223 }
224 
225 static void
226 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
227 {
228 	switch (size) {
229 	case 1:
230 		bus_space_write_1(sc->st, sc->sh, regno, data);
231 		break;
232 	case 2:
233 		bus_space_write_2(sc->st, sc->sh, regno, data);
234 		break;
235 	case 4:
236 		bus_space_write_4(sc->st, sc->sh, regno, data);
237 		break;
238 	}
239 }
240 
241 static u_int32_t
242 emu_rdptr(struct sc_info *sc, int chn, int reg)
243 {
244 	u_int32_t ptr, val, mask, size, offset;
245 
246 	ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
247 	emu_wr(sc, PTR, ptr, 4);
248 	val = emu_rd(sc, DATA, 4);
249 	if (reg & 0xff000000) {
250 		size = (reg >> 24) & 0x3f;
251 		offset = (reg >> 16) & 0x1f;
252 		mask = ((1 << size) - 1) << offset;
253 		val &= mask;
254 		val >>= offset;
255 	}
256 	return val;
257 }
258 
259 static void
260 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data)
261 {
262 	u_int32_t ptr, mask, size, offset;
263 
264 	ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
265 	emu_wr(sc, PTR, ptr, 4);
266 	if (reg & 0xff000000) {
267 		size = (reg >> 24) & 0x3f;
268 		offset = (reg >> 16) & 0x1f;
269 		mask = ((1 << size) - 1) << offset;
270 		data <<= offset;
271 		data &= mask;
272 		data |= emu_rd(sc, DATA, 4) & ~mask;
273 	}
274 	emu_wr(sc, DATA, data, 4);
275 }
276 
277 static void
278 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data)
279 {
280 	pc += sc->audigy ? A_MICROCODEBASE : MICROCODEBASE;
281 	emu_wrptr(sc, 0, pc, data);
282 }
283 
284 /* -------------------------------------------------------------------- */
285 /* ac97 codec */
286 /* no locking needed */
287 
288 static int
289 emu_rdcd(kobj_t obj, void *devinfo, int regno)
290 {
291 	struct sc_info *sc = (struct sc_info *)devinfo;
292 
293 	emu_wr(sc, AC97ADDRESS, regno, 1);
294 	return emu_rd(sc, AC97DATA, 2);
295 }
296 
297 static int
298 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
299 {
300 	struct sc_info *sc = (struct sc_info *)devinfo;
301 
302 	emu_wr(sc, AC97ADDRESS, regno, 1);
303 	emu_wr(sc, AC97DATA, data, 2);
304 	return 0;
305 }
306 
307 static kobj_method_t emu_ac97_methods[] = {
308 	KOBJMETHOD(ac97_read,		emu_rdcd),
309 	KOBJMETHOD(ac97_write,		emu_wrcd),
310 	{ 0, 0 }
311 };
312 AC97_DECLARE(emu_ac97);
313 
314 /* -------------------------------------------------------------------- */
315 /* stuff */
316 static int
317 emu_settimer(struct sc_info *sc)
318 {
319 	struct sc_pchinfo *pch;
320 	struct sc_rchinfo *rch;
321 	int i, tmp, rate;
322 
323 	rate = 0;
324 	for (i = 0; i < sc->nchans; i++) {
325 		pch = &sc->pch[i];
326 		if (pch->buffer) {
327 			tmp = (pch->spd * sndbuf_getbps(pch->buffer))
328 			    / pch->blksz;
329 			if (tmp > rate)
330 				rate = tmp;
331 		}
332 	}
333 
334 	for (i = 0; i < 3; i++) {
335 		rch = &sc->rch[i];
336 		if (rch->buffer) {
337 			tmp = (rch->spd * sndbuf_getbps(rch->buffer))
338 			    / rch->blksz;
339 			if (tmp > rate)
340 				rate = tmp;
341 		}
342 	}
343 	RANGE(rate, 48, 9600);
344 	sc->timerinterval = 48000 / rate;
345 	emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2);
346 
347 	return sc->timerinterval;
348 }
349 
350 static int
351 emu_enatimer(struct sc_info *sc, int go)
352 {
353 	u_int32_t x;
354 	if (go) {
355 		if (sc->timer++ == 0) {
356 			x = emu_rd(sc, INTE, 4);
357 			x |= INTE_INTERVALTIMERENB;
358 			emu_wr(sc, INTE, x, 4);
359 		}
360 	} else {
361 		sc->timer = 0;
362 		x = emu_rd(sc, INTE, 4);
363 		x &= ~INTE_INTERVALTIMERENB;
364 		emu_wr(sc, INTE, x, 4);
365 	}
366 	return 0;
367 }
368 
369 static void
370 emu_enastop(struct sc_info *sc, char channel, int enable)
371 {
372 	int reg = (channel & 0x20) ? SOLEH : SOLEL;
373 	channel &= 0x1f;
374 	reg |= 1 << 24;
375 	reg |= channel << 16;
376 	emu_wrptr(sc, 0, reg, enable);
377 }
378 
379 static int
380 emu_recval(int speed) {
381 	int val;
382 
383 	val = 0;
384 	while (val < 7 && speed < adcspeed[val])
385 		val++;
386 	return val;
387 }
388 
389 static int
390 audigy_recval(int speed) {
391 	int val;
392 
393 	val = 0;
394 	while (val < 8 && speed < audigy_adcspeed[val])
395 		val++;
396 	return val;
397 }
398 
399 static u_int32_t
400 emu_rate_to_pitch(u_int32_t rate)
401 {
402 	static u_int32_t logMagTable[128] = {
403 		0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
404 		0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
405 		0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,
406 		0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,
407 		0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,
408 		0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
409 		0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
410 		0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,
411 		0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
412 		0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,
413 		0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
414 		0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
415 		0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
416 		0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
417 		0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,
418 		0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
419 	};
420 	static char logSlopeTable[128] = {
421 		0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
422 		0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
423 		0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
424 		0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
425 		0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
426 		0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
427 		0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
428 		0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
429 		0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
430 		0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
431 		0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
432 		0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
433 		0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
434 		0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
435 		0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
436 		0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
437 	};
438 	int i;
439 
440 	if (rate == 0)
441 		return 0;	/* Bail out if no leading "1" */
442 	rate *= 11185;	/* Scale 48000 to 0x20002380 */
443 	for (i = 31; i > 0; i--) {
444 		if (rate & 0x80000000) {	/* Detect leading "1" */
445 			return (((u_int32_t) (i - 15) << 20) +
446 			    logMagTable[0x7f & (rate >> 24)] +
447 			    (0x7f & (rate >> 17)) *
448 			    logSlopeTable[0x7f & (rate >> 24)]);
449 		}
450 		rate <<= 1;
451 	}
452 
453 	return 0;		/* Should never reach this point */
454 }
455 
456 static u_int32_t
457 emu_rate_to_linearpitch(u_int32_t rate)
458 {
459 	rate = (rate << 8) / 375;
460 	return (rate >> 1) + (rate & 1);
461 }
462 
463 static struct emu_voice *
464 emu_valloc(struct sc_info *sc)
465 {
466 	struct emu_voice *v;
467 	int i;
468 
469 	v = NULL;
470 	for (i = 0; i < 64 && sc->voice[i].busy; i++);
471 	if (i < 64) {
472 		v = &sc->voice[i];
473 		v->busy = 1;
474 	}
475 	return v;
476 }
477 
478 static int
479 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s,
480 	  u_int32_t sz, struct snd_dbuf *b)
481 {
482 	void *buf;
483 	bus_addr_t tmp_addr;
484 
485 	buf = emu_memalloc(sc, sz, &tmp_addr);
486 	if (buf == NULL)
487 		return -1;
488 	if (b != NULL)
489 		sndbuf_setup(b, buf, sz);
490 	m->start = emu_memstart(sc, buf) * EMUPAGESIZE;
491 	m->end = m->start + sz;
492 	m->channel = NULL;
493 	m->speed = 0;
494 	m->b16 = 0;
495 	m->stereo = 0;
496 	m->running = 0;
497 	m->ismaster = 1;
498 	m->vol = 0xff;
499 	m->buf = tmp_addr;
500 	m->slave = s;
501 	if (sc->audigy) {
502 		m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 8 |
503 		    FXBUS_PCM_LEFT << 16 | FXBUS_MIDI_REVERB << 24;
504 		m->fxrt2 = 0x3f3f3f3f;	/* No effects on second route */
505 	} else {
506 		m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 4 |
507 		    FXBUS_PCM_LEFT << 8 | FXBUS_MIDI_REVERB << 12;
508 		m->fxrt2 = 0;
509 	}
510 
511 	if (s != NULL) {
512 		s->start = m->start;
513 		s->end = m->end;
514 		s->channel = NULL;
515 		s->speed = 0;
516 		s->b16 = 0;
517 		s->stereo = 0;
518 		s->running = 0;
519 		s->ismaster = 0;
520 		s->vol = m->vol;
521 		s->buf = m->buf;
522 		s->fxrt1 = m->fxrt1;
523 		s->fxrt2 = m->fxrt2;
524 		s->slave = NULL;
525 	}
526 	return 0;
527 }
528 
529 static void
530 emu_vsetup(struct sc_pchinfo *ch)
531 {
532 	struct emu_voice *v = ch->master;
533 
534 	if (ch->fmt) {
535 		v->b16 = (ch->fmt & AFMT_16BIT) ? 1 : 0;
536 		v->stereo = (ch->fmt & AFMT_STEREO) ? 1 : 0;
537 		if (v->slave != NULL) {
538 			v->slave->b16 = v->b16;
539 			v->slave->stereo = v->stereo;
540 		}
541 	}
542 	if (ch->spd) {
543 		v->speed = ch->spd;
544 		if (v->slave != NULL)
545 			v->slave->speed = v->speed;
546 	}
547 }
548 
549 static void
550 emu_vwrite(struct sc_info *sc, struct emu_voice *v)
551 {
552 	int s;
553 	int l, r, x, y;
554 	u_int32_t sa, ea, start, val, silent_page;
555 
556 	s = (v->stereo ? 1 : 0) + (v->b16 ? 1 : 0);
557 
558 	sa = v->start >> s;
559 	ea = v->end >> s;
560 
561 	l = r = x = y = v->vol;
562 	if (v->stereo) {
563 		l = v->ismaster ? l : 0;
564 		r = v->ismaster ? 0 : r;
565 	}
566 
567 	emu_wrptr(sc, v->vnum, CPF, v->stereo ? CPF_STEREO_MASK : 0);
568 	val = v->stereo ? 28 : 30;
569 	val *= v->b16 ? 1 : 2;
570 	start = sa + val;
571 
572 	if (sc->audigy) {
573 		emu_wrptr(sc, v->vnum, A_FXRT1, v->fxrt1);
574 		emu_wrptr(sc, v->vnum, A_FXRT2, v->fxrt2);
575 		emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, 0);
576 	}
577 	else
578 		emu_wrptr(sc, v->vnum, FXRT, v->fxrt1 << 16);
579 
580 	emu_wrptr(sc, v->vnum, PTRX, (x << 8) | r);
581 	emu_wrptr(sc, v->vnum, DSL, ea | (y << 24));
582 	emu_wrptr(sc, v->vnum, PSST, sa | (l << 24));
583 	emu_wrptr(sc, v->vnum, CCCA, start | (v->b16 ? 0 : CCCA_8BITSELECT));
584 
585 	emu_wrptr(sc, v->vnum, Z1, 0);
586 	emu_wrptr(sc, v->vnum, Z2, 0);
587 
588 	silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1)
589 	    | MAP_PTI_MASK;
590 	emu_wrptr(sc, v->vnum, MAPA, silent_page);
591 	emu_wrptr(sc, v->vnum, MAPB, silent_page);
592 
593 	emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK);
594 	emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK);
595 	emu_wrptr(sc, v->vnum, ATKHLDM, 0);
596 	emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK);
597 	emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000);
598 	emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000);
599 	emu_wrptr(sc, v->vnum, FMMOD, 0);
600 	emu_wrptr(sc, v->vnum, TREMFRQ, 0);
601 	emu_wrptr(sc, v->vnum, FM2FRQ2, 0);
602 	emu_wrptr(sc, v->vnum, ENVVAL, 0x8000);
603 
604 	emu_wrptr(sc, v->vnum, ATKHLDV,
605 	    ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK);
606 	emu_wrptr(sc, v->vnum, ENVVOL, 0x8000);
607 
608 	emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f);
609 	emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0);
610 
611 	if (v->slave != NULL)
612 		emu_vwrite(sc, v->slave);
613 }
614 
615 static void
616 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go)
617 {
618 	u_int32_t pitch_target, initial_pitch;
619 	u_int32_t cra, cs, ccis;
620 	u_int32_t sample, i;
621 
622 	if (go) {
623 		cra = 64;
624 		cs = v->stereo ? 4 : 2;
625 		ccis = v->stereo ? 28 : 30;
626 		ccis *= v->b16 ? 1 : 2;
627 		sample = v->b16 ? 0x00000000 : 0x80808080;
628 
629 		for (i = 0; i < cs; i++)
630 			emu_wrptr(sc, v->vnum, CD0 + i, sample);
631 		emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0);
632 		emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra);
633 		emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis);
634 
635 		emu_wrptr(sc, v->vnum, IFATN, 0xff00);
636 		emu_wrptr(sc, v->vnum, VTFT, 0xffffffff);
637 		emu_wrptr(sc, v->vnum, CVCF, 0xffffffff);
638 		emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f);
639 		emu_enastop(sc, v->vnum, 0);
640 
641 		pitch_target = emu_rate_to_linearpitch(v->speed);
642 		initial_pitch = emu_rate_to_pitch(v->speed) >> 8;
643 		emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target);
644 		emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target);
645 		emu_wrptr(sc, v->vnum, IP, initial_pitch);
646 	} else {
647 		emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0);
648 		emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0);
649 		emu_wrptr(sc, v->vnum, IFATN, 0xffff);
650 		emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff);
651 		emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff);
652 		emu_wrptr(sc, v->vnum, IP, 0);
653 		emu_enastop(sc, v->vnum, 1);
654 	}
655 	if (v->slave != NULL)
656 		emu_vtrigger(sc, v->slave, go);
657 }
658 
659 static int
660 emu_vpos(struct sc_info *sc, struct emu_voice *v)
661 {
662 	int s, ptr;
663 
664 	s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0);
665 	ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s;
666 	return ptr & ~0x0000001f;
667 }
668 
669 #ifdef EMUDEBUG
670 static void
671 emu_vdump(struct sc_info *sc, struct emu_voice *v)
672 {
673 	char *regname[] = {
674 		"cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl",
675 		"ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL,
676 		"envvol", "atkhldv", "dcysusv", "lfoval1",
677 		"envval", "atkhldm", "dcysusm", "lfoval2",
678 		"ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2",
679 		"tempenv"
680 	};
681 	char *regname2[] = {
682 		"mudata1", "mustat1", "mudata2", "mustat2",
683 		"fxwc1", "fxwc2", "spdrate", NULL, NULL,
684 		NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1",
685 		NULL, NULL
686 	};
687 	int i, x;
688 
689 	printf("voice number %d\n", v->vnum);
690 	for (i = 0, x = 0; i <= 0x1e; i++) {
691 		if (regname[i] == NULL)
692 			continue;
693 		printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i));
694 		printf("%s", (x == 2) ? "\n" : "\t");
695 		x++;
696 		if (x > 2)
697 			x = 0;
698 	}
699 
700 	/* Print out audigy extra registers */
701 	if (sc->audigy) {
702 		for (i = 0; i <= 0xe; i++) {
703 			if (regname2[i] == NULL)
704 				continue;
705 			printf("%s\t[%08x]", regname2[i],
706 			    emu_rdptr(sc, v->vnum, i + 0x70));
707 			printf("%s", (x == 2)? "\n" : "\t");
708 			x++;
709 			if (x > 2)
710 				x = 0;
711 		}
712 	}
713 	printf("\n\n");
714 }
715 #endif
716 
717 /* channel interface */
718 static void *
719 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
720     struct pcm_channel *c, int dir)
721 {
722 	struct sc_info *sc = devinfo;
723 	struct sc_pchinfo *ch;
724 	void *r;
725 
726 	KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction"));
727 	ch = &sc->pch[sc->pnum++];
728 	ch->buffer = b;
729 	ch->parent = sc;
730 	ch->channel = c;
731 	ch->blksz = sc->bufsz / 2;
732 	ch->fmt = AFMT_U8;
733 	ch->spd = 8000;
734 	snd_mtxlock(sc->lock);
735 	ch->master = emu_valloc(sc);
736 	ch->slave = emu_valloc(sc);
737 	snd_mtxunlock(sc->lock);
738 	r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer))
739 	    ? NULL : ch;
740 
741 	return r;
742 }
743 
744 static int
745 emupchan_free(kobj_t obj, void *data)
746 {
747 	struct sc_pchinfo *ch = data;
748 	struct sc_info *sc = ch->parent;
749 	int r;
750 
751 	snd_mtxlock(sc->lock);
752 	r = emu_memfree(sc, sndbuf_getbuf(ch->buffer));
753 	snd_mtxunlock(sc->lock);
754 
755 	return r;
756 }
757 
758 static int
759 emupchan_setformat(kobj_t obj, void *data, u_int32_t format)
760 {
761 	struct sc_pchinfo *ch = data;
762 
763 	ch->fmt = format;
764 	return 0;
765 }
766 
767 static int
768 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
769 {
770 	struct sc_pchinfo *ch = data;
771 
772 	ch->spd = speed;
773 	return ch->spd;
774 }
775 
776 static int
777 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
778 {
779 	struct sc_pchinfo *ch = data;
780 	struct sc_info *sc = ch->parent;
781 	int irqrate, blksz;
782 
783 	ch->blksz = blocksize;
784 	snd_mtxlock(sc->lock);
785 	emu_settimer(sc);
786 	irqrate = 48000 / sc->timerinterval;
787 	snd_mtxunlock(sc->lock);
788 	blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate;
789 	return blocksize;
790 }
791 
792 static int
793 emupchan_trigger(kobj_t obj, void *data, int go)
794 {
795 	struct sc_pchinfo *ch = data;
796 	struct sc_info *sc = ch->parent;
797 
798 	if (!PCMTRIG_COMMON(go))
799 		return 0;
800 
801 	snd_mtxlock(sc->lock);
802 	if (go == PCMTRIG_START) {
803 		emu_vsetup(ch);
804 		emu_vwrite(sc, ch->master);
805 		emu_settimer(sc);
806 		emu_enatimer(sc, 1);
807 #ifdef EMUDEBUG
808 		printf("start [%d bit, %s, %d hz]\n",
809 			ch->master->b16 ? 16 : 8,
810 			ch->master->stereo ? "stereo" : "mono",
811 			ch->master->speed);
812 		emu_vdump(sc, ch->master);
813 		emu_vdump(sc, ch->slave);
814 #endif
815 	}
816 	ch->run = (go == PCMTRIG_START) ? 1 : 0;
817 	emu_vtrigger(sc, ch->master, ch->run);
818 	snd_mtxunlock(sc->lock);
819 	return 0;
820 }
821 
822 static int
823 emupchan_getptr(kobj_t obj, void *data)
824 {
825 	struct sc_pchinfo *ch = data;
826 	struct sc_info *sc = ch->parent;
827 	int r;
828 
829 	snd_mtxlock(sc->lock);
830 	r = emu_vpos(sc, ch->master);
831 	snd_mtxunlock(sc->lock);
832 
833 	return r;
834 }
835 
836 static struct pcmchan_caps *
837 emupchan_getcaps(kobj_t obj, void *data)
838 {
839 	return &emu_playcaps;
840 }
841 
842 static kobj_method_t emupchan_methods[] = {
843 	KOBJMETHOD(channel_init,		emupchan_init),
844 	KOBJMETHOD(channel_free,		emupchan_free),
845 	KOBJMETHOD(channel_setformat,		emupchan_setformat),
846 	KOBJMETHOD(channel_setspeed,		emupchan_setspeed),
847 	KOBJMETHOD(channel_setblocksize,	emupchan_setblocksize),
848 	KOBJMETHOD(channel_trigger,		emupchan_trigger),
849 	KOBJMETHOD(channel_getptr,		emupchan_getptr),
850 	KOBJMETHOD(channel_getcaps,		emupchan_getcaps),
851 	{ 0, 0 }
852 };
853 CHANNEL_DECLARE(emupchan);
854 
855 /* channel interface */
856 static void *
857 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
858     struct pcm_channel *c, int dir)
859 {
860 	struct sc_info *sc = devinfo;
861 	struct sc_rchinfo *ch;
862 
863 	KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction"));
864 	ch = &sc->rch[sc->rnum];
865 	ch->buffer = b;
866 	ch->parent = sc;
867 	ch->channel = c;
868 	ch->blksz = sc->bufsz / 2;
869 	ch->fmt = AFMT_U8;
870 	ch->spd = 8000;
871 	ch->num = sc->rnum;
872 	switch(sc->rnum) {
873 	case 0:
874 		ch->idxreg = sc->audigy ? A_ADCIDX : ADCIDX;
875 		ch->basereg = ADCBA;
876 		ch->sizereg = ADCBS;
877 		ch->setupreg = ADCCR;
878 		ch->irqmask = INTE_ADCBUFENABLE;
879 		break;
880 
881 	case 1:
882 		ch->idxreg = FXIDX;
883 		ch->basereg = FXBA;
884 		ch->sizereg = FXBS;
885 		ch->setupreg = FXWC;
886 		ch->irqmask = INTE_EFXBUFENABLE;
887 		break;
888 
889 	case 2:
890 		ch->idxreg = MICIDX;
891 		ch->basereg = MICBA;
892 		ch->sizereg = MICBS;
893 		ch->setupreg = 0;
894 		ch->irqmask = INTE_MICBUFENABLE;
895 		break;
896 	}
897 	sc->rnum++;
898 	if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0)
899 		return NULL;
900 	else {
901 		snd_mtxlock(sc->lock);
902 		emu_wrptr(sc, 0, ch->basereg, sndbuf_getbufaddr(ch->buffer));
903 		emu_wrptr(sc, 0, ch->sizereg, 0); /* off */
904 		snd_mtxunlock(sc->lock);
905 		return ch;
906 	}
907 }
908 
909 static int
910 emurchan_setformat(kobj_t obj, void *data, u_int32_t format)
911 {
912 	struct sc_rchinfo *ch = data;
913 
914 	ch->fmt = format;
915 	return 0;
916 }
917 
918 static int
919 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
920 {
921 	struct sc_rchinfo *ch = data;
922 
923 	if (ch->num == 0) {
924 		if (ch->parent->audigy)
925 			speed = audigy_adcspeed[audigy_recval(speed)];
926 		else
927 			speed = adcspeed[emu_recval(speed)];
928 	}
929 	if (ch->num == 1)
930 		speed = 48000;
931 	if (ch->num == 2)
932 		speed = 8000;
933 	ch->spd = speed;
934 	return ch->spd;
935 }
936 
937 static int
938 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
939 {
940 	struct sc_rchinfo *ch = data;
941 	struct sc_info *sc = ch->parent;
942 	int irqrate, blksz;
943 
944 	ch->blksz = blocksize;
945 	snd_mtxlock(sc->lock);
946 	emu_settimer(sc);
947 	irqrate = 48000 / sc->timerinterval;
948 	snd_mtxunlock(sc->lock);
949 	blksz = (ch->spd * sndbuf_getbps(ch->buffer)) / irqrate;
950 	return blocksize;
951 }
952 
953 /* semantic note: must start at beginning of buffer */
954 static int
955 emurchan_trigger(kobj_t obj, void *data, int go)
956 {
957 	struct sc_rchinfo *ch = data;
958 	struct sc_info *sc = ch->parent;
959 	u_int32_t val, sz;
960 
961 	if (!PCMTRIG_COMMON(go))
962 		return 0;
963 
964 	switch(sc->bufsz) {
965 	case 4096:
966 		sz = ADCBS_BUFSIZE_4096;
967 		break;
968 
969 	case 8192:
970 		sz = ADCBS_BUFSIZE_8192;
971 		break;
972 
973 	case 16384:
974 		sz = ADCBS_BUFSIZE_16384;
975 		break;
976 
977 	case 32768:
978 		sz = ADCBS_BUFSIZE_32768;
979 		break;
980 
981 	case 65536:
982 		sz = ADCBS_BUFSIZE_65536;
983 		break;
984 
985 	default:
986 		sz = ADCBS_BUFSIZE_4096;
987 	}
988 
989 	snd_mtxlock(sc->lock);
990 	switch(go) {
991 	case PCMTRIG_START:
992 		ch->run = 1;
993 		emu_wrptr(sc, 0, ch->sizereg, sz);
994 		if (ch->num == 0) {
995 			if (sc->audigy) {
996 				val = A_ADCCR_LCHANENABLE;
997 				if (ch->fmt & AFMT_STEREO)
998 					val |= A_ADCCR_RCHANENABLE;
999 				val |= audigy_recval(ch->spd);
1000 			} else {
1001 				val = ADCCR_LCHANENABLE;
1002 				if (ch->fmt & AFMT_STEREO)
1003 					val |= ADCCR_RCHANENABLE;
1004 				val |= emu_recval(ch->spd);
1005 			}
1006 
1007 			emu_wrptr(sc, 0, ch->setupreg, 0);
1008 			emu_wrptr(sc, 0, ch->setupreg, val);
1009 		}
1010 		val = emu_rd(sc, INTE, 4);
1011 		val |= ch->irqmask;
1012 		emu_wr(sc, INTE, val, 4);
1013 		break;
1014 
1015 	case PCMTRIG_STOP:
1016 	case PCMTRIG_ABORT:
1017 		ch->run = 0;
1018 		emu_wrptr(sc, 0, ch->sizereg, 0);
1019 		if (ch->setupreg)
1020 			emu_wrptr(sc, 0, ch->setupreg, 0);
1021 		val = emu_rd(sc, INTE, 4);
1022 		val &= ~ch->irqmask;
1023 		emu_wr(sc, INTE, val, 4);
1024 		break;
1025 
1026 	case PCMTRIG_EMLDMAWR:
1027 	case PCMTRIG_EMLDMARD:
1028 	default:
1029 		break;
1030 	}
1031 	snd_mtxunlock(sc->lock);
1032 
1033 	return 0;
1034 }
1035 
1036 static int
1037 emurchan_getptr(kobj_t obj, void *data)
1038 {
1039 	struct sc_rchinfo *ch = data;
1040 	struct sc_info *sc = ch->parent;
1041 	int r;
1042 
1043 	snd_mtxlock(sc->lock);
1044 	r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff;
1045 	snd_mtxunlock(sc->lock);
1046 
1047 	return r;
1048 }
1049 
1050 static struct pcmchan_caps *
1051 emurchan_getcaps(kobj_t obj, void *data)
1052 {
1053 	struct sc_rchinfo *ch = data;
1054 
1055 	return &emu_reccaps[ch->num];
1056 }
1057 
1058 static kobj_method_t emurchan_methods[] = {
1059 	KOBJMETHOD(channel_init,		emurchan_init),
1060 	KOBJMETHOD(channel_setformat,		emurchan_setformat),
1061 	KOBJMETHOD(channel_setspeed,		emurchan_setspeed),
1062 	KOBJMETHOD(channel_setblocksize,	emurchan_setblocksize),
1063 	KOBJMETHOD(channel_trigger,		emurchan_trigger),
1064 	KOBJMETHOD(channel_getptr,		emurchan_getptr),
1065 	KOBJMETHOD(channel_getcaps,		emurchan_getcaps),
1066 	{ 0, 0 }
1067 };
1068 CHANNEL_DECLARE(emurchan);
1069 
1070 static unsigned char
1071 emu_mread(void *arg, struct sc_info *sc, int reg)
1072 {
1073 	unsigned int d;
1074 
1075 	d = emu_rd(sc, 0x18 + reg, 1);
1076 	return d;
1077 }
1078 
1079 static void
1080 emu_mwrite(void *arg, struct sc_info *sc, int reg, unsigned char b)
1081 {
1082 
1083 	emu_wr(sc, 0x18 + reg, b, 1);
1084 }
1085 
1086 static int
1087 emu_muninit(void *arg, struct sc_info *sc)
1088 {
1089 
1090 	snd_mtxlock(sc->lock);
1091 	sc->mpu_intr = 0;
1092 	snd_mtxunlock(sc->lock);
1093 
1094 	return 0;
1095 }
1096 
1097 static kobj_method_t emu_mpu_methods[] = {
1098     	KOBJMETHOD(mpufoi_read,		emu_mread),
1099     	KOBJMETHOD(mpufoi_write,	emu_mwrite),
1100     	KOBJMETHOD(mpufoi_uninit,	emu_muninit),
1101 	{ 0, 0 }
1102 };
1103 
1104 static DEFINE_CLASS(emu_mpu, emu_mpu_methods, 0);
1105 
1106 static void
1107 emu_intr2(void *p)
1108 {
1109 	struct sc_info *sc = (struct sc_info *)p;
1110 
1111 	if (sc->mpu_intr)
1112 	    (sc->mpu_intr)(sc->mpu);
1113 }
1114 
1115 static void
1116 emu_midiattach(struct sc_info *sc)
1117 {
1118 	int i;
1119 
1120 	i = emu_rd(sc, INTE, 4);
1121 	i |= INTE_MIDIRXENABLE;
1122 	emu_wr(sc, INTE, i, 4);
1123 
1124 	sc->mpu = mpu401_init(&emu_mpu_class, sc, emu_intr2, &sc->mpu_intr);
1125 }
1126 /* -------------------------------------------------------------------- */
1127 /* The interrupt handler */
1128 
1129 static void
1130 emu_intr(void *data)
1131 {
1132 	struct sc_info *sc = data;
1133 	u_int32_t stat, ack, i, x;
1134 
1135 	snd_mtxlock(sc->lock);
1136 	while (1) {
1137 		stat = emu_rd(sc, IPR, 4);
1138 		if (stat == 0)
1139 			break;
1140 		ack = 0;
1141 
1142 		/* process irq */
1143 		if (stat & IPR_INTERVALTIMER)
1144 			ack |= IPR_INTERVALTIMER;
1145 
1146 		if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL))
1147 			ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL);
1148 
1149 		if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL))
1150 			ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL);
1151 
1152 		if (stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL))
1153 			ack |= stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL);
1154 
1155 		if (stat & IPR_PCIERROR) {
1156 			ack |= IPR_PCIERROR;
1157 			device_printf(sc->dev, "pci error\n");
1158 			/* we still get an nmi with ecc ram even if we ack this */
1159 		}
1160 		if (stat & IPR_SAMPLERATETRACKER) {
1161 			ack |= IPR_SAMPLERATETRACKER;
1162 #ifdef EMUDEBUG
1163 			device_printf(sc->dev,
1164 			    "sample rate tracker lock status change\n");
1165 #endif
1166 		}
1167 
1168 	    if (stat & IPR_MIDIRECVBUFEMPTY)
1169 		if (sc->mpu_intr) {
1170 		    (sc->mpu_intr)(sc->mpu);
1171 		    ack |= IPR_MIDIRECVBUFEMPTY | IPR_MIDITRANSBUFEMPTY;
1172  		}
1173 		if (stat & ~ack)
1174 			device_printf(sc->dev, "dodgy irq: %x (harmless)\n",
1175 			    stat & ~ack);
1176 
1177 		emu_wr(sc, IPR, stat, 4);
1178 
1179 		if (ack) {
1180 			snd_mtxunlock(sc->lock);
1181 
1182 			if (ack & IPR_INTERVALTIMER) {
1183 				x = 0;
1184 				for (i = 0; i < sc->nchans; i++) {
1185 					if (sc->pch[i].run) {
1186 						x = 1;
1187 						chn_intr(sc->pch[i].channel);
1188 					}
1189 				}
1190 				if (x == 0)
1191 					emu_enatimer(sc, 0);
1192 			}
1193 
1194 
1195 			if (ack & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) {
1196 				if (sc->rch[0].channel)
1197 					chn_intr(sc->rch[0].channel);
1198 			}
1199 			if (ack & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) {
1200 				if (sc->rch[1].channel)
1201 					chn_intr(sc->rch[1].channel);
1202 			}
1203 			if (ack & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) {
1204 				if (sc->rch[2].channel)
1205 					chn_intr(sc->rch[2].channel);
1206 			}
1207 
1208 			snd_mtxlock(sc->lock);
1209 		}
1210 	}
1211 	snd_mtxunlock(sc->lock);
1212 }
1213 
1214 /* -------------------------------------------------------------------- */
1215 
1216 static void
1217 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1218 {
1219 	bus_addr_t *phys = arg;
1220 
1221 	*phys = error ? 0 : (bus_addr_t)segs->ds_addr;
1222 
1223 	if (bootverbose) {
1224 		printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n",
1225 		    (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1226 		    nseg, error);
1227 	}
1228 }
1229 
1230 static void *
1231 emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr)
1232 {
1233 	void *buf;
1234 	bus_dmamap_t map;
1235 
1236 	*addr = 0;
1237 	if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map))
1238 		return NULL;
1239 	if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, emu_setmap, addr, 0)
1240 	    || !*addr)
1241 		return NULL;
1242 	return buf;
1243 }
1244 
1245 static void
1246 emu_free(struct sc_info *sc, void *buf)
1247 {
1248 	bus_dmamem_free(sc->parent_dmat, buf, NULL);
1249 }
1250 
1251 static void *
1252 emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr)
1253 {
1254 	u_int32_t blksz, start, idx, ofs, tmp, found;
1255 	struct emu_mem *mem = &sc->mem;
1256 	struct emu_memblk *blk;
1257 	void *buf;
1258 
1259 	blksz = sz / EMUPAGESIZE;
1260 	if (sz > (blksz * EMUPAGESIZE))
1261 		blksz++;
1262 	/* find a free block in the bitmap */
1263 	found = 0;
1264 	start = 1;
1265 	while (!found && start + blksz < EMUMAXPAGES) {
1266 		found = 1;
1267 		for (idx = start; idx < start + blksz; idx++)
1268 			if (mem->bmap[idx >> 3] & (1 << (idx & 7)))
1269 				found = 0;
1270 		if (!found)
1271 			start++;
1272 	}
1273 	if (!found)
1274 		return NULL;
1275 	blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT);
1276 	if (blk == NULL)
1277 		return NULL;
1278 	buf = emu_malloc(sc, sz, &blk->buf_addr);
1279 	*addr = blk->buf_addr;
1280 	if (buf == NULL) {
1281 		free(blk, M_DEVBUF);
1282 		return NULL;
1283 	}
1284 	blk->buf = buf;
1285 	blk->pte_start = start;
1286 	blk->pte_size = blksz;
1287 #ifdef EMUDEBUG
1288 	printf("buf %p, pte_start %d, pte_size %d\n", blk->buf,
1289 	    blk->pte_start, blk->pte_size);
1290 #endif
1291 	ofs = 0;
1292 	for (idx = start; idx < start + blksz; idx++) {
1293 		mem->bmap[idx >> 3] |= 1 << (idx & 7);
1294 		tmp = (u_int32_t)(u_long)((u_int8_t *)blk->buf_addr + ofs);
1295 #ifdef EMUDEBUG
1296 		printf("pte[%d] -> %x phys, %x virt\n", idx, tmp,
1297 		    ((u_int32_t)buf) + ofs);
1298 #endif
1299 		mem->ptb_pages[idx] = (tmp << 1) | idx;
1300 		ofs += EMUPAGESIZE;
1301 	}
1302 	SLIST_INSERT_HEAD(&mem->blocks, blk, link);
1303 	return buf;
1304 }
1305 
1306 static int
1307 emu_memfree(struct sc_info *sc, void *buf)
1308 {
1309 	u_int32_t idx, tmp;
1310 	struct emu_mem *mem = &sc->mem;
1311 	struct emu_memblk *blk, *i;
1312 
1313 	blk = NULL;
1314 	SLIST_FOREACH(i, &mem->blocks, link) {
1315 		if (i->buf == buf)
1316 			blk = i;
1317 	}
1318 	if (blk == NULL)
1319 		return EINVAL;
1320 	SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link);
1321 	emu_free(sc, buf);
1322 	tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
1323 	for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) {
1324 		mem->bmap[idx >> 3] &= ~(1 << (idx & 7));
1325 		mem->ptb_pages[idx] = tmp | idx;
1326 	}
1327 	free(blk, M_DEVBUF);
1328 	return 0;
1329 }
1330 
1331 static int
1332 emu_memstart(struct sc_info *sc, void *buf)
1333 {
1334 	struct emu_mem *mem = &sc->mem;
1335 	struct emu_memblk *blk, *i;
1336 
1337 	blk = NULL;
1338 	SLIST_FOREACH(i, &mem->blocks, link) {
1339 		if (i->buf == buf)
1340 			blk = i;
1341 	}
1342 	if (blk == NULL)
1343 		return -EINVAL;
1344 	return blk->pte_start;
1345 }
1346 
1347 static void
1348 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y,
1349     u_int32_t *pc)
1350 {
1351 	emu_wrefx(sc, (*pc) * 2, (x << 10) | y);
1352 	emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w);
1353 	(*pc)++;
1354 }
1355 
1356 static void
1357 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y,
1358     u_int32_t *pc)
1359 {
1360 	emu_wrefx(sc, (*pc) * 2, (x << 12) | y);
1361 	emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w);
1362 	(*pc)++;
1363 }
1364 
1365 static void
1366 audigy_initefx(struct sc_info *sc)
1367 {
1368 	int i;
1369 	u_int32_t pc = 0;
1370 
1371 	/* skip 0, 0, -1, 0 - NOPs */
1372 	for (i = 0; i < 512; i++)
1373 		audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc);
1374 
1375 	for (i = 0; i < 512; i++)
1376 		emu_wrptr(sc, 0, A_FXGPREGBASE + i, 0x0);
1377 
1378 	pc = 16;
1379 
1380 	/* stop fx processor */
1381 	emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
1382 
1383 	/* Audigy 2 (EMU10K2) DSP Registers:
1384 	   FX Bus
1385 		0x000-0x00f : 16 registers (?)
1386 	   Input
1387 		0x040/0x041 : AC97 Codec (l/r)
1388 		0x042/0x043 : ADC, S/PDIF (l/r)
1389 		0x044/0x045 : Optical S/PDIF in (l/r)
1390 		0x046/0x047 : ?
1391 		0x048/0x049 : Line/Mic 2 (l/r)
1392 		0x04a/0x04b : RCA S/PDIF (l/r)
1393 		0x04c/0x04d : Aux 2 (l/r)
1394 	   Output
1395 		0x060/0x061 : Digital Front (l/r)
1396 		0x062/0x063 : Digital Center/LFE
1397 		0x064/0x065 : AudigyDrive Heaphone (l/r)
1398 		0x066/0x067 : Digital Rear (l/r)
1399 		0x068/0x069 : Analog Front (l/r)
1400 		0x06a/0x06b : Analog Center/LFE
1401 		0x06c/0x06d : ?
1402 		0x06e/0x06f : Analog Rear (l/r)
1403 		0x070/0x071 : AC97 Output (l/r)
1404 		0x072/0x073 : ?
1405 		0x074/0x075 : ?
1406 		0x076/0x077 : ADC Recording Buffer (l/r)
1407 	   Constants
1408 		0x0c0 - 0x0c4 = 0 - 4
1409 		0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20
1410 		0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000
1411 		0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000
1412 		0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff
1413 		0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc
1414 		0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (?)
1415 	   Temporary Values
1416 		0x0d6 : Accumulator (?)
1417 		0x0d7 : Condition Register
1418 		0x0d8 : Noise source
1419 		0x0d9 : Noise source
1420 	   Tank Memory Data Registers
1421 		0x200 - 0x2ff
1422 	   Tank Memory Address Registers
1423 		0x300 - 0x3ff
1424 	   General Purpose Registers
1425 		0x400 - 0x5ff
1426 	 */
1427 
1428 	/* AC97Output[l/r] = FXBus PCM[l/r] */
1429 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000,
1430 			A_C_00000000, A_FXBUS(FXBUS_PCM_LEFT), &pc);
1431 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000,
1432 			A_C_00000000, A_FXBUS(FXBUS_PCM_RIGHT), &pc);
1433 
1434 	/* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */
1435 	audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000,
1436 			A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_L), &pc);
1437 	audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000,
1438 			A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_R), &pc);
1439 
1440 	/* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1441 	audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1),
1442 			A_C_40000000, A_GPR(0), &pc);
1443 
1444 	/* Headphones[l/r] = GPR[0/1] */
1445 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L),
1446 			A_C_00000000, A_C_00000000, A_GPR(0), &pc);
1447 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R),
1448 			A_C_00000000, A_C_00000000, A_GPR(1), &pc);
1449 
1450 	/* Analog Front[l/r] = GPR[0/1] */
1451 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000,
1452 			A_C_00000000, A_GPR(0), &pc);
1453 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000,
1454 			A_C_00000000, A_GPR(1), &pc);
1455 
1456 	/* Digital Front[l/r] = GPR[0/1] */
1457 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000,
1458 			A_C_00000000, A_GPR(0), &pc);
1459 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000,
1460 			A_C_00000000, A_GPR(1), &pc);
1461 
1462 	/* Center and Subwoofer configuration */
1463 	/* Analog Center = GPR[0] + GPR[2] */
1464 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000,
1465 			A_GPR(0), A_GPR(2), &pc);
1466 	/* Analog Sub = GPR[1] + GPR[2] */
1467 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000,
1468 			A_GPR(1), A_GPR(2), &pc);
1469 
1470 	/* Digital Center = GPR[0] + GPR[2] */
1471 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000,
1472 			A_GPR(0), A_GPR(2), &pc);
1473 	/* Digital Sub = GPR[1] + GPR[2] */
1474 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000,
1475 			A_GPR(1), A_GPR(2), &pc);
1476 
1477 #if 0
1478 	/* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1479 	/*   RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1480 	audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1481 			A_GPR(16), A_GPR(0), &pc);
1482 	audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1483 			A_GPR(17), A_GPR(1), &pc);
1484 
1485 	/* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1486 	/*   RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1487 	audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1488 			A_GPR(16), A_GPR(0), &pc);
1489 	audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1490 			A_GPR(17), A_GPR(1), &pc);
1491 #else
1492 	/* XXX This is just a copy to the channel, since we do not have
1493 	 *     a patch manager, it is useful for have another output enabled.
1494 	 */
1495 
1496 	/* Analog Rear[l/r] = GPR[0/1] */
1497 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1498 			A_C_00000000, A_GPR(0), &pc);
1499 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1500 			A_C_00000000, A_GPR(1), &pc);
1501 
1502 	/* Digital Rear[l/r] = GPR[0/1] */
1503 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1504 			A_C_00000000, A_GPR(0), &pc);
1505 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1506 			A_C_00000000, A_GPR(1), &pc);
1507 #endif
1508 
1509 	/* ADC Recording buffer[l/r] = AC97Input[l/r] */
1510 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000,
1511 			A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc);
1512 	audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000,
1513 			A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc);
1514 
1515 	/* resume normal operations */
1516 	emu_wrptr(sc, 0, A_DBG, 0);
1517 }
1518 
1519 static void
1520 emu_initefx(struct sc_info *sc)
1521 {
1522 	int i;
1523 	u_int32_t pc = 16;
1524 
1525 	/* acc3 0,0,0,0 - NOPs */
1526 	for (i = 0; i < 512; i++) {
1527 		emu_wrefx(sc, i * 2, 0x10040);
1528 		emu_wrefx(sc, i * 2 + 1, 0x610040);
1529 	}
1530 
1531 	for (i = 0; i < 256; i++)
1532 		emu_wrptr(sc, 0, FXGPREGBASE + i, 0);
1533 
1534 	/* FX-8010 DSP Registers:
1535 	   FX Bus
1536 	     0x000-0x00f : 16 registers
1537 	   Input
1538 	     0x010/0x011 : AC97 Codec (l/r)
1539 	     0x012/0x013 : ADC, S/PDIF (l/r)
1540 	     0x014/0x015 : Mic(left), Zoom (l/r)
1541 	     0x016/0x017 : TOS link in (l/r)
1542 	     0x018/0x019 : Line/Mic 1 (l/r)
1543 	     0x01a/0x01b : COAX S/PDIF (l/r)
1544 	     0x01c/0x01d : Line/Mic 2 (l/r)
1545 	   Output
1546 	     0x020/0x021 : AC97 Output (l/r)
1547 	     0x022/0x023 : TOS link out (l/r)
1548 	     0x024/0x025 : Center/LFE
1549 	     0x026/0x027 : LiveDrive Headphone (l/r)
1550 	     0x028/0x029 : Rear Channel (l/r)
1551 	     0x02a/0x02b : ADC Recording Buffer (l/r)
1552 	     0x02c       : Mic Recording Buffer
1553 	     0x031/0x032 : Analog Center/LFE
1554 	   Constants
1555 	     0x040 - 0x044 = 0 - 4
1556 	     0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20
1557 	     0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000
1558 	     0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000
1559 	     0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff
1560 	     0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc
1561 	     0x054 = 0x5a7ef9db, 0x055 = 0x00100000
1562 	   Temporary Values
1563 	     0x056 : Accumulator
1564 	     0x057 : Condition Register
1565 	     0x058 : Noise source
1566 	     0x059 : Noise source
1567 	     0x05a : IRQ Register
1568 	     0x05b : TRAM Delay Base Address Count
1569 	   General Purpose Registers
1570 	     0x100 - 0x1ff
1571 	   Tank Memory Data Registers
1572 	     0x200 - 0x2ff
1573 	   Tank Memory Address Registers
1574 	     0x300 - 0x3ff
1575 	     */
1576 
1577 	/* Routing - this will be configurable in later version */
1578 
1579 	/* GPR[0/1] = FX * 4 + SPDIF-in */
1580 	emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L),
1581 			FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc);
1582 	emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R),
1583 			FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc);
1584 
1585 	/* GPR[0/1] += APS-input */
1586 	emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000,
1587 			sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc);
1588 	emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000,
1589 			sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc);
1590 
1591 	/* FrontOut (AC97) = GPR[0/1] */
1592 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000,
1593 			C_00000000, GPR(0), &pc);
1594 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000,
1595 			C_00000001, GPR(1), &pc);
1596 
1597 	/* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1598 	emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc);
1599 
1600 #if 0
1601 	/* RearOut = (GPR[0/1] * RearVolume) >> 31 */
1602 	/*   RearVolume = GPR[0x10/0x11] */
1603 	emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000,
1604 			GPR(16), GPR(0), &pc);
1605 	emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000,
1606 			GPR(17), GPR(1), &pc);
1607 #else
1608 	/* XXX This is just a copy to the channel, since we do not have
1609 	 *     a patch manager, it is useful for have another output enabled.
1610 	 */
1611 
1612 	/* Rear[l/r] = GPR[0/1] */
1613 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000,
1614 			C_00000000, GPR(0), &pc);
1615 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000,
1616 			C_00000000, GPR(1), &pc);
1617 #endif
1618 
1619 	/* TOS out[l/r] = GPR[0/1] */
1620 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000,
1621 			C_00000000, GPR(0), &pc);
1622 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000,
1623 			C_00000000, GPR(1), &pc);
1624 
1625 	/* Center and Subwoofer configuration */
1626 	/* Analog Center = GPR[0] + GPR[2] */
1627 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000,
1628 			GPR(0), GPR(2), &pc);
1629 	/* Analog Sub = GPR[1] + GPR[2] */
1630 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000,
1631 			GPR(1), GPR(2), &pc);
1632 	/* Digital Center = GPR[0] + GPR[2] */
1633 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_CENTER), C_00000000,
1634 			GPR(0), GPR(2), &pc);
1635 	/* Digital Sub = GPR[1] + GPR[2] */
1636 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_LFE), C_00000000,
1637 			GPR(1), GPR(2), &pc);
1638 
1639 	/* Headphones[l/r] = GPR[0/1] */
1640 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000,
1641 			C_00000000, GPR(0), &pc);
1642 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000,
1643 			C_00000000, GPR(1), &pc);
1644 
1645 	/* ADC Recording buffer[l/r] = AC97Input[l/r] */
1646 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000,
1647 			C_00000000, EXTIN(EXTIN_AC97_L), &pc);
1648 	emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000,
1649 			C_00000000, EXTIN(EXTIN_AC97_R), &pc);
1650 
1651 	/* resume normal operations */
1652 	emu_wrptr(sc, 0, DBG, 0);
1653 }
1654 
1655 /* Probe and attach the card */
1656 static int
1657 emu_init(struct sc_info *sc)
1658 {
1659 	u_int32_t spcs, ch, tmp, i;
1660 
1661 	if (sc->audigy) {
1662 		/* enable additional AC97 slots */
1663 		emu_wrptr(sc, 0, AC97SLOT, AC97SLOT_CNTR | AC97SLOT_LFE);
1664 	}
1665 
1666 	/* disable audio and lock cache */
1667 	emu_wr(sc, HCFG,
1668 	    HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
1669 	    4);
1670 
1671 	/* reset recording buffers */
1672 	emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
1673 	emu_wrptr(sc, 0, MICBA, 0);
1674 	emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
1675 	emu_wrptr(sc, 0, FXBA, 0);
1676 	emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
1677 	emu_wrptr(sc, 0, ADCBA, 0);
1678 
1679 	/* disable channel interrupt */
1680 	emu_wr(sc, INTE,
1681 	    INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE,
1682 	    4);
1683 	emu_wrptr(sc, 0, CLIEL, 0);
1684 	emu_wrptr(sc, 0, CLIEH, 0);
1685 	emu_wrptr(sc, 0, SOLEL, 0);
1686 	emu_wrptr(sc, 0, SOLEH, 0);
1687 
1688 	/* wonder what these do... */
1689 	if (sc->audigy) {
1690 		emu_wrptr(sc, 0, SPBYPASS, 0xf00);
1691 		emu_wrptr(sc, 0, AC97SLOT, 0x3);
1692 	}
1693 
1694 	/* init envelope engine */
1695 	for (ch = 0; ch < NUM_G; ch++) {
1696 		emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
1697 		emu_wrptr(sc, ch, IP, 0);
1698 		emu_wrptr(sc, ch, VTFT, 0xffff);
1699 		emu_wrptr(sc, ch, CVCF, 0xffff);
1700 		emu_wrptr(sc, ch, PTRX, 0);
1701 		emu_wrptr(sc, ch, CPF, 0);
1702 		emu_wrptr(sc, ch, CCR, 0);
1703 
1704 		emu_wrptr(sc, ch, PSST, 0);
1705 		emu_wrptr(sc, ch, DSL, 0x10);
1706 		emu_wrptr(sc, ch, CCCA, 0);
1707 		emu_wrptr(sc, ch, Z1, 0);
1708 		emu_wrptr(sc, ch, Z2, 0);
1709 		emu_wrptr(sc, ch, FXRT, 0xd01c0000);
1710 
1711 		emu_wrptr(sc, ch, ATKHLDM, 0);
1712 		emu_wrptr(sc, ch, DCYSUSM, 0);
1713 		emu_wrptr(sc, ch, IFATN, 0xffff);
1714 		emu_wrptr(sc, ch, PEFE, 0);
1715 		emu_wrptr(sc, ch, FMMOD, 0);
1716 		emu_wrptr(sc, ch, TREMFRQ, 24);	/* 1 Hz */
1717 		emu_wrptr(sc, ch, FM2FRQ2, 24);	/* 1 Hz */
1718 		emu_wrptr(sc, ch, TEMPENV, 0);
1719 
1720 		/*** these are last so OFF prevents writing ***/
1721 		emu_wrptr(sc, ch, LFOVAL2, 0);
1722 		emu_wrptr(sc, ch, LFOVAL1, 0);
1723 		emu_wrptr(sc, ch, ATKHLDV, 0);
1724 		emu_wrptr(sc, ch, ENVVOL, 0);
1725 		emu_wrptr(sc, ch, ENVVAL, 0);
1726 
1727 		if (sc->audigy) {
1728 			/* audigy cards need this to initialize correctly */
1729 			emu_wrptr(sc, ch, 0x4c, 0);
1730 			emu_wrptr(sc, ch, 0x4d, 0);
1731 			emu_wrptr(sc, ch, 0x4e, 0);
1732 			emu_wrptr(sc, ch, 0x4f, 0);
1733 			/* set default routing */
1734 			emu_wrptr(sc, ch, A_FXRT1, 0x03020100);
1735 			emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f);
1736 			emu_wrptr(sc, ch, A_SENDAMOUNTS, 0);
1737 		}
1738 
1739 		sc->voice[ch].vnum = ch;
1740 		sc->voice[ch].slave = NULL;
1741 		sc->voice[ch].busy = 0;
1742 		sc->voice[ch].ismaster = 0;
1743 		sc->voice[ch].running = 0;
1744 		sc->voice[ch].b16 = 0;
1745 		sc->voice[ch].stereo = 0;
1746 		sc->voice[ch].speed = 0;
1747 		sc->voice[ch].start = 0;
1748 		sc->voice[ch].end = 0;
1749 		sc->voice[ch].channel = NULL;
1750 	}
1751 	sc->pnum = sc->rnum = 0;
1752 
1753 	/*
1754 	 *  Init to 0x02109204 :
1755 	 *  Clock accuracy    = 0     (1000ppm)
1756 	 *  Sample Rate       = 2     (48kHz)
1757 	 *  Audio Channel     = 1     (Left of 2)
1758 	 *  Source Number     = 0     (Unspecified)
1759 	 *  Generation Status = 1     (Original for Cat Code 12)
1760 	 *  Cat Code          = 12    (Digital Signal Mixer)
1761 	 *  Mode              = 0     (Mode 0)
1762 	 *  Emphasis          = 0     (None)
1763 	 *  CP                = 1     (Copyright unasserted)
1764 	 *  AN                = 0     (Audio data)
1765 	 *  P                 = 0     (Consumer)
1766 	 */
1767 	spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
1768 	    SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
1769 	    SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
1770 	    SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
1771 	emu_wrptr(sc, 0, SPCS0, spcs);
1772 	emu_wrptr(sc, 0, SPCS1, spcs);
1773 	emu_wrptr(sc, 0, SPCS2, spcs);
1774 
1775 	if (!sc->audigy)
1776 		emu_initefx(sc);
1777 	else if (sc->audigy2) {	/* Audigy 2 */
1778 		/* from ALSA initialization code: */
1779 
1780 		/* Hack for Alice3 to work independent of haP16V driver */
1781 		u_int32_t tmp;
1782 
1783 		/* Setup SRCMulti_I2S SamplingRate */
1784 		tmp = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE) & 0xfffff1ff;
1785 		emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, tmp | 0x400);
1786 
1787 		/* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */
1788 		emu_wr(sc, 0x20, 0x00600000, 4);
1789 		emu_wr(sc, 0x24, 0x00000014, 4);
1790 
1791 		/* Setup SRCMulti Input Audio Enable */
1792 		emu_wr(sc, 0x20, 0x006e0000, 4);
1793 		emu_wr(sc, 0x24, 0xff00ff00, 4);
1794 	}
1795 
1796 	SLIST_INIT(&sc->mem.blocks);
1797 	sc->mem.ptb_pages = emu_malloc(sc, EMUMAXPAGES * sizeof(u_int32_t),
1798 	    &sc->mem.ptb_pages_addr);
1799 	if (sc->mem.ptb_pages == NULL)
1800 		return -1;
1801 
1802 	sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE,
1803 	    &sc->mem.silent_page_addr);
1804 	if (sc->mem.silent_page == NULL) {
1805 		emu_free(sc, sc->mem.ptb_pages);
1806 		return -1;
1807 	}
1808 	/* Clear page with silence & setup all pointers to this page */
1809 	bzero(sc->mem.silent_page, EMUPAGESIZE);
1810 	tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
1811 	for (i = 0; i < EMUMAXPAGES; i++)
1812 		sc->mem.ptb_pages[i] = tmp | i;
1813 
1814 	emu_wrptr(sc, 0, PTB, (sc->mem.ptb_pages_addr));
1815 	emu_wrptr(sc, 0, TCB, 0);	/* taken from original driver */
1816 	emu_wrptr(sc, 0, TCBS, 0);	/* taken from original driver */
1817 
1818 	for (ch = 0; ch < NUM_G; ch++) {
1819 		emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK);
1820 		emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK);
1821 	}
1822 
1823 	/* emu_memalloc(sc, EMUPAGESIZE); */
1824 	/*
1825 	 *  Hokay, now enable the AUD bit
1826 	 *
1827 	 *  Audigy
1828 	 *   Enable Audio = 0 (enabled after fx processor initialization)
1829 	 *   Mute Disable Audio = 0
1830 	 *   Joystick = 1
1831 	 *
1832 	 *  Audigy 2
1833 	 *   Enable Audio = 1
1834 	 *   Mute Disable Audio = 0
1835 	 *   Joystick = 1
1836 	 *   GP S/PDIF AC3 Enable = 1
1837 	 *   CD S/PDIF AC3 Enable = 1
1838 	 *
1839 	 *  EMU10K1
1840 	 *   Enable Audio = 1
1841 	 *   Mute Disable Audio = 0
1842 	 *   Lock Tank Memory = 1
1843 	 *   Lock Sound Memory = 0
1844 	 *   Auto Mute = 1
1845 	 */
1846 
1847 	if (sc->audigy) {
1848 		tmp = HCFG_AUTOMUTE | HCFG_JOYENABLE;
1849 		if (sc->audigy2)	/* Audigy 2 */
1850 			tmp = HCFG_AUDIOENABLE | HCFG_AC3ENABLE_CDSPDIF |
1851 			    HCFG_AC3ENABLE_GPSPDIF;
1852 		emu_wr(sc, HCFG, tmp, 4);
1853 
1854 		audigy_initefx(sc);
1855 
1856 		/* from ALSA initialization code: */
1857 
1858 		/* enable audio and disable both audio/digital outputs */
1859 		emu_wr(sc, HCFG, emu_rd(sc, HCFG, 4) | HCFG_AUDIOENABLE, 4);
1860 		emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) & ~A_IOCFG_GPOUT_AD,
1861 		    4);
1862 		if (sc->audigy2) {	/* Audigy 2 */
1863 			/* Unmute Analog.
1864 			 * Set GPO6 to 1 for Apollo. This has to be done after
1865 			 * init Alice3 I2SOut beyond 48kHz.
1866 			 * So, sequence is important.
1867 			 */
1868 			emu_wr(sc, A_IOCFG,
1869 			    emu_rd(sc, A_IOCFG, 4) | A_IOCFG_GPOUT_A, 4);
1870 		}
1871 	} else {
1872 		/* EMU10K1 initialization code */
1873 		tmp = HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK
1874 		    | HCFG_AUTOMUTE;
1875 		if (sc->rev >= 6)
1876 			tmp |= HCFG_JOYENABLE;
1877 
1878 		emu_wr(sc, HCFG, tmp, 4);
1879 
1880 		/* TOSLink detection */
1881 		sc->tos_link = 0;
1882 		tmp = emu_rd(sc, HCFG, 4);
1883 		if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
1884 			emu_wr(sc, HCFG, tmp | HCFG_GPOUT1, 4);
1885 			DELAY(50);
1886 			if (tmp != (emu_rd(sc, HCFG, 4) & ~HCFG_GPOUT1)) {
1887 				sc->tos_link = 1;
1888 				emu_wr(sc, HCFG, tmp, 4);
1889 			}
1890 		}
1891 	}
1892 
1893 	return 0;
1894 }
1895 
1896 static int
1897 emu_uninit(struct sc_info *sc)
1898 {
1899 	u_int32_t ch;
1900 
1901 	emu_wr(sc, INTE, 0, 4);
1902 	for (ch = 0; ch < NUM_G; ch++)
1903 		emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
1904 	for (ch = 0; ch < NUM_G; ch++) {
1905 		emu_wrptr(sc, ch, VTFT, 0);
1906 		emu_wrptr(sc, ch, CVCF, 0);
1907 		emu_wrptr(sc, ch, PTRX, 0);
1908 		emu_wrptr(sc, ch, CPF, 0);
1909 	}
1910 
1911 	if (sc->audigy) {	/* stop fx processor */
1912 		emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
1913 	}
1914 
1915 	/* disable audio and lock cache */
1916 	emu_wr(sc, HCFG,
1917 	    HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
1918 	    4);
1919 
1920 	emu_wrptr(sc, 0, PTB, 0);
1921 	/* reset recording buffers */
1922 	emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
1923 	emu_wrptr(sc, 0, MICBA, 0);
1924 	emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
1925 	emu_wrptr(sc, 0, FXBA, 0);
1926 	emu_wrptr(sc, 0, FXWC, 0);
1927 	emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
1928 	emu_wrptr(sc, 0, ADCBA, 0);
1929 	emu_wrptr(sc, 0, TCB, 0);
1930 	emu_wrptr(sc, 0, TCBS, 0);
1931 
1932 	/* disable channel interrupt */
1933 	emu_wrptr(sc, 0, CLIEL, 0);
1934 	emu_wrptr(sc, 0, CLIEH, 0);
1935 	emu_wrptr(sc, 0, SOLEL, 0);
1936 	emu_wrptr(sc, 0, SOLEH, 0);
1937 
1938 	/* init envelope engine */
1939 	if (!SLIST_EMPTY(&sc->mem.blocks))
1940 		device_printf(sc->dev, "warning: memblock list not empty\n");
1941 	emu_free(sc, sc->mem.ptb_pages);
1942 	emu_free(sc, sc->mem.silent_page);
1943 
1944 	if(sc->mpu)
1945 	    mpu401_uninit(sc->mpu);
1946 	return 0;
1947 }
1948 
1949 static int
1950 emu_pci_probe(device_t dev)
1951 {
1952 	char *s = NULL;
1953 
1954 	switch (pci_get_devid(dev)) {
1955 	case EMU10K1_PCI_ID:
1956 		s = "Creative EMU10K1";
1957 		break;
1958 
1959 	case EMU10K2_PCI_ID:
1960 		if (pci_get_revid(dev) == 0x04)
1961 			s = "Creative Audigy 2 (EMU10K2)";
1962 		else
1963 			s = "Creative Audigy (EMU10K2)";
1964 		break;
1965 
1966 	case EMU10K3_PCI_ID:
1967 		s = "Creative Audigy 2 (EMU10K3)";
1968 		break;
1969 
1970 	default:
1971 		return ENXIO;
1972 	}
1973 
1974 	device_set_desc(dev, s);
1975 	return BUS_PROBE_LOW_PRIORITY;
1976 }
1977 
1978 static int
1979 emu_pci_attach(device_t dev)
1980 {
1981 	struct ac97_info *codec = NULL;
1982 	struct sc_info *sc;
1983 	u_int32_t data;
1984 	int i, gotmic;
1985 	char status[SND_STATUSLEN];
1986 
1987 	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
1988 	sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_emu10k1 softc");
1989 	sc->dev = dev;
1990 	sc->type = pci_get_devid(dev);
1991 	sc->rev = pci_get_revid(dev);
1992 	sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID;
1993 	sc->audigy2 = (sc->audigy && sc->rev == 0x04);
1994 	sc->nchans = sc->audigy ? 8 : 4;
1995 	sc->addrmask = sc->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK;
1996 
1997 	data = pci_read_config(dev, PCIR_COMMAND, 2);
1998 	data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
1999 	pci_write_config(dev, PCIR_COMMAND, data, 2);
2000 	data = pci_read_config(dev, PCIR_COMMAND, 2);
2001 
2002 	i = PCIR_BAR(0);
2003 	sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);
2004 	if (sc->reg == NULL) {
2005 		device_printf(dev, "unable to map register space\n");
2006 		goto bad;
2007 	}
2008 	sc->st = rman_get_bustag(sc->reg);
2009 	sc->sh = rman_get_bushandle(sc->reg);
2010 
2011 	sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536);
2012 
2013 	if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
2014 		/*boundary*/0,
2015 		/*lowaddr*/1 << 31, /* can only access 0-2gb */
2016 		/*highaddr*/BUS_SPACE_MAXADDR,
2017 		/*filter*/NULL, /*filterarg*/NULL,
2018 		/*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
2019 		/*flags*/0, /*lockfunc*/busdma_lock_mutex,
2020 		/*lockarg*/&Giant, &sc->parent_dmat) != 0) {
2021 		device_printf(dev, "unable to create dma tag\n");
2022 		goto bad;
2023 	}
2024 
2025 	if (emu_init(sc) == -1) {
2026 		device_printf(dev, "unable to initialize the card\n");
2027 		goto bad;
2028 	}
2029 
2030 	codec = AC97_CREATE(dev, sc, emu_ac97);
2031 	if (codec == NULL) goto bad;
2032 	gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL) ? 1 : 0;
2033 	if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
2034 
2035 	emu_midiattach(sc);
2036 
2037 	i = 0;
2038 	sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
2039 	    RF_ACTIVE | RF_SHAREABLE);
2040 	if (!sc->irq ||
2041 	    snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) {
2042 		device_printf(dev, "unable to map interrupt\n");
2043 		goto bad;
2044 	}
2045 
2046 	snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
2047 	    rman_get_start(sc->reg), rman_get_start(sc->irq),
2048 	    PCM_KLDSTRING(snd_emu10k1));
2049 
2050 	if (pcm_register(dev, sc, sc->nchans, gotmic ? 3 : 2)) goto bad;
2051 	for (i = 0; i < sc->nchans; i++)
2052 		pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc);
2053 	for (i = 0; i < (gotmic ? 3 : 2); i++)
2054 		pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc);
2055 
2056 	pcm_setstatus(dev, status);
2057 
2058 	return 0;
2059 
2060 bad:
2061 	if (codec) ac97_destroy(codec);
2062 	if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);
2063 	if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih);
2064 	if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
2065 	if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat);
2066 	if (sc->lock) snd_mtxfree(sc->lock);
2067 	free(sc, M_DEVBUF);
2068 	return ENXIO;
2069 }
2070 
2071 static int
2072 emu_pci_detach(device_t dev)
2073 {
2074 	int r;
2075 	struct sc_info *sc;
2076 
2077 	r = pcm_unregister(dev);
2078 	if (r)
2079 		return r;
2080 
2081 	sc = pcm_getdevinfo(dev);
2082 	/* shutdown chip */
2083 	emu_uninit(sc);
2084 
2085 	bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);
2086 	bus_teardown_intr(dev, sc->irq, sc->ih);
2087 	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
2088 	bus_dma_tag_destroy(sc->parent_dmat);
2089 	snd_mtxfree(sc->lock);
2090 	free(sc, M_DEVBUF);
2091 
2092 	return 0;
2093 }
2094 
2095 /* add suspend, resume */
2096 static device_method_t emu_methods[] = {
2097 	/* Device interface */
2098 	DEVMETHOD(device_probe,		emu_pci_probe),
2099 	DEVMETHOD(device_attach,	emu_pci_attach),
2100 	DEVMETHOD(device_detach,	emu_pci_detach),
2101 
2102 	{ 0, 0 }
2103 };
2104 
2105 static driver_t emu_driver = {
2106 	"pcm",
2107 	emu_methods,
2108 	PCM_SOFTC_SIZE,
2109 };
2110 
2111 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, 0, 0);
2112 DRIVER_MODULE(snd_emu10k1, cardbus, emu_driver, pcm_devclass, 0, 0);
2113 MODULE_DEPEND(snd_emu10k1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2114 MODULE_VERSION(snd_emu10k1, 1);
2115 MODULE_DEPEND(snd_emu10k1, midi, 1, 1, 1);
2116 
2117 /* dummy driver to silence the joystick device */
2118 static int
2119 emujoy_pci_probe(device_t dev)
2120 {
2121 	char *s = NULL;
2122 
2123 	switch (pci_get_devid(dev)) {
2124 	case 0x70021102:
2125 		s = "Creative EMU10K1 Joystick";
2126 		device_quiet(dev);
2127 		break;
2128 	case 0x70031102:
2129 		s = "Creative EMU10K2 Joystick";
2130 		device_quiet(dev);
2131 		break;
2132 	}
2133 
2134 	if (s) device_set_desc(dev, s);
2135 	return s ? -1000 : ENXIO;
2136 }
2137 
2138 static int
2139 emujoy_pci_attach(device_t dev)
2140 {
2141 	return 0;
2142 }
2143 
2144 static int
2145 emujoy_pci_detach(device_t dev)
2146 {
2147 	return 0;
2148 }
2149 
2150 static device_method_t emujoy_methods[] = {
2151 	DEVMETHOD(device_probe,		emujoy_pci_probe),
2152 	DEVMETHOD(device_attach,	emujoy_pci_attach),
2153 	DEVMETHOD(device_detach,	emujoy_pci_detach),
2154 
2155 	{ 0, 0 }
2156 };
2157 
2158 static driver_t emujoy_driver = {
2159 	"emujoy",
2160 	emujoy_methods,
2161 	8,
2162 };
2163 
2164 static devclass_t emujoy_devclass;
2165 
2166 DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, 0, 0);
2167 
2168