1 /*- 2 * Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org> 3 * Copyright (c) 2003 Orlando Bassotto <orlando.bassotto@ieo-research.it> 4 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifdef HAVE_KERNEL_OPTION_HEADERS 30 #include "opt_snd.h" 31 #endif 32 33 #include <dev/sound/pcm/sound.h> 34 #include <dev/sound/pcm/ac97.h> 35 #include "emu10k1-alsa%diked.h" 36 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 #include <sys/queue.h> 40 41 #include <dev/sound/midi/mpu401.h> 42 #include "mpufoi_if.h" 43 44 SND_DECLARE_FILE("$FreeBSD$"); 45 46 /* -------------------------------------------------------------------- */ 47 48 #define NUM_G 64 /* use all channels */ 49 #define WAVEOUT_MAXBUFSIZE 32768 50 #define EMUPAGESIZE 4096 /* don't change */ 51 #define EMUMAXPAGES (WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE) 52 #define EMU10K1_PCI_ID 0x00021102 /* 1102 => Creative Labs Vendor ID */ 53 #define EMU10K2_PCI_ID 0x00041102 54 #define EMU10K3_PCI_ID 0x00081102 55 #define EMU_DEFAULT_BUFSZ 4096 56 #define EMU_MAX_CHANS 8 57 #define EMU_CHANS 4 58 59 #define MAXREQVOICES 8 60 #define RESERVED 0 61 #define NUM_MIDI 16 62 #define NUM_FXSENDS 4 63 64 #define TMEMSIZE 256*1024 65 #define TMEMSIZEREG 4 66 67 #define ENABLE 0xffffffff 68 #define DISABLE 0x00000000 69 #define ENV_ON DCYSUSV_CHANNELENABLE_MASK 70 #define ENV_OFF 0x00 /* XXX: should this be 1? */ 71 72 #define A_IOCFG_GPOUT_A 0x40 /* Analog Output */ 73 #define A_IOCFG_GPOUT_D 0x04 /* Digital Output */ 74 #define A_IOCFG_GPOUT_AD (A_IOCFG_GPOUT_A|A_IOCFG_GPOUT_D) /* A_IOCFG_GPOUT0 */ 75 76 struct emu_memblk { 77 SLIST_ENTRY(emu_memblk) link; 78 void *buf; 79 bus_addr_t buf_addr; 80 u_int32_t pte_start, pte_size; 81 }; 82 83 struct emu_mem { 84 u_int8_t bmap[EMUMAXPAGES / 8]; 85 u_int32_t *ptb_pages; 86 void *silent_page; 87 bus_addr_t silent_page_addr; 88 bus_addr_t ptb_pages_addr; 89 SLIST_HEAD(, emu_memblk) blocks; 90 }; 91 92 struct emu_voice { 93 int vnum; 94 unsigned int b16:1, stereo:1, busy:1, running:1, ismaster:1; 95 int speed; 96 int start, end, vol; 97 int fxrt1; /* FX routing */ 98 int fxrt2; /* FX routing (only for audigy) */ 99 u_int32_t buf; 100 struct emu_voice *slave; 101 struct pcm_channel *channel; 102 }; 103 104 struct sc_info; 105 106 /* channel registers */ 107 struct sc_pchinfo { 108 int spd, fmt, blksz, run; 109 struct emu_voice *master, *slave; 110 struct snd_dbuf *buffer; 111 struct pcm_channel *channel; 112 struct sc_info *parent; 113 }; 114 115 struct sc_rchinfo { 116 int spd, fmt, run, blksz, num; 117 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask; 118 struct snd_dbuf *buffer; 119 struct pcm_channel *channel; 120 struct sc_info *parent; 121 }; 122 123 /* device private data */ 124 struct sc_info { 125 device_t dev; 126 u_int32_t type, rev; 127 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1; 128 u_int32_t addrmask; /* wider if audigy */ 129 130 bus_space_tag_t st; 131 bus_space_handle_t sh; 132 bus_dma_tag_t parent_dmat; 133 134 struct resource *reg, *irq; 135 void *ih; 136 struct mtx *lock; 137 138 unsigned int bufsz; 139 int timer, timerinterval; 140 int pnum, rnum; 141 int nchans; 142 struct emu_mem mem; 143 struct emu_voice voice[64]; 144 struct sc_pchinfo pch[EMU_MAX_CHANS]; 145 struct sc_rchinfo rch[3]; 146 struct mpu401 *mpu; 147 mpu401_intr_t *mpu_intr; 148 int mputx; 149 }; 150 151 /* -------------------------------------------------------------------- */ 152 153 /* 154 * prototypes 155 */ 156 157 /* stuff */ 158 static int emu_init(struct sc_info *); 159 static void emu_intr(void *); 160 static void *emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr); 161 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr); 162 static int emu_memfree(struct sc_info *sc, void *buf); 163 static int emu_memstart(struct sc_info *sc, void *buf); 164 #ifdef EMUDEBUG 165 static void emu_vdump(struct sc_info *sc, struct emu_voice *v); 166 #endif 167 168 /* talk to the card */ 169 static u_int32_t emu_rd(struct sc_info *, int, int); 170 static void emu_wr(struct sc_info *, int, u_int32_t, int); 171 172 /* -------------------------------------------------------------------- */ 173 174 static u_int32_t emu_rfmt_ac97[] = { 175 SND_FORMAT(AFMT_S16_LE, 1, 0), 176 SND_FORMAT(AFMT_S16_LE, 2, 0), 177 0 178 }; 179 180 static u_int32_t emu_rfmt_mic[] = { 181 SND_FORMAT(AFMT_U8, 1, 0), 182 0 183 }; 184 185 static u_int32_t emu_rfmt_efx[] = { 186 SND_FORMAT(AFMT_S16_LE, 2, 0), 187 0 188 }; 189 190 static struct pcmchan_caps emu_reccaps[3] = { 191 {8000, 48000, emu_rfmt_ac97, 0}, 192 {8000, 8000, emu_rfmt_mic, 0}, 193 {48000, 48000, emu_rfmt_efx, 0}, 194 }; 195 196 static u_int32_t emu_pfmt[] = { 197 SND_FORMAT(AFMT_U8, 1, 0), 198 SND_FORMAT(AFMT_U8, 2, 0), 199 SND_FORMAT(AFMT_S16_LE, 1, 0), 200 SND_FORMAT(AFMT_S16_LE, 2, 0), 201 0 202 }; 203 204 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0}; 205 206 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000}; 207 /* audigy supports 12kHz. */ 208 static int audigy_adcspeed[9] = { 209 48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000 210 }; 211 212 /* -------------------------------------------------------------------- */ 213 /* Hardware */ 214 static u_int32_t 215 emu_rd(struct sc_info *sc, int regno, int size) 216 { 217 switch (size) { 218 case 1: 219 return bus_space_read_1(sc->st, sc->sh, regno); 220 case 2: 221 return bus_space_read_2(sc->st, sc->sh, regno); 222 case 4: 223 return bus_space_read_4(sc->st, sc->sh, regno); 224 default: 225 return 0xffffffff; 226 } 227 } 228 229 static void 230 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 231 { 232 switch (size) { 233 case 1: 234 bus_space_write_1(sc->st, sc->sh, regno, data); 235 break; 236 case 2: 237 bus_space_write_2(sc->st, sc->sh, regno, data); 238 break; 239 case 4: 240 bus_space_write_4(sc->st, sc->sh, regno, data); 241 break; 242 } 243 } 244 245 static u_int32_t 246 emu_rdptr(struct sc_info *sc, int chn, int reg) 247 { 248 u_int32_t ptr, val, mask, size, offset; 249 250 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK); 251 emu_wr(sc, PTR, ptr, 4); 252 val = emu_rd(sc, DATA, 4); 253 if (reg & 0xff000000) { 254 size = (reg >> 24) & 0x3f; 255 offset = (reg >> 16) & 0x1f; 256 mask = ((1 << size) - 1) << offset; 257 val &= mask; 258 val >>= offset; 259 } 260 return val; 261 } 262 263 static void 264 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data) 265 { 266 u_int32_t ptr, mask, size, offset; 267 268 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK); 269 emu_wr(sc, PTR, ptr, 4); 270 if (reg & 0xff000000) { 271 size = (reg >> 24) & 0x3f; 272 offset = (reg >> 16) & 0x1f; 273 mask = ((1 << size) - 1) << offset; 274 data <<= offset; 275 data &= mask; 276 data |= emu_rd(sc, DATA, 4) & ~mask; 277 } 278 emu_wr(sc, DATA, data, 4); 279 } 280 281 static void 282 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data) 283 { 284 pc += sc->audigy ? A_MICROCODEBASE : MICROCODEBASE; 285 emu_wrptr(sc, 0, pc, data); 286 } 287 288 /* -------------------------------------------------------------------- */ 289 /* ac97 codec */ 290 /* no locking needed */ 291 292 static int 293 emu_rdcd(kobj_t obj, void *devinfo, int regno) 294 { 295 struct sc_info *sc = (struct sc_info *)devinfo; 296 297 emu_wr(sc, AC97ADDRESS, regno, 1); 298 return emu_rd(sc, AC97DATA, 2); 299 } 300 301 static int 302 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 303 { 304 struct sc_info *sc = (struct sc_info *)devinfo; 305 306 emu_wr(sc, AC97ADDRESS, regno, 1); 307 emu_wr(sc, AC97DATA, data, 2); 308 return 0; 309 } 310 311 static kobj_method_t emu_ac97_methods[] = { 312 KOBJMETHOD(ac97_read, emu_rdcd), 313 KOBJMETHOD(ac97_write, emu_wrcd), 314 KOBJMETHOD_END 315 }; 316 AC97_DECLARE(emu_ac97); 317 318 /* -------------------------------------------------------------------- */ 319 /* stuff */ 320 static int 321 emu_settimer(struct sc_info *sc) 322 { 323 struct sc_pchinfo *pch; 324 struct sc_rchinfo *rch; 325 int i, tmp, rate; 326 327 rate = 0; 328 for (i = 0; i < sc->nchans; i++) { 329 pch = &sc->pch[i]; 330 if (pch->buffer) { 331 tmp = (pch->spd * sndbuf_getalign(pch->buffer)) 332 / pch->blksz; 333 if (tmp > rate) 334 rate = tmp; 335 } 336 } 337 338 for (i = 0; i < 3; i++) { 339 rch = &sc->rch[i]; 340 if (rch->buffer) { 341 tmp = (rch->spd * sndbuf_getalign(rch->buffer)) 342 / rch->blksz; 343 if (tmp > rate) 344 rate = tmp; 345 } 346 } 347 RANGE(rate, 48, 9600); 348 sc->timerinterval = 48000 / rate; 349 emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2); 350 351 return sc->timerinterval; 352 } 353 354 static int 355 emu_enatimer(struct sc_info *sc, int go) 356 { 357 u_int32_t x; 358 if (go) { 359 if (sc->timer++ == 0) { 360 x = emu_rd(sc, INTE, 4); 361 x |= INTE_INTERVALTIMERENB; 362 emu_wr(sc, INTE, x, 4); 363 } 364 } else { 365 sc->timer = 0; 366 x = emu_rd(sc, INTE, 4); 367 x &= ~INTE_INTERVALTIMERENB; 368 emu_wr(sc, INTE, x, 4); 369 } 370 return 0; 371 } 372 373 static void 374 emu_enastop(struct sc_info *sc, char channel, int enable) 375 { 376 int reg = (channel & 0x20) ? SOLEH : SOLEL; 377 channel &= 0x1f; 378 reg |= 1 << 24; 379 reg |= channel << 16; 380 emu_wrptr(sc, 0, reg, enable); 381 } 382 383 static int 384 emu_recval(int speed) { 385 int val; 386 387 val = 0; 388 while (val < 7 && speed < adcspeed[val]) 389 val++; 390 return val; 391 } 392 393 static int 394 audigy_recval(int speed) { 395 int val; 396 397 val = 0; 398 while (val < 8 && speed < audigy_adcspeed[val]) 399 val++; 400 return val; 401 } 402 403 static u_int32_t 404 emu_rate_to_pitch(u_int32_t rate) 405 { 406 static u_int32_t logMagTable[128] = { 407 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2, 408 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5, 409 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081, 410 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191, 411 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7, 412 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829, 413 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e, 414 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26, 415 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d, 416 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885, 417 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899, 418 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c, 419 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3, 420 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3, 421 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83, 422 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df 423 }; 424 static char logSlopeTable[128] = { 425 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58, 426 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53, 427 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f, 428 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b, 429 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47, 430 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44, 431 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41, 432 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e, 433 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c, 434 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 435 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37, 436 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35, 437 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34, 438 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32, 439 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30, 440 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f 441 }; 442 int i; 443 444 if (rate == 0) 445 return 0; /* Bail out if no leading "1" */ 446 rate *= 11185; /* Scale 48000 to 0x20002380 */ 447 for (i = 31; i > 0; i--) { 448 if (rate & 0x80000000) { /* Detect leading "1" */ 449 return (((u_int32_t) (i - 15) << 20) + 450 logMagTable[0x7f & (rate >> 24)] + 451 (0x7f & (rate >> 17)) * 452 logSlopeTable[0x7f & (rate >> 24)]); 453 } 454 rate <<= 1; 455 } 456 457 return 0; /* Should never reach this point */ 458 } 459 460 static u_int32_t 461 emu_rate_to_linearpitch(u_int32_t rate) 462 { 463 rate = (rate << 8) / 375; 464 return (rate >> 1) + (rate & 1); 465 } 466 467 static struct emu_voice * 468 emu_valloc(struct sc_info *sc) 469 { 470 struct emu_voice *v; 471 int i; 472 473 v = NULL; 474 for (i = 0; i < 64 && sc->voice[i].busy; i++); 475 if (i < 64) { 476 v = &sc->voice[i]; 477 v->busy = 1; 478 } 479 return v; 480 } 481 482 static int 483 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s, 484 u_int32_t sz, struct snd_dbuf *b) 485 { 486 void *buf; 487 bus_addr_t tmp_addr; 488 489 buf = emu_memalloc(sc, sz, &tmp_addr); 490 if (buf == NULL) 491 return -1; 492 if (b != NULL) 493 sndbuf_setup(b, buf, sz); 494 m->start = emu_memstart(sc, buf) * EMUPAGESIZE; 495 m->end = m->start + sz; 496 m->channel = NULL; 497 m->speed = 0; 498 m->b16 = 0; 499 m->stereo = 0; 500 m->running = 0; 501 m->ismaster = 1; 502 m->vol = 0xff; 503 m->buf = tmp_addr; 504 m->slave = s; 505 if (sc->audigy) { 506 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 8 | 507 FXBUS_PCM_LEFT << 16 | FXBUS_MIDI_REVERB << 24; 508 m->fxrt2 = 0x3f3f3f3f; /* No effects on second route */ 509 } else { 510 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 4 | 511 FXBUS_PCM_LEFT << 8 | FXBUS_MIDI_REVERB << 12; 512 m->fxrt2 = 0; 513 } 514 515 if (s != NULL) { 516 s->start = m->start; 517 s->end = m->end; 518 s->channel = NULL; 519 s->speed = 0; 520 s->b16 = 0; 521 s->stereo = 0; 522 s->running = 0; 523 s->ismaster = 0; 524 s->vol = m->vol; 525 s->buf = m->buf; 526 s->fxrt1 = m->fxrt1; 527 s->fxrt2 = m->fxrt2; 528 s->slave = NULL; 529 } 530 return 0; 531 } 532 533 static void 534 emu_vsetup(struct sc_pchinfo *ch) 535 { 536 struct emu_voice *v = ch->master; 537 538 if (ch->fmt) { 539 v->b16 = (ch->fmt & AFMT_16BIT) ? 1 : 0; 540 v->stereo = (AFMT_CHANNEL(ch->fmt) > 1) ? 1 : 0; 541 if (v->slave != NULL) { 542 v->slave->b16 = v->b16; 543 v->slave->stereo = v->stereo; 544 } 545 } 546 if (ch->spd) { 547 v->speed = ch->spd; 548 if (v->slave != NULL) 549 v->slave->speed = v->speed; 550 } 551 } 552 553 static void 554 emu_vwrite(struct sc_info *sc, struct emu_voice *v) 555 { 556 int s; 557 int l, r, x, y; 558 u_int32_t sa, ea, start, val, silent_page; 559 560 s = (v->stereo ? 1 : 0) + (v->b16 ? 1 : 0); 561 562 sa = v->start >> s; 563 ea = v->end >> s; 564 565 l = r = x = y = v->vol; 566 if (v->stereo) { 567 l = v->ismaster ? l : 0; 568 r = v->ismaster ? 0 : r; 569 } 570 571 emu_wrptr(sc, v->vnum, CPF, v->stereo ? CPF_STEREO_MASK : 0); 572 val = v->stereo ? 28 : 30; 573 val *= v->b16 ? 1 : 2; 574 start = sa + val; 575 576 if (sc->audigy) { 577 emu_wrptr(sc, v->vnum, A_FXRT1, v->fxrt1); 578 emu_wrptr(sc, v->vnum, A_FXRT2, v->fxrt2); 579 emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, 0); 580 } 581 else 582 emu_wrptr(sc, v->vnum, FXRT, v->fxrt1 << 16); 583 584 emu_wrptr(sc, v->vnum, PTRX, (x << 8) | r); 585 emu_wrptr(sc, v->vnum, DSL, ea | (y << 24)); 586 emu_wrptr(sc, v->vnum, PSST, sa | (l << 24)); 587 emu_wrptr(sc, v->vnum, CCCA, start | (v->b16 ? 0 : CCCA_8BITSELECT)); 588 589 emu_wrptr(sc, v->vnum, Z1, 0); 590 emu_wrptr(sc, v->vnum, Z2, 0); 591 592 silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1) 593 | MAP_PTI_MASK; 594 emu_wrptr(sc, v->vnum, MAPA, silent_page); 595 emu_wrptr(sc, v->vnum, MAPB, silent_page); 596 597 emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK); 598 emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK); 599 emu_wrptr(sc, v->vnum, ATKHLDM, 0); 600 emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK); 601 emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000); 602 emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000); 603 emu_wrptr(sc, v->vnum, FMMOD, 0); 604 emu_wrptr(sc, v->vnum, TREMFRQ, 0); 605 emu_wrptr(sc, v->vnum, FM2FRQ2, 0); 606 emu_wrptr(sc, v->vnum, ENVVAL, 0x8000); 607 608 emu_wrptr(sc, v->vnum, ATKHLDV, 609 ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK); 610 emu_wrptr(sc, v->vnum, ENVVOL, 0x8000); 611 612 emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f); 613 emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0); 614 615 if (v->slave != NULL) 616 emu_vwrite(sc, v->slave); 617 } 618 619 static void 620 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go) 621 { 622 u_int32_t pitch_target, initial_pitch; 623 u_int32_t cra, cs, ccis; 624 u_int32_t sample, i; 625 626 if (go) { 627 cra = 64; 628 cs = v->stereo ? 4 : 2; 629 ccis = v->stereo ? 28 : 30; 630 ccis *= v->b16 ? 1 : 2; 631 sample = v->b16 ? 0x00000000 : 0x80808080; 632 633 for (i = 0; i < cs; i++) 634 emu_wrptr(sc, v->vnum, CD0 + i, sample); 635 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0); 636 emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra); 637 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis); 638 639 emu_wrptr(sc, v->vnum, IFATN, 0xff00); 640 emu_wrptr(sc, v->vnum, VTFT, 0xffffffff); 641 emu_wrptr(sc, v->vnum, CVCF, 0xffffffff); 642 emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f); 643 emu_enastop(sc, v->vnum, 0); 644 645 pitch_target = emu_rate_to_linearpitch(v->speed); 646 initial_pitch = emu_rate_to_pitch(v->speed) >> 8; 647 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target); 648 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target); 649 emu_wrptr(sc, v->vnum, IP, initial_pitch); 650 } else { 651 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0); 652 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0); 653 emu_wrptr(sc, v->vnum, IFATN, 0xffff); 654 emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff); 655 emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff); 656 emu_wrptr(sc, v->vnum, IP, 0); 657 emu_enastop(sc, v->vnum, 1); 658 } 659 if (v->slave != NULL) 660 emu_vtrigger(sc, v->slave, go); 661 } 662 663 static int 664 emu_vpos(struct sc_info *sc, struct emu_voice *v) 665 { 666 int s, ptr; 667 668 s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0); 669 ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s; 670 return ptr & ~0x0000001f; 671 } 672 673 #ifdef EMUDEBUG 674 static void 675 emu_vdump(struct sc_info *sc, struct emu_voice *v) 676 { 677 char *regname[] = { 678 "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl", 679 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL, 680 "envvol", "atkhldv", "dcysusv", "lfoval1", 681 "envval", "atkhldm", "dcysusm", "lfoval2", 682 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2", 683 "tempenv" 684 }; 685 char *regname2[] = { 686 "mudata1", "mustat1", "mudata2", "mustat2", 687 "fxwc1", "fxwc2", "spdrate", NULL, NULL, 688 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1", 689 NULL, NULL 690 }; 691 int i, x; 692 693 printf("voice number %d\n", v->vnum); 694 for (i = 0, x = 0; i <= 0x1e; i++) { 695 if (regname[i] == NULL) 696 continue; 697 printf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i)); 698 printf("%s", (x == 2) ? "\n" : "\t"); 699 x++; 700 if (x > 2) 701 x = 0; 702 } 703 704 /* Print out audigy extra registers */ 705 if (sc->audigy) { 706 for (i = 0; i <= 0xe; i++) { 707 if (regname2[i] == NULL) 708 continue; 709 printf("%s\t[%08x]", regname2[i], 710 emu_rdptr(sc, v->vnum, i + 0x70)); 711 printf("%s", (x == 2)? "\n" : "\t"); 712 x++; 713 if (x > 2) 714 x = 0; 715 } 716 } 717 printf("\n\n"); 718 } 719 #endif 720 721 /* channel interface */ 722 static void * 723 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 724 struct pcm_channel *c, int dir) 725 { 726 struct sc_info *sc = devinfo; 727 struct sc_pchinfo *ch; 728 void *r; 729 730 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction")); 731 ch = &sc->pch[sc->pnum++]; 732 ch->buffer = b; 733 ch->parent = sc; 734 ch->channel = c; 735 ch->blksz = sc->bufsz / 2; 736 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 737 ch->spd = 8000; 738 snd_mtxlock(sc->lock); 739 ch->master = emu_valloc(sc); 740 ch->slave = emu_valloc(sc); 741 snd_mtxunlock(sc->lock); 742 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer)) 743 ? NULL : ch; 744 745 return r; 746 } 747 748 static int 749 emupchan_free(kobj_t obj, void *data) 750 { 751 struct sc_pchinfo *ch = data; 752 struct sc_info *sc = ch->parent; 753 int r; 754 755 snd_mtxlock(sc->lock); 756 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer)); 757 snd_mtxunlock(sc->lock); 758 759 return r; 760 } 761 762 static int 763 emupchan_setformat(kobj_t obj, void *data, u_int32_t format) 764 { 765 struct sc_pchinfo *ch = data; 766 767 ch->fmt = format; 768 return 0; 769 } 770 771 static u_int32_t 772 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 773 { 774 struct sc_pchinfo *ch = data; 775 776 ch->spd = speed; 777 return ch->spd; 778 } 779 780 static u_int32_t 781 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 782 { 783 struct sc_pchinfo *ch = data; 784 struct sc_info *sc = ch->parent; 785 int irqrate, blksz; 786 787 ch->blksz = blocksize; 788 snd_mtxlock(sc->lock); 789 emu_settimer(sc); 790 irqrate = 48000 / sc->timerinterval; 791 snd_mtxunlock(sc->lock); 792 blksz = (ch->spd * sndbuf_getalign(ch->buffer)) / irqrate; 793 return blocksize; 794 } 795 796 static int 797 emupchan_trigger(kobj_t obj, void *data, int go) 798 { 799 struct sc_pchinfo *ch = data; 800 struct sc_info *sc = ch->parent; 801 802 if (!PCMTRIG_COMMON(go)) 803 return 0; 804 805 snd_mtxlock(sc->lock); 806 if (go == PCMTRIG_START) { 807 emu_vsetup(ch); 808 emu_vwrite(sc, ch->master); 809 emu_settimer(sc); 810 emu_enatimer(sc, 1); 811 #ifdef EMUDEBUG 812 printf("start [%d bit, %s, %d hz]\n", 813 ch->master->b16 ? 16 : 8, 814 ch->master->stereo ? "stereo" : "mono", 815 ch->master->speed); 816 emu_vdump(sc, ch->master); 817 emu_vdump(sc, ch->slave); 818 #endif 819 } 820 ch->run = (go == PCMTRIG_START) ? 1 : 0; 821 emu_vtrigger(sc, ch->master, ch->run); 822 snd_mtxunlock(sc->lock); 823 return 0; 824 } 825 826 static u_int32_t 827 emupchan_getptr(kobj_t obj, void *data) 828 { 829 struct sc_pchinfo *ch = data; 830 struct sc_info *sc = ch->parent; 831 int r; 832 833 snd_mtxlock(sc->lock); 834 r = emu_vpos(sc, ch->master); 835 snd_mtxunlock(sc->lock); 836 837 return r; 838 } 839 840 static struct pcmchan_caps * 841 emupchan_getcaps(kobj_t obj, void *data) 842 { 843 return &emu_playcaps; 844 } 845 846 static kobj_method_t emupchan_methods[] = { 847 KOBJMETHOD(channel_init, emupchan_init), 848 KOBJMETHOD(channel_free, emupchan_free), 849 KOBJMETHOD(channel_setformat, emupchan_setformat), 850 KOBJMETHOD(channel_setspeed, emupchan_setspeed), 851 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize), 852 KOBJMETHOD(channel_trigger, emupchan_trigger), 853 KOBJMETHOD(channel_getptr, emupchan_getptr), 854 KOBJMETHOD(channel_getcaps, emupchan_getcaps), 855 KOBJMETHOD_END 856 }; 857 CHANNEL_DECLARE(emupchan); 858 859 /* channel interface */ 860 static void * 861 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 862 struct pcm_channel *c, int dir) 863 { 864 struct sc_info *sc = devinfo; 865 struct sc_rchinfo *ch; 866 867 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction")); 868 ch = &sc->rch[sc->rnum]; 869 ch->buffer = b; 870 ch->parent = sc; 871 ch->channel = c; 872 ch->blksz = sc->bufsz / 2; 873 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 874 ch->spd = 8000; 875 ch->num = sc->rnum; 876 switch(sc->rnum) { 877 case 0: 878 ch->idxreg = sc->audigy ? A_ADCIDX : ADCIDX; 879 ch->basereg = ADCBA; 880 ch->sizereg = ADCBS; 881 ch->setupreg = ADCCR; 882 ch->irqmask = INTE_ADCBUFENABLE; 883 break; 884 885 case 1: 886 ch->idxreg = FXIDX; 887 ch->basereg = FXBA; 888 ch->sizereg = FXBS; 889 ch->setupreg = FXWC; 890 ch->irqmask = INTE_EFXBUFENABLE; 891 break; 892 893 case 2: 894 ch->idxreg = MICIDX; 895 ch->basereg = MICBA; 896 ch->sizereg = MICBS; 897 ch->setupreg = 0; 898 ch->irqmask = INTE_MICBUFENABLE; 899 break; 900 } 901 sc->rnum++; 902 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) 903 return NULL; 904 else { 905 snd_mtxlock(sc->lock); 906 emu_wrptr(sc, 0, ch->basereg, sndbuf_getbufaddr(ch->buffer)); 907 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */ 908 snd_mtxunlock(sc->lock); 909 return ch; 910 } 911 } 912 913 static int 914 emurchan_setformat(kobj_t obj, void *data, u_int32_t format) 915 { 916 struct sc_rchinfo *ch = data; 917 918 ch->fmt = format; 919 return 0; 920 } 921 922 static u_int32_t 923 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 924 { 925 struct sc_rchinfo *ch = data; 926 927 if (ch->num == 0) { 928 if (ch->parent->audigy) 929 speed = audigy_adcspeed[audigy_recval(speed)]; 930 else 931 speed = adcspeed[emu_recval(speed)]; 932 } 933 if (ch->num == 1) 934 speed = 48000; 935 if (ch->num == 2) 936 speed = 8000; 937 ch->spd = speed; 938 return ch->spd; 939 } 940 941 static u_int32_t 942 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 943 { 944 struct sc_rchinfo *ch = data; 945 struct sc_info *sc = ch->parent; 946 int irqrate, blksz; 947 948 ch->blksz = blocksize; 949 snd_mtxlock(sc->lock); 950 emu_settimer(sc); 951 irqrate = 48000 / sc->timerinterval; 952 snd_mtxunlock(sc->lock); 953 blksz = (ch->spd * sndbuf_getalign(ch->buffer)) / irqrate; 954 return blocksize; 955 } 956 957 /* semantic note: must start at beginning of buffer */ 958 static int 959 emurchan_trigger(kobj_t obj, void *data, int go) 960 { 961 struct sc_rchinfo *ch = data; 962 struct sc_info *sc = ch->parent; 963 u_int32_t val, sz; 964 965 if (!PCMTRIG_COMMON(go)) 966 return 0; 967 968 switch(sc->bufsz) { 969 case 4096: 970 sz = ADCBS_BUFSIZE_4096; 971 break; 972 973 case 8192: 974 sz = ADCBS_BUFSIZE_8192; 975 break; 976 977 case 16384: 978 sz = ADCBS_BUFSIZE_16384; 979 break; 980 981 case 32768: 982 sz = ADCBS_BUFSIZE_32768; 983 break; 984 985 case 65536: 986 sz = ADCBS_BUFSIZE_65536; 987 break; 988 989 default: 990 sz = ADCBS_BUFSIZE_4096; 991 } 992 993 snd_mtxlock(sc->lock); 994 switch(go) { 995 case PCMTRIG_START: 996 ch->run = 1; 997 emu_wrptr(sc, 0, ch->sizereg, sz); 998 if (ch->num == 0) { 999 if (sc->audigy) { 1000 val = A_ADCCR_LCHANENABLE; 1001 if (AFMT_CHANNEL(ch->fmt) > 1) 1002 val |= A_ADCCR_RCHANENABLE; 1003 val |= audigy_recval(ch->spd); 1004 } else { 1005 val = ADCCR_LCHANENABLE; 1006 if (AFMT_CHANNEL(ch->fmt) > 1) 1007 val |= ADCCR_RCHANENABLE; 1008 val |= emu_recval(ch->spd); 1009 } 1010 1011 emu_wrptr(sc, 0, ch->setupreg, 0); 1012 emu_wrptr(sc, 0, ch->setupreg, val); 1013 } 1014 val = emu_rd(sc, INTE, 4); 1015 val |= ch->irqmask; 1016 emu_wr(sc, INTE, val, 4); 1017 break; 1018 1019 case PCMTRIG_STOP: 1020 case PCMTRIG_ABORT: 1021 ch->run = 0; 1022 emu_wrptr(sc, 0, ch->sizereg, 0); 1023 if (ch->setupreg) 1024 emu_wrptr(sc, 0, ch->setupreg, 0); 1025 val = emu_rd(sc, INTE, 4); 1026 val &= ~ch->irqmask; 1027 emu_wr(sc, INTE, val, 4); 1028 break; 1029 1030 case PCMTRIG_EMLDMAWR: 1031 case PCMTRIG_EMLDMARD: 1032 default: 1033 break; 1034 } 1035 snd_mtxunlock(sc->lock); 1036 1037 return 0; 1038 } 1039 1040 static u_int32_t 1041 emurchan_getptr(kobj_t obj, void *data) 1042 { 1043 struct sc_rchinfo *ch = data; 1044 struct sc_info *sc = ch->parent; 1045 int r; 1046 1047 snd_mtxlock(sc->lock); 1048 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff; 1049 snd_mtxunlock(sc->lock); 1050 1051 return r; 1052 } 1053 1054 static struct pcmchan_caps * 1055 emurchan_getcaps(kobj_t obj, void *data) 1056 { 1057 struct sc_rchinfo *ch = data; 1058 1059 return &emu_reccaps[ch->num]; 1060 } 1061 1062 static kobj_method_t emurchan_methods[] = { 1063 KOBJMETHOD(channel_init, emurchan_init), 1064 KOBJMETHOD(channel_setformat, emurchan_setformat), 1065 KOBJMETHOD(channel_setspeed, emurchan_setspeed), 1066 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize), 1067 KOBJMETHOD(channel_trigger, emurchan_trigger), 1068 KOBJMETHOD(channel_getptr, emurchan_getptr), 1069 KOBJMETHOD(channel_getcaps, emurchan_getcaps), 1070 KOBJMETHOD_END 1071 }; 1072 CHANNEL_DECLARE(emurchan); 1073 1074 static unsigned char 1075 emu_mread(struct mpu401 *arg, void *sc, int reg) 1076 { 1077 unsigned int d; 1078 1079 d = emu_rd((struct sc_info *)sc, 0x18 + reg, 1); 1080 return d; 1081 } 1082 1083 static void 1084 emu_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b) 1085 { 1086 1087 emu_wr((struct sc_info *)sc, 0x18 + reg, b, 1); 1088 } 1089 1090 static int 1091 emu_muninit(struct mpu401 *arg, void *cookie) 1092 { 1093 struct sc_info *sc = cookie; 1094 1095 snd_mtxlock(sc->lock); 1096 sc->mpu_intr = 0; 1097 snd_mtxunlock(sc->lock); 1098 1099 return 0; 1100 } 1101 1102 static kobj_method_t emu_mpu_methods[] = { 1103 KOBJMETHOD(mpufoi_read, emu_mread), 1104 KOBJMETHOD(mpufoi_write, emu_mwrite), 1105 KOBJMETHOD(mpufoi_uninit, emu_muninit), 1106 KOBJMETHOD_END 1107 }; 1108 1109 static DEFINE_CLASS(emu_mpu, emu_mpu_methods, 0); 1110 1111 static void 1112 emu_intr2(void *p) 1113 { 1114 struct sc_info *sc = (struct sc_info *)p; 1115 1116 if (sc->mpu_intr) 1117 (sc->mpu_intr)(sc->mpu); 1118 } 1119 1120 static void 1121 emu_midiattach(struct sc_info *sc) 1122 { 1123 int i; 1124 1125 i = emu_rd(sc, INTE, 4); 1126 i |= INTE_MIDIRXENABLE; 1127 emu_wr(sc, INTE, i, 4); 1128 1129 sc->mpu = mpu401_init(&emu_mpu_class, sc, emu_intr2, &sc->mpu_intr); 1130 } 1131 /* -------------------------------------------------------------------- */ 1132 /* The interrupt handler */ 1133 1134 static void 1135 emu_intr(void *data) 1136 { 1137 struct sc_info *sc = data; 1138 u_int32_t stat, ack, i, x; 1139 1140 snd_mtxlock(sc->lock); 1141 while (1) { 1142 stat = emu_rd(sc, IPR, 4); 1143 if (stat == 0) 1144 break; 1145 ack = 0; 1146 1147 /* process irq */ 1148 if (stat & IPR_INTERVALTIMER) 1149 ack |= IPR_INTERVALTIMER; 1150 1151 if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) 1152 ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL); 1153 1154 if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) 1155 ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL); 1156 1157 if (stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) 1158 ack |= stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL); 1159 1160 if (stat & IPR_PCIERROR) { 1161 ack |= IPR_PCIERROR; 1162 device_printf(sc->dev, "pci error\n"); 1163 /* we still get an nmi with ecc ram even if we ack this */ 1164 } 1165 if (stat & IPR_SAMPLERATETRACKER) { 1166 ack |= IPR_SAMPLERATETRACKER; 1167 #ifdef EMUDEBUG 1168 device_printf(sc->dev, 1169 "sample rate tracker lock status change\n"); 1170 #endif 1171 } 1172 1173 if (stat & IPR_MIDIRECVBUFEMPTY) 1174 if (sc->mpu_intr) { 1175 (sc->mpu_intr)(sc->mpu); 1176 ack |= IPR_MIDIRECVBUFEMPTY | IPR_MIDITRANSBUFEMPTY; 1177 } 1178 if (stat & ~ack) 1179 device_printf(sc->dev, "dodgy irq: %x (harmless)\n", 1180 stat & ~ack); 1181 1182 emu_wr(sc, IPR, stat, 4); 1183 1184 if (ack) { 1185 snd_mtxunlock(sc->lock); 1186 1187 if (ack & IPR_INTERVALTIMER) { 1188 x = 0; 1189 for (i = 0; i < sc->nchans; i++) { 1190 if (sc->pch[i].run) { 1191 x = 1; 1192 chn_intr(sc->pch[i].channel); 1193 } 1194 } 1195 if (x == 0) 1196 emu_enatimer(sc, 0); 1197 } 1198 1199 1200 if (ack & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) { 1201 if (sc->rch[0].channel) 1202 chn_intr(sc->rch[0].channel); 1203 } 1204 if (ack & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) { 1205 if (sc->rch[1].channel) 1206 chn_intr(sc->rch[1].channel); 1207 } 1208 if (ack & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) { 1209 if (sc->rch[2].channel) 1210 chn_intr(sc->rch[2].channel); 1211 } 1212 1213 snd_mtxlock(sc->lock); 1214 } 1215 } 1216 snd_mtxunlock(sc->lock); 1217 } 1218 1219 /* -------------------------------------------------------------------- */ 1220 1221 static void 1222 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1223 { 1224 bus_addr_t *phys = arg; 1225 1226 *phys = error ? 0 : (bus_addr_t)segs->ds_addr; 1227 1228 if (bootverbose) { 1229 printf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n", 1230 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len, 1231 nseg, error); 1232 } 1233 } 1234 1235 static void * 1236 emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr) 1237 { 1238 void *buf; 1239 bus_dmamap_t map; 1240 1241 *addr = 0; 1242 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map)) 1243 return NULL; 1244 if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, emu_setmap, addr, 0) 1245 || !*addr) 1246 return NULL; 1247 return buf; 1248 } 1249 1250 static void 1251 emu_free(struct sc_info *sc, void *buf) 1252 { 1253 bus_dmamem_free(sc->parent_dmat, buf, NULL); 1254 } 1255 1256 static void * 1257 emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr) 1258 { 1259 u_int32_t blksz, start, idx, ofs, tmp, found; 1260 struct emu_mem *mem = &sc->mem; 1261 struct emu_memblk *blk; 1262 void *buf; 1263 1264 blksz = sz / EMUPAGESIZE; 1265 if (sz > (blksz * EMUPAGESIZE)) 1266 blksz++; 1267 /* find a free block in the bitmap */ 1268 found = 0; 1269 start = 1; 1270 while (!found && start + blksz < EMUMAXPAGES) { 1271 found = 1; 1272 for (idx = start; idx < start + blksz; idx++) 1273 if (mem->bmap[idx >> 3] & (1 << (idx & 7))) 1274 found = 0; 1275 if (!found) 1276 start++; 1277 } 1278 if (!found) 1279 return NULL; 1280 blk = malloc(sizeof(*blk), M_DEVBUF, M_NOWAIT); 1281 if (blk == NULL) 1282 return NULL; 1283 buf = emu_malloc(sc, sz, &blk->buf_addr); 1284 *addr = blk->buf_addr; 1285 if (buf == NULL) { 1286 free(blk, M_DEVBUF); 1287 return NULL; 1288 } 1289 blk->buf = buf; 1290 blk->pte_start = start; 1291 blk->pte_size = blksz; 1292 #ifdef EMUDEBUG 1293 printf("buf %p, pte_start %d, pte_size %d\n", blk->buf, 1294 blk->pte_start, blk->pte_size); 1295 #endif 1296 ofs = 0; 1297 for (idx = start; idx < start + blksz; idx++) { 1298 mem->bmap[idx >> 3] |= 1 << (idx & 7); 1299 tmp = (u_int32_t)(u_long)((u_int8_t *)blk->buf_addr + ofs); 1300 #ifdef EMUDEBUG 1301 printf("pte[%d] -> %x phys, %x virt\n", idx, tmp, 1302 ((u_int32_t)buf) + ofs); 1303 #endif 1304 mem->ptb_pages[idx] = (tmp << 1) | idx; 1305 ofs += EMUPAGESIZE; 1306 } 1307 SLIST_INSERT_HEAD(&mem->blocks, blk, link); 1308 return buf; 1309 } 1310 1311 static int 1312 emu_memfree(struct sc_info *sc, void *buf) 1313 { 1314 u_int32_t idx, tmp; 1315 struct emu_mem *mem = &sc->mem; 1316 struct emu_memblk *blk, *i; 1317 1318 blk = NULL; 1319 SLIST_FOREACH(i, &mem->blocks, link) { 1320 if (i->buf == buf) 1321 blk = i; 1322 } 1323 if (blk == NULL) 1324 return EINVAL; 1325 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link); 1326 emu_free(sc, buf); 1327 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1328 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) { 1329 mem->bmap[idx >> 3] &= ~(1 << (idx & 7)); 1330 mem->ptb_pages[idx] = tmp | idx; 1331 } 1332 free(blk, M_DEVBUF); 1333 return 0; 1334 } 1335 1336 static int 1337 emu_memstart(struct sc_info *sc, void *buf) 1338 { 1339 struct emu_mem *mem = &sc->mem; 1340 struct emu_memblk *blk, *i; 1341 1342 blk = NULL; 1343 SLIST_FOREACH(i, &mem->blocks, link) { 1344 if (i->buf == buf) 1345 blk = i; 1346 } 1347 if (blk == NULL) 1348 return -EINVAL; 1349 return blk->pte_start; 1350 } 1351 1352 static void 1353 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1354 u_int32_t *pc) 1355 { 1356 emu_wrefx(sc, (*pc) * 2, (x << 10) | y); 1357 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w); 1358 (*pc)++; 1359 } 1360 1361 static void 1362 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y, 1363 u_int32_t *pc) 1364 { 1365 emu_wrefx(sc, (*pc) * 2, (x << 12) | y); 1366 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w); 1367 (*pc)++; 1368 } 1369 1370 static void 1371 audigy_initefx(struct sc_info *sc) 1372 { 1373 int i; 1374 u_int32_t pc = 0; 1375 1376 /* skip 0, 0, -1, 0 - NOPs */ 1377 for (i = 0; i < 512; i++) 1378 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc); 1379 1380 for (i = 0; i < 512; i++) 1381 emu_wrptr(sc, 0, A_FXGPREGBASE + i, 0x0); 1382 1383 pc = 16; 1384 1385 /* stop fx processor */ 1386 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP); 1387 1388 /* Audigy 2 (EMU10K2) DSP Registers: 1389 FX Bus 1390 0x000-0x00f : 16 registers (?) 1391 Input 1392 0x040/0x041 : AC97 Codec (l/r) 1393 0x042/0x043 : ADC, S/PDIF (l/r) 1394 0x044/0x045 : Optical S/PDIF in (l/r) 1395 0x046/0x047 : ? 1396 0x048/0x049 : Line/Mic 2 (l/r) 1397 0x04a/0x04b : RCA S/PDIF (l/r) 1398 0x04c/0x04d : Aux 2 (l/r) 1399 Output 1400 0x060/0x061 : Digital Front (l/r) 1401 0x062/0x063 : Digital Center/LFE 1402 0x064/0x065 : AudigyDrive Heaphone (l/r) 1403 0x066/0x067 : Digital Rear (l/r) 1404 0x068/0x069 : Analog Front (l/r) 1405 0x06a/0x06b : Analog Center/LFE 1406 0x06c/0x06d : ? 1407 0x06e/0x06f : Analog Rear (l/r) 1408 0x070/0x071 : AC97 Output (l/r) 1409 0x072/0x073 : ? 1410 0x074/0x075 : ? 1411 0x076/0x077 : ADC Recording Buffer (l/r) 1412 Constants 1413 0x0c0 - 0x0c4 = 0 - 4 1414 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20 1415 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000 1416 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000 1417 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff 1418 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc 1419 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (?) 1420 Temporary Values 1421 0x0d6 : Accumulator (?) 1422 0x0d7 : Condition Register 1423 0x0d8 : Noise source 1424 0x0d9 : Noise source 1425 Tank Memory Data Registers 1426 0x200 - 0x2ff 1427 Tank Memory Address Registers 1428 0x300 - 0x3ff 1429 General Purpose Registers 1430 0x400 - 0x5ff 1431 */ 1432 1433 /* AC97Output[l/r] = FXBus PCM[l/r] */ 1434 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000, 1435 A_C_00000000, A_FXBUS(FXBUS_PCM_LEFT), &pc); 1436 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000, 1437 A_C_00000000, A_FXBUS(FXBUS_PCM_RIGHT), &pc); 1438 1439 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */ 1440 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000, 1441 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_L), &pc); 1442 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000, 1443 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_R), &pc); 1444 1445 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1446 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1), 1447 A_C_40000000, A_GPR(0), &pc); 1448 1449 /* Headphones[l/r] = GPR[0/1] */ 1450 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L), 1451 A_C_00000000, A_C_00000000, A_GPR(0), &pc); 1452 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R), 1453 A_C_00000000, A_C_00000000, A_GPR(1), &pc); 1454 1455 /* Analog Front[l/r] = GPR[0/1] */ 1456 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000, 1457 A_C_00000000, A_GPR(0), &pc); 1458 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000, 1459 A_C_00000000, A_GPR(1), &pc); 1460 1461 /* Digital Front[l/r] = GPR[0/1] */ 1462 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000, 1463 A_C_00000000, A_GPR(0), &pc); 1464 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000, 1465 A_C_00000000, A_GPR(1), &pc); 1466 1467 /* Center and Subwoofer configuration */ 1468 /* Analog Center = GPR[0] + GPR[2] */ 1469 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000, 1470 A_GPR(0), A_GPR(2), &pc); 1471 /* Analog Sub = GPR[1] + GPR[2] */ 1472 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000, 1473 A_GPR(1), A_GPR(2), &pc); 1474 1475 /* Digital Center = GPR[0] + GPR[2] */ 1476 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000, 1477 A_GPR(0), A_GPR(2), &pc); 1478 /* Digital Sub = GPR[1] + GPR[2] */ 1479 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000, 1480 A_GPR(1), A_GPR(2), &pc); 1481 1482 #if 0 1483 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1484 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1485 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1486 A_GPR(16), A_GPR(0), &pc); 1487 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1488 A_GPR(17), A_GPR(1), &pc); 1489 1490 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */ 1491 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */ 1492 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1493 A_GPR(16), A_GPR(0), &pc); 1494 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1495 A_GPR(17), A_GPR(1), &pc); 1496 #else 1497 /* XXX This is just a copy to the channel, since we do not have 1498 * a patch manager, it is useful for have another output enabled. 1499 */ 1500 1501 /* Analog Rear[l/r] = GPR[0/1] */ 1502 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000, 1503 A_C_00000000, A_GPR(0), &pc); 1504 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000, 1505 A_C_00000000, A_GPR(1), &pc); 1506 1507 /* Digital Rear[l/r] = GPR[0/1] */ 1508 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000, 1509 A_C_00000000, A_GPR(0), &pc); 1510 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000, 1511 A_C_00000000, A_GPR(1), &pc); 1512 #endif 1513 1514 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1515 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000, 1516 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc); 1517 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000, 1518 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc); 1519 1520 /* resume normal operations */ 1521 emu_wrptr(sc, 0, A_DBG, 0); 1522 } 1523 1524 static void 1525 emu_initefx(struct sc_info *sc) 1526 { 1527 int i; 1528 u_int32_t pc = 16; 1529 1530 /* acc3 0,0,0,0 - NOPs */ 1531 for (i = 0; i < 512; i++) { 1532 emu_wrefx(sc, i * 2, 0x10040); 1533 emu_wrefx(sc, i * 2 + 1, 0x610040); 1534 } 1535 1536 for (i = 0; i < 256; i++) 1537 emu_wrptr(sc, 0, FXGPREGBASE + i, 0); 1538 1539 /* FX-8010 DSP Registers: 1540 FX Bus 1541 0x000-0x00f : 16 registers 1542 Input 1543 0x010/0x011 : AC97 Codec (l/r) 1544 0x012/0x013 : ADC, S/PDIF (l/r) 1545 0x014/0x015 : Mic(left), Zoom (l/r) 1546 0x016/0x017 : TOS link in (l/r) 1547 0x018/0x019 : Line/Mic 1 (l/r) 1548 0x01a/0x01b : COAX S/PDIF (l/r) 1549 0x01c/0x01d : Line/Mic 2 (l/r) 1550 Output 1551 0x020/0x021 : AC97 Output (l/r) 1552 0x022/0x023 : TOS link out (l/r) 1553 0x024/0x025 : Center/LFE 1554 0x026/0x027 : LiveDrive Headphone (l/r) 1555 0x028/0x029 : Rear Channel (l/r) 1556 0x02a/0x02b : ADC Recording Buffer (l/r) 1557 0x02c : Mic Recording Buffer 1558 0x031/0x032 : Analog Center/LFE 1559 Constants 1560 0x040 - 0x044 = 0 - 4 1561 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20 1562 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000 1563 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000 1564 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff 1565 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc 1566 0x054 = 0x5a7ef9db, 0x055 = 0x00100000 1567 Temporary Values 1568 0x056 : Accumulator 1569 0x057 : Condition Register 1570 0x058 : Noise source 1571 0x059 : Noise source 1572 0x05a : IRQ Register 1573 0x05b : TRAM Delay Base Address Count 1574 General Purpose Registers 1575 0x100 - 0x1ff 1576 Tank Memory Data Registers 1577 0x200 - 0x2ff 1578 Tank Memory Address Registers 1579 0x300 - 0x3ff 1580 */ 1581 1582 /* Routing - this will be configurable in later version */ 1583 1584 /* GPR[0/1] = FX * 4 + SPDIF-in */ 1585 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L), 1586 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc); 1587 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R), 1588 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc); 1589 1590 /* GPR[0/1] += APS-input */ 1591 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000, 1592 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc); 1593 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000, 1594 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc); 1595 1596 /* FrontOut (AC97) = GPR[0/1] */ 1597 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000, 1598 C_00000000, GPR(0), &pc); 1599 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000, 1600 C_00000001, GPR(1), &pc); 1601 1602 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */ 1603 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc); 1604 1605 #if 0 1606 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */ 1607 /* RearVolume = GPR[0x10/0x11] */ 1608 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000, 1609 GPR(16), GPR(0), &pc); 1610 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000, 1611 GPR(17), GPR(1), &pc); 1612 #else 1613 /* XXX This is just a copy to the channel, since we do not have 1614 * a patch manager, it is useful for have another output enabled. 1615 */ 1616 1617 /* Rear[l/r] = GPR[0/1] */ 1618 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000, 1619 C_00000000, GPR(0), &pc); 1620 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000, 1621 C_00000000, GPR(1), &pc); 1622 #endif 1623 1624 /* TOS out[l/r] = GPR[0/1] */ 1625 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000, 1626 C_00000000, GPR(0), &pc); 1627 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000, 1628 C_00000000, GPR(1), &pc); 1629 1630 /* Center and Subwoofer configuration */ 1631 /* Analog Center = GPR[0] + GPR[2] */ 1632 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000, 1633 GPR(0), GPR(2), &pc); 1634 /* Analog Sub = GPR[1] + GPR[2] */ 1635 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000, 1636 GPR(1), GPR(2), &pc); 1637 /* Digital Center = GPR[0] + GPR[2] */ 1638 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_CENTER), C_00000000, 1639 GPR(0), GPR(2), &pc); 1640 /* Digital Sub = GPR[1] + GPR[2] */ 1641 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_LFE), C_00000000, 1642 GPR(1), GPR(2), &pc); 1643 1644 /* Headphones[l/r] = GPR[0/1] */ 1645 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000, 1646 C_00000000, GPR(0), &pc); 1647 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000, 1648 C_00000000, GPR(1), &pc); 1649 1650 /* ADC Recording buffer[l/r] = AC97Input[l/r] */ 1651 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000, 1652 C_00000000, EXTIN(EXTIN_AC97_L), &pc); 1653 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000, 1654 C_00000000, EXTIN(EXTIN_AC97_R), &pc); 1655 1656 /* resume normal operations */ 1657 emu_wrptr(sc, 0, DBG, 0); 1658 } 1659 1660 /* Probe and attach the card */ 1661 static int 1662 emu_init(struct sc_info *sc) 1663 { 1664 u_int32_t spcs, ch, tmp, i; 1665 1666 if (sc->audigy) { 1667 /* enable additional AC97 slots */ 1668 emu_wrptr(sc, 0, AC97SLOT, AC97SLOT_CNTR | AC97SLOT_LFE); 1669 } 1670 1671 /* disable audio and lock cache */ 1672 emu_wr(sc, HCFG, 1673 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, 1674 4); 1675 1676 /* reset recording buffers */ 1677 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE); 1678 emu_wrptr(sc, 0, MICBA, 0); 1679 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE); 1680 emu_wrptr(sc, 0, FXBA, 0); 1681 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE); 1682 emu_wrptr(sc, 0, ADCBA, 0); 1683 1684 /* disable channel interrupt */ 1685 emu_wr(sc, INTE, 1686 INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE, 1687 4); 1688 emu_wrptr(sc, 0, CLIEL, 0); 1689 emu_wrptr(sc, 0, CLIEH, 0); 1690 emu_wrptr(sc, 0, SOLEL, 0); 1691 emu_wrptr(sc, 0, SOLEH, 0); 1692 1693 /* wonder what these do... */ 1694 if (sc->audigy) { 1695 emu_wrptr(sc, 0, SPBYPASS, 0xf00); 1696 emu_wrptr(sc, 0, AC97SLOT, 0x3); 1697 } 1698 1699 /* init envelope engine */ 1700 for (ch = 0; ch < NUM_G; ch++) { 1701 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF); 1702 emu_wrptr(sc, ch, IP, 0); 1703 emu_wrptr(sc, ch, VTFT, 0xffff); 1704 emu_wrptr(sc, ch, CVCF, 0xffff); 1705 emu_wrptr(sc, ch, PTRX, 0); 1706 emu_wrptr(sc, ch, CPF, 0); 1707 emu_wrptr(sc, ch, CCR, 0); 1708 1709 emu_wrptr(sc, ch, PSST, 0); 1710 emu_wrptr(sc, ch, DSL, 0x10); 1711 emu_wrptr(sc, ch, CCCA, 0); 1712 emu_wrptr(sc, ch, Z1, 0); 1713 emu_wrptr(sc, ch, Z2, 0); 1714 emu_wrptr(sc, ch, FXRT, 0xd01c0000); 1715 1716 emu_wrptr(sc, ch, ATKHLDM, 0); 1717 emu_wrptr(sc, ch, DCYSUSM, 0); 1718 emu_wrptr(sc, ch, IFATN, 0xffff); 1719 emu_wrptr(sc, ch, PEFE, 0); 1720 emu_wrptr(sc, ch, FMMOD, 0); 1721 emu_wrptr(sc, ch, TREMFRQ, 24); /* 1 Hz */ 1722 emu_wrptr(sc, ch, FM2FRQ2, 24); /* 1 Hz */ 1723 emu_wrptr(sc, ch, TEMPENV, 0); 1724 1725 /*** these are last so OFF prevents writing ***/ 1726 emu_wrptr(sc, ch, LFOVAL2, 0); 1727 emu_wrptr(sc, ch, LFOVAL1, 0); 1728 emu_wrptr(sc, ch, ATKHLDV, 0); 1729 emu_wrptr(sc, ch, ENVVOL, 0); 1730 emu_wrptr(sc, ch, ENVVAL, 0); 1731 1732 if (sc->audigy) { 1733 /* audigy cards need this to initialize correctly */ 1734 emu_wrptr(sc, ch, 0x4c, 0); 1735 emu_wrptr(sc, ch, 0x4d, 0); 1736 emu_wrptr(sc, ch, 0x4e, 0); 1737 emu_wrptr(sc, ch, 0x4f, 0); 1738 /* set default routing */ 1739 emu_wrptr(sc, ch, A_FXRT1, 0x03020100); 1740 emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f); 1741 emu_wrptr(sc, ch, A_SENDAMOUNTS, 0); 1742 } 1743 1744 sc->voice[ch].vnum = ch; 1745 sc->voice[ch].slave = NULL; 1746 sc->voice[ch].busy = 0; 1747 sc->voice[ch].ismaster = 0; 1748 sc->voice[ch].running = 0; 1749 sc->voice[ch].b16 = 0; 1750 sc->voice[ch].stereo = 0; 1751 sc->voice[ch].speed = 0; 1752 sc->voice[ch].start = 0; 1753 sc->voice[ch].end = 0; 1754 sc->voice[ch].channel = NULL; 1755 } 1756 sc->pnum = sc->rnum = 0; 1757 1758 /* 1759 * Init to 0x02109204 : 1760 * Clock accuracy = 0 (1000ppm) 1761 * Sample Rate = 2 (48kHz) 1762 * Audio Channel = 1 (Left of 2) 1763 * Source Number = 0 (Unspecified) 1764 * Generation Status = 1 (Original for Cat Code 12) 1765 * Cat Code = 12 (Digital Signal Mixer) 1766 * Mode = 0 (Mode 0) 1767 * Emphasis = 0 (None) 1768 * CP = 1 (Copyright unasserted) 1769 * AN = 0 (Audio data) 1770 * P = 0 (Consumer) 1771 */ 1772 spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 | 1773 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | 1774 SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 | 1775 SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT; 1776 emu_wrptr(sc, 0, SPCS0, spcs); 1777 emu_wrptr(sc, 0, SPCS1, spcs); 1778 emu_wrptr(sc, 0, SPCS2, spcs); 1779 1780 if (!sc->audigy) 1781 emu_initefx(sc); 1782 else if (sc->audigy2) { /* Audigy 2 */ 1783 /* from ALSA initialization code: */ 1784 1785 /* Hack for Alice3 to work independent of haP16V driver */ 1786 u_int32_t tmp; 1787 1788 /* Setup SRCMulti_I2S SamplingRate */ 1789 tmp = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE) & 0xfffff1ff; 1790 emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, tmp | 0x400); 1791 1792 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */ 1793 emu_wr(sc, 0x20, 0x00600000, 4); 1794 emu_wr(sc, 0x24, 0x00000014, 4); 1795 1796 /* Setup SRCMulti Input Audio Enable */ 1797 emu_wr(sc, 0x20, 0x006e0000, 4); 1798 emu_wr(sc, 0x24, 0xff00ff00, 4); 1799 } 1800 1801 SLIST_INIT(&sc->mem.blocks); 1802 sc->mem.ptb_pages = emu_malloc(sc, EMUMAXPAGES * sizeof(u_int32_t), 1803 &sc->mem.ptb_pages_addr); 1804 if (sc->mem.ptb_pages == NULL) 1805 return -1; 1806 1807 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE, 1808 &sc->mem.silent_page_addr); 1809 if (sc->mem.silent_page == NULL) { 1810 emu_free(sc, sc->mem.ptb_pages); 1811 return -1; 1812 } 1813 /* Clear page with silence & setup all pointers to this page */ 1814 bzero(sc->mem.silent_page, EMUPAGESIZE); 1815 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1; 1816 for (i = 0; i < EMUMAXPAGES; i++) 1817 sc->mem.ptb_pages[i] = tmp | i; 1818 1819 emu_wrptr(sc, 0, PTB, (sc->mem.ptb_pages_addr)); 1820 emu_wrptr(sc, 0, TCB, 0); /* taken from original driver */ 1821 emu_wrptr(sc, 0, TCBS, 0); /* taken from original driver */ 1822 1823 for (ch = 0; ch < NUM_G; ch++) { 1824 emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK); 1825 emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK); 1826 } 1827 1828 /* emu_memalloc(sc, EMUPAGESIZE); */ 1829 /* 1830 * Hokay, now enable the AUD bit 1831 * 1832 * Audigy 1833 * Enable Audio = 0 (enabled after fx processor initialization) 1834 * Mute Disable Audio = 0 1835 * Joystick = 1 1836 * 1837 * Audigy 2 1838 * Enable Audio = 1 1839 * Mute Disable Audio = 0 1840 * Joystick = 1 1841 * GP S/PDIF AC3 Enable = 1 1842 * CD S/PDIF AC3 Enable = 1 1843 * 1844 * EMU10K1 1845 * Enable Audio = 1 1846 * Mute Disable Audio = 0 1847 * Lock Tank Memory = 1 1848 * Lock Sound Memory = 0 1849 * Auto Mute = 1 1850 */ 1851 1852 if (sc->audigy) { 1853 tmp = HCFG_AUTOMUTE | HCFG_JOYENABLE; 1854 if (sc->audigy2) /* Audigy 2 */ 1855 tmp = HCFG_AUDIOENABLE | HCFG_AC3ENABLE_CDSPDIF | 1856 HCFG_AC3ENABLE_GPSPDIF; 1857 emu_wr(sc, HCFG, tmp, 4); 1858 1859 audigy_initefx(sc); 1860 1861 /* from ALSA initialization code: */ 1862 1863 /* enable audio and disable both audio/digital outputs */ 1864 emu_wr(sc, HCFG, emu_rd(sc, HCFG, 4) | HCFG_AUDIOENABLE, 4); 1865 emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) & ~A_IOCFG_GPOUT_AD, 1866 4); 1867 if (sc->audigy2) { /* Audigy 2 */ 1868 /* Unmute Analog. 1869 * Set GPO6 to 1 for Apollo. This has to be done after 1870 * init Alice3 I2SOut beyond 48kHz. 1871 * So, sequence is important. 1872 */ 1873 emu_wr(sc, A_IOCFG, 1874 emu_rd(sc, A_IOCFG, 4) | A_IOCFG_GPOUT_A, 4); 1875 } 1876 } else { 1877 /* EMU10K1 initialization code */ 1878 tmp = HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK 1879 | HCFG_AUTOMUTE; 1880 if (sc->rev >= 6) 1881 tmp |= HCFG_JOYENABLE; 1882 1883 emu_wr(sc, HCFG, tmp, 4); 1884 1885 /* TOSLink detection */ 1886 sc->tos_link = 0; 1887 tmp = emu_rd(sc, HCFG, 4); 1888 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) { 1889 emu_wr(sc, HCFG, tmp | HCFG_GPOUT1, 4); 1890 DELAY(50); 1891 if (tmp != (emu_rd(sc, HCFG, 4) & ~HCFG_GPOUT1)) { 1892 sc->tos_link = 1; 1893 emu_wr(sc, HCFG, tmp, 4); 1894 } 1895 } 1896 } 1897 1898 return 0; 1899 } 1900 1901 static int 1902 emu_uninit(struct sc_info *sc) 1903 { 1904 u_int32_t ch; 1905 1906 emu_wr(sc, INTE, 0, 4); 1907 for (ch = 0; ch < NUM_G; ch++) 1908 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF); 1909 for (ch = 0; ch < NUM_G; ch++) { 1910 emu_wrptr(sc, ch, VTFT, 0); 1911 emu_wrptr(sc, ch, CVCF, 0); 1912 emu_wrptr(sc, ch, PTRX, 0); 1913 emu_wrptr(sc, ch, CPF, 0); 1914 } 1915 1916 if (sc->audigy) { /* stop fx processor */ 1917 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP); 1918 } 1919 1920 /* disable audio and lock cache */ 1921 emu_wr(sc, HCFG, 1922 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, 1923 4); 1924 1925 emu_wrptr(sc, 0, PTB, 0); 1926 /* reset recording buffers */ 1927 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE); 1928 emu_wrptr(sc, 0, MICBA, 0); 1929 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE); 1930 emu_wrptr(sc, 0, FXBA, 0); 1931 emu_wrptr(sc, 0, FXWC, 0); 1932 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE); 1933 emu_wrptr(sc, 0, ADCBA, 0); 1934 emu_wrptr(sc, 0, TCB, 0); 1935 emu_wrptr(sc, 0, TCBS, 0); 1936 1937 /* disable channel interrupt */ 1938 emu_wrptr(sc, 0, CLIEL, 0); 1939 emu_wrptr(sc, 0, CLIEH, 0); 1940 emu_wrptr(sc, 0, SOLEL, 0); 1941 emu_wrptr(sc, 0, SOLEH, 0); 1942 1943 /* init envelope engine */ 1944 if (!SLIST_EMPTY(&sc->mem.blocks)) 1945 device_printf(sc->dev, "warning: memblock list not empty\n"); 1946 emu_free(sc, sc->mem.ptb_pages); 1947 emu_free(sc, sc->mem.silent_page); 1948 1949 if(sc->mpu) 1950 mpu401_uninit(sc->mpu); 1951 return 0; 1952 } 1953 1954 static int 1955 emu_pci_probe(device_t dev) 1956 { 1957 char *s = NULL; 1958 1959 switch (pci_get_devid(dev)) { 1960 case EMU10K1_PCI_ID: 1961 s = "Creative EMU10K1"; 1962 break; 1963 1964 case EMU10K2_PCI_ID: 1965 if (pci_get_revid(dev) == 0x04) 1966 s = "Creative Audigy 2 (EMU10K2)"; 1967 else 1968 s = "Creative Audigy (EMU10K2)"; 1969 break; 1970 1971 case EMU10K3_PCI_ID: 1972 s = "Creative Audigy 2 (EMU10K3)"; 1973 break; 1974 1975 default: 1976 return ENXIO; 1977 } 1978 1979 device_set_desc(dev, s); 1980 return BUS_PROBE_LOW_PRIORITY; 1981 } 1982 1983 static int 1984 emu_pci_attach(device_t dev) 1985 { 1986 struct ac97_info *codec = NULL; 1987 struct sc_info *sc; 1988 u_int32_t data; 1989 int i, gotmic; 1990 char status[SND_STATUSLEN]; 1991 1992 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 1993 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_emu10k1 softc"); 1994 sc->dev = dev; 1995 sc->type = pci_get_devid(dev); 1996 sc->rev = pci_get_revid(dev); 1997 sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID; 1998 sc->audigy2 = (sc->audigy && sc->rev == 0x04); 1999 sc->nchans = sc->audigy ? 8 : 4; 2000 sc->addrmask = sc->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK; 2001 2002 data = pci_read_config(dev, PCIR_COMMAND, 2); 2003 data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN); 2004 pci_write_config(dev, PCIR_COMMAND, data, 2); 2005 data = pci_read_config(dev, PCIR_COMMAND, 2); 2006 2007 i = PCIR_BAR(0); 2008 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE); 2009 if (sc->reg == NULL) { 2010 device_printf(dev, "unable to map register space\n"); 2011 goto bad; 2012 } 2013 sc->st = rman_get_bustag(sc->reg); 2014 sc->sh = rman_get_bushandle(sc->reg); 2015 2016 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536); 2017 2018 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 2019 /*boundary*/0, 2020 /*lowaddr*/1 << 31, /* can only access 0-2gb */ 2021 /*highaddr*/BUS_SPACE_MAXADDR, 2022 /*filter*/NULL, /*filterarg*/NULL, 2023 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 2024 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 2025 /*lockarg*/&Giant, &sc->parent_dmat) != 0) { 2026 device_printf(dev, "unable to create dma tag\n"); 2027 goto bad; 2028 } 2029 2030 if (emu_init(sc) == -1) { 2031 device_printf(dev, "unable to initialize the card\n"); 2032 goto bad; 2033 } 2034 2035 codec = AC97_CREATE(dev, sc, emu_ac97); 2036 if (codec == NULL) goto bad; 2037 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL) ? 1 : 0; 2038 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 2039 2040 emu_midiattach(sc); 2041 2042 i = 0; 2043 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, 2044 RF_ACTIVE | RF_SHAREABLE); 2045 if (!sc->irq || 2046 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) { 2047 device_printf(dev, "unable to map interrupt\n"); 2048 goto bad; 2049 } 2050 2051 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 2052 rman_get_start(sc->reg), rman_get_start(sc->irq), 2053 PCM_KLDSTRING(snd_emu10k1)); 2054 2055 if (pcm_register(dev, sc, sc->nchans, gotmic ? 3 : 2)) goto bad; 2056 for (i = 0; i < sc->nchans; i++) 2057 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc); 2058 for (i = 0; i < (gotmic ? 3 : 2); i++) 2059 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc); 2060 2061 pcm_setstatus(dev, status); 2062 2063 return 0; 2064 2065 bad: 2066 if (codec) ac97_destroy(codec); 2067 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2068 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih); 2069 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2070 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat); 2071 if (sc->lock) snd_mtxfree(sc->lock); 2072 free(sc, M_DEVBUF); 2073 return ENXIO; 2074 } 2075 2076 static int 2077 emu_pci_detach(device_t dev) 2078 { 2079 int r; 2080 struct sc_info *sc; 2081 2082 r = pcm_unregister(dev); 2083 if (r) 2084 return r; 2085 2086 sc = pcm_getdevinfo(dev); 2087 /* shutdown chip */ 2088 emu_uninit(sc); 2089 2090 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg); 2091 bus_teardown_intr(dev, sc->irq, sc->ih); 2092 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 2093 bus_dma_tag_destroy(sc->parent_dmat); 2094 snd_mtxfree(sc->lock); 2095 free(sc, M_DEVBUF); 2096 2097 return 0; 2098 } 2099 2100 /* add suspend, resume */ 2101 static device_method_t emu_methods[] = { 2102 /* Device interface */ 2103 DEVMETHOD(device_probe, emu_pci_probe), 2104 DEVMETHOD(device_attach, emu_pci_attach), 2105 DEVMETHOD(device_detach, emu_pci_detach), 2106 2107 { 0, 0 } 2108 }; 2109 2110 static driver_t emu_driver = { 2111 "pcm", 2112 emu_methods, 2113 PCM_SOFTC_SIZE, 2114 }; 2115 2116 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, 0, 0); 2117 MODULE_DEPEND(snd_emu10k1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 2118 MODULE_VERSION(snd_emu10k1, 1); 2119 MODULE_DEPEND(snd_emu10k1, midi, 1, 1, 1); 2120 2121 /* dummy driver to silence the joystick device */ 2122 static int 2123 emujoy_pci_probe(device_t dev) 2124 { 2125 char *s = NULL; 2126 2127 switch (pci_get_devid(dev)) { 2128 case 0x70021102: 2129 s = "Creative EMU10K1 Joystick"; 2130 device_quiet(dev); 2131 break; 2132 case 0x70031102: 2133 s = "Creative EMU10K2 Joystick"; 2134 device_quiet(dev); 2135 break; 2136 } 2137 2138 if (s) device_set_desc(dev, s); 2139 return s ? -1000 : ENXIO; 2140 } 2141 2142 static int 2143 emujoy_pci_attach(device_t dev) 2144 { 2145 return 0; 2146 } 2147 2148 static int 2149 emujoy_pci_detach(device_t dev) 2150 { 2151 return 0; 2152 } 2153 2154 static device_method_t emujoy_methods[] = { 2155 DEVMETHOD(device_probe, emujoy_pci_probe), 2156 DEVMETHOD(device_attach, emujoy_pci_attach), 2157 DEVMETHOD(device_detach, emujoy_pci_detach), 2158 2159 { 0, 0 } 2160 }; 2161 2162 static driver_t emujoy_driver = { 2163 "emujoy", 2164 emujoy_methods, 2165 8, 2166 }; 2167 2168 static devclass_t emujoy_devclass; 2169 2170 DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, 0, 0); 2171 2172