1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1999 Seigo Tanimura 5 * All rights reserved. 6 * 7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 43 #ifdef HAVE_KERNEL_OPTION_HEADERS 44 #include "opt_snd.h" 45 #endif 46 47 #include <dev/sound/pcm/sound.h> 48 #include <dev/sound/pci/csareg.h> 49 #include <dev/sound/pci/csavar.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <dev/sound/pci/cs461x_dsp.h> 55 56 /* This is the pci device id. */ 57 #define CS4610_PCI_ID 0x60011013 58 #define CS4614_PCI_ID 0x60031013 59 #define CS4615_PCI_ID 0x60041013 60 61 /* Here is the parameter structure per a device. */ 62 struct csa_softc { 63 device_t dev; /* device */ 64 csa_res res; /* resources */ 65 66 device_t pcm; /* pcm device */ 67 driver_intr_t* pcmintr; /* pcm intr */ 68 void *pcmintr_arg; /* pcm intr arg */ 69 device_t midi; /* midi device */ 70 driver_intr_t* midiintr; /* midi intr */ 71 void *midiintr_arg; /* midi intr arg */ 72 void *ih; /* cookie */ 73 74 struct csa_card *card; 75 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 76 }; 77 78 typedef struct csa_softc *sc_p; 79 80 static int csa_probe(device_t dev); 81 static int csa_attach(device_t dev); 82 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 83 rman_res_t start, rman_res_t end, 84 rman_res_t count, u_int flags); 85 static int csa_release_resource(device_t bus, device_t child, struct resource *r); 86 static int csa_setup_intr(device_t bus, device_t child, 87 struct resource *irq, int flags, 88 driver_filter_t *filter, 89 driver_intr_t *intr, void *arg, void **cookiep); 90 static int csa_teardown_intr(device_t bus, device_t child, 91 struct resource *irq, void *cookie); 92 static driver_intr_t csa_intr; 93 static int csa_initialize(sc_p scp); 94 static int csa_downloadimage(csa_res *resp); 95 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len); 96 97 static void 98 amp_none(void) 99 { 100 } 101 102 static void 103 amp_voyetra(void) 104 { 105 } 106 107 static int 108 clkrun_hack(int run) 109 { 110 #ifdef __i386__ 111 device_t child; 112 int port; 113 u_int16_t control; 114 bus_space_tag_t btag; 115 116 child = pci_find_device(0x8086, 0x7113); 117 if (child == NULL) 118 return (ENXIO); 119 120 port = (pci_read_config(child, 0x41, 1) << 8) + 0x10; 121 /* XXX */ 122 btag = X86_BUS_SPACE_IO; 123 124 control = bus_space_read_2(btag, 0x0, port); 125 control &= ~0x2000; 126 control |= run? 0 : 0x2000; 127 bus_space_write_2(btag, 0x0, port, control); 128 #endif 129 return (0); 130 } 131 132 static struct csa_card cards_4610[] = { 133 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 134 }; 135 136 static struct csa_card cards_4614[] = { 137 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 138 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 139 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 140 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 141 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 142 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 143 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 144 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 145 {0x153b, 0x1136, "Terratec SiXPack 5.1+", NULL, NULL, NULL, 0}, 146 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 147 }; 148 149 static struct csa_card cards_4615[] = { 150 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 151 }; 152 153 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 154 155 struct card_type { 156 u_int32_t devid; 157 char *name; 158 struct csa_card *cards; 159 }; 160 161 static struct card_type cards[] = { 162 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 163 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 164 {CS4615_PCI_ID, "CS4615", cards_4615}, 165 {0, NULL, NULL}, 166 }; 167 168 static struct card_type * 169 csa_findcard(device_t dev) 170 { 171 int i; 172 173 i = 0; 174 while (cards[i].devid != 0) { 175 if (pci_get_devid(dev) == cards[i].devid) 176 return &cards[i]; 177 i++; 178 } 179 return NULL; 180 } 181 182 struct csa_card * 183 csa_findsubcard(device_t dev) 184 { 185 int i; 186 struct card_type *card; 187 struct csa_card *subcard; 188 189 card = csa_findcard(dev); 190 if (card == NULL) 191 return &nocard; 192 subcard = card->cards; 193 i = 0; 194 while (subcard[i].subvendor != 0) { 195 if (pci_get_subvendor(dev) == subcard[i].subvendor 196 && pci_get_subdevice(dev) == subcard[i].subdevice) { 197 return &subcard[i]; 198 } 199 i++; 200 } 201 return &subcard[i]; 202 } 203 204 static int 205 csa_probe(device_t dev) 206 { 207 struct card_type *card; 208 209 card = csa_findcard(dev); 210 if (card) { 211 device_set_desc(dev, card->name); 212 return BUS_PROBE_DEFAULT; 213 } 214 return ENXIO; 215 } 216 217 static int 218 csa_attach(device_t dev) 219 { 220 sc_p scp; 221 csa_res *resp; 222 struct sndcard_func *func; 223 int error = ENXIO; 224 225 scp = device_get_softc(dev); 226 227 /* Fill in the softc. */ 228 bzero(scp, sizeof(*scp)); 229 scp->dev = dev; 230 231 pci_enable_busmaster(dev); 232 233 /* Allocate the resources. */ 234 resp = &scp->res; 235 scp->card = csa_findsubcard(dev); 236 scp->binfo.card = scp->card; 237 printf("csa: card is %s\n", scp->card->name); 238 resp->io_rid = PCIR_BAR(0); 239 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 240 &resp->io_rid, RF_ACTIVE); 241 if (resp->io == NULL) 242 return (ENXIO); 243 resp->mem_rid = PCIR_BAR(1); 244 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 245 &resp->mem_rid, RF_ACTIVE); 246 if (resp->mem == NULL) 247 goto err_io; 248 resp->irq_rid = 0; 249 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 250 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 251 if (resp->irq == NULL) 252 goto err_mem; 253 254 /* Enable interrupt. */ 255 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 256 goto err_intr; 257 #if 0 258 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 259 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 260 #endif 261 262 /* Initialize the chip. */ 263 if (csa_initialize(scp)) 264 goto err_teardown; 265 266 /* Reset the Processor. */ 267 csa_resetdsp(resp); 268 269 /* Download the Processor Image to the processor. */ 270 if (csa_downloadimage(resp)) 271 goto err_teardown; 272 273 /* Attach the children. */ 274 275 /* PCM Audio */ 276 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_WAITOK | M_ZERO); 277 func->varinfo = &scp->binfo; 278 func->func = SCF_PCM; 279 scp->pcm = device_add_child(dev, "pcm", DEVICE_UNIT_ANY); 280 device_set_ivars(scp->pcm, func); 281 282 /* Midi Interface */ 283 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_WAITOK | M_ZERO); 284 func->varinfo = &scp->binfo; 285 func->func = SCF_MIDI; 286 scp->midi = device_add_child(dev, "midi", DEVICE_UNIT_ANY); 287 device_set_ivars(scp->midi, func); 288 289 bus_attach_children(dev); 290 291 return (0); 292 293 err_teardown: 294 bus_teardown_intr(dev, resp->irq, scp->ih); 295 err_intr: 296 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 297 err_mem: 298 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 299 err_io: 300 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 301 return (error); 302 } 303 304 static void 305 csa_child_deleted(device_t dev, device_t child) 306 { 307 free(device_get_ivars(child), M_DEVBUF); 308 } 309 310 static int 311 csa_detach(device_t dev) 312 { 313 csa_res *resp; 314 sc_p scp; 315 int err; 316 317 scp = device_get_softc(dev); 318 resp = &scp->res; 319 320 err = bus_generic_detach(dev); 321 if (err != 0) 322 return err; 323 324 bus_teardown_intr(dev, resp->irq, scp->ih); 325 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 326 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 327 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 328 329 return (0); 330 } 331 332 static int 333 csa_resume(device_t dev) 334 { 335 csa_res *resp; 336 sc_p scp; 337 338 scp = device_get_softc(dev); 339 resp = &scp->res; 340 341 /* Initialize the chip. */ 342 if (csa_initialize(scp)) 343 return (ENXIO); 344 345 /* Reset the Processor. */ 346 csa_resetdsp(resp); 347 348 /* Download the Processor Image to the processor. */ 349 if (csa_downloadimage(resp)) 350 return (ENXIO); 351 352 return (bus_generic_resume(dev)); 353 } 354 355 static struct resource * 356 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 357 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 358 { 359 sc_p scp; 360 csa_res *resp; 361 struct resource *res; 362 363 scp = device_get_softc(bus); 364 resp = &scp->res; 365 switch (type) { 366 case SYS_RES_IRQ: 367 if (*rid != 0) 368 return (NULL); 369 res = resp->irq; 370 break; 371 case SYS_RES_MEMORY: 372 switch (*rid) { 373 case PCIR_BAR(0): 374 res = resp->io; 375 break; 376 case PCIR_BAR(1): 377 res = resp->mem; 378 break; 379 default: 380 return (NULL); 381 } 382 break; 383 default: 384 return (NULL); 385 } 386 387 return res; 388 } 389 390 static int 391 csa_release_resource(device_t bus, device_t child, struct resource *r) 392 { 393 return (0); 394 } 395 396 /* 397 * The following three functions deal with interrupt handling. 398 * An interrupt is primarily handled by the bridge driver. 399 * The bridge driver then determines the child devices to pass 400 * the interrupt. Certain information of the device can be read 401 * only once(eg the value of HISR). The bridge driver is responsible 402 * to pass such the information to the children. 403 */ 404 405 static int 406 csa_setup_intr(device_t bus, device_t child, 407 struct resource *irq, int flags, 408 driver_filter_t *filter, 409 driver_intr_t *intr, void *arg, void **cookiep) 410 { 411 sc_p scp; 412 csa_res *resp; 413 struct sndcard_func *func; 414 415 if (filter != NULL) { 416 printf("ata-csa.c: we cannot use a filter here\n"); 417 return (EINVAL); 418 } 419 scp = device_get_softc(bus); 420 resp = &scp->res; 421 422 /* 423 * Look at the function code of the child to determine 424 * the appropriate handler for it. 425 */ 426 func = device_get_ivars(child); 427 if (func == NULL || irq != resp->irq) 428 return (EINVAL); 429 430 switch (func->func) { 431 case SCF_PCM: 432 scp->pcmintr = intr; 433 scp->pcmintr_arg = arg; 434 break; 435 436 case SCF_MIDI: 437 scp->midiintr = intr; 438 scp->midiintr_arg = arg; 439 break; 440 441 default: 442 return (EINVAL); 443 } 444 *cookiep = scp; 445 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 446 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 447 448 return (0); 449 } 450 451 static int 452 csa_teardown_intr(device_t bus, device_t child, 453 struct resource *irq, void *cookie) 454 { 455 sc_p scp; 456 csa_res *resp; 457 struct sndcard_func *func; 458 459 scp = device_get_softc(bus); 460 resp = &scp->res; 461 462 /* 463 * Look at the function code of the child to determine 464 * the appropriate handler for it. 465 */ 466 func = device_get_ivars(child); 467 if (func == NULL || irq != resp->irq || cookie != scp) 468 return (EINVAL); 469 470 switch (func->func) { 471 case SCF_PCM: 472 scp->pcmintr = NULL; 473 scp->pcmintr_arg = NULL; 474 break; 475 476 case SCF_MIDI: 477 scp->midiintr = NULL; 478 scp->midiintr_arg = NULL; 479 break; 480 481 default: 482 return (EINVAL); 483 } 484 485 return (0); 486 } 487 488 /* The interrupt handler */ 489 static void 490 csa_intr(void *arg) 491 { 492 sc_p scp = arg; 493 csa_res *resp; 494 u_int32_t hisr; 495 496 resp = &scp->res; 497 498 /* Is this interrupt for us? */ 499 hisr = csa_readio(resp, BA0_HISR); 500 if ((hisr & 0x7fffffff) == 0) { 501 /* Throw an eoi. */ 502 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 503 return; 504 } 505 506 /* 507 * Pass the value of HISR via struct csa_bridgeinfo. 508 * The children get access through their ivars. 509 */ 510 scp->binfo.hisr = hisr; 511 512 /* Invoke the handlers of the children. */ 513 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 514 scp->pcmintr(scp->pcmintr_arg); 515 hisr &= ~(HISR_VC0 | HISR_VC1); 516 } 517 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 518 scp->midiintr(scp->midiintr_arg); 519 hisr &= ~HISR_MIDI; 520 } 521 522 /* Throw an eoi. */ 523 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 524 } 525 526 static int 527 csa_initialize(sc_p scp) 528 { 529 int i; 530 u_int32_t acsts, acisv; 531 csa_res *resp; 532 533 resp = &scp->res; 534 535 /* 536 * First, blast the clock control register to zero so that the PLL starts 537 * out in a known state, and blast the master serial port control register 538 * to zero so that the serial ports also start out in a known state. 539 */ 540 csa_writeio(resp, BA0_CLKCR1, 0); 541 csa_writeio(resp, BA0_SERMC1, 0); 542 543 /* 544 * If we are in AC97 mode, then we must set the part to a host controlled 545 * AC-link. Otherwise, we won't be able to bring up the link. 546 */ 547 #if 1 548 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 549 #else 550 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 551 #endif /* 1 */ 552 553 /* 554 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 555 * spec) and then drive it high. This is done for non AC97 modes since 556 * there might be logic external to the CS461x that uses the ARST# line 557 * for a reset. 558 */ 559 csa_writeio(resp, BA0_ACCTL, 1); 560 DELAY(50); 561 csa_writeio(resp, BA0_ACCTL, 0); 562 DELAY(50); 563 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 564 565 /* 566 * The first thing we do here is to enable sync generation. As soon 567 * as we start receiving bit clock, we'll start producing the SYNC 568 * signal. 569 */ 570 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 571 572 /* 573 * Now wait for a short while to allow the AC97 part to start 574 * generating bit clock (so we don't try to start the PLL without an 575 * input clock). 576 */ 577 DELAY(50000); 578 579 /* 580 * Set the serial port timing configuration, so that 581 * the clock control circuit gets its clock from the correct place. 582 */ 583 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 584 DELAY(700000); 585 586 /* 587 * Write the selected clock control setup to the hardware. Do not turn on 588 * SWCE yet (if requested), so that the devices clocked by the output of 589 * PLL are not clocked until the PLL is stable. 590 */ 591 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 592 csa_writeio(resp, BA0_PLLM, 0x3a); 593 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 594 595 /* 596 * Power up the PLL. 597 */ 598 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 599 600 /* 601 * Wait until the PLL has stabilized. 602 */ 603 DELAY(5000); 604 605 /* 606 * Turn on clocking of the core so that we can setup the serial ports. 607 */ 608 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 609 610 /* 611 * Fill the serial port FIFOs with silence. 612 */ 613 csa_clearserialfifos(resp); 614 615 /* 616 * Set the serial port FIFO pointer to the first sample in the FIFO. 617 */ 618 #ifdef notdef 619 csa_writeio(resp, BA0_SERBSP, 0); 620 #endif /* notdef */ 621 622 /* 623 * Write the serial port configuration to the part. The master 624 * enable bit is not set until all other values have been written. 625 */ 626 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 627 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 628 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 629 630 /* 631 * Wait for the codec ready signal from the AC97 codec. 632 */ 633 acsts = 0; 634 for (i = 0 ; i < 1000 ; i++) { 635 /* 636 * First, lets wait a short while to let things settle out a bit, 637 * and to prevent retrying the read too quickly. 638 */ 639 DELAY(125); 640 641 /* 642 * Read the AC97 status register to see if we've seen a CODEC READY 643 * signal from the AC97 codec. 644 */ 645 acsts = csa_readio(resp, BA0_ACSTS); 646 if ((acsts & ACSTS_CRDY) != 0) 647 break; 648 } 649 650 /* 651 * Make sure we sampled CODEC READY. 652 */ 653 if ((acsts & ACSTS_CRDY) == 0) 654 return (ENXIO); 655 656 /* 657 * Assert the vaid frame signal so that we can start sending commands 658 * to the AC97 codec. 659 */ 660 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 661 662 /* 663 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 664 * the codec is pumping ADC data across the AC-link. 665 */ 666 acisv = 0; 667 for (i = 0 ; i < 2000 ; i++) { 668 /* 669 * First, lets wait a short while to let things settle out a bit, 670 * and to prevent retrying the read too quickly. 671 */ 672 #ifdef notdef 673 DELAY(10000000L); /* clw */ 674 #else 675 DELAY(1000); 676 #endif /* notdef */ 677 /* 678 * Read the input slot valid register and see if input slots 3 and 679 * 4 are valid yet. 680 */ 681 acisv = csa_readio(resp, BA0_ACISV); 682 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 683 break; 684 } 685 /* 686 * Make sure we sampled valid input slots 3 and 4. If not, then return 687 * an error. 688 */ 689 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 690 return (ENXIO); 691 692 /* 693 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 694 * commense the transfer of digital audio data to the AC97 codec. 695 */ 696 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 697 698 /* 699 * Power down the DAC and ADC. We will power them up (if) when we need 700 * them. 701 */ 702 #ifdef notdef 703 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 704 #endif /* notdef */ 705 706 /* 707 * Turn off the Processor by turning off the software clock enable flag in 708 * the clock control register. 709 */ 710 #ifdef notdef 711 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 712 csa_writeio(resp, BA0_CLKCR1, clkcr1); 713 #endif /* notdef */ 714 715 /* 716 * Enable interrupts on the part. 717 */ 718 #if 0 719 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 720 #endif /* notdef */ 721 722 return (0); 723 } 724 725 void 726 csa_clearserialfifos(csa_res *resp) 727 { 728 int i, j, pwr; 729 u_int8_t clkcr1, serbst; 730 731 /* 732 * See if the devices are powered down. If so, we must power them up first 733 * or they will not respond. 734 */ 735 pwr = 1; 736 clkcr1 = csa_readio(resp, BA0_CLKCR1); 737 if ((clkcr1 & CLKCR1_SWCE) == 0) { 738 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 739 pwr = 0; 740 } 741 742 /* 743 * We want to clear out the serial port FIFOs so we don't end up playing 744 * whatever random garbage happens to be in them. We fill the sample FIFOs 745 * with zero (silence). 746 */ 747 csa_writeio(resp, BA0_SERBWP, 0); 748 749 /* Fill all 256 sample FIFO locations. */ 750 serbst = 0; 751 for (i = 0 ; i < 256 ; i++) { 752 /* Make sure the previous FIFO write operation has completed. */ 753 for (j = 0 ; j < 5 ; j++) { 754 DELAY(100); 755 serbst = csa_readio(resp, BA0_SERBST); 756 if ((serbst & SERBST_WBSY) == 0) 757 break; 758 } 759 if ((serbst & SERBST_WBSY) != 0) { 760 if (!pwr) 761 csa_writeio(resp, BA0_CLKCR1, clkcr1); 762 } 763 /* Write the serial port FIFO index. */ 764 csa_writeio(resp, BA0_SERBAD, i); 765 /* Tell the serial port to load the new value into the FIFO location. */ 766 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 767 } 768 /* 769 * Now, if we powered up the devices, then power them back down again. 770 * This is kinda ugly, but should never happen. 771 */ 772 if (!pwr) 773 csa_writeio(resp, BA0_CLKCR1, clkcr1); 774 } 775 776 void 777 csa_resetdsp(csa_res *resp) 778 { 779 int i; 780 781 /* 782 * Write the reset bit of the SP control register. 783 */ 784 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 785 786 /* 787 * Write the control register. 788 */ 789 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 790 791 /* 792 * Clear the trap registers. 793 */ 794 for (i = 0 ; i < 8 ; i++) { 795 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 796 csa_writemem(resp, BA1_TWPR, 0xffff); 797 } 798 csa_writemem(resp, BA1_DREG, 0); 799 800 /* 801 * Set the frame timer to reflect the number of cycles per frame. 802 */ 803 csa_writemem(resp, BA1_FRMT, 0xadf); 804 } 805 806 static int 807 csa_downloadimage(csa_res *resp) 808 { 809 int ret; 810 u_long ul, offset; 811 812 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 813 /* 814 * DMA this block from host memory to the appropriate 815 * memory on the CSDevice. 816 */ 817 ret = csa_transferimage(resp, 818 cs461x_firmware.BA1Array + offset, 819 cs461x_firmware.MemoryStat[ul].ulDestAddr, 820 cs461x_firmware.MemoryStat[ul].ulSourceSize); 821 if (ret) 822 return (ret); 823 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2; 824 } 825 return (0); 826 } 827 828 static int 829 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len) 830 { 831 u_long ul; 832 833 /* 834 * We do not allow DMAs from host memory to host memory (although the DMA 835 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 836 * in size (because that DMA can not do that). Return an error if either 837 * of these conditions exist. 838 */ 839 if ((len & 0x3) != 0) 840 return (EINVAL); 841 842 /* Check the destination address that it is a multiple of 4 */ 843 if ((dest & 0x3) != 0) 844 return (EINVAL); 845 846 /* Write the buffer out. */ 847 for (ul = 0 ; ul < len ; ul += 4) 848 csa_writemem(resp, dest + ul, src[ul >> 2]); 849 return (0); 850 } 851 852 int 853 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 854 { 855 int i; 856 u_int32_t acctl, acsts; 857 858 /* 859 * Make sure that there is not data sitting around from a previous 860 * uncompleted access. ACSDA = Status Data Register = 47Ch 861 */ 862 csa_readio(resp, BA0_ACSDA); 863 864 /* 865 * Setup the AC97 control registers on the CS461x to send the 866 * appropriate command to the AC97 to perform the read. 867 * ACCAD = Command Address Register = 46Ch 868 * ACCDA = Command Data Register = 470h 869 * ACCTL = Control Register = 460h 870 * set DCV - will clear when process completed 871 * set CRW - Read command 872 * set VFRM - valid frame enabled 873 * set ESYN - ASYNC generation enabled 874 * set RSTN - ARST# inactive, AC97 codec not reset 875 */ 876 877 /* 878 * Get the actual AC97 register from the offset 879 */ 880 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 881 csa_writeio(resp, BA0_ACCDA, 0); 882 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 883 884 /* 885 * Wait for the read to occur. 886 */ 887 acctl = 0; 888 for (i = 0 ; i < 10 ; i++) { 889 /* 890 * First, we want to wait for a short time. 891 */ 892 DELAY(25); 893 894 /* 895 * Now, check to see if the read has completed. 896 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 897 */ 898 acctl = csa_readio(resp, BA0_ACCTL); 899 if ((acctl & ACCTL_DCV) == 0) 900 break; 901 } 902 903 /* 904 * Make sure the read completed. 905 */ 906 if ((acctl & ACCTL_DCV) != 0) 907 return (EAGAIN); 908 909 /* 910 * Wait for the valid status bit to go active. 911 */ 912 acsts = 0; 913 for (i = 0 ; i < 10 ; i++) { 914 /* 915 * Read the AC97 status register. 916 * ACSTS = Status Register = 464h 917 */ 918 acsts = csa_readio(resp, BA0_ACSTS); 919 /* 920 * See if we have valid status. 921 * VSTS - Valid Status 922 */ 923 if ((acsts & ACSTS_VSTS) != 0) 924 break; 925 /* 926 * Wait for a short while. 927 */ 928 DELAY(25); 929 } 930 931 /* 932 * Make sure we got valid status. 933 */ 934 if ((acsts & ACSTS_VSTS) == 0) 935 return (EAGAIN); 936 937 /* 938 * Read the data returned from the AC97 register. 939 * ACSDA = Status Data Register = 474h 940 */ 941 *data = csa_readio(resp, BA0_ACSDA); 942 943 return (0); 944 } 945 946 int 947 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 948 { 949 int i; 950 u_int32_t acctl; 951 952 /* 953 * Setup the AC97 control registers on the CS461x to send the 954 * appropriate command to the AC97 to perform the write. 955 * ACCAD = Command Address Register = 46Ch 956 * ACCDA = Command Data Register = 470h 957 * ACCTL = Control Register = 460h 958 * set DCV - will clear when process completed 959 * set VFRM - valid frame enabled 960 * set ESYN - ASYNC generation enabled 961 * set RSTN - ARST# inactive, AC97 codec not reset 962 */ 963 964 /* 965 * Get the actual AC97 register from the offset 966 */ 967 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 968 csa_writeio(resp, BA0_ACCDA, data); 969 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 970 971 /* 972 * Wait for the write to occur. 973 */ 974 acctl = 0; 975 for (i = 0 ; i < 10 ; i++) { 976 /* 977 * First, we want to wait for a short time. 978 */ 979 DELAY(25); 980 981 /* 982 * Now, check to see if the read has completed. 983 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 984 */ 985 acctl = csa_readio(resp, BA0_ACCTL); 986 if ((acctl & ACCTL_DCV) == 0) 987 break; 988 } 989 990 /* 991 * Make sure the write completed. 992 */ 993 if ((acctl & ACCTL_DCV) != 0) 994 return (EAGAIN); 995 996 return (0); 997 } 998 999 u_int32_t 1000 csa_readio(csa_res *resp, u_long offset) 1001 { 1002 u_int32_t ul; 1003 1004 if (offset < BA0_AC97_RESET) 1005 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1006 else { 1007 if (csa_readcodec(resp, offset, &ul)) 1008 ul = 0; 1009 return (ul); 1010 } 1011 } 1012 1013 void 1014 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1015 { 1016 if (offset < BA0_AC97_RESET) 1017 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1018 else 1019 csa_writecodec(resp, offset, data); 1020 } 1021 1022 u_int32_t 1023 csa_readmem(csa_res *resp, u_long offset) 1024 { 1025 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1026 } 1027 1028 void 1029 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1030 { 1031 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1032 } 1033 1034 static device_method_t csa_methods[] = { 1035 /* Device interface */ 1036 DEVMETHOD(device_probe, csa_probe), 1037 DEVMETHOD(device_attach, csa_attach), 1038 DEVMETHOD(device_detach, csa_detach), 1039 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1040 DEVMETHOD(device_suspend, bus_generic_suspend), 1041 DEVMETHOD(device_resume, csa_resume), 1042 1043 /* Bus interface */ 1044 DEVMETHOD(bus_child_deleted, csa_child_deleted), 1045 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1046 DEVMETHOD(bus_release_resource, csa_release_resource), 1047 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1048 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1049 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1050 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1051 1052 DEVMETHOD_END 1053 }; 1054 1055 static driver_t csa_driver = { 1056 "csa", 1057 csa_methods, 1058 sizeof(struct csa_softc), 1059 }; 1060 1061 /* 1062 * csa can be attached to a pci bus. 1063 */ 1064 DRIVER_MODULE(snd_csa, pci, csa_driver, 0, 0); 1065 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1066 MODULE_VERSION(snd_csa, 1); 1067