1 /* 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <machine/clock.h> 42 #include <sys/rman.h> 43 #include <sys/soundcard.h> 44 #include <dev/sound/chip.h> 45 #include <dev/sound/pci/csareg.h> 46 #include <dev/sound/pci/csavar.h> 47 48 #include <pci/pcireg.h> 49 #include <pci/pcivar.h> 50 51 #include <dev/sound/pci/csaimg.h> 52 53 /* Here is the parameter structure per a device. */ 54 struct csa_softc { 55 device_t dev; /* device */ 56 csa_res res; /* resources */ 57 58 device_t pcm; /* pcm device */ 59 driver_intr_t* pcmintr; /* pcm intr */ 60 void *pcmintr_arg; /* pcm intr arg */ 61 #if notyet 62 device_t midi; /* midi device */ 63 driver_intr_t* midiintr; /* midi intr */ 64 void *midiintr_arg; /* midi intr arg */ 65 #endif /* notyet */ 66 void *ih; /* cookie */ 67 68 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 69 }; 70 71 typedef struct csa_softc *sc_p; 72 73 static int csa_probe(device_t dev); 74 static int csa_attach(device_t dev); 75 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 76 u_long start, u_long end, u_long count, u_int flags); 77 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 78 struct resource *r); 79 static int csa_setup_intr(device_t bus, device_t child, 80 struct resource *irq, int flags, 81 driver_intr_t *intr, void *arg, void **cookiep); 82 static int csa_teardown_intr(device_t bus, device_t child, 83 struct resource *irq, void *cookie); 84 static driver_intr_t csa_intr; 85 static int csa_initialize(sc_p scp); 86 static void csa_resetdsp(csa_res *resp); 87 static int csa_downloadimage(csa_res *resp); 88 static int csa_transferimage(csa_res *resp, u_long *src, u_long dest, u_long len); 89 90 static devclass_t csa_devclass; 91 92 static int 93 csa_probe(device_t dev) 94 { 95 char *s; 96 97 s = NULL; 98 switch (pci_get_devid(dev)) { 99 case CS4610_PCI_ID: 100 s = "Crystal Semiconductor CS4610/4611 Audio accelerator"; 101 break; 102 case CS4614_PCI_ID: 103 s = "Crystal Semiconductor CS4614/4622/4624 Audio accelerator/4280 Audio controller"; 104 break; 105 case CS4615_PCI_ID: 106 s = "Crystal Semiconductor CS4615 Audio accelerator"; 107 break; 108 case CS4281_PCI_ID: 109 s = "Crystal Semiconductor CS4281 Audio controller"; 110 break; 111 } 112 113 if (s != NULL) { 114 device_set_desc(dev, s); 115 return (0); 116 } 117 118 return (ENXIO); 119 } 120 121 static int 122 csa_attach(device_t dev) 123 { 124 u_int32_t stcmd; 125 sc_p scp; 126 csa_res *resp; 127 struct sndcard_func *func; 128 129 scp = device_get_softc(dev); 130 131 /* Fill in the softc. */ 132 bzero(scp, sizeof(*scp)); 133 scp->dev = dev; 134 135 /* Wake up the device. */ 136 stcmd = pci_read_config(dev, PCIR_COMMAND, 4); 137 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 138 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 139 pci_write_config(dev, PCIR_COMMAND, 4, stcmd); 140 } 141 142 /* Allocate the resources. */ 143 resp = &scp->res; 144 resp->io_rid = CS461x_IO_OFFSET; 145 resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, CS461x_IO_SIZE, RF_ACTIVE); 146 if (resp->io == NULL) 147 return (ENXIO); 148 resp->mem_rid = CS461x_MEM_OFFSET; 149 resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, CS461x_MEM_SIZE, RF_ACTIVE); 150 if (resp->mem == NULL) { 151 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 152 return (ENXIO); 153 } 154 resp->irq_rid = 0; 155 resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 156 if (resp->irq == NULL) { 157 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 158 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 159 return (ENXIO); 160 } 161 162 /* Enable interrupt. */ 163 if (bus_setup_intr(dev, resp->irq, INTR_TYPE_TTY, csa_intr, scp, &scp->ih)) { 164 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 165 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 166 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 167 return (ENXIO); 168 } 169 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 170 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 171 172 /* Initialize the chip. */ 173 if (csa_initialize(scp)) { 174 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 175 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 176 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 177 return (ENXIO); 178 } 179 180 /* Reset the Processor. */ 181 csa_resetdsp(resp); 182 183 /* Download the Processor Image to the processor. */ 184 if (csa_downloadimage(resp)) { 185 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 186 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 187 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 188 return (ENXIO); 189 } 190 191 /* Attach the children. */ 192 193 /* PCM Audio */ 194 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT); 195 if (func == NULL) 196 return (ENOMEM); 197 bzero(func, sizeof(*func)); 198 func->varinfo = &scp->binfo; 199 func->func = SCF_PCM; 200 scp->pcm = device_add_child(dev, "pcm", -1); 201 device_set_ivars(scp->pcm, func); 202 203 #if notyet 204 /* Midi Interface */ 205 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT); 206 if (func == NULL) 207 return (ENOMEM); 208 bzero(func, sizeof(*func)); 209 func->varinfo = &scp->binfo; 210 func->func = SCF_MIDI; 211 scp->midi = device_add_child(dev, "midi", -1); 212 device_set_ivars(scp->midi, func); 213 #endif /* notyet */ 214 215 bus_generic_attach(dev); 216 217 return (0); 218 } 219 220 static struct resource * 221 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 222 u_long start, u_long end, u_long count, u_int flags) 223 { 224 sc_p scp; 225 csa_res *resp; 226 struct resource *res; 227 228 scp = device_get_softc(bus); 229 resp = &scp->res; 230 switch (type) { 231 case SYS_RES_IRQ: 232 if (*rid != 0) 233 return (NULL); 234 res = resp->irq; 235 break; 236 case SYS_RES_MEMORY: 237 switch (*rid) { 238 case CS461x_IO_OFFSET: 239 res = resp->io; 240 break; 241 case CS461x_MEM_OFFSET: 242 res = resp->mem; 243 break; 244 default: 245 return (NULL); 246 } 247 break; 248 default: 249 return (NULL); 250 } 251 252 return res; 253 } 254 255 static int 256 csa_release_resource(device_t bus, device_t child, int type, int rid, 257 struct resource *r) 258 { 259 return (0); 260 } 261 262 /* 263 * The following three functions deal with interrupt handling. 264 * An interrupt is primarily handled by the bridge driver. 265 * The bridge driver then determines the child devices to pass 266 * the interrupt. Certain information of the device can be read 267 * only once(eg the value of HISR). The bridge driver is responsible 268 * to pass such the information to the children. 269 */ 270 271 static int 272 csa_setup_intr(device_t bus, device_t child, 273 struct resource *irq, int flags, 274 driver_intr_t *intr, void *arg, void **cookiep) 275 { 276 sc_p scp; 277 csa_res *resp; 278 struct sndcard_func *func; 279 280 scp = device_get_softc(bus); 281 resp = &scp->res; 282 283 /* 284 * Look at the function code of the child to determine 285 * the appropriate hander for it. 286 */ 287 func = device_get_ivars(child); 288 if (func == NULL || irq != resp->irq) 289 return (EINVAL); 290 291 switch (func->func) { 292 case SCF_PCM: 293 scp->pcmintr = intr; 294 scp->pcmintr_arg = arg; 295 break; 296 297 #if notyet 298 case SCF_MIDI: 299 scp->midiintr = intr; 300 scp->midiintr_arg = arg; 301 break; 302 #endif /* notyet */ 303 304 default: 305 return (EINVAL); 306 } 307 *cookiep = scp; 308 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 309 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 310 311 return (0); 312 } 313 314 static int 315 csa_teardown_intr(device_t bus, device_t child, 316 struct resource *irq, void *cookie) 317 { 318 sc_p scp; 319 csa_res *resp; 320 struct sndcard_func *func; 321 322 scp = device_get_softc(bus); 323 resp = &scp->res; 324 325 /* 326 * Look at the function code of the child to determine 327 * the appropriate hander for it. 328 */ 329 func = device_get_ivars(child); 330 if (func == NULL || irq != resp->irq || cookie != scp) 331 return (EINVAL); 332 333 switch (func->func) { 334 case SCF_PCM: 335 scp->pcmintr = NULL; 336 scp->pcmintr_arg = NULL; 337 break; 338 339 #if notyet 340 case SCF_MIDI: 341 scp->midiintr = NULL; 342 scp->midiintr_arg = NULL; 343 break; 344 #endif /* notyet */ 345 346 default: 347 return (EINVAL); 348 } 349 350 return (0); 351 } 352 353 /* The interrupt handler */ 354 static void 355 csa_intr(void *arg) 356 { 357 sc_p scp = arg; 358 csa_res *resp; 359 u_int32_t hisr; 360 361 resp = &scp->res; 362 363 /* Is this interrupt for us? */ 364 hisr = csa_readio(resp, BA0_HISR); 365 if ((hisr & ~HISR_INTENA) == 0) { 366 /* Throw an eoi. */ 367 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 368 return; 369 } 370 371 /* 372 * Pass the value of HISR via struct csa_bridgeinfo. 373 * The children get access through their ivars. 374 */ 375 scp->binfo.hisr = hisr; 376 377 /* Invoke the handlers of the children. */ 378 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) 379 scp->pcmintr(scp->pcmintr_arg); 380 #if notyet 381 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) 382 scp->midiintr(scp->midiintr_arg); 383 #endif /* notyet */ 384 385 /* Throw an eoi. */ 386 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 387 } 388 389 static int 390 csa_initialize(sc_p scp) 391 { 392 int i; 393 u_int32_t acsts, acisv; 394 csa_res *resp; 395 396 resp = &scp->res; 397 398 /* 399 * First, blast the clock control register to zero so that the PLL starts 400 * out in a known state, and blast the master serial port control register 401 * to zero so that the serial ports also start out in a known state. 402 */ 403 csa_writeio(resp, BA0_CLKCR1, 0); 404 csa_writeio(resp, BA0_SERMC1, 0); 405 406 /* 407 * If we are in AC97 mode, then we must set the part to a host controlled 408 * AC-link. Otherwise, we won't be able to bring up the link. 409 */ 410 #if 1 411 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 412 #else 413 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 414 #endif /* 1 */ 415 416 /* 417 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 418 * spec) and then drive it high. This is done for non AC97 modes since 419 * there might be logic external to the CS461x that uses the ARST# line 420 * for a reset. 421 */ 422 csa_writeio(resp, BA0_ACCTL, 0); 423 DELAY(100); 424 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 425 426 /* 427 * The first thing we do here is to enable sync generation. As soon 428 * as we start receiving bit clock, we'll start producing the SYNC 429 * signal. 430 */ 431 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 432 433 /* 434 * Now wait for a short while to allow the AC97 part to start 435 * generating bit clock (so we don't try to start the PLL without an 436 * input clock). 437 */ 438 DELAY(50000); 439 440 /* 441 * Set the serial port timing configuration, so that 442 * the clock control circuit gets its clock from the correct place. 443 */ 444 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 445 446 /* 447 * Write the selected clock control setup to the hardware. Do not turn on 448 * SWCE yet (if requested), so that the devices clocked by the output of 449 * PLL are not clocked until the PLL is stable. 450 */ 451 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 452 csa_writeio(resp, BA0_PLLM, 0x3a); 453 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 454 455 /* 456 * Power up the PLL. 457 */ 458 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 459 460 /* 461 * Wait until the PLL has stabilized. 462 */ 463 DELAY(50000); 464 465 /* 466 * Turn on clocking of the core so that we can setup the serial ports. 467 */ 468 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 469 470 /* 471 * Fill the serial port FIFOs with silence. 472 */ 473 csa_clearserialfifos(resp); 474 475 /* 476 * Set the serial port FIFO pointer to the first sample in the FIFO. 477 */ 478 #if notdef 479 csa_writeio(resp, BA0_SERBSP, 0); 480 #endif /* notdef */ 481 482 /* 483 * Write the serial port configuration to the part. The master 484 * enable bit is not set until all other values have been written. 485 */ 486 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 487 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 488 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 489 490 /* 491 * Wait for the codec ready signal from the AC97 codec. 492 */ 493 acsts = 0; 494 for (i = 0 ; i < 1000 ; i++) { 495 /* 496 * First, lets wait a short while to let things settle out a bit, 497 * and to prevent retrying the read too quickly. 498 */ 499 DELAY(125); 500 501 /* 502 * Read the AC97 status register to see if we've seen a CODEC READY 503 * signal from the AC97 codec. 504 */ 505 acsts = csa_readio(resp, BA0_ACSTS); 506 if ((acsts & ACSTS_CRDY) != 0) 507 break; 508 } 509 510 /* 511 * Make sure we sampled CODEC READY. 512 */ 513 if ((acsts & ACSTS_CRDY) == 0) 514 return (ENXIO); 515 516 /* 517 * Assert the vaid frame signal so that we can start sending commands 518 * to the AC97 codec. 519 */ 520 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 521 522 /* 523 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 524 * the codec is pumping ADC data across the AC-link. 525 */ 526 acisv = 0; 527 for (i = 0 ; i < 1000 ; i++) { 528 /* 529 * First, lets wait a short while to let things settle out a bit, 530 * and to prevent retrying the read too quickly. 531 */ 532 #if notdef 533 DELAY(10000000L); /* clw */ 534 #else 535 DELAY(1000); 536 #endif /* notdef */ 537 /* 538 * Read the input slot valid register and see if input slots 3 and 539 * 4 are valid yet. 540 */ 541 acisv = csa_readio(resp, BA0_ACISV); 542 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 543 break; 544 } 545 /* 546 * Make sure we sampled valid input slots 3 and 4. If not, then return 547 * an error. 548 */ 549 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 550 return (ENXIO); 551 552 /* 553 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 554 * commense the transfer of digital audio data to the AC97 codec. 555 */ 556 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 557 558 /* 559 * Power down the DAC and ADC. We will power them up (if) when we need 560 * them. 561 */ 562 #if notdef 563 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 564 #endif /* notdef */ 565 566 /* 567 * Turn off the Processor by turning off the software clock enable flag in 568 * the clock control register. 569 */ 570 #if notdef 571 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 572 csa_writeio(resp, BA0_CLKCR1, clkcr1); 573 #endif /* notdef */ 574 575 /* 576 * Enable interrupts on the part. 577 */ 578 #if notdef 579 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 580 #endif /* notdef */ 581 582 return (0); 583 } 584 585 void 586 csa_clearserialfifos(csa_res *resp) 587 { 588 int i, j, pwr; 589 u_int8_t clkcr1, serbst; 590 591 /* 592 * See if the devices are powered down. If so, we must power them up first 593 * or they will not respond. 594 */ 595 pwr = 1; 596 clkcr1 = csa_readio(resp, BA0_CLKCR1); 597 if ((clkcr1 & CLKCR1_SWCE) == 0) { 598 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 599 pwr = 0; 600 } 601 602 /* 603 * We want to clear out the serial port FIFOs so we don't end up playing 604 * whatever random garbage happens to be in them. We fill the sample FIFOs 605 * with zero (silence). 606 */ 607 csa_writeio(resp, BA0_SERBWP, 0); 608 609 /* Fill all 256 sample FIFO locations. */ 610 serbst = 0; 611 for (i = 0 ; i < 256 ; i++) { 612 /* Make sure the previous FIFO write operation has completed. */ 613 for (j = 0 ; j < 5 ; j++) { 614 DELAY(100); 615 serbst = csa_readio(resp, BA0_SERBST); 616 if ((serbst & SERBST_WBSY) == 0) 617 break; 618 } 619 if ((serbst & SERBST_WBSY) != 0) { 620 if (!pwr) 621 csa_writeio(resp, BA0_CLKCR1, clkcr1); 622 } 623 /* Write the serial port FIFO index. */ 624 csa_writeio(resp, BA0_SERBAD, i); 625 /* Tell the serial port to load the new value into the FIFO location. */ 626 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 627 } 628 /* 629 * Now, if we powered up the devices, then power them back down again. 630 * This is kinda ugly, but should never happen. 631 */ 632 if (!pwr) 633 csa_writeio(resp, BA0_CLKCR1, clkcr1); 634 } 635 636 static void 637 csa_resetdsp(csa_res *resp) 638 { 639 int i; 640 641 /* 642 * Write the reset bit of the SP control register. 643 */ 644 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 645 646 /* 647 * Write the control register. 648 */ 649 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 650 651 /* 652 * Clear the trap registers. 653 */ 654 for (i = 0 ; i < 8 ; i++) { 655 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 656 csa_writemem(resp, BA1_TWPR, 0xffff); 657 } 658 csa_writemem(resp, BA1_DREG, 0); 659 660 /* 661 * Set the frame timer to reflect the number of cycles per frame. 662 */ 663 csa_writemem(resp, BA1_FRMT, 0xadf); 664 } 665 666 static int 667 csa_downloadimage(csa_res *resp) 668 { 669 int ret; 670 u_long ul, offset; 671 672 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 673 /* 674 * DMA this block from host memory to the appropriate 675 * memory on the CSDevice. 676 */ 677 ret = csa_transferimage( 678 resp, 679 BA1Struct.BA1Array + offset, 680 BA1Struct.MemoryStat[ul].ulDestByteOffset, 681 BA1Struct.MemoryStat[ul].ulSourceByteSize); 682 if (ret) 683 return (ret); 684 offset += BA1Struct.MemoryStat[ul].ulSourceByteSize >> 2; 685 } 686 687 return (0); 688 } 689 690 static int 691 csa_transferimage(csa_res *resp, u_long *src, u_long dest, u_long len) 692 { 693 u_long ul; 694 695 /* 696 * We do not allow DMAs from host memory to host memory (although the DMA 697 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 698 * in size (because that DMA can not do that). Return an error if either 699 * of these conditions exist. 700 */ 701 if ((len & 0x3) != 0) 702 return (EINVAL); 703 704 /* Check the destination address that it is a multiple of 4 */ 705 if ((dest & 0x3) != 0) 706 return (EINVAL); 707 708 /* Write the buffer out. */ 709 for (ul = 0 ; ul < len ; ul += 4) 710 csa_writemem(resp, dest + ul, src[ul >> 2]); 711 712 return (0); 713 } 714 715 int 716 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 717 { 718 int i; 719 u_int32_t acsda, acctl, acsts; 720 721 /* 722 * Make sure that there is not data sitting around from a previous 723 * uncompleted access. ACSDA = Status Data Register = 47Ch 724 */ 725 acsda = csa_readio(resp, BA0_ACSDA); 726 727 /* 728 * Setup the AC97 control registers on the CS461x to send the 729 * appropriate command to the AC97 to perform the read. 730 * ACCAD = Command Address Register = 46Ch 731 * ACCDA = Command Data Register = 470h 732 * ACCTL = Control Register = 460h 733 * set DCV - will clear when process completed 734 * set CRW - Read command 735 * set VFRM - valid frame enabled 736 * set ESYN - ASYNC generation enabled 737 * set RSTN - ARST# inactive, AC97 codec not reset 738 */ 739 740 /* 741 * Get the actual AC97 register from the offset 742 */ 743 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 744 csa_writeio(resp, BA0_ACCDA, 0); 745 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 746 747 /* 748 * Wait for the read to occur. 749 */ 750 acctl = 0; 751 for (i = 0 ; i < 10 ; i++) { 752 /* 753 * First, we want to wait for a short time. 754 */ 755 DELAY(25); 756 757 /* 758 * Now, check to see if the read has completed. 759 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 760 */ 761 acctl = csa_readio(resp, BA0_ACCTL); 762 if ((acctl & ACCTL_DCV) == 0) 763 break; 764 } 765 766 /* 767 * Make sure the read completed. 768 */ 769 if ((acctl & ACCTL_DCV) != 0) 770 return (EAGAIN); 771 772 /* 773 * Wait for the valid status bit to go active. 774 */ 775 acsts = 0; 776 for (i = 0 ; i < 10 ; i++) { 777 /* 778 * Read the AC97 status register. 779 * ACSTS = Status Register = 464h 780 */ 781 acsts = csa_readio(resp, BA0_ACSTS); 782 /* 783 * See if we have valid status. 784 * VSTS - Valid Status 785 */ 786 if ((acsts & ACSTS_VSTS) != 0) 787 break; 788 /* 789 * Wait for a short while. 790 */ 791 DELAY(25); 792 } 793 794 /* 795 * Make sure we got valid status. 796 */ 797 if ((acsts & ACSTS_VSTS) == 0) 798 return (EAGAIN); 799 800 /* 801 * Read the data returned from the AC97 register. 802 * ACSDA = Status Data Register = 474h 803 */ 804 *data = csa_readio(resp, BA0_ACSDA); 805 806 return (0); 807 } 808 809 int 810 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 811 { 812 int i; 813 u_int32_t acctl; 814 815 /* 816 * Setup the AC97 control registers on the CS461x to send the 817 * appropriate command to the AC97 to perform the write. 818 * ACCAD = Command Address Register = 46Ch 819 * ACCDA = Command Data Register = 470h 820 * ACCTL = Control Register = 460h 821 * set DCV - will clear when process completed 822 * set VFRM - valid frame enabled 823 * set ESYN - ASYNC generation enabled 824 * set RSTN - ARST# inactive, AC97 codec not reset 825 */ 826 827 /* 828 * Get the actual AC97 register from the offset 829 */ 830 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 831 csa_writeio(resp, BA0_ACCDA, data); 832 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 833 834 /* 835 * Wait for the write to occur. 836 */ 837 acctl = 0; 838 for (i = 0 ; i < 10 ; i++) { 839 /* 840 * First, we want to wait for a short time. 841 */ 842 DELAY(25); 843 844 /* 845 * Now, check to see if the read has completed. 846 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 847 */ 848 acctl = csa_readio(resp, BA0_ACCTL); 849 if ((acctl & ACCTL_DCV) == 0) 850 break; 851 } 852 853 /* 854 * Make sure the write completed. 855 */ 856 if ((acctl & ACCTL_DCV) != 0) 857 return (EAGAIN); 858 859 return (0); 860 } 861 862 u_int32_t 863 csa_readio(csa_res *resp, u_long offset) 864 { 865 u_int32_t ul; 866 867 if (offset < BA0_AC97_RESET) 868 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 869 else { 870 if (csa_readcodec(resp, offset, &ul)) 871 ul = 0; 872 return (ul); 873 } 874 } 875 876 void 877 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 878 { 879 if (offset < BA0_AC97_RESET) 880 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 881 else 882 csa_writecodec(resp, offset, data); 883 } 884 885 u_int32_t 886 csa_readmem(csa_res *resp, u_long offset) 887 { 888 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset) & 0xffffffff; 889 } 890 891 void 892 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 893 { 894 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 895 } 896 897 static device_method_t csa_methods[] = { 898 /* Device interface */ 899 DEVMETHOD(device_probe, csa_probe), 900 DEVMETHOD(device_attach, csa_attach), 901 DEVMETHOD(device_detach, bus_generic_detach), 902 DEVMETHOD(device_shutdown, bus_generic_shutdown), 903 DEVMETHOD(device_suspend, bus_generic_suspend), 904 DEVMETHOD(device_resume, bus_generic_resume), 905 906 /* Bus interface */ 907 DEVMETHOD(bus_print_child, bus_generic_print_child), 908 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 909 DEVMETHOD(bus_release_resource, csa_release_resource), 910 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 911 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 912 DEVMETHOD(bus_setup_intr, csa_setup_intr), 913 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 914 915 { 0, 0 } 916 }; 917 918 static driver_t csa_driver = { 919 "csa", 920 csa_methods, 921 sizeof(struct csa_softc), 922 }; 923 924 /* 925 * csa can be attached to a pci bus. 926 */ 927 DRIVER_MODULE(csa, pci, csa_driver, csa_devclass, 0, 0); 928