1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1999 Seigo Tanimura 5 * All rights reserved. 6 * 7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 43 #ifdef HAVE_KERNEL_OPTION_HEADERS 44 #include "opt_snd.h" 45 #endif 46 47 #include <dev/sound/pcm/sound.h> 48 #include <dev/sound/pci/csareg.h> 49 #include <dev/sound/pci/csavar.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <dev/sound/pci/cs461x_dsp.h> 55 56 /* This is the pci device id. */ 57 #define CS4610_PCI_ID 0x60011013 58 #define CS4614_PCI_ID 0x60031013 59 #define CS4615_PCI_ID 0x60041013 60 61 /* Here is the parameter structure per a device. */ 62 struct csa_softc { 63 device_t dev; /* device */ 64 csa_res res; /* resources */ 65 66 device_t pcm; /* pcm device */ 67 driver_intr_t* pcmintr; /* pcm intr */ 68 void *pcmintr_arg; /* pcm intr arg */ 69 device_t midi; /* midi device */ 70 driver_intr_t* midiintr; /* midi intr */ 71 void *midiintr_arg; /* midi intr arg */ 72 void *ih; /* cookie */ 73 74 struct csa_card *card; 75 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 76 }; 77 78 typedef struct csa_softc *sc_p; 79 80 static int csa_probe(device_t dev); 81 static int csa_attach(device_t dev); 82 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 83 rman_res_t start, rman_res_t end, 84 rman_res_t count, u_int flags); 85 static int csa_release_resource(device_t bus, device_t child, struct resource *r); 86 static int csa_setup_intr(device_t bus, device_t child, 87 struct resource *irq, int flags, 88 driver_filter_t *filter, 89 driver_intr_t *intr, void *arg, void **cookiep); 90 static int csa_teardown_intr(device_t bus, device_t child, 91 struct resource *irq, void *cookie); 92 static driver_intr_t csa_intr; 93 static int csa_initialize(sc_p scp); 94 static int csa_downloadimage(csa_res *resp); 95 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len); 96 97 static void 98 amp_none(void) 99 { 100 } 101 102 static void 103 amp_voyetra(void) 104 { 105 } 106 107 static int 108 clkrun_hack(int run) 109 { 110 #ifdef __i386__ 111 device_t child; 112 int port; 113 u_int16_t control; 114 bus_space_tag_t btag; 115 116 child = pci_find_device(0x8086, 0x7113); 117 if (child == NULL) 118 return (ENXIO); 119 120 port = (pci_read_config(child, 0x41, 1) << 8) + 0x10; 121 /* XXX */ 122 btag = X86_BUS_SPACE_IO; 123 124 control = bus_space_read_2(btag, 0x0, port); 125 control &= ~0x2000; 126 control |= run? 0 : 0x2000; 127 bus_space_write_2(btag, 0x0, port, control); 128 #endif 129 return (0); 130 } 131 132 static struct csa_card cards_4610[] = { 133 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 134 }; 135 136 static struct csa_card cards_4614[] = { 137 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 138 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 139 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 140 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 141 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 142 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 143 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 144 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 145 {0x153b, 0x1136, "Terratec SiXPack 5.1+", NULL, NULL, NULL, 0}, 146 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 147 }; 148 149 static struct csa_card cards_4615[] = { 150 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 151 }; 152 153 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 154 155 struct card_type { 156 u_int32_t devid; 157 char *name; 158 struct csa_card *cards; 159 }; 160 161 static struct card_type cards[] = { 162 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 163 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 164 {CS4615_PCI_ID, "CS4615", cards_4615}, 165 {0, NULL, NULL}, 166 }; 167 168 static struct card_type * 169 csa_findcard(device_t dev) 170 { 171 int i; 172 173 i = 0; 174 while (cards[i].devid != 0) { 175 if (pci_get_devid(dev) == cards[i].devid) 176 return &cards[i]; 177 i++; 178 } 179 return NULL; 180 } 181 182 struct csa_card * 183 csa_findsubcard(device_t dev) 184 { 185 int i; 186 struct card_type *card; 187 struct csa_card *subcard; 188 189 card = csa_findcard(dev); 190 if (card == NULL) 191 return &nocard; 192 subcard = card->cards; 193 i = 0; 194 while (subcard[i].subvendor != 0) { 195 if (pci_get_subvendor(dev) == subcard[i].subvendor 196 && pci_get_subdevice(dev) == subcard[i].subdevice) { 197 return &subcard[i]; 198 } 199 i++; 200 } 201 return &subcard[i]; 202 } 203 204 static int 205 csa_probe(device_t dev) 206 { 207 struct card_type *card; 208 209 card = csa_findcard(dev); 210 if (card) { 211 device_set_desc(dev, card->name); 212 return BUS_PROBE_DEFAULT; 213 } 214 return ENXIO; 215 } 216 217 static int 218 csa_attach(device_t dev) 219 { 220 sc_p scp; 221 csa_res *resp; 222 struct sndcard_func *func; 223 int error = ENXIO; 224 225 scp = device_get_softc(dev); 226 227 /* Fill in the softc. */ 228 bzero(scp, sizeof(*scp)); 229 scp->dev = dev; 230 231 pci_enable_busmaster(dev); 232 233 /* Allocate the resources. */ 234 resp = &scp->res; 235 scp->card = csa_findsubcard(dev); 236 scp->binfo.card = scp->card; 237 printf("csa: card is %s\n", scp->card->name); 238 resp->io_rid = PCIR_BAR(0); 239 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 240 &resp->io_rid, RF_ACTIVE); 241 if (resp->io == NULL) 242 return (ENXIO); 243 resp->mem_rid = PCIR_BAR(1); 244 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 245 &resp->mem_rid, RF_ACTIVE); 246 if (resp->mem == NULL) 247 goto err_io; 248 resp->irq_rid = 0; 249 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 250 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 251 if (resp->irq == NULL) 252 goto err_mem; 253 254 /* Enable interrupt. */ 255 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 256 goto err_intr; 257 #if 0 258 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 259 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 260 #endif 261 262 /* Initialize the chip. */ 263 if (csa_initialize(scp)) 264 goto err_teardown; 265 266 /* Reset the Processor. */ 267 csa_resetdsp(resp); 268 269 /* Download the Processor Image to the processor. */ 270 if (csa_downloadimage(resp)) 271 goto err_teardown; 272 273 /* Attach the children. */ 274 275 /* PCM Audio */ 276 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_WAITOK | M_ZERO); 277 func->varinfo = &scp->binfo; 278 func->func = SCF_PCM; 279 scp->pcm = device_add_child(dev, "pcm", DEVICE_UNIT_ANY); 280 device_set_ivars(scp->pcm, func); 281 282 /* Midi Interface */ 283 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_WAITOK | M_ZERO); 284 func->varinfo = &scp->binfo; 285 func->func = SCF_MIDI; 286 scp->midi = device_add_child(dev, "midi", DEVICE_UNIT_ANY); 287 device_set_ivars(scp->midi, func); 288 289 bus_generic_attach(dev); 290 291 return (0); 292 293 err_teardown: 294 bus_teardown_intr(dev, resp->irq, scp->ih); 295 err_intr: 296 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 297 err_mem: 298 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 299 err_io: 300 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 301 return (error); 302 } 303 304 static void 305 csa_child_deleted(device_t dev, device_t child) 306 { 307 free(device_get_ivars(child), M_DEVBUF); 308 } 309 310 static int 311 csa_detach(device_t dev) 312 { 313 csa_res *resp; 314 sc_p scp; 315 int err; 316 317 scp = device_get_softc(dev); 318 resp = &scp->res; 319 320 if (scp->midi != NULL) { 321 err = device_delete_child(dev, scp->midi); 322 if (err != 0) 323 return err; 324 scp->midi = NULL; 325 } 326 327 if (scp->pcm != NULL) { 328 err = device_delete_child(dev, scp->pcm); 329 if (err != 0) 330 return err; 331 scp->pcm = NULL; 332 } 333 334 bus_teardown_intr(dev, resp->irq, scp->ih); 335 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 336 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 337 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 338 339 return bus_generic_detach(dev); 340 } 341 342 static int 343 csa_resume(device_t dev) 344 { 345 csa_res *resp; 346 sc_p scp; 347 348 scp = device_get_softc(dev); 349 resp = &scp->res; 350 351 /* Initialize the chip. */ 352 if (csa_initialize(scp)) 353 return (ENXIO); 354 355 /* Reset the Processor. */ 356 csa_resetdsp(resp); 357 358 /* Download the Processor Image to the processor. */ 359 if (csa_downloadimage(resp)) 360 return (ENXIO); 361 362 return (bus_generic_resume(dev)); 363 } 364 365 static struct resource * 366 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 367 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 368 { 369 sc_p scp; 370 csa_res *resp; 371 struct resource *res; 372 373 scp = device_get_softc(bus); 374 resp = &scp->res; 375 switch (type) { 376 case SYS_RES_IRQ: 377 if (*rid != 0) 378 return (NULL); 379 res = resp->irq; 380 break; 381 case SYS_RES_MEMORY: 382 switch (*rid) { 383 case PCIR_BAR(0): 384 res = resp->io; 385 break; 386 case PCIR_BAR(1): 387 res = resp->mem; 388 break; 389 default: 390 return (NULL); 391 } 392 break; 393 default: 394 return (NULL); 395 } 396 397 return res; 398 } 399 400 static int 401 csa_release_resource(device_t bus, device_t child, struct resource *r) 402 { 403 return (0); 404 } 405 406 /* 407 * The following three functions deal with interrupt handling. 408 * An interrupt is primarily handled by the bridge driver. 409 * The bridge driver then determines the child devices to pass 410 * the interrupt. Certain information of the device can be read 411 * only once(eg the value of HISR). The bridge driver is responsible 412 * to pass such the information to the children. 413 */ 414 415 static int 416 csa_setup_intr(device_t bus, device_t child, 417 struct resource *irq, int flags, 418 driver_filter_t *filter, 419 driver_intr_t *intr, void *arg, void **cookiep) 420 { 421 sc_p scp; 422 csa_res *resp; 423 struct sndcard_func *func; 424 425 if (filter != NULL) { 426 printf("ata-csa.c: we cannot use a filter here\n"); 427 return (EINVAL); 428 } 429 scp = device_get_softc(bus); 430 resp = &scp->res; 431 432 /* 433 * Look at the function code of the child to determine 434 * the appropriate handler for it. 435 */ 436 func = device_get_ivars(child); 437 if (func == NULL || irq != resp->irq) 438 return (EINVAL); 439 440 switch (func->func) { 441 case SCF_PCM: 442 scp->pcmintr = intr; 443 scp->pcmintr_arg = arg; 444 break; 445 446 case SCF_MIDI: 447 scp->midiintr = intr; 448 scp->midiintr_arg = arg; 449 break; 450 451 default: 452 return (EINVAL); 453 } 454 *cookiep = scp; 455 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 456 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 457 458 return (0); 459 } 460 461 static int 462 csa_teardown_intr(device_t bus, device_t child, 463 struct resource *irq, void *cookie) 464 { 465 sc_p scp; 466 csa_res *resp; 467 struct sndcard_func *func; 468 469 scp = device_get_softc(bus); 470 resp = &scp->res; 471 472 /* 473 * Look at the function code of the child to determine 474 * the appropriate handler for it. 475 */ 476 func = device_get_ivars(child); 477 if (func == NULL || irq != resp->irq || cookie != scp) 478 return (EINVAL); 479 480 switch (func->func) { 481 case SCF_PCM: 482 scp->pcmintr = NULL; 483 scp->pcmintr_arg = NULL; 484 break; 485 486 case SCF_MIDI: 487 scp->midiintr = NULL; 488 scp->midiintr_arg = NULL; 489 break; 490 491 default: 492 return (EINVAL); 493 } 494 495 return (0); 496 } 497 498 /* The interrupt handler */ 499 static void 500 csa_intr(void *arg) 501 { 502 sc_p scp = arg; 503 csa_res *resp; 504 u_int32_t hisr; 505 506 resp = &scp->res; 507 508 /* Is this interrupt for us? */ 509 hisr = csa_readio(resp, BA0_HISR); 510 if ((hisr & 0x7fffffff) == 0) { 511 /* Throw an eoi. */ 512 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 513 return; 514 } 515 516 /* 517 * Pass the value of HISR via struct csa_bridgeinfo. 518 * The children get access through their ivars. 519 */ 520 scp->binfo.hisr = hisr; 521 522 /* Invoke the handlers of the children. */ 523 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 524 scp->pcmintr(scp->pcmintr_arg); 525 hisr &= ~(HISR_VC0 | HISR_VC1); 526 } 527 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 528 scp->midiintr(scp->midiintr_arg); 529 hisr &= ~HISR_MIDI; 530 } 531 532 /* Throw an eoi. */ 533 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 534 } 535 536 static int 537 csa_initialize(sc_p scp) 538 { 539 int i; 540 u_int32_t acsts, acisv; 541 csa_res *resp; 542 543 resp = &scp->res; 544 545 /* 546 * First, blast the clock control register to zero so that the PLL starts 547 * out in a known state, and blast the master serial port control register 548 * to zero so that the serial ports also start out in a known state. 549 */ 550 csa_writeio(resp, BA0_CLKCR1, 0); 551 csa_writeio(resp, BA0_SERMC1, 0); 552 553 /* 554 * If we are in AC97 mode, then we must set the part to a host controlled 555 * AC-link. Otherwise, we won't be able to bring up the link. 556 */ 557 #if 1 558 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 559 #else 560 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 561 #endif /* 1 */ 562 563 /* 564 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 565 * spec) and then drive it high. This is done for non AC97 modes since 566 * there might be logic external to the CS461x that uses the ARST# line 567 * for a reset. 568 */ 569 csa_writeio(resp, BA0_ACCTL, 1); 570 DELAY(50); 571 csa_writeio(resp, BA0_ACCTL, 0); 572 DELAY(50); 573 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 574 575 /* 576 * The first thing we do here is to enable sync generation. As soon 577 * as we start receiving bit clock, we'll start producing the SYNC 578 * signal. 579 */ 580 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 581 582 /* 583 * Now wait for a short while to allow the AC97 part to start 584 * generating bit clock (so we don't try to start the PLL without an 585 * input clock). 586 */ 587 DELAY(50000); 588 589 /* 590 * Set the serial port timing configuration, so that 591 * the clock control circuit gets its clock from the correct place. 592 */ 593 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 594 DELAY(700000); 595 596 /* 597 * Write the selected clock control setup to the hardware. Do not turn on 598 * SWCE yet (if requested), so that the devices clocked by the output of 599 * PLL are not clocked until the PLL is stable. 600 */ 601 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 602 csa_writeio(resp, BA0_PLLM, 0x3a); 603 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 604 605 /* 606 * Power up the PLL. 607 */ 608 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 609 610 /* 611 * Wait until the PLL has stabilized. 612 */ 613 DELAY(5000); 614 615 /* 616 * Turn on clocking of the core so that we can setup the serial ports. 617 */ 618 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 619 620 /* 621 * Fill the serial port FIFOs with silence. 622 */ 623 csa_clearserialfifos(resp); 624 625 /* 626 * Set the serial port FIFO pointer to the first sample in the FIFO. 627 */ 628 #ifdef notdef 629 csa_writeio(resp, BA0_SERBSP, 0); 630 #endif /* notdef */ 631 632 /* 633 * Write the serial port configuration to the part. The master 634 * enable bit is not set until all other values have been written. 635 */ 636 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 637 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 638 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 639 640 /* 641 * Wait for the codec ready signal from the AC97 codec. 642 */ 643 acsts = 0; 644 for (i = 0 ; i < 1000 ; i++) { 645 /* 646 * First, lets wait a short while to let things settle out a bit, 647 * and to prevent retrying the read too quickly. 648 */ 649 DELAY(125); 650 651 /* 652 * Read the AC97 status register to see if we've seen a CODEC READY 653 * signal from the AC97 codec. 654 */ 655 acsts = csa_readio(resp, BA0_ACSTS); 656 if ((acsts & ACSTS_CRDY) != 0) 657 break; 658 } 659 660 /* 661 * Make sure we sampled CODEC READY. 662 */ 663 if ((acsts & ACSTS_CRDY) == 0) 664 return (ENXIO); 665 666 /* 667 * Assert the vaid frame signal so that we can start sending commands 668 * to the AC97 codec. 669 */ 670 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 671 672 /* 673 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 674 * the codec is pumping ADC data across the AC-link. 675 */ 676 acisv = 0; 677 for (i = 0 ; i < 2000 ; i++) { 678 /* 679 * First, lets wait a short while to let things settle out a bit, 680 * and to prevent retrying the read too quickly. 681 */ 682 #ifdef notdef 683 DELAY(10000000L); /* clw */ 684 #else 685 DELAY(1000); 686 #endif /* notdef */ 687 /* 688 * Read the input slot valid register and see if input slots 3 and 689 * 4 are valid yet. 690 */ 691 acisv = csa_readio(resp, BA0_ACISV); 692 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 693 break; 694 } 695 /* 696 * Make sure we sampled valid input slots 3 and 4. If not, then return 697 * an error. 698 */ 699 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 700 return (ENXIO); 701 702 /* 703 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 704 * commense the transfer of digital audio data to the AC97 codec. 705 */ 706 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 707 708 /* 709 * Power down the DAC and ADC. We will power them up (if) when we need 710 * them. 711 */ 712 #ifdef notdef 713 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 714 #endif /* notdef */ 715 716 /* 717 * Turn off the Processor by turning off the software clock enable flag in 718 * the clock control register. 719 */ 720 #ifdef notdef 721 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 722 csa_writeio(resp, BA0_CLKCR1, clkcr1); 723 #endif /* notdef */ 724 725 /* 726 * Enable interrupts on the part. 727 */ 728 #if 0 729 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 730 #endif /* notdef */ 731 732 return (0); 733 } 734 735 void 736 csa_clearserialfifos(csa_res *resp) 737 { 738 int i, j, pwr; 739 u_int8_t clkcr1, serbst; 740 741 /* 742 * See if the devices are powered down. If so, we must power them up first 743 * or they will not respond. 744 */ 745 pwr = 1; 746 clkcr1 = csa_readio(resp, BA0_CLKCR1); 747 if ((clkcr1 & CLKCR1_SWCE) == 0) { 748 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 749 pwr = 0; 750 } 751 752 /* 753 * We want to clear out the serial port FIFOs so we don't end up playing 754 * whatever random garbage happens to be in them. We fill the sample FIFOs 755 * with zero (silence). 756 */ 757 csa_writeio(resp, BA0_SERBWP, 0); 758 759 /* Fill all 256 sample FIFO locations. */ 760 serbst = 0; 761 for (i = 0 ; i < 256 ; i++) { 762 /* Make sure the previous FIFO write operation has completed. */ 763 for (j = 0 ; j < 5 ; j++) { 764 DELAY(100); 765 serbst = csa_readio(resp, BA0_SERBST); 766 if ((serbst & SERBST_WBSY) == 0) 767 break; 768 } 769 if ((serbst & SERBST_WBSY) != 0) { 770 if (!pwr) 771 csa_writeio(resp, BA0_CLKCR1, clkcr1); 772 } 773 /* Write the serial port FIFO index. */ 774 csa_writeio(resp, BA0_SERBAD, i); 775 /* Tell the serial port to load the new value into the FIFO location. */ 776 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 777 } 778 /* 779 * Now, if we powered up the devices, then power them back down again. 780 * This is kinda ugly, but should never happen. 781 */ 782 if (!pwr) 783 csa_writeio(resp, BA0_CLKCR1, clkcr1); 784 } 785 786 void 787 csa_resetdsp(csa_res *resp) 788 { 789 int i; 790 791 /* 792 * Write the reset bit of the SP control register. 793 */ 794 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 795 796 /* 797 * Write the control register. 798 */ 799 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 800 801 /* 802 * Clear the trap registers. 803 */ 804 for (i = 0 ; i < 8 ; i++) { 805 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 806 csa_writemem(resp, BA1_TWPR, 0xffff); 807 } 808 csa_writemem(resp, BA1_DREG, 0); 809 810 /* 811 * Set the frame timer to reflect the number of cycles per frame. 812 */ 813 csa_writemem(resp, BA1_FRMT, 0xadf); 814 } 815 816 static int 817 csa_downloadimage(csa_res *resp) 818 { 819 int ret; 820 u_long ul, offset; 821 822 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 823 /* 824 * DMA this block from host memory to the appropriate 825 * memory on the CSDevice. 826 */ 827 ret = csa_transferimage(resp, 828 cs461x_firmware.BA1Array + offset, 829 cs461x_firmware.MemoryStat[ul].ulDestAddr, 830 cs461x_firmware.MemoryStat[ul].ulSourceSize); 831 if (ret) 832 return (ret); 833 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2; 834 } 835 return (0); 836 } 837 838 static int 839 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len) 840 { 841 u_long ul; 842 843 /* 844 * We do not allow DMAs from host memory to host memory (although the DMA 845 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 846 * in size (because that DMA can not do that). Return an error if either 847 * of these conditions exist. 848 */ 849 if ((len & 0x3) != 0) 850 return (EINVAL); 851 852 /* Check the destination address that it is a multiple of 4 */ 853 if ((dest & 0x3) != 0) 854 return (EINVAL); 855 856 /* Write the buffer out. */ 857 for (ul = 0 ; ul < len ; ul += 4) 858 csa_writemem(resp, dest + ul, src[ul >> 2]); 859 return (0); 860 } 861 862 int 863 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 864 { 865 int i; 866 u_int32_t acctl, acsts; 867 868 /* 869 * Make sure that there is not data sitting around from a previous 870 * uncompleted access. ACSDA = Status Data Register = 47Ch 871 */ 872 csa_readio(resp, BA0_ACSDA); 873 874 /* 875 * Setup the AC97 control registers on the CS461x to send the 876 * appropriate command to the AC97 to perform the read. 877 * ACCAD = Command Address Register = 46Ch 878 * ACCDA = Command Data Register = 470h 879 * ACCTL = Control Register = 460h 880 * set DCV - will clear when process completed 881 * set CRW - Read command 882 * set VFRM - valid frame enabled 883 * set ESYN - ASYNC generation enabled 884 * set RSTN - ARST# inactive, AC97 codec not reset 885 */ 886 887 /* 888 * Get the actual AC97 register from the offset 889 */ 890 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 891 csa_writeio(resp, BA0_ACCDA, 0); 892 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 893 894 /* 895 * Wait for the read to occur. 896 */ 897 acctl = 0; 898 for (i = 0 ; i < 10 ; i++) { 899 /* 900 * First, we want to wait for a short time. 901 */ 902 DELAY(25); 903 904 /* 905 * Now, check to see if the read has completed. 906 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 907 */ 908 acctl = csa_readio(resp, BA0_ACCTL); 909 if ((acctl & ACCTL_DCV) == 0) 910 break; 911 } 912 913 /* 914 * Make sure the read completed. 915 */ 916 if ((acctl & ACCTL_DCV) != 0) 917 return (EAGAIN); 918 919 /* 920 * Wait for the valid status bit to go active. 921 */ 922 acsts = 0; 923 for (i = 0 ; i < 10 ; i++) { 924 /* 925 * Read the AC97 status register. 926 * ACSTS = Status Register = 464h 927 */ 928 acsts = csa_readio(resp, BA0_ACSTS); 929 /* 930 * See if we have valid status. 931 * VSTS - Valid Status 932 */ 933 if ((acsts & ACSTS_VSTS) != 0) 934 break; 935 /* 936 * Wait for a short while. 937 */ 938 DELAY(25); 939 } 940 941 /* 942 * Make sure we got valid status. 943 */ 944 if ((acsts & ACSTS_VSTS) == 0) 945 return (EAGAIN); 946 947 /* 948 * Read the data returned from the AC97 register. 949 * ACSDA = Status Data Register = 474h 950 */ 951 *data = csa_readio(resp, BA0_ACSDA); 952 953 return (0); 954 } 955 956 int 957 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 958 { 959 int i; 960 u_int32_t acctl; 961 962 /* 963 * Setup the AC97 control registers on the CS461x to send the 964 * appropriate command to the AC97 to perform the write. 965 * ACCAD = Command Address Register = 46Ch 966 * ACCDA = Command Data Register = 470h 967 * ACCTL = Control Register = 460h 968 * set DCV - will clear when process completed 969 * set VFRM - valid frame enabled 970 * set ESYN - ASYNC generation enabled 971 * set RSTN - ARST# inactive, AC97 codec not reset 972 */ 973 974 /* 975 * Get the actual AC97 register from the offset 976 */ 977 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 978 csa_writeio(resp, BA0_ACCDA, data); 979 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 980 981 /* 982 * Wait for the write to occur. 983 */ 984 acctl = 0; 985 for (i = 0 ; i < 10 ; i++) { 986 /* 987 * First, we want to wait for a short time. 988 */ 989 DELAY(25); 990 991 /* 992 * Now, check to see if the read has completed. 993 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 994 */ 995 acctl = csa_readio(resp, BA0_ACCTL); 996 if ((acctl & ACCTL_DCV) == 0) 997 break; 998 } 999 1000 /* 1001 * Make sure the write completed. 1002 */ 1003 if ((acctl & ACCTL_DCV) != 0) 1004 return (EAGAIN); 1005 1006 return (0); 1007 } 1008 1009 u_int32_t 1010 csa_readio(csa_res *resp, u_long offset) 1011 { 1012 u_int32_t ul; 1013 1014 if (offset < BA0_AC97_RESET) 1015 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1016 else { 1017 if (csa_readcodec(resp, offset, &ul)) 1018 ul = 0; 1019 return (ul); 1020 } 1021 } 1022 1023 void 1024 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1025 { 1026 if (offset < BA0_AC97_RESET) 1027 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1028 else 1029 csa_writecodec(resp, offset, data); 1030 } 1031 1032 u_int32_t 1033 csa_readmem(csa_res *resp, u_long offset) 1034 { 1035 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1036 } 1037 1038 void 1039 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1040 { 1041 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1042 } 1043 1044 static device_method_t csa_methods[] = { 1045 /* Device interface */ 1046 DEVMETHOD(device_probe, csa_probe), 1047 DEVMETHOD(device_attach, csa_attach), 1048 DEVMETHOD(device_detach, csa_detach), 1049 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1050 DEVMETHOD(device_suspend, bus_generic_suspend), 1051 DEVMETHOD(device_resume, csa_resume), 1052 1053 /* Bus interface */ 1054 DEVMETHOD(bus_child_deleted, csa_child_deleted), 1055 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1056 DEVMETHOD(bus_release_resource, csa_release_resource), 1057 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1058 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1059 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1060 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1061 1062 DEVMETHOD_END 1063 }; 1064 1065 static driver_t csa_driver = { 1066 "csa", 1067 csa_methods, 1068 sizeof(struct csa_softc), 1069 }; 1070 1071 /* 1072 * csa can be attached to a pci bus. 1073 */ 1074 DRIVER_MODULE(snd_csa, pci, csa_driver, 0, 0); 1075 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1076 MODULE_VERSION(snd_csa, 1); 1077