1 /*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 #include <sys/soundcard.h> 41 #include <dev/sound/pcm/sound.h> 42 #include <dev/sound/chip.h> 43 #include <dev/sound/pci/csareg.h> 44 #include <dev/sound/pci/csavar.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <gnu/dev/sound/pci/csaimg.h> 50 51 SND_DECLARE_FILE("$FreeBSD$"); 52 53 /* This is the pci device id. */ 54 #define CS4610_PCI_ID 0x60011013 55 #define CS4614_PCI_ID 0x60031013 56 #define CS4615_PCI_ID 0x60041013 57 58 /* Here is the parameter structure per a device. */ 59 struct csa_softc { 60 device_t dev; /* device */ 61 csa_res res; /* resources */ 62 63 device_t pcm; /* pcm device */ 64 driver_intr_t* pcmintr; /* pcm intr */ 65 void *pcmintr_arg; /* pcm intr arg */ 66 device_t midi; /* midi device */ 67 driver_intr_t* midiintr; /* midi intr */ 68 void *midiintr_arg; /* midi intr arg */ 69 void *ih; /* cookie */ 70 71 struct csa_card *card; 72 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 73 }; 74 75 typedef struct csa_softc *sc_p; 76 77 static int csa_probe(device_t dev); 78 static int csa_attach(device_t dev); 79 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 80 u_long start, u_long end, u_long count, u_int flags); 81 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 82 struct resource *r); 83 static int csa_setup_intr(device_t bus, device_t child, 84 struct resource *irq, int flags, 85 #if __FreeBSD_version >= 700031 86 driver_filter_t *filter, 87 #endif 88 driver_intr_t *intr, void *arg, void **cookiep); 89 static int csa_teardown_intr(device_t bus, device_t child, 90 struct resource *irq, void *cookie); 91 static driver_intr_t csa_intr; 92 static int csa_initialize(sc_p scp); 93 static int csa_downloadimage(csa_res *resp); 94 95 static devclass_t csa_devclass; 96 97 static void 98 amp_none(void) 99 { 100 } 101 102 static void 103 amp_voyetra(void) 104 { 105 } 106 107 static int 108 clkrun_hack(int run) 109 { 110 #ifdef __i386__ 111 devclass_t pci_devclass; 112 device_t *pci_devices, *pci_children, *busp, *childp; 113 int pci_count = 0, pci_childcount = 0; 114 int i, j, port; 115 u_int16_t control; 116 bus_space_tag_t btag; 117 118 if ((pci_devclass = devclass_find("pci")) == NULL) { 119 return ENXIO; 120 } 121 122 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 123 124 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 125 pci_childcount = 0; 126 if (device_get_children(*busp, &pci_children, &pci_childcount)) 127 continue; 128 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 129 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 130 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 131 /* XXX */ 132 btag = I386_BUS_SPACE_IO; 133 134 control = bus_space_read_2(btag, 0x0, port); 135 control &= ~0x2000; 136 control |= run? 0 : 0x2000; 137 bus_space_write_2(btag, 0x0, port, control); 138 free(pci_devices, M_TEMP); 139 free(pci_children, M_TEMP); 140 return 0; 141 } 142 } 143 free(pci_children, M_TEMP); 144 } 145 146 free(pci_devices, M_TEMP); 147 return ENXIO; 148 #else 149 return 0; 150 #endif 151 } 152 153 static struct csa_card cards_4610[] = { 154 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 155 }; 156 157 static struct csa_card cards_4614[] = { 158 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 159 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 160 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 161 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 162 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 163 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 164 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 165 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 166 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 167 }; 168 169 static struct csa_card cards_4615[] = { 170 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 171 }; 172 173 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 174 175 struct card_type { 176 u_int32_t devid; 177 char *name; 178 struct csa_card *cards; 179 }; 180 181 static struct card_type cards[] = { 182 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 183 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 184 {CS4615_PCI_ID, "CS4615", cards_4615}, 185 {0, NULL, NULL}, 186 }; 187 188 static struct card_type * 189 csa_findcard(device_t dev) 190 { 191 int i; 192 193 i = 0; 194 while (cards[i].devid != 0) { 195 if (pci_get_devid(dev) == cards[i].devid) 196 return &cards[i]; 197 i++; 198 } 199 return NULL; 200 } 201 202 struct csa_card * 203 csa_findsubcard(device_t dev) 204 { 205 int i; 206 struct card_type *card; 207 struct csa_card *subcard; 208 209 card = csa_findcard(dev); 210 if (card == NULL) 211 return &nocard; 212 subcard = card->cards; 213 i = 0; 214 while (subcard[i].subvendor != 0) { 215 if (pci_get_subvendor(dev) == subcard[i].subvendor 216 && pci_get_subdevice(dev) == subcard[i].subdevice) { 217 return &subcard[i]; 218 } 219 i++; 220 } 221 return &subcard[i]; 222 } 223 224 static int 225 csa_probe(device_t dev) 226 { 227 struct card_type *card; 228 229 card = csa_findcard(dev); 230 if (card) { 231 device_set_desc(dev, card->name); 232 return BUS_PROBE_DEFAULT; 233 } 234 return ENXIO; 235 } 236 237 static int 238 csa_attach(device_t dev) 239 { 240 u_int32_t stcmd; 241 sc_p scp; 242 csa_res *resp; 243 struct sndcard_func *func; 244 int error = ENXIO; 245 246 scp = device_get_softc(dev); 247 248 /* Fill in the softc. */ 249 bzero(scp, sizeof(*scp)); 250 scp->dev = dev; 251 252 /* Wake up the device. */ 253 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 254 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 255 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 256 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 257 } 258 259 /* Allocate the resources. */ 260 resp = &scp->res; 261 scp->card = csa_findsubcard(dev); 262 scp->binfo.card = scp->card; 263 printf("csa: card is %s\n", scp->card->name); 264 resp->io_rid = PCIR_BAR(0); 265 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 266 &resp->io_rid, RF_ACTIVE); 267 if (resp->io == NULL) 268 return (ENXIO); 269 resp->mem_rid = PCIR_BAR(1); 270 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 271 &resp->mem_rid, RF_ACTIVE); 272 if (resp->mem == NULL) 273 goto err_io; 274 resp->irq_rid = 0; 275 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 276 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 277 if (resp->irq == NULL) 278 goto err_mem; 279 280 /* Enable interrupt. */ 281 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 282 goto err_intr; 283 #if 0 284 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 285 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 286 #endif 287 288 /* Initialize the chip. */ 289 if (csa_initialize(scp)) 290 goto err_teardown; 291 292 /* Reset the Processor. */ 293 csa_resetdsp(resp); 294 295 /* Download the Processor Image to the processor. */ 296 if (csa_downloadimage(resp)) 297 goto err_teardown; 298 299 /* Attach the children. */ 300 301 /* PCM Audio */ 302 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 303 if (func == NULL) { 304 error = ENOMEM; 305 goto err_teardown; 306 } 307 func->varinfo = &scp->binfo; 308 func->func = SCF_PCM; 309 scp->pcm = device_add_child(dev, "pcm", -1); 310 device_set_ivars(scp->pcm, func); 311 312 /* Midi Interface */ 313 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 314 if (func == NULL) { 315 error = ENOMEM; 316 goto err_teardown; 317 } 318 func->varinfo = &scp->binfo; 319 func->func = SCF_MIDI; 320 scp->midi = device_add_child(dev, "midi", -1); 321 device_set_ivars(scp->midi, func); 322 323 bus_generic_attach(dev); 324 325 return (0); 326 327 err_teardown: 328 bus_teardown_intr(dev, resp->irq, scp->ih); 329 err_intr: 330 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 331 err_mem: 332 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 333 err_io: 334 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 335 return (error); 336 } 337 338 static int 339 csa_detach(device_t dev) 340 { 341 csa_res *resp; 342 sc_p scp; 343 struct sndcard_func *func; 344 int err; 345 346 scp = device_get_softc(dev); 347 resp = &scp->res; 348 349 if (scp->midi != NULL) { 350 func = device_get_ivars(scp->midi); 351 err = device_delete_child(dev, scp->midi); 352 if (err != 0) 353 return err; 354 if (func != NULL) 355 free(func, M_DEVBUF); 356 scp->midi = NULL; 357 } 358 359 if (scp->pcm != NULL) { 360 func = device_get_ivars(scp->pcm); 361 err = device_delete_child(dev, scp->pcm); 362 if (err != 0) 363 return err; 364 if (func != NULL) 365 free(func, M_DEVBUF); 366 scp->pcm = NULL; 367 } 368 369 bus_teardown_intr(dev, resp->irq, scp->ih); 370 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 371 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 372 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 373 374 return bus_generic_detach(dev); 375 } 376 377 static int 378 csa_resume(device_t dev) 379 { 380 csa_res *resp; 381 sc_p scp; 382 383 scp = device_get_softc(dev); 384 resp = &scp->res; 385 386 /* Initialize the chip. */ 387 if (csa_initialize(scp)) 388 return (ENXIO); 389 390 /* Reset the Processor. */ 391 csa_resetdsp(resp); 392 393 /* Download the Processor Image to the processor. */ 394 if (csa_downloadimage(resp)) 395 return (ENXIO); 396 397 return (bus_generic_resume(dev)); 398 } 399 400 static struct resource * 401 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 402 u_long start, u_long end, u_long count, u_int flags) 403 { 404 sc_p scp; 405 csa_res *resp; 406 struct resource *res; 407 408 scp = device_get_softc(bus); 409 resp = &scp->res; 410 switch (type) { 411 case SYS_RES_IRQ: 412 if (*rid != 0) 413 return (NULL); 414 res = resp->irq; 415 break; 416 case SYS_RES_MEMORY: 417 switch (*rid) { 418 case PCIR_BAR(0): 419 res = resp->io; 420 break; 421 case PCIR_BAR(1): 422 res = resp->mem; 423 break; 424 default: 425 return (NULL); 426 } 427 break; 428 default: 429 return (NULL); 430 } 431 432 return res; 433 } 434 435 static int 436 csa_release_resource(device_t bus, device_t child, int type, int rid, 437 struct resource *r) 438 { 439 return (0); 440 } 441 442 /* 443 * The following three functions deal with interrupt handling. 444 * An interrupt is primarily handled by the bridge driver. 445 * The bridge driver then determines the child devices to pass 446 * the interrupt. Certain information of the device can be read 447 * only once(eg the value of HISR). The bridge driver is responsible 448 * to pass such the information to the children. 449 */ 450 451 static int 452 csa_setup_intr(device_t bus, device_t child, 453 struct resource *irq, int flags, 454 #if __FreeBSD_version >= 700031 455 driver_filter_t *filter, 456 #endif 457 driver_intr_t *intr, void *arg, void **cookiep) 458 { 459 sc_p scp; 460 csa_res *resp; 461 struct sndcard_func *func; 462 463 #if __FreeBSD_version >= 700031 464 if (filter != NULL) { 465 printf("ata-csa.c: we cannot use a filter here\n"); 466 return (EINVAL); 467 } 468 #endif 469 scp = device_get_softc(bus); 470 resp = &scp->res; 471 472 /* 473 * Look at the function code of the child to determine 474 * the appropriate hander for it. 475 */ 476 func = device_get_ivars(child); 477 if (func == NULL || irq != resp->irq) 478 return (EINVAL); 479 480 switch (func->func) { 481 case SCF_PCM: 482 scp->pcmintr = intr; 483 scp->pcmintr_arg = arg; 484 break; 485 486 case SCF_MIDI: 487 scp->midiintr = intr; 488 scp->midiintr_arg = arg; 489 break; 490 491 default: 492 return (EINVAL); 493 } 494 *cookiep = scp; 495 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 496 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 497 498 return (0); 499 } 500 501 static int 502 csa_teardown_intr(device_t bus, device_t child, 503 struct resource *irq, void *cookie) 504 { 505 sc_p scp; 506 csa_res *resp; 507 struct sndcard_func *func; 508 509 scp = device_get_softc(bus); 510 resp = &scp->res; 511 512 /* 513 * Look at the function code of the child to determine 514 * the appropriate hander for it. 515 */ 516 func = device_get_ivars(child); 517 if (func == NULL || irq != resp->irq || cookie != scp) 518 return (EINVAL); 519 520 switch (func->func) { 521 case SCF_PCM: 522 scp->pcmintr = NULL; 523 scp->pcmintr_arg = NULL; 524 break; 525 526 case SCF_MIDI: 527 scp->midiintr = NULL; 528 scp->midiintr_arg = NULL; 529 break; 530 531 default: 532 return (EINVAL); 533 } 534 535 return (0); 536 } 537 538 /* The interrupt handler */ 539 static void 540 csa_intr(void *arg) 541 { 542 sc_p scp = arg; 543 csa_res *resp; 544 u_int32_t hisr; 545 546 resp = &scp->res; 547 548 /* Is this interrupt for us? */ 549 hisr = csa_readio(resp, BA0_HISR); 550 if ((hisr & 0x7fffffff) == 0) { 551 /* Throw an eoi. */ 552 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 553 return; 554 } 555 556 /* 557 * Pass the value of HISR via struct csa_bridgeinfo. 558 * The children get access through their ivars. 559 */ 560 scp->binfo.hisr = hisr; 561 562 /* Invoke the handlers of the children. */ 563 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 564 scp->pcmintr(scp->pcmintr_arg); 565 hisr &= ~(HISR_VC0 | HISR_VC1); 566 } 567 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 568 scp->midiintr(scp->midiintr_arg); 569 hisr &= ~HISR_MIDI; 570 } 571 572 /* Throw an eoi. */ 573 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 574 } 575 576 static int 577 csa_initialize(sc_p scp) 578 { 579 int i; 580 u_int32_t acsts, acisv; 581 csa_res *resp; 582 583 resp = &scp->res; 584 585 /* 586 * First, blast the clock control register to zero so that the PLL starts 587 * out in a known state, and blast the master serial port control register 588 * to zero so that the serial ports also start out in a known state. 589 */ 590 csa_writeio(resp, BA0_CLKCR1, 0); 591 csa_writeio(resp, BA0_SERMC1, 0); 592 593 /* 594 * If we are in AC97 mode, then we must set the part to a host controlled 595 * AC-link. Otherwise, we won't be able to bring up the link. 596 */ 597 #if 1 598 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 599 #else 600 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 601 #endif /* 1 */ 602 603 /* 604 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 605 * spec) and then drive it high. This is done for non AC97 modes since 606 * there might be logic external to the CS461x that uses the ARST# line 607 * for a reset. 608 */ 609 csa_writeio(resp, BA0_ACCTL, 1); 610 DELAY(50); 611 csa_writeio(resp, BA0_ACCTL, 0); 612 DELAY(50); 613 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 614 615 /* 616 * The first thing we do here is to enable sync generation. As soon 617 * as we start receiving bit clock, we'll start producing the SYNC 618 * signal. 619 */ 620 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 621 622 /* 623 * Now wait for a short while to allow the AC97 part to start 624 * generating bit clock (so we don't try to start the PLL without an 625 * input clock). 626 */ 627 DELAY(50000); 628 629 /* 630 * Set the serial port timing configuration, so that 631 * the clock control circuit gets its clock from the correct place. 632 */ 633 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 634 DELAY(700000); 635 636 /* 637 * Write the selected clock control setup to the hardware. Do not turn on 638 * SWCE yet (if requested), so that the devices clocked by the output of 639 * PLL are not clocked until the PLL is stable. 640 */ 641 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 642 csa_writeio(resp, BA0_PLLM, 0x3a); 643 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 644 645 /* 646 * Power up the PLL. 647 */ 648 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 649 650 /* 651 * Wait until the PLL has stabilized. 652 */ 653 DELAY(5000); 654 655 /* 656 * Turn on clocking of the core so that we can setup the serial ports. 657 */ 658 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 659 660 /* 661 * Fill the serial port FIFOs with silence. 662 */ 663 csa_clearserialfifos(resp); 664 665 /* 666 * Set the serial port FIFO pointer to the first sample in the FIFO. 667 */ 668 #ifdef notdef 669 csa_writeio(resp, BA0_SERBSP, 0); 670 #endif /* notdef */ 671 672 /* 673 * Write the serial port configuration to the part. The master 674 * enable bit is not set until all other values have been written. 675 */ 676 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 677 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 678 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 679 680 /* 681 * Wait for the codec ready signal from the AC97 codec. 682 */ 683 acsts = 0; 684 for (i = 0 ; i < 1000 ; i++) { 685 /* 686 * First, lets wait a short while to let things settle out a bit, 687 * and to prevent retrying the read too quickly. 688 */ 689 DELAY(125); 690 691 /* 692 * Read the AC97 status register to see if we've seen a CODEC READY 693 * signal from the AC97 codec. 694 */ 695 acsts = csa_readio(resp, BA0_ACSTS); 696 if ((acsts & ACSTS_CRDY) != 0) 697 break; 698 } 699 700 /* 701 * Make sure we sampled CODEC READY. 702 */ 703 if ((acsts & ACSTS_CRDY) == 0) 704 return (ENXIO); 705 706 /* 707 * Assert the vaid frame signal so that we can start sending commands 708 * to the AC97 codec. 709 */ 710 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 711 712 /* 713 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 714 * the codec is pumping ADC data across the AC-link. 715 */ 716 acisv = 0; 717 for (i = 0 ; i < 1000 ; i++) { 718 /* 719 * First, lets wait a short while to let things settle out a bit, 720 * and to prevent retrying the read too quickly. 721 */ 722 #ifdef notdef 723 DELAY(10000000L); /* clw */ 724 #else 725 DELAY(1000); 726 #endif /* notdef */ 727 /* 728 * Read the input slot valid register and see if input slots 3 and 729 * 4 are valid yet. 730 */ 731 acisv = csa_readio(resp, BA0_ACISV); 732 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 733 break; 734 } 735 /* 736 * Make sure we sampled valid input slots 3 and 4. If not, then return 737 * an error. 738 */ 739 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 740 return (ENXIO); 741 742 /* 743 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 744 * commense the transfer of digital audio data to the AC97 codec. 745 */ 746 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 747 748 /* 749 * Power down the DAC and ADC. We will power them up (if) when we need 750 * them. 751 */ 752 #ifdef notdef 753 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 754 #endif /* notdef */ 755 756 /* 757 * Turn off the Processor by turning off the software clock enable flag in 758 * the clock control register. 759 */ 760 #ifdef notdef 761 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 762 csa_writeio(resp, BA0_CLKCR1, clkcr1); 763 #endif /* notdef */ 764 765 /* 766 * Enable interrupts on the part. 767 */ 768 #if 0 769 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 770 #endif /* notdef */ 771 772 return (0); 773 } 774 775 void 776 csa_clearserialfifos(csa_res *resp) 777 { 778 int i, j, pwr; 779 u_int8_t clkcr1, serbst; 780 781 /* 782 * See if the devices are powered down. If so, we must power them up first 783 * or they will not respond. 784 */ 785 pwr = 1; 786 clkcr1 = csa_readio(resp, BA0_CLKCR1); 787 if ((clkcr1 & CLKCR1_SWCE) == 0) { 788 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 789 pwr = 0; 790 } 791 792 /* 793 * We want to clear out the serial port FIFOs so we don't end up playing 794 * whatever random garbage happens to be in them. We fill the sample FIFOs 795 * with zero (silence). 796 */ 797 csa_writeio(resp, BA0_SERBWP, 0); 798 799 /* Fill all 256 sample FIFO locations. */ 800 serbst = 0; 801 for (i = 0 ; i < 256 ; i++) { 802 /* Make sure the previous FIFO write operation has completed. */ 803 for (j = 0 ; j < 5 ; j++) { 804 DELAY(100); 805 serbst = csa_readio(resp, BA0_SERBST); 806 if ((serbst & SERBST_WBSY) == 0) 807 break; 808 } 809 if ((serbst & SERBST_WBSY) != 0) { 810 if (!pwr) 811 csa_writeio(resp, BA0_CLKCR1, clkcr1); 812 } 813 /* Write the serial port FIFO index. */ 814 csa_writeio(resp, BA0_SERBAD, i); 815 /* Tell the serial port to load the new value into the FIFO location. */ 816 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 817 } 818 /* 819 * Now, if we powered up the devices, then power them back down again. 820 * This is kinda ugly, but should never happen. 821 */ 822 if (!pwr) 823 csa_writeio(resp, BA0_CLKCR1, clkcr1); 824 } 825 826 void 827 csa_resetdsp(csa_res *resp) 828 { 829 int i; 830 831 /* 832 * Write the reset bit of the SP control register. 833 */ 834 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 835 836 /* 837 * Write the control register. 838 */ 839 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 840 841 /* 842 * Clear the trap registers. 843 */ 844 for (i = 0 ; i < 8 ; i++) { 845 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 846 csa_writemem(resp, BA1_TWPR, 0xffff); 847 } 848 csa_writemem(resp, BA1_DREG, 0); 849 850 /* 851 * Set the frame timer to reflect the number of cycles per frame. 852 */ 853 csa_writemem(resp, BA1_FRMT, 0xadf); 854 } 855 856 static int 857 csa_downloadimage(csa_res *resp) 858 { 859 int i; 860 u_int32_t tmp, src, dst, count, data; 861 862 for (i = 0; i < CLEAR__COUNT; i++) { 863 dst = ClrStat[i].BA1__DestByteOffset; 864 count = ClrStat[i].BA1__SourceSize; 865 for (tmp = 0; tmp < count; tmp += 4) 866 csa_writemem(resp, dst + tmp, 0x00000000); 867 } 868 869 for (i = 0; i < FILL__COUNT; i++) { 870 src = 0; 871 dst = FillStat[i].Offset; 872 count = FillStat[i].Size; 873 for (tmp = 0; tmp < count; tmp += 4) { 874 data = FillStat[i].pFill[src]; 875 csa_writemem(resp, dst + tmp, data); 876 src++; 877 } 878 } 879 880 return (0); 881 } 882 883 int 884 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 885 { 886 int i; 887 u_int32_t acsda, acctl, acsts; 888 889 /* 890 * Make sure that there is not data sitting around from a previous 891 * uncompleted access. ACSDA = Status Data Register = 47Ch 892 */ 893 acsda = csa_readio(resp, BA0_ACSDA); 894 895 /* 896 * Setup the AC97 control registers on the CS461x to send the 897 * appropriate command to the AC97 to perform the read. 898 * ACCAD = Command Address Register = 46Ch 899 * ACCDA = Command Data Register = 470h 900 * ACCTL = Control Register = 460h 901 * set DCV - will clear when process completed 902 * set CRW - Read command 903 * set VFRM - valid frame enabled 904 * set ESYN - ASYNC generation enabled 905 * set RSTN - ARST# inactive, AC97 codec not reset 906 */ 907 908 /* 909 * Get the actual AC97 register from the offset 910 */ 911 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 912 csa_writeio(resp, BA0_ACCDA, 0); 913 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 914 915 /* 916 * Wait for the read to occur. 917 */ 918 acctl = 0; 919 for (i = 0 ; i < 10 ; i++) { 920 /* 921 * First, we want to wait for a short time. 922 */ 923 DELAY(25); 924 925 /* 926 * Now, check to see if the read has completed. 927 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 928 */ 929 acctl = csa_readio(resp, BA0_ACCTL); 930 if ((acctl & ACCTL_DCV) == 0) 931 break; 932 } 933 934 /* 935 * Make sure the read completed. 936 */ 937 if ((acctl & ACCTL_DCV) != 0) 938 return (EAGAIN); 939 940 /* 941 * Wait for the valid status bit to go active. 942 */ 943 acsts = 0; 944 for (i = 0 ; i < 10 ; i++) { 945 /* 946 * Read the AC97 status register. 947 * ACSTS = Status Register = 464h 948 */ 949 acsts = csa_readio(resp, BA0_ACSTS); 950 /* 951 * See if we have valid status. 952 * VSTS - Valid Status 953 */ 954 if ((acsts & ACSTS_VSTS) != 0) 955 break; 956 /* 957 * Wait for a short while. 958 */ 959 DELAY(25); 960 } 961 962 /* 963 * Make sure we got valid status. 964 */ 965 if ((acsts & ACSTS_VSTS) == 0) 966 return (EAGAIN); 967 968 /* 969 * Read the data returned from the AC97 register. 970 * ACSDA = Status Data Register = 474h 971 */ 972 *data = csa_readio(resp, BA0_ACSDA); 973 974 return (0); 975 } 976 977 int 978 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 979 { 980 int i; 981 u_int32_t acctl; 982 983 /* 984 * Setup the AC97 control registers on the CS461x to send the 985 * appropriate command to the AC97 to perform the write. 986 * ACCAD = Command Address Register = 46Ch 987 * ACCDA = Command Data Register = 470h 988 * ACCTL = Control Register = 460h 989 * set DCV - will clear when process completed 990 * set VFRM - valid frame enabled 991 * set ESYN - ASYNC generation enabled 992 * set RSTN - ARST# inactive, AC97 codec not reset 993 */ 994 995 /* 996 * Get the actual AC97 register from the offset 997 */ 998 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 999 csa_writeio(resp, BA0_ACCDA, data); 1000 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1001 1002 /* 1003 * Wait for the write to occur. 1004 */ 1005 acctl = 0; 1006 for (i = 0 ; i < 10 ; i++) { 1007 /* 1008 * First, we want to wait for a short time. 1009 */ 1010 DELAY(25); 1011 1012 /* 1013 * Now, check to see if the read has completed. 1014 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1015 */ 1016 acctl = csa_readio(resp, BA0_ACCTL); 1017 if ((acctl & ACCTL_DCV) == 0) 1018 break; 1019 } 1020 1021 /* 1022 * Make sure the write completed. 1023 */ 1024 if ((acctl & ACCTL_DCV) != 0) 1025 return (EAGAIN); 1026 1027 return (0); 1028 } 1029 1030 u_int32_t 1031 csa_readio(csa_res *resp, u_long offset) 1032 { 1033 u_int32_t ul; 1034 1035 if (offset < BA0_AC97_RESET) 1036 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1037 else { 1038 if (csa_readcodec(resp, offset, &ul)) 1039 ul = 0; 1040 return (ul); 1041 } 1042 } 1043 1044 void 1045 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1046 { 1047 if (offset < BA0_AC97_RESET) 1048 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1049 else 1050 csa_writecodec(resp, offset, data); 1051 } 1052 1053 u_int32_t 1054 csa_readmem(csa_res *resp, u_long offset) 1055 { 1056 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1057 } 1058 1059 void 1060 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1061 { 1062 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1063 } 1064 1065 static device_method_t csa_methods[] = { 1066 /* Device interface */ 1067 DEVMETHOD(device_probe, csa_probe), 1068 DEVMETHOD(device_attach, csa_attach), 1069 DEVMETHOD(device_detach, csa_detach), 1070 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1071 DEVMETHOD(device_suspend, bus_generic_suspend), 1072 DEVMETHOD(device_resume, csa_resume), 1073 1074 /* Bus interface */ 1075 DEVMETHOD(bus_print_child, bus_generic_print_child), 1076 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1077 DEVMETHOD(bus_release_resource, csa_release_resource), 1078 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1079 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1080 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1081 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1082 1083 { 0, 0 } 1084 }; 1085 1086 static driver_t csa_driver = { 1087 "csa", 1088 csa_methods, 1089 sizeof(struct csa_softc), 1090 }; 1091 1092 /* 1093 * csa can be attached to a pci bus. 1094 */ 1095 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1096 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1097 MODULE_VERSION(snd_csa, 1); 1098