1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1999 Seigo Tanimura 5 * All rights reserved. 6 * 7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 43 #ifdef HAVE_KERNEL_OPTION_HEADERS 44 #include "opt_snd.h" 45 #endif 46 47 #include <dev/sound/pcm/sound.h> 48 #include <dev/sound/pci/csareg.h> 49 #include <dev/sound/pci/csavar.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <dev/sound/pci/cs461x_dsp.h> 55 56 /* This is the pci device id. */ 57 #define CS4610_PCI_ID 0x60011013 58 #define CS4614_PCI_ID 0x60031013 59 #define CS4615_PCI_ID 0x60041013 60 61 /* Here is the parameter structure per a device. */ 62 struct csa_softc { 63 device_t dev; /* device */ 64 csa_res res; /* resources */ 65 66 device_t pcm; /* pcm device */ 67 driver_intr_t* pcmintr; /* pcm intr */ 68 void *pcmintr_arg; /* pcm intr arg */ 69 device_t midi; /* midi device */ 70 driver_intr_t* midiintr; /* midi intr */ 71 void *midiintr_arg; /* midi intr arg */ 72 void *ih; /* cookie */ 73 74 struct csa_card *card; 75 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 76 }; 77 78 typedef struct csa_softc *sc_p; 79 80 static int csa_probe(device_t dev); 81 static int csa_attach(device_t dev); 82 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 83 rman_res_t start, rman_res_t end, 84 rman_res_t count, u_int flags); 85 static int csa_release_resource(device_t bus, device_t child, struct resource *r); 86 static int csa_setup_intr(device_t bus, device_t child, 87 struct resource *irq, int flags, 88 driver_filter_t *filter, 89 driver_intr_t *intr, void *arg, void **cookiep); 90 static int csa_teardown_intr(device_t bus, device_t child, 91 struct resource *irq, void *cookie); 92 static driver_intr_t csa_intr; 93 static int csa_initialize(sc_p scp); 94 static int csa_downloadimage(csa_res *resp); 95 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len); 96 97 static void 98 amp_none(void) 99 { 100 } 101 102 static void 103 amp_voyetra(void) 104 { 105 } 106 107 static int 108 clkrun_hack(int run) 109 { 110 #ifdef __i386__ 111 devclass_t pci_devclass; 112 device_t *pci_devices, *pci_children, *busp, *childp; 113 int pci_count = 0, pci_childcount = 0; 114 int i, j, port; 115 u_int16_t control; 116 bus_space_tag_t btag; 117 118 if ((pci_devclass = devclass_find("pci")) == NULL) { 119 return ENXIO; 120 } 121 122 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 123 124 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 125 pci_childcount = 0; 126 if (device_get_children(*busp, &pci_children, &pci_childcount)) 127 continue; 128 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 129 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 130 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 131 /* XXX */ 132 btag = X86_BUS_SPACE_IO; 133 134 control = bus_space_read_2(btag, 0x0, port); 135 control &= ~0x2000; 136 control |= run? 0 : 0x2000; 137 bus_space_write_2(btag, 0x0, port, control); 138 free(pci_devices, M_TEMP); 139 free(pci_children, M_TEMP); 140 return 0; 141 } 142 } 143 free(pci_children, M_TEMP); 144 } 145 146 free(pci_devices, M_TEMP); 147 return ENXIO; 148 #else 149 return 0; 150 #endif 151 } 152 153 static struct csa_card cards_4610[] = { 154 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 155 }; 156 157 static struct csa_card cards_4614[] = { 158 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 159 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 160 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 161 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 162 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 163 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 164 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 165 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 166 {0x153b, 0x1136, "Terratec SiXPack 5.1+", NULL, NULL, NULL, 0}, 167 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 168 }; 169 170 static struct csa_card cards_4615[] = { 171 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 172 }; 173 174 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 175 176 struct card_type { 177 u_int32_t devid; 178 char *name; 179 struct csa_card *cards; 180 }; 181 182 static struct card_type cards[] = { 183 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 184 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 185 {CS4615_PCI_ID, "CS4615", cards_4615}, 186 {0, NULL, NULL}, 187 }; 188 189 static struct card_type * 190 csa_findcard(device_t dev) 191 { 192 int i; 193 194 i = 0; 195 while (cards[i].devid != 0) { 196 if (pci_get_devid(dev) == cards[i].devid) 197 return &cards[i]; 198 i++; 199 } 200 return NULL; 201 } 202 203 struct csa_card * 204 csa_findsubcard(device_t dev) 205 { 206 int i; 207 struct card_type *card; 208 struct csa_card *subcard; 209 210 card = csa_findcard(dev); 211 if (card == NULL) 212 return &nocard; 213 subcard = card->cards; 214 i = 0; 215 while (subcard[i].subvendor != 0) { 216 if (pci_get_subvendor(dev) == subcard[i].subvendor 217 && pci_get_subdevice(dev) == subcard[i].subdevice) { 218 return &subcard[i]; 219 } 220 i++; 221 } 222 return &subcard[i]; 223 } 224 225 static int 226 csa_probe(device_t dev) 227 { 228 struct card_type *card; 229 230 card = csa_findcard(dev); 231 if (card) { 232 device_set_desc(dev, card->name); 233 return BUS_PROBE_DEFAULT; 234 } 235 return ENXIO; 236 } 237 238 static int 239 csa_attach(device_t dev) 240 { 241 sc_p scp; 242 csa_res *resp; 243 struct sndcard_func *func; 244 int error = ENXIO; 245 246 scp = device_get_softc(dev); 247 248 /* Fill in the softc. */ 249 bzero(scp, sizeof(*scp)); 250 scp->dev = dev; 251 252 pci_enable_busmaster(dev); 253 254 /* Allocate the resources. */ 255 resp = &scp->res; 256 scp->card = csa_findsubcard(dev); 257 scp->binfo.card = scp->card; 258 printf("csa: card is %s\n", scp->card->name); 259 resp->io_rid = PCIR_BAR(0); 260 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 261 &resp->io_rid, RF_ACTIVE); 262 if (resp->io == NULL) 263 return (ENXIO); 264 resp->mem_rid = PCIR_BAR(1); 265 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 266 &resp->mem_rid, RF_ACTIVE); 267 if (resp->mem == NULL) 268 goto err_io; 269 resp->irq_rid = 0; 270 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 271 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 272 if (resp->irq == NULL) 273 goto err_mem; 274 275 /* Enable interrupt. */ 276 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 277 goto err_intr; 278 #if 0 279 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 280 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 281 #endif 282 283 /* Initialize the chip. */ 284 if (csa_initialize(scp)) 285 goto err_teardown; 286 287 /* Reset the Processor. */ 288 csa_resetdsp(resp); 289 290 /* Download the Processor Image to the processor. */ 291 if (csa_downloadimage(resp)) 292 goto err_teardown; 293 294 /* Attach the children. */ 295 296 /* PCM Audio */ 297 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 298 if (func == NULL) { 299 error = ENOMEM; 300 goto err_teardown; 301 } 302 func->varinfo = &scp->binfo; 303 func->func = SCF_PCM; 304 scp->pcm = device_add_child(dev, "pcm", -1); 305 device_set_ivars(scp->pcm, func); 306 307 /* Midi Interface */ 308 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 309 if (func == NULL) { 310 error = ENOMEM; 311 goto err_teardown; 312 } 313 func->varinfo = &scp->binfo; 314 func->func = SCF_MIDI; 315 scp->midi = device_add_child(dev, "midi", -1); 316 device_set_ivars(scp->midi, func); 317 318 bus_generic_attach(dev); 319 320 return (0); 321 322 err_teardown: 323 bus_teardown_intr(dev, resp->irq, scp->ih); 324 err_intr: 325 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 326 err_mem: 327 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 328 err_io: 329 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 330 return (error); 331 } 332 333 static int 334 csa_detach(device_t dev) 335 { 336 csa_res *resp; 337 sc_p scp; 338 struct sndcard_func *func; 339 int err; 340 341 scp = device_get_softc(dev); 342 resp = &scp->res; 343 344 if (scp->midi != NULL) { 345 func = device_get_ivars(scp->midi); 346 err = device_delete_child(dev, scp->midi); 347 if (err != 0) 348 return err; 349 if (func != NULL) 350 free(func, M_DEVBUF); 351 scp->midi = NULL; 352 } 353 354 if (scp->pcm != NULL) { 355 func = device_get_ivars(scp->pcm); 356 err = device_delete_child(dev, scp->pcm); 357 if (err != 0) 358 return err; 359 if (func != NULL) 360 free(func, M_DEVBUF); 361 scp->pcm = NULL; 362 } 363 364 bus_teardown_intr(dev, resp->irq, scp->ih); 365 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 366 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 367 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 368 369 return bus_generic_detach(dev); 370 } 371 372 static int 373 csa_resume(device_t dev) 374 { 375 csa_res *resp; 376 sc_p scp; 377 378 scp = device_get_softc(dev); 379 resp = &scp->res; 380 381 /* Initialize the chip. */ 382 if (csa_initialize(scp)) 383 return (ENXIO); 384 385 /* Reset the Processor. */ 386 csa_resetdsp(resp); 387 388 /* Download the Processor Image to the processor. */ 389 if (csa_downloadimage(resp)) 390 return (ENXIO); 391 392 return (bus_generic_resume(dev)); 393 } 394 395 static struct resource * 396 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 397 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 398 { 399 sc_p scp; 400 csa_res *resp; 401 struct resource *res; 402 403 scp = device_get_softc(bus); 404 resp = &scp->res; 405 switch (type) { 406 case SYS_RES_IRQ: 407 if (*rid != 0) 408 return (NULL); 409 res = resp->irq; 410 break; 411 case SYS_RES_MEMORY: 412 switch (*rid) { 413 case PCIR_BAR(0): 414 res = resp->io; 415 break; 416 case PCIR_BAR(1): 417 res = resp->mem; 418 break; 419 default: 420 return (NULL); 421 } 422 break; 423 default: 424 return (NULL); 425 } 426 427 return res; 428 } 429 430 static int 431 csa_release_resource(device_t bus, device_t child, struct resource *r) 432 { 433 return (0); 434 } 435 436 /* 437 * The following three functions deal with interrupt handling. 438 * An interrupt is primarily handled by the bridge driver. 439 * The bridge driver then determines the child devices to pass 440 * the interrupt. Certain information of the device can be read 441 * only once(eg the value of HISR). The bridge driver is responsible 442 * to pass such the information to the children. 443 */ 444 445 static int 446 csa_setup_intr(device_t bus, device_t child, 447 struct resource *irq, int flags, 448 driver_filter_t *filter, 449 driver_intr_t *intr, void *arg, void **cookiep) 450 { 451 sc_p scp; 452 csa_res *resp; 453 struct sndcard_func *func; 454 455 if (filter != NULL) { 456 printf("ata-csa.c: we cannot use a filter here\n"); 457 return (EINVAL); 458 } 459 scp = device_get_softc(bus); 460 resp = &scp->res; 461 462 /* 463 * Look at the function code of the child to determine 464 * the appropriate handler for it. 465 */ 466 func = device_get_ivars(child); 467 if (func == NULL || irq != resp->irq) 468 return (EINVAL); 469 470 switch (func->func) { 471 case SCF_PCM: 472 scp->pcmintr = intr; 473 scp->pcmintr_arg = arg; 474 break; 475 476 case SCF_MIDI: 477 scp->midiintr = intr; 478 scp->midiintr_arg = arg; 479 break; 480 481 default: 482 return (EINVAL); 483 } 484 *cookiep = scp; 485 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 486 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 487 488 return (0); 489 } 490 491 static int 492 csa_teardown_intr(device_t bus, device_t child, 493 struct resource *irq, void *cookie) 494 { 495 sc_p scp; 496 csa_res *resp; 497 struct sndcard_func *func; 498 499 scp = device_get_softc(bus); 500 resp = &scp->res; 501 502 /* 503 * Look at the function code of the child to determine 504 * the appropriate handler for it. 505 */ 506 func = device_get_ivars(child); 507 if (func == NULL || irq != resp->irq || cookie != scp) 508 return (EINVAL); 509 510 switch (func->func) { 511 case SCF_PCM: 512 scp->pcmintr = NULL; 513 scp->pcmintr_arg = NULL; 514 break; 515 516 case SCF_MIDI: 517 scp->midiintr = NULL; 518 scp->midiintr_arg = NULL; 519 break; 520 521 default: 522 return (EINVAL); 523 } 524 525 return (0); 526 } 527 528 /* The interrupt handler */ 529 static void 530 csa_intr(void *arg) 531 { 532 sc_p scp = arg; 533 csa_res *resp; 534 u_int32_t hisr; 535 536 resp = &scp->res; 537 538 /* Is this interrupt for us? */ 539 hisr = csa_readio(resp, BA0_HISR); 540 if ((hisr & 0x7fffffff) == 0) { 541 /* Throw an eoi. */ 542 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 543 return; 544 } 545 546 /* 547 * Pass the value of HISR via struct csa_bridgeinfo. 548 * The children get access through their ivars. 549 */ 550 scp->binfo.hisr = hisr; 551 552 /* Invoke the handlers of the children. */ 553 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 554 scp->pcmintr(scp->pcmintr_arg); 555 hisr &= ~(HISR_VC0 | HISR_VC1); 556 } 557 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 558 scp->midiintr(scp->midiintr_arg); 559 hisr &= ~HISR_MIDI; 560 } 561 562 /* Throw an eoi. */ 563 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 564 } 565 566 static int 567 csa_initialize(sc_p scp) 568 { 569 int i; 570 u_int32_t acsts, acisv; 571 csa_res *resp; 572 573 resp = &scp->res; 574 575 /* 576 * First, blast the clock control register to zero so that the PLL starts 577 * out in a known state, and blast the master serial port control register 578 * to zero so that the serial ports also start out in a known state. 579 */ 580 csa_writeio(resp, BA0_CLKCR1, 0); 581 csa_writeio(resp, BA0_SERMC1, 0); 582 583 /* 584 * If we are in AC97 mode, then we must set the part to a host controlled 585 * AC-link. Otherwise, we won't be able to bring up the link. 586 */ 587 #if 1 588 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 589 #else 590 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 591 #endif /* 1 */ 592 593 /* 594 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 595 * spec) and then drive it high. This is done for non AC97 modes since 596 * there might be logic external to the CS461x that uses the ARST# line 597 * for a reset. 598 */ 599 csa_writeio(resp, BA0_ACCTL, 1); 600 DELAY(50); 601 csa_writeio(resp, BA0_ACCTL, 0); 602 DELAY(50); 603 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 604 605 /* 606 * The first thing we do here is to enable sync generation. As soon 607 * as we start receiving bit clock, we'll start producing the SYNC 608 * signal. 609 */ 610 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 611 612 /* 613 * Now wait for a short while to allow the AC97 part to start 614 * generating bit clock (so we don't try to start the PLL without an 615 * input clock). 616 */ 617 DELAY(50000); 618 619 /* 620 * Set the serial port timing configuration, so that 621 * the clock control circuit gets its clock from the correct place. 622 */ 623 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 624 DELAY(700000); 625 626 /* 627 * Write the selected clock control setup to the hardware. Do not turn on 628 * SWCE yet (if requested), so that the devices clocked by the output of 629 * PLL are not clocked until the PLL is stable. 630 */ 631 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 632 csa_writeio(resp, BA0_PLLM, 0x3a); 633 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 634 635 /* 636 * Power up the PLL. 637 */ 638 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 639 640 /* 641 * Wait until the PLL has stabilized. 642 */ 643 DELAY(5000); 644 645 /* 646 * Turn on clocking of the core so that we can setup the serial ports. 647 */ 648 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 649 650 /* 651 * Fill the serial port FIFOs with silence. 652 */ 653 csa_clearserialfifos(resp); 654 655 /* 656 * Set the serial port FIFO pointer to the first sample in the FIFO. 657 */ 658 #ifdef notdef 659 csa_writeio(resp, BA0_SERBSP, 0); 660 #endif /* notdef */ 661 662 /* 663 * Write the serial port configuration to the part. The master 664 * enable bit is not set until all other values have been written. 665 */ 666 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 667 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 668 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 669 670 /* 671 * Wait for the codec ready signal from the AC97 codec. 672 */ 673 acsts = 0; 674 for (i = 0 ; i < 1000 ; i++) { 675 /* 676 * First, lets wait a short while to let things settle out a bit, 677 * and to prevent retrying the read too quickly. 678 */ 679 DELAY(125); 680 681 /* 682 * Read the AC97 status register to see if we've seen a CODEC READY 683 * signal from the AC97 codec. 684 */ 685 acsts = csa_readio(resp, BA0_ACSTS); 686 if ((acsts & ACSTS_CRDY) != 0) 687 break; 688 } 689 690 /* 691 * Make sure we sampled CODEC READY. 692 */ 693 if ((acsts & ACSTS_CRDY) == 0) 694 return (ENXIO); 695 696 /* 697 * Assert the vaid frame signal so that we can start sending commands 698 * to the AC97 codec. 699 */ 700 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 701 702 /* 703 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 704 * the codec is pumping ADC data across the AC-link. 705 */ 706 acisv = 0; 707 for (i = 0 ; i < 2000 ; i++) { 708 /* 709 * First, lets wait a short while to let things settle out a bit, 710 * and to prevent retrying the read too quickly. 711 */ 712 #ifdef notdef 713 DELAY(10000000L); /* clw */ 714 #else 715 DELAY(1000); 716 #endif /* notdef */ 717 /* 718 * Read the input slot valid register and see if input slots 3 and 719 * 4 are valid yet. 720 */ 721 acisv = csa_readio(resp, BA0_ACISV); 722 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 723 break; 724 } 725 /* 726 * Make sure we sampled valid input slots 3 and 4. If not, then return 727 * an error. 728 */ 729 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 730 return (ENXIO); 731 732 /* 733 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 734 * commense the transfer of digital audio data to the AC97 codec. 735 */ 736 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 737 738 /* 739 * Power down the DAC and ADC. We will power them up (if) when we need 740 * them. 741 */ 742 #ifdef notdef 743 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 744 #endif /* notdef */ 745 746 /* 747 * Turn off the Processor by turning off the software clock enable flag in 748 * the clock control register. 749 */ 750 #ifdef notdef 751 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 752 csa_writeio(resp, BA0_CLKCR1, clkcr1); 753 #endif /* notdef */ 754 755 /* 756 * Enable interrupts on the part. 757 */ 758 #if 0 759 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 760 #endif /* notdef */ 761 762 return (0); 763 } 764 765 void 766 csa_clearserialfifos(csa_res *resp) 767 { 768 int i, j, pwr; 769 u_int8_t clkcr1, serbst; 770 771 /* 772 * See if the devices are powered down. If so, we must power them up first 773 * or they will not respond. 774 */ 775 pwr = 1; 776 clkcr1 = csa_readio(resp, BA0_CLKCR1); 777 if ((clkcr1 & CLKCR1_SWCE) == 0) { 778 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 779 pwr = 0; 780 } 781 782 /* 783 * We want to clear out the serial port FIFOs so we don't end up playing 784 * whatever random garbage happens to be in them. We fill the sample FIFOs 785 * with zero (silence). 786 */ 787 csa_writeio(resp, BA0_SERBWP, 0); 788 789 /* Fill all 256 sample FIFO locations. */ 790 serbst = 0; 791 for (i = 0 ; i < 256 ; i++) { 792 /* Make sure the previous FIFO write operation has completed. */ 793 for (j = 0 ; j < 5 ; j++) { 794 DELAY(100); 795 serbst = csa_readio(resp, BA0_SERBST); 796 if ((serbst & SERBST_WBSY) == 0) 797 break; 798 } 799 if ((serbst & SERBST_WBSY) != 0) { 800 if (!pwr) 801 csa_writeio(resp, BA0_CLKCR1, clkcr1); 802 } 803 /* Write the serial port FIFO index. */ 804 csa_writeio(resp, BA0_SERBAD, i); 805 /* Tell the serial port to load the new value into the FIFO location. */ 806 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 807 } 808 /* 809 * Now, if we powered up the devices, then power them back down again. 810 * This is kinda ugly, but should never happen. 811 */ 812 if (!pwr) 813 csa_writeio(resp, BA0_CLKCR1, clkcr1); 814 } 815 816 void 817 csa_resetdsp(csa_res *resp) 818 { 819 int i; 820 821 /* 822 * Write the reset bit of the SP control register. 823 */ 824 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 825 826 /* 827 * Write the control register. 828 */ 829 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 830 831 /* 832 * Clear the trap registers. 833 */ 834 for (i = 0 ; i < 8 ; i++) { 835 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 836 csa_writemem(resp, BA1_TWPR, 0xffff); 837 } 838 csa_writemem(resp, BA1_DREG, 0); 839 840 /* 841 * Set the frame timer to reflect the number of cycles per frame. 842 */ 843 csa_writemem(resp, BA1_FRMT, 0xadf); 844 } 845 846 static int 847 csa_downloadimage(csa_res *resp) 848 { 849 int ret; 850 u_long ul, offset; 851 852 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 853 /* 854 * DMA this block from host memory to the appropriate 855 * memory on the CSDevice. 856 */ 857 ret = csa_transferimage(resp, 858 cs461x_firmware.BA1Array + offset, 859 cs461x_firmware.MemoryStat[ul].ulDestAddr, 860 cs461x_firmware.MemoryStat[ul].ulSourceSize); 861 if (ret) 862 return (ret); 863 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2; 864 } 865 return (0); 866 } 867 868 static int 869 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len) 870 { 871 u_long ul; 872 873 /* 874 * We do not allow DMAs from host memory to host memory (although the DMA 875 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 876 * in size (because that DMA can not do that). Return an error if either 877 * of these conditions exist. 878 */ 879 if ((len & 0x3) != 0) 880 return (EINVAL); 881 882 /* Check the destination address that it is a multiple of 4 */ 883 if ((dest & 0x3) != 0) 884 return (EINVAL); 885 886 /* Write the buffer out. */ 887 for (ul = 0 ; ul < len ; ul += 4) 888 csa_writemem(resp, dest + ul, src[ul >> 2]); 889 return (0); 890 } 891 892 int 893 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 894 { 895 int i; 896 u_int32_t acctl, acsts; 897 898 /* 899 * Make sure that there is not data sitting around from a previous 900 * uncompleted access. ACSDA = Status Data Register = 47Ch 901 */ 902 csa_readio(resp, BA0_ACSDA); 903 904 /* 905 * Setup the AC97 control registers on the CS461x to send the 906 * appropriate command to the AC97 to perform the read. 907 * ACCAD = Command Address Register = 46Ch 908 * ACCDA = Command Data Register = 470h 909 * ACCTL = Control Register = 460h 910 * set DCV - will clear when process completed 911 * set CRW - Read command 912 * set VFRM - valid frame enabled 913 * set ESYN - ASYNC generation enabled 914 * set RSTN - ARST# inactive, AC97 codec not reset 915 */ 916 917 /* 918 * Get the actual AC97 register from the offset 919 */ 920 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 921 csa_writeio(resp, BA0_ACCDA, 0); 922 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 923 924 /* 925 * Wait for the read to occur. 926 */ 927 acctl = 0; 928 for (i = 0 ; i < 10 ; i++) { 929 /* 930 * First, we want to wait for a short time. 931 */ 932 DELAY(25); 933 934 /* 935 * Now, check to see if the read has completed. 936 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 937 */ 938 acctl = csa_readio(resp, BA0_ACCTL); 939 if ((acctl & ACCTL_DCV) == 0) 940 break; 941 } 942 943 /* 944 * Make sure the read completed. 945 */ 946 if ((acctl & ACCTL_DCV) != 0) 947 return (EAGAIN); 948 949 /* 950 * Wait for the valid status bit to go active. 951 */ 952 acsts = 0; 953 for (i = 0 ; i < 10 ; i++) { 954 /* 955 * Read the AC97 status register. 956 * ACSTS = Status Register = 464h 957 */ 958 acsts = csa_readio(resp, BA0_ACSTS); 959 /* 960 * See if we have valid status. 961 * VSTS - Valid Status 962 */ 963 if ((acsts & ACSTS_VSTS) != 0) 964 break; 965 /* 966 * Wait for a short while. 967 */ 968 DELAY(25); 969 } 970 971 /* 972 * Make sure we got valid status. 973 */ 974 if ((acsts & ACSTS_VSTS) == 0) 975 return (EAGAIN); 976 977 /* 978 * Read the data returned from the AC97 register. 979 * ACSDA = Status Data Register = 474h 980 */ 981 *data = csa_readio(resp, BA0_ACSDA); 982 983 return (0); 984 } 985 986 int 987 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 988 { 989 int i; 990 u_int32_t acctl; 991 992 /* 993 * Setup the AC97 control registers on the CS461x to send the 994 * appropriate command to the AC97 to perform the write. 995 * ACCAD = Command Address Register = 46Ch 996 * ACCDA = Command Data Register = 470h 997 * ACCTL = Control Register = 460h 998 * set DCV - will clear when process completed 999 * set VFRM - valid frame enabled 1000 * set ESYN - ASYNC generation enabled 1001 * set RSTN - ARST# inactive, AC97 codec not reset 1002 */ 1003 1004 /* 1005 * Get the actual AC97 register from the offset 1006 */ 1007 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 1008 csa_writeio(resp, BA0_ACCDA, data); 1009 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1010 1011 /* 1012 * Wait for the write to occur. 1013 */ 1014 acctl = 0; 1015 for (i = 0 ; i < 10 ; i++) { 1016 /* 1017 * First, we want to wait for a short time. 1018 */ 1019 DELAY(25); 1020 1021 /* 1022 * Now, check to see if the read has completed. 1023 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1024 */ 1025 acctl = csa_readio(resp, BA0_ACCTL); 1026 if ((acctl & ACCTL_DCV) == 0) 1027 break; 1028 } 1029 1030 /* 1031 * Make sure the write completed. 1032 */ 1033 if ((acctl & ACCTL_DCV) != 0) 1034 return (EAGAIN); 1035 1036 return (0); 1037 } 1038 1039 u_int32_t 1040 csa_readio(csa_res *resp, u_long offset) 1041 { 1042 u_int32_t ul; 1043 1044 if (offset < BA0_AC97_RESET) 1045 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1046 else { 1047 if (csa_readcodec(resp, offset, &ul)) 1048 ul = 0; 1049 return (ul); 1050 } 1051 } 1052 1053 void 1054 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1055 { 1056 if (offset < BA0_AC97_RESET) 1057 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1058 else 1059 csa_writecodec(resp, offset, data); 1060 } 1061 1062 u_int32_t 1063 csa_readmem(csa_res *resp, u_long offset) 1064 { 1065 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1066 } 1067 1068 void 1069 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1070 { 1071 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1072 } 1073 1074 static device_method_t csa_methods[] = { 1075 /* Device interface */ 1076 DEVMETHOD(device_probe, csa_probe), 1077 DEVMETHOD(device_attach, csa_attach), 1078 DEVMETHOD(device_detach, csa_detach), 1079 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1080 DEVMETHOD(device_suspend, bus_generic_suspend), 1081 DEVMETHOD(device_resume, csa_resume), 1082 1083 /* Bus interface */ 1084 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1085 DEVMETHOD(bus_release_resource, csa_release_resource), 1086 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1087 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1088 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1089 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1090 1091 DEVMETHOD_END 1092 }; 1093 1094 static driver_t csa_driver = { 1095 "csa", 1096 csa_methods, 1097 sizeof(struct csa_softc), 1098 }; 1099 1100 /* 1101 * csa can be attached to a pci bus. 1102 */ 1103 DRIVER_MODULE(snd_csa, pci, csa_driver, 0, 0); 1104 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1105 MODULE_VERSION(snd_csa, 1); 1106