1 /*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 41 #ifdef HAVE_KERNEL_OPTION_HEADERS 42 #include "opt_snd.h" 43 #endif 44 45 #include <dev/sound/pcm/sound.h> 46 #include <dev/sound/chip.h> 47 #include <dev/sound/pci/csareg.h> 48 #include <dev/sound/pci/csavar.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <dev/sound/pci/cs461x_dsp.h> 54 55 SND_DECLARE_FILE("$FreeBSD$"); 56 57 /* This is the pci device id. */ 58 #define CS4610_PCI_ID 0x60011013 59 #define CS4614_PCI_ID 0x60031013 60 #define CS4615_PCI_ID 0x60041013 61 62 /* Here is the parameter structure per a device. */ 63 struct csa_softc { 64 device_t dev; /* device */ 65 csa_res res; /* resources */ 66 67 device_t pcm; /* pcm device */ 68 driver_intr_t* pcmintr; /* pcm intr */ 69 void *pcmintr_arg; /* pcm intr arg */ 70 device_t midi; /* midi device */ 71 driver_intr_t* midiintr; /* midi intr */ 72 void *midiintr_arg; /* midi intr arg */ 73 void *ih; /* cookie */ 74 75 struct csa_card *card; 76 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 77 }; 78 79 typedef struct csa_softc *sc_p; 80 81 static int csa_probe(device_t dev); 82 static int csa_attach(device_t dev); 83 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 84 u_long start, u_long end, u_long count, u_int flags); 85 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 86 struct resource *r); 87 static int csa_setup_intr(device_t bus, device_t child, 88 struct resource *irq, int flags, 89 driver_filter_t *filter, 90 driver_intr_t *intr, void *arg, void **cookiep); 91 static int csa_teardown_intr(device_t bus, device_t child, 92 struct resource *irq, void *cookie); 93 static driver_intr_t csa_intr; 94 static int csa_initialize(sc_p scp); 95 static int csa_downloadimage(csa_res *resp); 96 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len); 97 98 static devclass_t csa_devclass; 99 100 static void 101 amp_none(void) 102 { 103 } 104 105 static void 106 amp_voyetra(void) 107 { 108 } 109 110 static int 111 clkrun_hack(int run) 112 { 113 #ifdef __i386__ 114 devclass_t pci_devclass; 115 device_t *pci_devices, *pci_children, *busp, *childp; 116 int pci_count = 0, pci_childcount = 0; 117 int i, j, port; 118 u_int16_t control; 119 bus_space_tag_t btag; 120 121 if ((pci_devclass = devclass_find("pci")) == NULL) { 122 return ENXIO; 123 } 124 125 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 126 127 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 128 pci_childcount = 0; 129 if (device_get_children(*busp, &pci_children, &pci_childcount)) 130 continue; 131 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 132 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 133 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 134 /* XXX */ 135 btag = X86_BUS_SPACE_IO; 136 137 control = bus_space_read_2(btag, 0x0, port); 138 control &= ~0x2000; 139 control |= run? 0 : 0x2000; 140 bus_space_write_2(btag, 0x0, port, control); 141 free(pci_devices, M_TEMP); 142 free(pci_children, M_TEMP); 143 return 0; 144 } 145 } 146 free(pci_children, M_TEMP); 147 } 148 149 free(pci_devices, M_TEMP); 150 return ENXIO; 151 #else 152 return 0; 153 #endif 154 } 155 156 static struct csa_card cards_4610[] = { 157 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 158 }; 159 160 static struct csa_card cards_4614[] = { 161 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 162 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 163 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 164 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 165 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 166 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 167 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 168 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 169 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 170 }; 171 172 static struct csa_card cards_4615[] = { 173 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 174 }; 175 176 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 177 178 struct card_type { 179 u_int32_t devid; 180 char *name; 181 struct csa_card *cards; 182 }; 183 184 static struct card_type cards[] = { 185 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 186 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 187 {CS4615_PCI_ID, "CS4615", cards_4615}, 188 {0, NULL, NULL}, 189 }; 190 191 static struct card_type * 192 csa_findcard(device_t dev) 193 { 194 int i; 195 196 i = 0; 197 while (cards[i].devid != 0) { 198 if (pci_get_devid(dev) == cards[i].devid) 199 return &cards[i]; 200 i++; 201 } 202 return NULL; 203 } 204 205 struct csa_card * 206 csa_findsubcard(device_t dev) 207 { 208 int i; 209 struct card_type *card; 210 struct csa_card *subcard; 211 212 card = csa_findcard(dev); 213 if (card == NULL) 214 return &nocard; 215 subcard = card->cards; 216 i = 0; 217 while (subcard[i].subvendor != 0) { 218 if (pci_get_subvendor(dev) == subcard[i].subvendor 219 && pci_get_subdevice(dev) == subcard[i].subdevice) { 220 return &subcard[i]; 221 } 222 i++; 223 } 224 return &subcard[i]; 225 } 226 227 static int 228 csa_probe(device_t dev) 229 { 230 struct card_type *card; 231 232 card = csa_findcard(dev); 233 if (card) { 234 device_set_desc(dev, card->name); 235 return BUS_PROBE_DEFAULT; 236 } 237 return ENXIO; 238 } 239 240 static int 241 csa_attach(device_t dev) 242 { 243 sc_p scp; 244 csa_res *resp; 245 struct sndcard_func *func; 246 int error = ENXIO; 247 248 scp = device_get_softc(dev); 249 250 /* Fill in the softc. */ 251 bzero(scp, sizeof(*scp)); 252 scp->dev = dev; 253 254 pci_enable_busmaster(dev); 255 256 /* Allocate the resources. */ 257 resp = &scp->res; 258 scp->card = csa_findsubcard(dev); 259 scp->binfo.card = scp->card; 260 printf("csa: card is %s\n", scp->card->name); 261 resp->io_rid = PCIR_BAR(0); 262 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 263 &resp->io_rid, RF_ACTIVE); 264 if (resp->io == NULL) 265 return (ENXIO); 266 resp->mem_rid = PCIR_BAR(1); 267 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 268 &resp->mem_rid, RF_ACTIVE); 269 if (resp->mem == NULL) 270 goto err_io; 271 resp->irq_rid = 0; 272 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 273 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 274 if (resp->irq == NULL) 275 goto err_mem; 276 277 /* Enable interrupt. */ 278 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 279 goto err_intr; 280 #if 0 281 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 282 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 283 #endif 284 285 /* Initialize the chip. */ 286 if (csa_initialize(scp)) 287 goto err_teardown; 288 289 /* Reset the Processor. */ 290 csa_resetdsp(resp); 291 292 /* Download the Processor Image to the processor. */ 293 if (csa_downloadimage(resp)) 294 goto err_teardown; 295 296 /* Attach the children. */ 297 298 /* PCM Audio */ 299 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 300 if (func == NULL) { 301 error = ENOMEM; 302 goto err_teardown; 303 } 304 func->varinfo = &scp->binfo; 305 func->func = SCF_PCM; 306 scp->pcm = device_add_child(dev, "pcm", -1); 307 device_set_ivars(scp->pcm, func); 308 309 /* Midi Interface */ 310 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 311 if (func == NULL) { 312 error = ENOMEM; 313 goto err_teardown; 314 } 315 func->varinfo = &scp->binfo; 316 func->func = SCF_MIDI; 317 scp->midi = device_add_child(dev, "midi", -1); 318 device_set_ivars(scp->midi, func); 319 320 bus_generic_attach(dev); 321 322 return (0); 323 324 err_teardown: 325 bus_teardown_intr(dev, resp->irq, scp->ih); 326 err_intr: 327 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 328 err_mem: 329 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 330 err_io: 331 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 332 return (error); 333 } 334 335 static int 336 csa_detach(device_t dev) 337 { 338 csa_res *resp; 339 sc_p scp; 340 struct sndcard_func *func; 341 int err; 342 343 scp = device_get_softc(dev); 344 resp = &scp->res; 345 346 if (scp->midi != NULL) { 347 func = device_get_ivars(scp->midi); 348 err = device_delete_child(dev, scp->midi); 349 if (err != 0) 350 return err; 351 if (func != NULL) 352 free(func, M_DEVBUF); 353 scp->midi = NULL; 354 } 355 356 if (scp->pcm != NULL) { 357 func = device_get_ivars(scp->pcm); 358 err = device_delete_child(dev, scp->pcm); 359 if (err != 0) 360 return err; 361 if (func != NULL) 362 free(func, M_DEVBUF); 363 scp->pcm = NULL; 364 } 365 366 bus_teardown_intr(dev, resp->irq, scp->ih); 367 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 368 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 369 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 370 371 return bus_generic_detach(dev); 372 } 373 374 static int 375 csa_resume(device_t dev) 376 { 377 csa_res *resp; 378 sc_p scp; 379 380 scp = device_get_softc(dev); 381 resp = &scp->res; 382 383 /* Initialize the chip. */ 384 if (csa_initialize(scp)) 385 return (ENXIO); 386 387 /* Reset the Processor. */ 388 csa_resetdsp(resp); 389 390 /* Download the Processor Image to the processor. */ 391 if (csa_downloadimage(resp)) 392 return (ENXIO); 393 394 return (bus_generic_resume(dev)); 395 } 396 397 static struct resource * 398 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 399 u_long start, u_long end, u_long count, u_int flags) 400 { 401 sc_p scp; 402 csa_res *resp; 403 struct resource *res; 404 405 scp = device_get_softc(bus); 406 resp = &scp->res; 407 switch (type) { 408 case SYS_RES_IRQ: 409 if (*rid != 0) 410 return (NULL); 411 res = resp->irq; 412 break; 413 case SYS_RES_MEMORY: 414 switch (*rid) { 415 case PCIR_BAR(0): 416 res = resp->io; 417 break; 418 case PCIR_BAR(1): 419 res = resp->mem; 420 break; 421 default: 422 return (NULL); 423 } 424 break; 425 default: 426 return (NULL); 427 } 428 429 return res; 430 } 431 432 static int 433 csa_release_resource(device_t bus, device_t child, int type, int rid, 434 struct resource *r) 435 { 436 return (0); 437 } 438 439 /* 440 * The following three functions deal with interrupt handling. 441 * An interrupt is primarily handled by the bridge driver. 442 * The bridge driver then determines the child devices to pass 443 * the interrupt. Certain information of the device can be read 444 * only once(eg the value of HISR). The bridge driver is responsible 445 * to pass such the information to the children. 446 */ 447 448 static int 449 csa_setup_intr(device_t bus, device_t child, 450 struct resource *irq, int flags, 451 driver_filter_t *filter, 452 driver_intr_t *intr, void *arg, void **cookiep) 453 { 454 sc_p scp; 455 csa_res *resp; 456 struct sndcard_func *func; 457 458 if (filter != NULL) { 459 printf("ata-csa.c: we cannot use a filter here\n"); 460 return (EINVAL); 461 } 462 scp = device_get_softc(bus); 463 resp = &scp->res; 464 465 /* 466 * Look at the function code of the child to determine 467 * the appropriate hander for it. 468 */ 469 func = device_get_ivars(child); 470 if (func == NULL || irq != resp->irq) 471 return (EINVAL); 472 473 switch (func->func) { 474 case SCF_PCM: 475 scp->pcmintr = intr; 476 scp->pcmintr_arg = arg; 477 break; 478 479 case SCF_MIDI: 480 scp->midiintr = intr; 481 scp->midiintr_arg = arg; 482 break; 483 484 default: 485 return (EINVAL); 486 } 487 *cookiep = scp; 488 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 489 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 490 491 return (0); 492 } 493 494 static int 495 csa_teardown_intr(device_t bus, device_t child, 496 struct resource *irq, void *cookie) 497 { 498 sc_p scp; 499 csa_res *resp; 500 struct sndcard_func *func; 501 502 scp = device_get_softc(bus); 503 resp = &scp->res; 504 505 /* 506 * Look at the function code of the child to determine 507 * the appropriate hander for it. 508 */ 509 func = device_get_ivars(child); 510 if (func == NULL || irq != resp->irq || cookie != scp) 511 return (EINVAL); 512 513 switch (func->func) { 514 case SCF_PCM: 515 scp->pcmintr = NULL; 516 scp->pcmintr_arg = NULL; 517 break; 518 519 case SCF_MIDI: 520 scp->midiintr = NULL; 521 scp->midiintr_arg = NULL; 522 break; 523 524 default: 525 return (EINVAL); 526 } 527 528 return (0); 529 } 530 531 /* The interrupt handler */ 532 static void 533 csa_intr(void *arg) 534 { 535 sc_p scp = arg; 536 csa_res *resp; 537 u_int32_t hisr; 538 539 resp = &scp->res; 540 541 /* Is this interrupt for us? */ 542 hisr = csa_readio(resp, BA0_HISR); 543 if ((hisr & 0x7fffffff) == 0) { 544 /* Throw an eoi. */ 545 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 546 return; 547 } 548 549 /* 550 * Pass the value of HISR via struct csa_bridgeinfo. 551 * The children get access through their ivars. 552 */ 553 scp->binfo.hisr = hisr; 554 555 /* Invoke the handlers of the children. */ 556 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 557 scp->pcmintr(scp->pcmintr_arg); 558 hisr &= ~(HISR_VC0 | HISR_VC1); 559 } 560 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 561 scp->midiintr(scp->midiintr_arg); 562 hisr &= ~HISR_MIDI; 563 } 564 565 /* Throw an eoi. */ 566 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 567 } 568 569 static int 570 csa_initialize(sc_p scp) 571 { 572 int i; 573 u_int32_t acsts, acisv; 574 csa_res *resp; 575 576 resp = &scp->res; 577 578 /* 579 * First, blast the clock control register to zero so that the PLL starts 580 * out in a known state, and blast the master serial port control register 581 * to zero so that the serial ports also start out in a known state. 582 */ 583 csa_writeio(resp, BA0_CLKCR1, 0); 584 csa_writeio(resp, BA0_SERMC1, 0); 585 586 /* 587 * If we are in AC97 mode, then we must set the part to a host controlled 588 * AC-link. Otherwise, we won't be able to bring up the link. 589 */ 590 #if 1 591 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 592 #else 593 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 594 #endif /* 1 */ 595 596 /* 597 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 598 * spec) and then drive it high. This is done for non AC97 modes since 599 * there might be logic external to the CS461x that uses the ARST# line 600 * for a reset. 601 */ 602 csa_writeio(resp, BA0_ACCTL, 1); 603 DELAY(50); 604 csa_writeio(resp, BA0_ACCTL, 0); 605 DELAY(50); 606 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 607 608 /* 609 * The first thing we do here is to enable sync generation. As soon 610 * as we start receiving bit clock, we'll start producing the SYNC 611 * signal. 612 */ 613 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 614 615 /* 616 * Now wait for a short while to allow the AC97 part to start 617 * generating bit clock (so we don't try to start the PLL without an 618 * input clock). 619 */ 620 DELAY(50000); 621 622 /* 623 * Set the serial port timing configuration, so that 624 * the clock control circuit gets its clock from the correct place. 625 */ 626 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 627 DELAY(700000); 628 629 /* 630 * Write the selected clock control setup to the hardware. Do not turn on 631 * SWCE yet (if requested), so that the devices clocked by the output of 632 * PLL are not clocked until the PLL is stable. 633 */ 634 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 635 csa_writeio(resp, BA0_PLLM, 0x3a); 636 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 637 638 /* 639 * Power up the PLL. 640 */ 641 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 642 643 /* 644 * Wait until the PLL has stabilized. 645 */ 646 DELAY(5000); 647 648 /* 649 * Turn on clocking of the core so that we can setup the serial ports. 650 */ 651 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 652 653 /* 654 * Fill the serial port FIFOs with silence. 655 */ 656 csa_clearserialfifos(resp); 657 658 /* 659 * Set the serial port FIFO pointer to the first sample in the FIFO. 660 */ 661 #ifdef notdef 662 csa_writeio(resp, BA0_SERBSP, 0); 663 #endif /* notdef */ 664 665 /* 666 * Write the serial port configuration to the part. The master 667 * enable bit is not set until all other values have been written. 668 */ 669 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 670 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 671 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 672 673 /* 674 * Wait for the codec ready signal from the AC97 codec. 675 */ 676 acsts = 0; 677 for (i = 0 ; i < 1000 ; i++) { 678 /* 679 * First, lets wait a short while to let things settle out a bit, 680 * and to prevent retrying the read too quickly. 681 */ 682 DELAY(125); 683 684 /* 685 * Read the AC97 status register to see if we've seen a CODEC READY 686 * signal from the AC97 codec. 687 */ 688 acsts = csa_readio(resp, BA0_ACSTS); 689 if ((acsts & ACSTS_CRDY) != 0) 690 break; 691 } 692 693 /* 694 * Make sure we sampled CODEC READY. 695 */ 696 if ((acsts & ACSTS_CRDY) == 0) 697 return (ENXIO); 698 699 /* 700 * Assert the vaid frame signal so that we can start sending commands 701 * to the AC97 codec. 702 */ 703 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 704 705 /* 706 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 707 * the codec is pumping ADC data across the AC-link. 708 */ 709 acisv = 0; 710 for (i = 0 ; i < 1000 ; i++) { 711 /* 712 * First, lets wait a short while to let things settle out a bit, 713 * and to prevent retrying the read too quickly. 714 */ 715 #ifdef notdef 716 DELAY(10000000L); /* clw */ 717 #else 718 DELAY(1000); 719 #endif /* notdef */ 720 /* 721 * Read the input slot valid register and see if input slots 3 and 722 * 4 are valid yet. 723 */ 724 acisv = csa_readio(resp, BA0_ACISV); 725 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 726 break; 727 } 728 /* 729 * Make sure we sampled valid input slots 3 and 4. If not, then return 730 * an error. 731 */ 732 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 733 return (ENXIO); 734 735 /* 736 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 737 * commense the transfer of digital audio data to the AC97 codec. 738 */ 739 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 740 741 /* 742 * Power down the DAC and ADC. We will power them up (if) when we need 743 * them. 744 */ 745 #ifdef notdef 746 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 747 #endif /* notdef */ 748 749 /* 750 * Turn off the Processor by turning off the software clock enable flag in 751 * the clock control register. 752 */ 753 #ifdef notdef 754 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 755 csa_writeio(resp, BA0_CLKCR1, clkcr1); 756 #endif /* notdef */ 757 758 /* 759 * Enable interrupts on the part. 760 */ 761 #if 0 762 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 763 #endif /* notdef */ 764 765 return (0); 766 } 767 768 void 769 csa_clearserialfifos(csa_res *resp) 770 { 771 int i, j, pwr; 772 u_int8_t clkcr1, serbst; 773 774 /* 775 * See if the devices are powered down. If so, we must power them up first 776 * or they will not respond. 777 */ 778 pwr = 1; 779 clkcr1 = csa_readio(resp, BA0_CLKCR1); 780 if ((clkcr1 & CLKCR1_SWCE) == 0) { 781 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 782 pwr = 0; 783 } 784 785 /* 786 * We want to clear out the serial port FIFOs so we don't end up playing 787 * whatever random garbage happens to be in them. We fill the sample FIFOs 788 * with zero (silence). 789 */ 790 csa_writeio(resp, BA0_SERBWP, 0); 791 792 /* Fill all 256 sample FIFO locations. */ 793 serbst = 0; 794 for (i = 0 ; i < 256 ; i++) { 795 /* Make sure the previous FIFO write operation has completed. */ 796 for (j = 0 ; j < 5 ; j++) { 797 DELAY(100); 798 serbst = csa_readio(resp, BA0_SERBST); 799 if ((serbst & SERBST_WBSY) == 0) 800 break; 801 } 802 if ((serbst & SERBST_WBSY) != 0) { 803 if (!pwr) 804 csa_writeio(resp, BA0_CLKCR1, clkcr1); 805 } 806 /* Write the serial port FIFO index. */ 807 csa_writeio(resp, BA0_SERBAD, i); 808 /* Tell the serial port to load the new value into the FIFO location. */ 809 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 810 } 811 /* 812 * Now, if we powered up the devices, then power them back down again. 813 * This is kinda ugly, but should never happen. 814 */ 815 if (!pwr) 816 csa_writeio(resp, BA0_CLKCR1, clkcr1); 817 } 818 819 void 820 csa_resetdsp(csa_res *resp) 821 { 822 int i; 823 824 /* 825 * Write the reset bit of the SP control register. 826 */ 827 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 828 829 /* 830 * Write the control register. 831 */ 832 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 833 834 /* 835 * Clear the trap registers. 836 */ 837 for (i = 0 ; i < 8 ; i++) { 838 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 839 csa_writemem(resp, BA1_TWPR, 0xffff); 840 } 841 csa_writemem(resp, BA1_DREG, 0); 842 843 /* 844 * Set the frame timer to reflect the number of cycles per frame. 845 */ 846 csa_writemem(resp, BA1_FRMT, 0xadf); 847 } 848 849 static int 850 csa_downloadimage(csa_res *resp) 851 { 852 int ret; 853 u_long ul, offset; 854 855 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 856 /* 857 * DMA this block from host memory to the appropriate 858 * memory on the CSDevice. 859 */ 860 ret = csa_transferimage(resp, 861 cs461x_firmware.BA1Array + offset, 862 cs461x_firmware.MemoryStat[ul].ulDestAddr, 863 cs461x_firmware.MemoryStat[ul].ulSourceSize); 864 if (ret) 865 return (ret); 866 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2; 867 } 868 return (0); 869 } 870 871 static int 872 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len) 873 { 874 u_long ul; 875 876 /* 877 * We do not allow DMAs from host memory to host memory (although the DMA 878 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 879 * in size (because that DMA can not do that). Return an error if either 880 * of these conditions exist. 881 */ 882 if ((len & 0x3) != 0) 883 return (EINVAL); 884 885 /* Check the destination address that it is a multiple of 4 */ 886 if ((dest & 0x3) != 0) 887 return (EINVAL); 888 889 /* Write the buffer out. */ 890 for (ul = 0 ; ul < len ; ul += 4) 891 csa_writemem(resp, dest + ul, src[ul >> 2]); 892 return (0); 893 } 894 895 int 896 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 897 { 898 int i; 899 u_int32_t acctl, acsts; 900 901 /* 902 * Make sure that there is not data sitting around from a previous 903 * uncompleted access. ACSDA = Status Data Register = 47Ch 904 */ 905 csa_readio(resp, BA0_ACSDA); 906 907 /* 908 * Setup the AC97 control registers on the CS461x to send the 909 * appropriate command to the AC97 to perform the read. 910 * ACCAD = Command Address Register = 46Ch 911 * ACCDA = Command Data Register = 470h 912 * ACCTL = Control Register = 460h 913 * set DCV - will clear when process completed 914 * set CRW - Read command 915 * set VFRM - valid frame enabled 916 * set ESYN - ASYNC generation enabled 917 * set RSTN - ARST# inactive, AC97 codec not reset 918 */ 919 920 /* 921 * Get the actual AC97 register from the offset 922 */ 923 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 924 csa_writeio(resp, BA0_ACCDA, 0); 925 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 926 927 /* 928 * Wait for the read to occur. 929 */ 930 acctl = 0; 931 for (i = 0 ; i < 10 ; i++) { 932 /* 933 * First, we want to wait for a short time. 934 */ 935 DELAY(25); 936 937 /* 938 * Now, check to see if the read has completed. 939 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 940 */ 941 acctl = csa_readio(resp, BA0_ACCTL); 942 if ((acctl & ACCTL_DCV) == 0) 943 break; 944 } 945 946 /* 947 * Make sure the read completed. 948 */ 949 if ((acctl & ACCTL_DCV) != 0) 950 return (EAGAIN); 951 952 /* 953 * Wait for the valid status bit to go active. 954 */ 955 acsts = 0; 956 for (i = 0 ; i < 10 ; i++) { 957 /* 958 * Read the AC97 status register. 959 * ACSTS = Status Register = 464h 960 */ 961 acsts = csa_readio(resp, BA0_ACSTS); 962 /* 963 * See if we have valid status. 964 * VSTS - Valid Status 965 */ 966 if ((acsts & ACSTS_VSTS) != 0) 967 break; 968 /* 969 * Wait for a short while. 970 */ 971 DELAY(25); 972 } 973 974 /* 975 * Make sure we got valid status. 976 */ 977 if ((acsts & ACSTS_VSTS) == 0) 978 return (EAGAIN); 979 980 /* 981 * Read the data returned from the AC97 register. 982 * ACSDA = Status Data Register = 474h 983 */ 984 *data = csa_readio(resp, BA0_ACSDA); 985 986 return (0); 987 } 988 989 int 990 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 991 { 992 int i; 993 u_int32_t acctl; 994 995 /* 996 * Setup the AC97 control registers on the CS461x to send the 997 * appropriate command to the AC97 to perform the write. 998 * ACCAD = Command Address Register = 46Ch 999 * ACCDA = Command Data Register = 470h 1000 * ACCTL = Control Register = 460h 1001 * set DCV - will clear when process completed 1002 * set VFRM - valid frame enabled 1003 * set ESYN - ASYNC generation enabled 1004 * set RSTN - ARST# inactive, AC97 codec not reset 1005 */ 1006 1007 /* 1008 * Get the actual AC97 register from the offset 1009 */ 1010 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 1011 csa_writeio(resp, BA0_ACCDA, data); 1012 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1013 1014 /* 1015 * Wait for the write to occur. 1016 */ 1017 acctl = 0; 1018 for (i = 0 ; i < 10 ; i++) { 1019 /* 1020 * First, we want to wait for a short time. 1021 */ 1022 DELAY(25); 1023 1024 /* 1025 * Now, check to see if the read has completed. 1026 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1027 */ 1028 acctl = csa_readio(resp, BA0_ACCTL); 1029 if ((acctl & ACCTL_DCV) == 0) 1030 break; 1031 } 1032 1033 /* 1034 * Make sure the write completed. 1035 */ 1036 if ((acctl & ACCTL_DCV) != 0) 1037 return (EAGAIN); 1038 1039 return (0); 1040 } 1041 1042 u_int32_t 1043 csa_readio(csa_res *resp, u_long offset) 1044 { 1045 u_int32_t ul; 1046 1047 if (offset < BA0_AC97_RESET) 1048 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1049 else { 1050 if (csa_readcodec(resp, offset, &ul)) 1051 ul = 0; 1052 return (ul); 1053 } 1054 } 1055 1056 void 1057 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1058 { 1059 if (offset < BA0_AC97_RESET) 1060 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1061 else 1062 csa_writecodec(resp, offset, data); 1063 } 1064 1065 u_int32_t 1066 csa_readmem(csa_res *resp, u_long offset) 1067 { 1068 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1069 } 1070 1071 void 1072 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1073 { 1074 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1075 } 1076 1077 static device_method_t csa_methods[] = { 1078 /* Device interface */ 1079 DEVMETHOD(device_probe, csa_probe), 1080 DEVMETHOD(device_attach, csa_attach), 1081 DEVMETHOD(device_detach, csa_detach), 1082 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1083 DEVMETHOD(device_suspend, bus_generic_suspend), 1084 DEVMETHOD(device_resume, csa_resume), 1085 1086 /* Bus interface */ 1087 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1088 DEVMETHOD(bus_release_resource, csa_release_resource), 1089 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1090 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1091 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1092 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1093 1094 DEVMETHOD_END 1095 }; 1096 1097 static driver_t csa_driver = { 1098 "csa", 1099 csa_methods, 1100 sizeof(struct csa_softc), 1101 }; 1102 1103 /* 1104 * csa can be attached to a pci bus. 1105 */ 1106 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1107 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1108 MODULE_VERSION(snd_csa, 1); 1109