1 /*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 41 #ifdef HAVE_KERNEL_OPTION_HEADERS 42 #include "opt_snd.h" 43 #endif 44 45 #include <dev/sound/pcm/sound.h> 46 #include <dev/sound/chip.h> 47 #include <dev/sound/pci/csareg.h> 48 #include <dev/sound/pci/csavar.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <gnu/dev/sound/pci/csaimg.h> 54 55 SND_DECLARE_FILE("$FreeBSD$"); 56 57 /* This is the pci device id. */ 58 #define CS4610_PCI_ID 0x60011013 59 #define CS4614_PCI_ID 0x60031013 60 #define CS4615_PCI_ID 0x60041013 61 62 /* Here is the parameter structure per a device. */ 63 struct csa_softc { 64 device_t dev; /* device */ 65 csa_res res; /* resources */ 66 67 device_t pcm; /* pcm device */ 68 driver_intr_t* pcmintr; /* pcm intr */ 69 void *pcmintr_arg; /* pcm intr arg */ 70 device_t midi; /* midi device */ 71 driver_intr_t* midiintr; /* midi intr */ 72 void *midiintr_arg; /* midi intr arg */ 73 void *ih; /* cookie */ 74 75 struct csa_card *card; 76 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 77 }; 78 79 typedef struct csa_softc *sc_p; 80 81 static int csa_probe(device_t dev); 82 static int csa_attach(device_t dev); 83 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 84 u_long start, u_long end, u_long count, u_int flags); 85 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 86 struct resource *r); 87 static int csa_setup_intr(device_t bus, device_t child, 88 struct resource *irq, int flags, 89 #if __FreeBSD_version >= 700031 90 driver_filter_t *filter, 91 #endif 92 driver_intr_t *intr, void *arg, void **cookiep); 93 static int csa_teardown_intr(device_t bus, device_t child, 94 struct resource *irq, void *cookie); 95 static driver_intr_t csa_intr; 96 static int csa_initialize(sc_p scp); 97 static int csa_downloadimage(csa_res *resp); 98 99 static devclass_t csa_devclass; 100 101 static void 102 amp_none(void) 103 { 104 } 105 106 static void 107 amp_voyetra(void) 108 { 109 } 110 111 static int 112 clkrun_hack(int run) 113 { 114 #ifdef __i386__ 115 devclass_t pci_devclass; 116 device_t *pci_devices, *pci_children, *busp, *childp; 117 int pci_count = 0, pci_childcount = 0; 118 int i, j, port; 119 u_int16_t control; 120 bus_space_tag_t btag; 121 122 if ((pci_devclass = devclass_find("pci")) == NULL) { 123 return ENXIO; 124 } 125 126 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 127 128 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 129 pci_childcount = 0; 130 if (device_get_children(*busp, &pci_children, &pci_childcount)) 131 continue; 132 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 133 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 134 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 135 /* XXX */ 136 btag = I386_BUS_SPACE_IO; 137 138 control = bus_space_read_2(btag, 0x0, port); 139 control &= ~0x2000; 140 control |= run? 0 : 0x2000; 141 bus_space_write_2(btag, 0x0, port, control); 142 free(pci_devices, M_TEMP); 143 free(pci_children, M_TEMP); 144 return 0; 145 } 146 } 147 free(pci_children, M_TEMP); 148 } 149 150 free(pci_devices, M_TEMP); 151 return ENXIO; 152 #else 153 return 0; 154 #endif 155 } 156 157 static struct csa_card cards_4610[] = { 158 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 159 }; 160 161 static struct csa_card cards_4614[] = { 162 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 163 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 164 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 165 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 166 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 167 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 168 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 169 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 170 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 171 }; 172 173 static struct csa_card cards_4615[] = { 174 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 175 }; 176 177 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 178 179 struct card_type { 180 u_int32_t devid; 181 char *name; 182 struct csa_card *cards; 183 }; 184 185 static struct card_type cards[] = { 186 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 187 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 188 {CS4615_PCI_ID, "CS4615", cards_4615}, 189 {0, NULL, NULL}, 190 }; 191 192 static struct card_type * 193 csa_findcard(device_t dev) 194 { 195 int i; 196 197 i = 0; 198 while (cards[i].devid != 0) { 199 if (pci_get_devid(dev) == cards[i].devid) 200 return &cards[i]; 201 i++; 202 } 203 return NULL; 204 } 205 206 struct csa_card * 207 csa_findsubcard(device_t dev) 208 { 209 int i; 210 struct card_type *card; 211 struct csa_card *subcard; 212 213 card = csa_findcard(dev); 214 if (card == NULL) 215 return &nocard; 216 subcard = card->cards; 217 i = 0; 218 while (subcard[i].subvendor != 0) { 219 if (pci_get_subvendor(dev) == subcard[i].subvendor 220 && pci_get_subdevice(dev) == subcard[i].subdevice) { 221 return &subcard[i]; 222 } 223 i++; 224 } 225 return &subcard[i]; 226 } 227 228 static int 229 csa_probe(device_t dev) 230 { 231 struct card_type *card; 232 233 card = csa_findcard(dev); 234 if (card) { 235 device_set_desc(dev, card->name); 236 return BUS_PROBE_DEFAULT; 237 } 238 return ENXIO; 239 } 240 241 static int 242 csa_attach(device_t dev) 243 { 244 u_int32_t stcmd; 245 sc_p scp; 246 csa_res *resp; 247 struct sndcard_func *func; 248 int error = ENXIO; 249 250 scp = device_get_softc(dev); 251 252 /* Fill in the softc. */ 253 bzero(scp, sizeof(*scp)); 254 scp->dev = dev; 255 256 /* Wake up the device. */ 257 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 258 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 259 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 260 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 261 } 262 263 /* Allocate the resources. */ 264 resp = &scp->res; 265 scp->card = csa_findsubcard(dev); 266 scp->binfo.card = scp->card; 267 printf("csa: card is %s\n", scp->card->name); 268 resp->io_rid = PCIR_BAR(0); 269 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 270 &resp->io_rid, RF_ACTIVE); 271 if (resp->io == NULL) 272 return (ENXIO); 273 resp->mem_rid = PCIR_BAR(1); 274 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 275 &resp->mem_rid, RF_ACTIVE); 276 if (resp->mem == NULL) 277 goto err_io; 278 resp->irq_rid = 0; 279 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 280 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 281 if (resp->irq == NULL) 282 goto err_mem; 283 284 /* Enable interrupt. */ 285 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 286 goto err_intr; 287 #if 0 288 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 289 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 290 #endif 291 292 /* Initialize the chip. */ 293 if (csa_initialize(scp)) 294 goto err_teardown; 295 296 /* Reset the Processor. */ 297 csa_resetdsp(resp); 298 299 /* Download the Processor Image to the processor. */ 300 if (csa_downloadimage(resp)) 301 goto err_teardown; 302 303 /* Attach the children. */ 304 305 /* PCM Audio */ 306 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 307 if (func == NULL) { 308 error = ENOMEM; 309 goto err_teardown; 310 } 311 func->varinfo = &scp->binfo; 312 func->func = SCF_PCM; 313 scp->pcm = device_add_child(dev, "pcm", -1); 314 device_set_ivars(scp->pcm, func); 315 316 /* Midi Interface */ 317 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 318 if (func == NULL) { 319 error = ENOMEM; 320 goto err_teardown; 321 } 322 func->varinfo = &scp->binfo; 323 func->func = SCF_MIDI; 324 scp->midi = device_add_child(dev, "midi", -1); 325 device_set_ivars(scp->midi, func); 326 327 bus_generic_attach(dev); 328 329 return (0); 330 331 err_teardown: 332 bus_teardown_intr(dev, resp->irq, scp->ih); 333 err_intr: 334 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 335 err_mem: 336 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 337 err_io: 338 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 339 return (error); 340 } 341 342 static int 343 csa_detach(device_t dev) 344 { 345 csa_res *resp; 346 sc_p scp; 347 struct sndcard_func *func; 348 int err; 349 350 scp = device_get_softc(dev); 351 resp = &scp->res; 352 353 if (scp->midi != NULL) { 354 func = device_get_ivars(scp->midi); 355 err = device_delete_child(dev, scp->midi); 356 if (err != 0) 357 return err; 358 if (func != NULL) 359 free(func, M_DEVBUF); 360 scp->midi = NULL; 361 } 362 363 if (scp->pcm != NULL) { 364 func = device_get_ivars(scp->pcm); 365 err = device_delete_child(dev, scp->pcm); 366 if (err != 0) 367 return err; 368 if (func != NULL) 369 free(func, M_DEVBUF); 370 scp->pcm = NULL; 371 } 372 373 bus_teardown_intr(dev, resp->irq, scp->ih); 374 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 375 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 376 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 377 378 return bus_generic_detach(dev); 379 } 380 381 static int 382 csa_resume(device_t dev) 383 { 384 csa_res *resp; 385 sc_p scp; 386 387 scp = device_get_softc(dev); 388 resp = &scp->res; 389 390 /* Initialize the chip. */ 391 if (csa_initialize(scp)) 392 return (ENXIO); 393 394 /* Reset the Processor. */ 395 csa_resetdsp(resp); 396 397 /* Download the Processor Image to the processor. */ 398 if (csa_downloadimage(resp)) 399 return (ENXIO); 400 401 return (bus_generic_resume(dev)); 402 } 403 404 static struct resource * 405 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 406 u_long start, u_long end, u_long count, u_int flags) 407 { 408 sc_p scp; 409 csa_res *resp; 410 struct resource *res; 411 412 scp = device_get_softc(bus); 413 resp = &scp->res; 414 switch (type) { 415 case SYS_RES_IRQ: 416 if (*rid != 0) 417 return (NULL); 418 res = resp->irq; 419 break; 420 case SYS_RES_MEMORY: 421 switch (*rid) { 422 case PCIR_BAR(0): 423 res = resp->io; 424 break; 425 case PCIR_BAR(1): 426 res = resp->mem; 427 break; 428 default: 429 return (NULL); 430 } 431 break; 432 default: 433 return (NULL); 434 } 435 436 return res; 437 } 438 439 static int 440 csa_release_resource(device_t bus, device_t child, int type, int rid, 441 struct resource *r) 442 { 443 return (0); 444 } 445 446 /* 447 * The following three functions deal with interrupt handling. 448 * An interrupt is primarily handled by the bridge driver. 449 * The bridge driver then determines the child devices to pass 450 * the interrupt. Certain information of the device can be read 451 * only once(eg the value of HISR). The bridge driver is responsible 452 * to pass such the information to the children. 453 */ 454 455 static int 456 csa_setup_intr(device_t bus, device_t child, 457 struct resource *irq, int flags, 458 #if __FreeBSD_version >= 700031 459 driver_filter_t *filter, 460 #endif 461 driver_intr_t *intr, void *arg, void **cookiep) 462 { 463 sc_p scp; 464 csa_res *resp; 465 struct sndcard_func *func; 466 467 #if __FreeBSD_version >= 700031 468 if (filter != NULL) { 469 printf("ata-csa.c: we cannot use a filter here\n"); 470 return (EINVAL); 471 } 472 #endif 473 scp = device_get_softc(bus); 474 resp = &scp->res; 475 476 /* 477 * Look at the function code of the child to determine 478 * the appropriate hander for it. 479 */ 480 func = device_get_ivars(child); 481 if (func == NULL || irq != resp->irq) 482 return (EINVAL); 483 484 switch (func->func) { 485 case SCF_PCM: 486 scp->pcmintr = intr; 487 scp->pcmintr_arg = arg; 488 break; 489 490 case SCF_MIDI: 491 scp->midiintr = intr; 492 scp->midiintr_arg = arg; 493 break; 494 495 default: 496 return (EINVAL); 497 } 498 *cookiep = scp; 499 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 500 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 501 502 return (0); 503 } 504 505 static int 506 csa_teardown_intr(device_t bus, device_t child, 507 struct resource *irq, void *cookie) 508 { 509 sc_p scp; 510 csa_res *resp; 511 struct sndcard_func *func; 512 513 scp = device_get_softc(bus); 514 resp = &scp->res; 515 516 /* 517 * Look at the function code of the child to determine 518 * the appropriate hander for it. 519 */ 520 func = device_get_ivars(child); 521 if (func == NULL || irq != resp->irq || cookie != scp) 522 return (EINVAL); 523 524 switch (func->func) { 525 case SCF_PCM: 526 scp->pcmintr = NULL; 527 scp->pcmintr_arg = NULL; 528 break; 529 530 case SCF_MIDI: 531 scp->midiintr = NULL; 532 scp->midiintr_arg = NULL; 533 break; 534 535 default: 536 return (EINVAL); 537 } 538 539 return (0); 540 } 541 542 /* The interrupt handler */ 543 static void 544 csa_intr(void *arg) 545 { 546 sc_p scp = arg; 547 csa_res *resp; 548 u_int32_t hisr; 549 550 resp = &scp->res; 551 552 /* Is this interrupt for us? */ 553 hisr = csa_readio(resp, BA0_HISR); 554 if ((hisr & 0x7fffffff) == 0) { 555 /* Throw an eoi. */ 556 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 557 return; 558 } 559 560 /* 561 * Pass the value of HISR via struct csa_bridgeinfo. 562 * The children get access through their ivars. 563 */ 564 scp->binfo.hisr = hisr; 565 566 /* Invoke the handlers of the children. */ 567 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 568 scp->pcmintr(scp->pcmintr_arg); 569 hisr &= ~(HISR_VC0 | HISR_VC1); 570 } 571 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 572 scp->midiintr(scp->midiintr_arg); 573 hisr &= ~HISR_MIDI; 574 } 575 576 /* Throw an eoi. */ 577 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 578 } 579 580 static int 581 csa_initialize(sc_p scp) 582 { 583 int i; 584 u_int32_t acsts, acisv; 585 csa_res *resp; 586 587 resp = &scp->res; 588 589 /* 590 * First, blast the clock control register to zero so that the PLL starts 591 * out in a known state, and blast the master serial port control register 592 * to zero so that the serial ports also start out in a known state. 593 */ 594 csa_writeio(resp, BA0_CLKCR1, 0); 595 csa_writeio(resp, BA0_SERMC1, 0); 596 597 /* 598 * If we are in AC97 mode, then we must set the part to a host controlled 599 * AC-link. Otherwise, we won't be able to bring up the link. 600 */ 601 #if 1 602 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 603 #else 604 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 605 #endif /* 1 */ 606 607 /* 608 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 609 * spec) and then drive it high. This is done for non AC97 modes since 610 * there might be logic external to the CS461x that uses the ARST# line 611 * for a reset. 612 */ 613 csa_writeio(resp, BA0_ACCTL, 1); 614 DELAY(50); 615 csa_writeio(resp, BA0_ACCTL, 0); 616 DELAY(50); 617 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 618 619 /* 620 * The first thing we do here is to enable sync generation. As soon 621 * as we start receiving bit clock, we'll start producing the SYNC 622 * signal. 623 */ 624 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 625 626 /* 627 * Now wait for a short while to allow the AC97 part to start 628 * generating bit clock (so we don't try to start the PLL without an 629 * input clock). 630 */ 631 DELAY(50000); 632 633 /* 634 * Set the serial port timing configuration, so that 635 * the clock control circuit gets its clock from the correct place. 636 */ 637 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 638 DELAY(700000); 639 640 /* 641 * Write the selected clock control setup to the hardware. Do not turn on 642 * SWCE yet (if requested), so that the devices clocked by the output of 643 * PLL are not clocked until the PLL is stable. 644 */ 645 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 646 csa_writeio(resp, BA0_PLLM, 0x3a); 647 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 648 649 /* 650 * Power up the PLL. 651 */ 652 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 653 654 /* 655 * Wait until the PLL has stabilized. 656 */ 657 DELAY(5000); 658 659 /* 660 * Turn on clocking of the core so that we can setup the serial ports. 661 */ 662 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 663 664 /* 665 * Fill the serial port FIFOs with silence. 666 */ 667 csa_clearserialfifos(resp); 668 669 /* 670 * Set the serial port FIFO pointer to the first sample in the FIFO. 671 */ 672 #ifdef notdef 673 csa_writeio(resp, BA0_SERBSP, 0); 674 #endif /* notdef */ 675 676 /* 677 * Write the serial port configuration to the part. The master 678 * enable bit is not set until all other values have been written. 679 */ 680 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 681 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 682 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 683 684 /* 685 * Wait for the codec ready signal from the AC97 codec. 686 */ 687 acsts = 0; 688 for (i = 0 ; i < 1000 ; i++) { 689 /* 690 * First, lets wait a short while to let things settle out a bit, 691 * and to prevent retrying the read too quickly. 692 */ 693 DELAY(125); 694 695 /* 696 * Read the AC97 status register to see if we've seen a CODEC READY 697 * signal from the AC97 codec. 698 */ 699 acsts = csa_readio(resp, BA0_ACSTS); 700 if ((acsts & ACSTS_CRDY) != 0) 701 break; 702 } 703 704 /* 705 * Make sure we sampled CODEC READY. 706 */ 707 if ((acsts & ACSTS_CRDY) == 0) 708 return (ENXIO); 709 710 /* 711 * Assert the vaid frame signal so that we can start sending commands 712 * to the AC97 codec. 713 */ 714 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 715 716 /* 717 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 718 * the codec is pumping ADC data across the AC-link. 719 */ 720 acisv = 0; 721 for (i = 0 ; i < 1000 ; i++) { 722 /* 723 * First, lets wait a short while to let things settle out a bit, 724 * and to prevent retrying the read too quickly. 725 */ 726 #ifdef notdef 727 DELAY(10000000L); /* clw */ 728 #else 729 DELAY(1000); 730 #endif /* notdef */ 731 /* 732 * Read the input slot valid register and see if input slots 3 and 733 * 4 are valid yet. 734 */ 735 acisv = csa_readio(resp, BA0_ACISV); 736 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 737 break; 738 } 739 /* 740 * Make sure we sampled valid input slots 3 and 4. If not, then return 741 * an error. 742 */ 743 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 744 return (ENXIO); 745 746 /* 747 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 748 * commense the transfer of digital audio data to the AC97 codec. 749 */ 750 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 751 752 /* 753 * Power down the DAC and ADC. We will power them up (if) when we need 754 * them. 755 */ 756 #ifdef notdef 757 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 758 #endif /* notdef */ 759 760 /* 761 * Turn off the Processor by turning off the software clock enable flag in 762 * the clock control register. 763 */ 764 #ifdef notdef 765 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 766 csa_writeio(resp, BA0_CLKCR1, clkcr1); 767 #endif /* notdef */ 768 769 /* 770 * Enable interrupts on the part. 771 */ 772 #if 0 773 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 774 #endif /* notdef */ 775 776 return (0); 777 } 778 779 void 780 csa_clearserialfifos(csa_res *resp) 781 { 782 int i, j, pwr; 783 u_int8_t clkcr1, serbst; 784 785 /* 786 * See if the devices are powered down. If so, we must power them up first 787 * or they will not respond. 788 */ 789 pwr = 1; 790 clkcr1 = csa_readio(resp, BA0_CLKCR1); 791 if ((clkcr1 & CLKCR1_SWCE) == 0) { 792 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 793 pwr = 0; 794 } 795 796 /* 797 * We want to clear out the serial port FIFOs so we don't end up playing 798 * whatever random garbage happens to be in them. We fill the sample FIFOs 799 * with zero (silence). 800 */ 801 csa_writeio(resp, BA0_SERBWP, 0); 802 803 /* Fill all 256 sample FIFO locations. */ 804 serbst = 0; 805 for (i = 0 ; i < 256 ; i++) { 806 /* Make sure the previous FIFO write operation has completed. */ 807 for (j = 0 ; j < 5 ; j++) { 808 DELAY(100); 809 serbst = csa_readio(resp, BA0_SERBST); 810 if ((serbst & SERBST_WBSY) == 0) 811 break; 812 } 813 if ((serbst & SERBST_WBSY) != 0) { 814 if (!pwr) 815 csa_writeio(resp, BA0_CLKCR1, clkcr1); 816 } 817 /* Write the serial port FIFO index. */ 818 csa_writeio(resp, BA0_SERBAD, i); 819 /* Tell the serial port to load the new value into the FIFO location. */ 820 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 821 } 822 /* 823 * Now, if we powered up the devices, then power them back down again. 824 * This is kinda ugly, but should never happen. 825 */ 826 if (!pwr) 827 csa_writeio(resp, BA0_CLKCR1, clkcr1); 828 } 829 830 void 831 csa_resetdsp(csa_res *resp) 832 { 833 int i; 834 835 /* 836 * Write the reset bit of the SP control register. 837 */ 838 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 839 840 /* 841 * Write the control register. 842 */ 843 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 844 845 /* 846 * Clear the trap registers. 847 */ 848 for (i = 0 ; i < 8 ; i++) { 849 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 850 csa_writemem(resp, BA1_TWPR, 0xffff); 851 } 852 csa_writemem(resp, BA1_DREG, 0); 853 854 /* 855 * Set the frame timer to reflect the number of cycles per frame. 856 */ 857 csa_writemem(resp, BA1_FRMT, 0xadf); 858 } 859 860 static int 861 csa_downloadimage(csa_res *resp) 862 { 863 int i; 864 u_int32_t tmp, src, dst, count, data; 865 866 for (i = 0; i < CLEAR__COUNT; i++) { 867 dst = ClrStat[i].BA1__DestByteOffset; 868 count = ClrStat[i].BA1__SourceSize; 869 for (tmp = 0; tmp < count; tmp += 4) 870 csa_writemem(resp, dst + tmp, 0x00000000); 871 } 872 873 for (i = 0; i < FILL__COUNT; i++) { 874 src = 0; 875 dst = FillStat[i].Offset; 876 count = FillStat[i].Size; 877 for (tmp = 0; tmp < count; tmp += 4) { 878 data = FillStat[i].pFill[src]; 879 csa_writemem(resp, dst + tmp, data); 880 src++; 881 } 882 } 883 884 return (0); 885 } 886 887 int 888 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 889 { 890 int i; 891 u_int32_t acctl, acsts; 892 893 /* 894 * Make sure that there is not data sitting around from a previous 895 * uncompleted access. ACSDA = Status Data Register = 47Ch 896 */ 897 csa_readio(resp, BA0_ACSDA); 898 899 /* 900 * Setup the AC97 control registers on the CS461x to send the 901 * appropriate command to the AC97 to perform the read. 902 * ACCAD = Command Address Register = 46Ch 903 * ACCDA = Command Data Register = 470h 904 * ACCTL = Control Register = 460h 905 * set DCV - will clear when process completed 906 * set CRW - Read command 907 * set VFRM - valid frame enabled 908 * set ESYN - ASYNC generation enabled 909 * set RSTN - ARST# inactive, AC97 codec not reset 910 */ 911 912 /* 913 * Get the actual AC97 register from the offset 914 */ 915 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 916 csa_writeio(resp, BA0_ACCDA, 0); 917 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 918 919 /* 920 * Wait for the read to occur. 921 */ 922 acctl = 0; 923 for (i = 0 ; i < 10 ; i++) { 924 /* 925 * First, we want to wait for a short time. 926 */ 927 DELAY(25); 928 929 /* 930 * Now, check to see if the read has completed. 931 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 932 */ 933 acctl = csa_readio(resp, BA0_ACCTL); 934 if ((acctl & ACCTL_DCV) == 0) 935 break; 936 } 937 938 /* 939 * Make sure the read completed. 940 */ 941 if ((acctl & ACCTL_DCV) != 0) 942 return (EAGAIN); 943 944 /* 945 * Wait for the valid status bit to go active. 946 */ 947 acsts = 0; 948 for (i = 0 ; i < 10 ; i++) { 949 /* 950 * Read the AC97 status register. 951 * ACSTS = Status Register = 464h 952 */ 953 acsts = csa_readio(resp, BA0_ACSTS); 954 /* 955 * See if we have valid status. 956 * VSTS - Valid Status 957 */ 958 if ((acsts & ACSTS_VSTS) != 0) 959 break; 960 /* 961 * Wait for a short while. 962 */ 963 DELAY(25); 964 } 965 966 /* 967 * Make sure we got valid status. 968 */ 969 if ((acsts & ACSTS_VSTS) == 0) 970 return (EAGAIN); 971 972 /* 973 * Read the data returned from the AC97 register. 974 * ACSDA = Status Data Register = 474h 975 */ 976 *data = csa_readio(resp, BA0_ACSDA); 977 978 return (0); 979 } 980 981 int 982 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 983 { 984 int i; 985 u_int32_t acctl; 986 987 /* 988 * Setup the AC97 control registers on the CS461x to send the 989 * appropriate command to the AC97 to perform the write. 990 * ACCAD = Command Address Register = 46Ch 991 * ACCDA = Command Data Register = 470h 992 * ACCTL = Control Register = 460h 993 * set DCV - will clear when process completed 994 * set VFRM - valid frame enabled 995 * set ESYN - ASYNC generation enabled 996 * set RSTN - ARST# inactive, AC97 codec not reset 997 */ 998 999 /* 1000 * Get the actual AC97 register from the offset 1001 */ 1002 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 1003 csa_writeio(resp, BA0_ACCDA, data); 1004 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1005 1006 /* 1007 * Wait for the write to occur. 1008 */ 1009 acctl = 0; 1010 for (i = 0 ; i < 10 ; i++) { 1011 /* 1012 * First, we want to wait for a short time. 1013 */ 1014 DELAY(25); 1015 1016 /* 1017 * Now, check to see if the read has completed. 1018 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1019 */ 1020 acctl = csa_readio(resp, BA0_ACCTL); 1021 if ((acctl & ACCTL_DCV) == 0) 1022 break; 1023 } 1024 1025 /* 1026 * Make sure the write completed. 1027 */ 1028 if ((acctl & ACCTL_DCV) != 0) 1029 return (EAGAIN); 1030 1031 return (0); 1032 } 1033 1034 u_int32_t 1035 csa_readio(csa_res *resp, u_long offset) 1036 { 1037 u_int32_t ul; 1038 1039 if (offset < BA0_AC97_RESET) 1040 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1041 else { 1042 if (csa_readcodec(resp, offset, &ul)) 1043 ul = 0; 1044 return (ul); 1045 } 1046 } 1047 1048 void 1049 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1050 { 1051 if (offset < BA0_AC97_RESET) 1052 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1053 else 1054 csa_writecodec(resp, offset, data); 1055 } 1056 1057 u_int32_t 1058 csa_readmem(csa_res *resp, u_long offset) 1059 { 1060 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1061 } 1062 1063 void 1064 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1065 { 1066 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1067 } 1068 1069 static device_method_t csa_methods[] = { 1070 /* Device interface */ 1071 DEVMETHOD(device_probe, csa_probe), 1072 DEVMETHOD(device_attach, csa_attach), 1073 DEVMETHOD(device_detach, csa_detach), 1074 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1075 DEVMETHOD(device_suspend, bus_generic_suspend), 1076 DEVMETHOD(device_resume, csa_resume), 1077 1078 /* Bus interface */ 1079 DEVMETHOD(bus_print_child, bus_generic_print_child), 1080 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1081 DEVMETHOD(bus_release_resource, csa_release_resource), 1082 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1083 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1084 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1085 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1086 1087 { 0, 0 } 1088 }; 1089 1090 static driver_t csa_driver = { 1091 "csa", 1092 csa_methods, 1093 sizeof(struct csa_softc), 1094 }; 1095 1096 /* 1097 * csa can be attached to a pci bus. 1098 */ 1099 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1100 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1101 MODULE_VERSION(snd_csa, 1); 1102