1 /* 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 #include <sys/soundcard.h> 41 #include <dev/sound/pcm/sound.h> 42 #include <dev/sound/chip.h> 43 #include <dev/sound/pci/csareg.h> 44 #include <dev/sound/pci/csavar.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <gnu/dev/sound/pci/csaimg.h> 50 51 SND_DECLARE_FILE("$FreeBSD$"); 52 53 /* This is the pci device id. */ 54 #define CS4610_PCI_ID 0x60011013 55 #define CS4614_PCI_ID 0x60031013 56 #define CS4615_PCI_ID 0x60041013 57 58 /* Here is the parameter structure per a device. */ 59 struct csa_softc { 60 device_t dev; /* device */ 61 csa_res res; /* resources */ 62 63 device_t pcm; /* pcm device */ 64 driver_intr_t* pcmintr; /* pcm intr */ 65 void *pcmintr_arg; /* pcm intr arg */ 66 device_t midi; /* midi device */ 67 driver_intr_t* midiintr; /* midi intr */ 68 void *midiintr_arg; /* midi intr arg */ 69 void *ih; /* cookie */ 70 71 struct csa_card *card; 72 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 73 }; 74 75 typedef struct csa_softc *sc_p; 76 77 static int csa_probe(device_t dev); 78 static int csa_attach(device_t dev); 79 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 80 u_long start, u_long end, u_long count, u_int flags); 81 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 82 struct resource *r); 83 static int csa_setup_intr(device_t bus, device_t child, 84 struct resource *irq, int flags, 85 driver_intr_t *intr, void *arg, void **cookiep); 86 static int csa_teardown_intr(device_t bus, device_t child, 87 struct resource *irq, void *cookie); 88 static driver_intr_t csa_intr; 89 static int csa_initialize(sc_p scp); 90 static void csa_resetdsp(csa_res *resp); 91 static int csa_downloadimage(csa_res *resp); 92 93 static devclass_t csa_devclass; 94 95 static void 96 amp_none(void) 97 { 98 } 99 100 static void 101 amp_voyetra(void) 102 { 103 } 104 105 static int 106 clkrun_hack(int run) 107 { 108 #ifdef __i386__ 109 devclass_t pci_devclass; 110 device_t *pci_devices, *pci_children, *busp, *childp; 111 int pci_count = 0, pci_childcount = 0; 112 int i, j, port; 113 u_int16_t control; 114 bus_space_tag_t btag; 115 116 if ((pci_devclass = devclass_find("pci")) == NULL) { 117 return ENXIO; 118 } 119 120 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 121 122 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 123 pci_childcount = 0; 124 device_get_children(*busp, &pci_children, &pci_childcount); 125 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 126 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 127 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 128 /* XXX */ 129 btag = I386_BUS_SPACE_IO; 130 131 control = bus_space_read_2(btag, 0x0, port); 132 control &= ~0x2000; 133 control |= run? 0 : 0x2000; 134 bus_space_write_2(btag, 0x0, port, control); 135 free(pci_devices, M_TEMP); 136 free(pci_children, M_TEMP); 137 return 0; 138 } 139 } 140 free(pci_children, M_TEMP); 141 } 142 143 free(pci_devices, M_TEMP); 144 return ENXIO; 145 #else 146 return 0; 147 #endif 148 } 149 150 static struct csa_card cards_4610[] = { 151 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 152 }; 153 154 static struct csa_card cards_4614[] = { 155 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 156 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 157 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 158 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 159 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 160 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 161 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 162 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 163 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 164 }; 165 166 static struct csa_card cards_4615[] = { 167 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 168 }; 169 170 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 171 172 struct card_type { 173 u_int32_t devid; 174 char *name; 175 struct csa_card *cards; 176 }; 177 178 static struct card_type cards[] = { 179 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 180 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 181 {CS4615_PCI_ID, "CS4615", cards_4615}, 182 {0, NULL, NULL}, 183 }; 184 185 static struct card_type * 186 csa_findcard(device_t dev) 187 { 188 int i; 189 190 i = 0; 191 while (cards[i].devid != 0) { 192 if (pci_get_devid(dev) == cards[i].devid) 193 return &cards[i]; 194 i++; 195 } 196 return NULL; 197 } 198 199 struct csa_card * 200 csa_findsubcard(device_t dev) 201 { 202 int i; 203 struct card_type *card; 204 struct csa_card *subcard; 205 206 card = csa_findcard(dev); 207 if (card == NULL) 208 return &nocard; 209 subcard = card->cards; 210 i = 0; 211 while (subcard[i].subvendor != 0) { 212 if (pci_get_subvendor(dev) == subcard[i].subvendor 213 && pci_get_subdevice(dev) == subcard[i].subdevice) { 214 return &subcard[i]; 215 } 216 i++; 217 } 218 return &subcard[i]; 219 } 220 221 static int 222 csa_probe(device_t dev) 223 { 224 struct card_type *card; 225 226 card = csa_findcard(dev); 227 if (card) { 228 device_set_desc(dev, card->name); 229 return 0; 230 } 231 return ENXIO; 232 } 233 234 static int 235 csa_attach(device_t dev) 236 { 237 u_int32_t stcmd; 238 sc_p scp; 239 csa_res *resp; 240 struct sndcard_func *func; 241 int error = ENXIO; 242 243 scp = device_get_softc(dev); 244 245 /* Fill in the softc. */ 246 bzero(scp, sizeof(*scp)); 247 scp->dev = dev; 248 249 /* Wake up the device. */ 250 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 251 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 252 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 253 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 254 } 255 256 /* Allocate the resources. */ 257 resp = &scp->res; 258 scp->card = csa_findsubcard(dev); 259 scp->binfo.card = scp->card; 260 printf("csa: card is %s\n", scp->card->name); 261 resp->io_rid = PCIR_BAR(0); 262 resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, 1, RF_ACTIVE); 263 if (resp->io == NULL) 264 return (ENXIO); 265 resp->mem_rid = PCIR_BAR(1); 266 resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, 1, RF_ACTIVE); 267 if (resp->mem == NULL) 268 goto err_io; 269 resp->irq_rid = 0; 270 resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 271 if (resp->irq == NULL) 272 goto err_mem; 273 274 /* Enable interrupt. */ 275 if (snd_setup_intr(dev, resp->irq, INTR_MPSAFE, csa_intr, scp, &scp->ih)) 276 goto err_intr; 277 #if 0 278 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 279 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 280 #endif 281 282 /* Initialize the chip. */ 283 if (csa_initialize(scp)) 284 goto err_teardown; 285 286 /* Reset the Processor. */ 287 csa_resetdsp(resp); 288 289 /* Download the Processor Image to the processor. */ 290 if (csa_downloadimage(resp)) 291 goto err_teardown; 292 293 /* Attach the children. */ 294 295 /* PCM Audio */ 296 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 297 if (func == NULL) { 298 error = ENOMEM; 299 goto err_teardown; 300 } 301 func->varinfo = &scp->binfo; 302 func->func = SCF_PCM; 303 scp->pcm = device_add_child(dev, "pcm", -1); 304 device_set_ivars(scp->pcm, func); 305 306 /* Midi Interface */ 307 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 308 if (func == NULL) { 309 error = ENOMEM; 310 goto err_teardown; 311 } 312 func->varinfo = &scp->binfo; 313 func->func = SCF_MIDI; 314 scp->midi = device_add_child(dev, "midi", -1); 315 device_set_ivars(scp->midi, func); 316 317 bus_generic_attach(dev); 318 319 return (0); 320 321 err_teardown: 322 bus_teardown_intr(dev, resp->irq, scp->ih); 323 err_intr: 324 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 325 err_mem: 326 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 327 err_io: 328 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 329 return (error); 330 } 331 332 static int 333 csa_detach(device_t dev) 334 { 335 csa_res *resp; 336 sc_p scp; 337 int err; 338 339 scp = device_get_softc(dev); 340 resp = &scp->res; 341 342 err = 0; 343 if (scp->midi != NULL) 344 err = device_delete_child(dev, scp->midi); 345 if (err) 346 return err; 347 scp->midi = NULL; 348 349 if (scp->pcm != NULL) 350 err = device_delete_child(dev, scp->pcm); 351 if (err) 352 return err; 353 scp->pcm = NULL; 354 355 bus_teardown_intr(dev, resp->irq, scp->ih); 356 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 357 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 358 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 359 360 return bus_generic_detach(dev); 361 } 362 363 static int 364 csa_resume(device_t dev) 365 { 366 #if 0 367 /* 368 * XXX: this cannot possibly work 369 * needs to be properly implemented 370 */ 371 csa_detach(dev); 372 csa_attach(dev); 373 #endif 374 return 0; 375 } 376 377 static struct resource * 378 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 379 u_long start, u_long end, u_long count, u_int flags) 380 { 381 sc_p scp; 382 csa_res *resp; 383 struct resource *res; 384 385 scp = device_get_softc(bus); 386 resp = &scp->res; 387 switch (type) { 388 case SYS_RES_IRQ: 389 if (*rid != 0) 390 return (NULL); 391 res = resp->irq; 392 break; 393 case SYS_RES_MEMORY: 394 switch (*rid) { 395 case PCIR_BAR(0): 396 res = resp->io; 397 break; 398 case PCIR_BAR(1): 399 res = resp->mem; 400 break; 401 default: 402 return (NULL); 403 } 404 break; 405 default: 406 return (NULL); 407 } 408 409 return res; 410 } 411 412 static int 413 csa_release_resource(device_t bus, device_t child, int type, int rid, 414 struct resource *r) 415 { 416 return (0); 417 } 418 419 /* 420 * The following three functions deal with interrupt handling. 421 * An interrupt is primarily handled by the bridge driver. 422 * The bridge driver then determines the child devices to pass 423 * the interrupt. Certain information of the device can be read 424 * only once(eg the value of HISR). The bridge driver is responsible 425 * to pass such the information to the children. 426 */ 427 428 static int 429 csa_setup_intr(device_t bus, device_t child, 430 struct resource *irq, int flags, 431 driver_intr_t *intr, void *arg, void **cookiep) 432 { 433 sc_p scp; 434 csa_res *resp; 435 struct sndcard_func *func; 436 437 scp = device_get_softc(bus); 438 resp = &scp->res; 439 440 /* 441 * Look at the function code of the child to determine 442 * the appropriate hander for it. 443 */ 444 func = device_get_ivars(child); 445 if (func == NULL || irq != resp->irq) 446 return (EINVAL); 447 448 switch (func->func) { 449 case SCF_PCM: 450 scp->pcmintr = intr; 451 scp->pcmintr_arg = arg; 452 break; 453 454 case SCF_MIDI: 455 scp->midiintr = intr; 456 scp->midiintr_arg = arg; 457 break; 458 459 default: 460 return (EINVAL); 461 } 462 *cookiep = scp; 463 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 464 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 465 466 return (0); 467 } 468 469 static int 470 csa_teardown_intr(device_t bus, device_t child, 471 struct resource *irq, void *cookie) 472 { 473 sc_p scp; 474 csa_res *resp; 475 struct sndcard_func *func; 476 477 scp = device_get_softc(bus); 478 resp = &scp->res; 479 480 /* 481 * Look at the function code of the child to determine 482 * the appropriate hander for it. 483 */ 484 func = device_get_ivars(child); 485 if (func == NULL || irq != resp->irq || cookie != scp) 486 return (EINVAL); 487 488 switch (func->func) { 489 case SCF_PCM: 490 scp->pcmintr = NULL; 491 scp->pcmintr_arg = NULL; 492 break; 493 494 case SCF_MIDI: 495 scp->midiintr = NULL; 496 scp->midiintr_arg = NULL; 497 break; 498 499 default: 500 return (EINVAL); 501 } 502 503 return (0); 504 } 505 506 /* The interrupt handler */ 507 static void 508 csa_intr(void *arg) 509 { 510 sc_p scp = arg; 511 csa_res *resp; 512 u_int32_t hisr; 513 514 resp = &scp->res; 515 516 /* Is this interrupt for us? */ 517 hisr = csa_readio(resp, BA0_HISR); 518 if ((hisr & 0x7fffffff) == 0) { 519 /* Throw an eoi. */ 520 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 521 return; 522 } 523 524 /* 525 * Pass the value of HISR via struct csa_bridgeinfo. 526 * The children get access through their ivars. 527 */ 528 scp->binfo.hisr = hisr; 529 530 /* Invoke the handlers of the children. */ 531 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 532 scp->pcmintr(scp->pcmintr_arg); 533 hisr &= ~(HISR_VC0 | HISR_VC1); 534 } 535 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 536 scp->midiintr(scp->midiintr_arg); 537 hisr &= ~HISR_MIDI; 538 } 539 540 /* Throw an eoi. */ 541 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 542 } 543 544 static int 545 csa_initialize(sc_p scp) 546 { 547 int i; 548 u_int32_t acsts, acisv; 549 csa_res *resp; 550 551 resp = &scp->res; 552 553 /* 554 * First, blast the clock control register to zero so that the PLL starts 555 * out in a known state, and blast the master serial port control register 556 * to zero so that the serial ports also start out in a known state. 557 */ 558 csa_writeio(resp, BA0_CLKCR1, 0); 559 csa_writeio(resp, BA0_SERMC1, 0); 560 561 /* 562 * If we are in AC97 mode, then we must set the part to a host controlled 563 * AC-link. Otherwise, we won't be able to bring up the link. 564 */ 565 #if 1 566 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 567 #else 568 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 569 #endif /* 1 */ 570 571 /* 572 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 573 * spec) and then drive it high. This is done for non AC97 modes since 574 * there might be logic external to the CS461x that uses the ARST# line 575 * for a reset. 576 */ 577 csa_writeio(resp, BA0_ACCTL, 1); 578 DELAY(50); 579 csa_writeio(resp, BA0_ACCTL, 0); 580 DELAY(50); 581 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 582 583 /* 584 * The first thing we do here is to enable sync generation. As soon 585 * as we start receiving bit clock, we'll start producing the SYNC 586 * signal. 587 */ 588 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 589 590 /* 591 * Now wait for a short while to allow the AC97 part to start 592 * generating bit clock (so we don't try to start the PLL without an 593 * input clock). 594 */ 595 DELAY(50000); 596 597 /* 598 * Set the serial port timing configuration, so that 599 * the clock control circuit gets its clock from the correct place. 600 */ 601 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 602 DELAY(700000); 603 604 /* 605 * Write the selected clock control setup to the hardware. Do not turn on 606 * SWCE yet (if requested), so that the devices clocked by the output of 607 * PLL are not clocked until the PLL is stable. 608 */ 609 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 610 csa_writeio(resp, BA0_PLLM, 0x3a); 611 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 612 613 /* 614 * Power up the PLL. 615 */ 616 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 617 618 /* 619 * Wait until the PLL has stabilized. 620 */ 621 DELAY(5000); 622 623 /* 624 * Turn on clocking of the core so that we can setup the serial ports. 625 */ 626 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 627 628 /* 629 * Fill the serial port FIFOs with silence. 630 */ 631 csa_clearserialfifos(resp); 632 633 /* 634 * Set the serial port FIFO pointer to the first sample in the FIFO. 635 */ 636 #if notdef 637 csa_writeio(resp, BA0_SERBSP, 0); 638 #endif /* notdef */ 639 640 /* 641 * Write the serial port configuration to the part. The master 642 * enable bit is not set until all other values have been written. 643 */ 644 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 645 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 646 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 647 648 /* 649 * Wait for the codec ready signal from the AC97 codec. 650 */ 651 acsts = 0; 652 for (i = 0 ; i < 1000 ; i++) { 653 /* 654 * First, lets wait a short while to let things settle out a bit, 655 * and to prevent retrying the read too quickly. 656 */ 657 DELAY(125); 658 659 /* 660 * Read the AC97 status register to see if we've seen a CODEC READY 661 * signal from the AC97 codec. 662 */ 663 acsts = csa_readio(resp, BA0_ACSTS); 664 if ((acsts & ACSTS_CRDY) != 0) 665 break; 666 } 667 668 /* 669 * Make sure we sampled CODEC READY. 670 */ 671 if ((acsts & ACSTS_CRDY) == 0) 672 return (ENXIO); 673 674 /* 675 * Assert the vaid frame signal so that we can start sending commands 676 * to the AC97 codec. 677 */ 678 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 679 680 /* 681 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 682 * the codec is pumping ADC data across the AC-link. 683 */ 684 acisv = 0; 685 for (i = 0 ; i < 1000 ; i++) { 686 /* 687 * First, lets wait a short while to let things settle out a bit, 688 * and to prevent retrying the read too quickly. 689 */ 690 #if notdef 691 DELAY(10000000L); /* clw */ 692 #else 693 DELAY(1000); 694 #endif /* notdef */ 695 /* 696 * Read the input slot valid register and see if input slots 3 and 697 * 4 are valid yet. 698 */ 699 acisv = csa_readio(resp, BA0_ACISV); 700 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 701 break; 702 } 703 /* 704 * Make sure we sampled valid input slots 3 and 4. If not, then return 705 * an error. 706 */ 707 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 708 return (ENXIO); 709 710 /* 711 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 712 * commense the transfer of digital audio data to the AC97 codec. 713 */ 714 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 715 716 /* 717 * Power down the DAC and ADC. We will power them up (if) when we need 718 * them. 719 */ 720 #if notdef 721 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 722 #endif /* notdef */ 723 724 /* 725 * Turn off the Processor by turning off the software clock enable flag in 726 * the clock control register. 727 */ 728 #if notdef 729 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 730 csa_writeio(resp, BA0_CLKCR1, clkcr1); 731 #endif /* notdef */ 732 733 /* 734 * Enable interrupts on the part. 735 */ 736 #if 0 737 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 738 #endif /* notdef */ 739 740 return (0); 741 } 742 743 void 744 csa_clearserialfifos(csa_res *resp) 745 { 746 int i, j, pwr; 747 u_int8_t clkcr1, serbst; 748 749 /* 750 * See if the devices are powered down. If so, we must power them up first 751 * or they will not respond. 752 */ 753 pwr = 1; 754 clkcr1 = csa_readio(resp, BA0_CLKCR1); 755 if ((clkcr1 & CLKCR1_SWCE) == 0) { 756 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 757 pwr = 0; 758 } 759 760 /* 761 * We want to clear out the serial port FIFOs so we don't end up playing 762 * whatever random garbage happens to be in them. We fill the sample FIFOs 763 * with zero (silence). 764 */ 765 csa_writeio(resp, BA0_SERBWP, 0); 766 767 /* Fill all 256 sample FIFO locations. */ 768 serbst = 0; 769 for (i = 0 ; i < 256 ; i++) { 770 /* Make sure the previous FIFO write operation has completed. */ 771 for (j = 0 ; j < 5 ; j++) { 772 DELAY(100); 773 serbst = csa_readio(resp, BA0_SERBST); 774 if ((serbst & SERBST_WBSY) == 0) 775 break; 776 } 777 if ((serbst & SERBST_WBSY) != 0) { 778 if (!pwr) 779 csa_writeio(resp, BA0_CLKCR1, clkcr1); 780 } 781 /* Write the serial port FIFO index. */ 782 csa_writeio(resp, BA0_SERBAD, i); 783 /* Tell the serial port to load the new value into the FIFO location. */ 784 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 785 } 786 /* 787 * Now, if we powered up the devices, then power them back down again. 788 * This is kinda ugly, but should never happen. 789 */ 790 if (!pwr) 791 csa_writeio(resp, BA0_CLKCR1, clkcr1); 792 } 793 794 static void 795 csa_resetdsp(csa_res *resp) 796 { 797 int i; 798 799 /* 800 * Write the reset bit of the SP control register. 801 */ 802 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 803 804 /* 805 * Write the control register. 806 */ 807 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 808 809 /* 810 * Clear the trap registers. 811 */ 812 for (i = 0 ; i < 8 ; i++) { 813 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 814 csa_writemem(resp, BA1_TWPR, 0xffff); 815 } 816 csa_writemem(resp, BA1_DREG, 0); 817 818 /* 819 * Set the frame timer to reflect the number of cycles per frame. 820 */ 821 csa_writemem(resp, BA1_FRMT, 0xadf); 822 } 823 824 static int 825 csa_downloadimage(csa_res *resp) 826 { 827 int i; 828 u_int32_t tmp, src, dst, count, data; 829 830 for (i = 0; i < CLEAR__COUNT; i++) { 831 dst = ClrStat[i].BA1__DestByteOffset; 832 count = ClrStat[i].BA1__SourceSize; 833 for (tmp = 0; tmp < count; tmp += 4) 834 csa_writemem(resp, dst + tmp, 0x00000000); 835 } 836 837 for (i = 0; i < FILL__COUNT; i++) { 838 src = 0; 839 dst = FillStat[i].Offset; 840 count = FillStat[i].Size; 841 for (tmp = 0; tmp < count; tmp += 4) { 842 data = FillStat[i].pFill[src]; 843 csa_writemem(resp, dst + tmp, data); 844 src++; 845 } 846 } 847 848 return (0); 849 } 850 851 int 852 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 853 { 854 int i; 855 u_int32_t acsda, acctl, acsts; 856 857 /* 858 * Make sure that there is not data sitting around from a previous 859 * uncompleted access. ACSDA = Status Data Register = 47Ch 860 */ 861 acsda = csa_readio(resp, BA0_ACSDA); 862 863 /* 864 * Setup the AC97 control registers on the CS461x to send the 865 * appropriate command to the AC97 to perform the read. 866 * ACCAD = Command Address Register = 46Ch 867 * ACCDA = Command Data Register = 470h 868 * ACCTL = Control Register = 460h 869 * set DCV - will clear when process completed 870 * set CRW - Read command 871 * set VFRM - valid frame enabled 872 * set ESYN - ASYNC generation enabled 873 * set RSTN - ARST# inactive, AC97 codec not reset 874 */ 875 876 /* 877 * Get the actual AC97 register from the offset 878 */ 879 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 880 csa_writeio(resp, BA0_ACCDA, 0); 881 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 882 883 /* 884 * Wait for the read to occur. 885 */ 886 acctl = 0; 887 for (i = 0 ; i < 10 ; i++) { 888 /* 889 * First, we want to wait for a short time. 890 */ 891 DELAY(25); 892 893 /* 894 * Now, check to see if the read has completed. 895 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 896 */ 897 acctl = csa_readio(resp, BA0_ACCTL); 898 if ((acctl & ACCTL_DCV) == 0) 899 break; 900 } 901 902 /* 903 * Make sure the read completed. 904 */ 905 if ((acctl & ACCTL_DCV) != 0) 906 return (EAGAIN); 907 908 /* 909 * Wait for the valid status bit to go active. 910 */ 911 acsts = 0; 912 for (i = 0 ; i < 10 ; i++) { 913 /* 914 * Read the AC97 status register. 915 * ACSTS = Status Register = 464h 916 */ 917 acsts = csa_readio(resp, BA0_ACSTS); 918 /* 919 * See if we have valid status. 920 * VSTS - Valid Status 921 */ 922 if ((acsts & ACSTS_VSTS) != 0) 923 break; 924 /* 925 * Wait for a short while. 926 */ 927 DELAY(25); 928 } 929 930 /* 931 * Make sure we got valid status. 932 */ 933 if ((acsts & ACSTS_VSTS) == 0) 934 return (EAGAIN); 935 936 /* 937 * Read the data returned from the AC97 register. 938 * ACSDA = Status Data Register = 474h 939 */ 940 *data = csa_readio(resp, BA0_ACSDA); 941 942 return (0); 943 } 944 945 int 946 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 947 { 948 int i; 949 u_int32_t acctl; 950 951 /* 952 * Setup the AC97 control registers on the CS461x to send the 953 * appropriate command to the AC97 to perform the write. 954 * ACCAD = Command Address Register = 46Ch 955 * ACCDA = Command Data Register = 470h 956 * ACCTL = Control Register = 460h 957 * set DCV - will clear when process completed 958 * set VFRM - valid frame enabled 959 * set ESYN - ASYNC generation enabled 960 * set RSTN - ARST# inactive, AC97 codec not reset 961 */ 962 963 /* 964 * Get the actual AC97 register from the offset 965 */ 966 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 967 csa_writeio(resp, BA0_ACCDA, data); 968 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 969 970 /* 971 * Wait for the write to occur. 972 */ 973 acctl = 0; 974 for (i = 0 ; i < 10 ; i++) { 975 /* 976 * First, we want to wait for a short time. 977 */ 978 DELAY(25); 979 980 /* 981 * Now, check to see if the read has completed. 982 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 983 */ 984 acctl = csa_readio(resp, BA0_ACCTL); 985 if ((acctl & ACCTL_DCV) == 0) 986 break; 987 } 988 989 /* 990 * Make sure the write completed. 991 */ 992 if ((acctl & ACCTL_DCV) != 0) 993 return (EAGAIN); 994 995 return (0); 996 } 997 998 u_int32_t 999 csa_readio(csa_res *resp, u_long offset) 1000 { 1001 u_int32_t ul; 1002 1003 if (offset < BA0_AC97_RESET) 1004 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1005 else { 1006 if (csa_readcodec(resp, offset, &ul)) 1007 ul = 0; 1008 return (ul); 1009 } 1010 } 1011 1012 void 1013 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1014 { 1015 if (offset < BA0_AC97_RESET) 1016 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1017 else 1018 csa_writecodec(resp, offset, data); 1019 } 1020 1021 u_int32_t 1022 csa_readmem(csa_res *resp, u_long offset) 1023 { 1024 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1025 } 1026 1027 void 1028 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1029 { 1030 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1031 } 1032 1033 static device_method_t csa_methods[] = { 1034 /* Device interface */ 1035 DEVMETHOD(device_probe, csa_probe), 1036 DEVMETHOD(device_attach, csa_attach), 1037 DEVMETHOD(device_detach, csa_detach), 1038 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1039 DEVMETHOD(device_suspend, bus_generic_suspend), 1040 DEVMETHOD(device_resume, csa_resume), 1041 1042 /* Bus interface */ 1043 DEVMETHOD(bus_print_child, bus_generic_print_child), 1044 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1045 DEVMETHOD(bus_release_resource, csa_release_resource), 1046 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1047 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1048 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1049 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1050 1051 { 0, 0 } 1052 }; 1053 1054 static driver_t csa_driver = { 1055 "csa", 1056 csa_methods, 1057 sizeof(struct csa_softc), 1058 }; 1059 1060 /* 1061 * csa can be attached to a pci bus. 1062 */ 1063 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1064 MODULE_DEPEND(snd_csa, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1065 MODULE_VERSION(snd_csa, 1); 1066