1 /* 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 #include <sys/soundcard.h> 41 #include <dev/sound/pcm/sound.h> 42 #include <dev/sound/chip.h> 43 #include <dev/sound/pci/csareg.h> 44 #include <dev/sound/pci/csavar.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <gnu/dev/sound/pci/csaimg.h> 50 51 SND_DECLARE_FILE("$FreeBSD$"); 52 53 /* This is the pci device id. */ 54 #define CS4610_PCI_ID 0x60011013 55 #define CS4614_PCI_ID 0x60031013 56 #define CS4615_PCI_ID 0x60041013 57 58 /* Here is the parameter structure per a device. */ 59 struct csa_softc { 60 device_t dev; /* device */ 61 csa_res res; /* resources */ 62 63 device_t pcm; /* pcm device */ 64 driver_intr_t* pcmintr; /* pcm intr */ 65 void *pcmintr_arg; /* pcm intr arg */ 66 device_t midi; /* midi device */ 67 driver_intr_t* midiintr; /* midi intr */ 68 void *midiintr_arg; /* midi intr arg */ 69 void *ih; /* cookie */ 70 71 struct csa_card *card; 72 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 73 }; 74 75 typedef struct csa_softc *sc_p; 76 77 static int csa_probe(device_t dev); 78 static int csa_attach(device_t dev); 79 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 80 u_long start, u_long end, u_long count, u_int flags); 81 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 82 struct resource *r); 83 static int csa_setup_intr(device_t bus, device_t child, 84 struct resource *irq, int flags, 85 driver_intr_t *intr, void *arg, void **cookiep); 86 static int csa_teardown_intr(device_t bus, device_t child, 87 struct resource *irq, void *cookie); 88 static driver_intr_t csa_intr; 89 static int csa_initialize(sc_p scp); 90 static void csa_resetdsp(csa_res *resp); 91 static int csa_downloadimage(csa_res *resp); 92 93 static devclass_t csa_devclass; 94 95 static void 96 amp_none(void) 97 { 98 } 99 100 static void 101 amp_voyetra(void) 102 { 103 } 104 105 static int 106 clkrun_hack(int run) 107 { 108 #ifdef __i386__ 109 devclass_t pci_devclass; 110 device_t *pci_devices, *pci_children, *busp, *childp; 111 int pci_count = 0, pci_childcount = 0; 112 int i, j, port; 113 u_int16_t control; 114 bus_space_tag_t btag; 115 116 if ((pci_devclass = devclass_find("pci")) == NULL) { 117 return ENXIO; 118 } 119 120 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 121 122 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 123 pci_childcount = 0; 124 device_get_children(*busp, &pci_children, &pci_childcount); 125 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 126 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 127 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 128 /* XXX */ 129 btag = I386_BUS_SPACE_IO; 130 131 control = bus_space_read_2(btag, 0x0, port); 132 control &= ~0x2000; 133 control |= run? 0 : 0x2000; 134 bus_space_write_2(btag, 0x0, port, control); 135 free(pci_devices, M_TEMP); 136 free(pci_children, M_TEMP); 137 return 0; 138 } 139 } 140 free(pci_children, M_TEMP); 141 } 142 143 free(pci_devices, M_TEMP); 144 return ENXIO; 145 #else 146 return 0; 147 #endif 148 } 149 150 static struct csa_card cards_4610[] = { 151 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 152 }; 153 154 static struct csa_card cards_4614[] = { 155 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 156 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 157 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 158 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 159 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 160 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 161 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 162 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 163 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 164 }; 165 166 static struct csa_card cards_4615[] = { 167 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 168 }; 169 170 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 171 172 struct card_type { 173 u_int32_t devid; 174 char *name; 175 struct csa_card *cards; 176 }; 177 178 static struct card_type cards[] = { 179 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 180 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 181 {CS4615_PCI_ID, "CS4615", cards_4615}, 182 {0, NULL, NULL}, 183 }; 184 185 static struct card_type * 186 csa_findcard(device_t dev) 187 { 188 int i; 189 190 i = 0; 191 while (cards[i].devid != 0) { 192 if (pci_get_devid(dev) == cards[i].devid) 193 return &cards[i]; 194 i++; 195 } 196 return NULL; 197 } 198 199 struct csa_card * 200 csa_findsubcard(device_t dev) 201 { 202 int i; 203 struct card_type *card; 204 struct csa_card *subcard; 205 206 card = csa_findcard(dev); 207 if (card == NULL) 208 return &nocard; 209 subcard = card->cards; 210 i = 0; 211 while (subcard[i].subvendor != 0) { 212 if (pci_get_subvendor(dev) == subcard[i].subvendor 213 && pci_get_subdevice(dev) == subcard[i].subdevice) { 214 return &subcard[i]; 215 } 216 i++; 217 } 218 return &subcard[i]; 219 } 220 221 static int 222 csa_probe(device_t dev) 223 { 224 struct card_type *card; 225 226 card = csa_findcard(dev); 227 if (card) { 228 device_set_desc(dev, card->name); 229 return 0; 230 } 231 return ENXIO; 232 } 233 234 static int 235 csa_attach(device_t dev) 236 { 237 u_int32_t stcmd; 238 sc_p scp; 239 csa_res *resp; 240 struct sndcard_func *func; 241 int error = ENXIO; 242 243 scp = device_get_softc(dev); 244 245 /* Fill in the softc. */ 246 bzero(scp, sizeof(*scp)); 247 scp->dev = dev; 248 249 /* Wake up the device. */ 250 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 251 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 252 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 253 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 254 } 255 256 /* Allocate the resources. */ 257 resp = &scp->res; 258 scp->card = csa_findsubcard(dev); 259 scp->binfo.card = scp->card; 260 printf("csa: card is %s\n", scp->card->name); 261 resp->io_rid = PCIR_BAR(0); 262 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 263 &resp->io_rid, RF_ACTIVE); 264 if (resp->io == NULL) 265 return (ENXIO); 266 resp->mem_rid = PCIR_BAR(1); 267 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 268 &resp->mem_rid, RF_ACTIVE); 269 if (resp->mem == NULL) 270 goto err_io; 271 resp->irq_rid = 0; 272 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 273 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 274 if (resp->irq == NULL) 275 goto err_mem; 276 277 /* Enable interrupt. */ 278 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 279 goto err_intr; 280 #if 0 281 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 282 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 283 #endif 284 285 /* Initialize the chip. */ 286 if (csa_initialize(scp)) 287 goto err_teardown; 288 289 /* Reset the Processor. */ 290 csa_resetdsp(resp); 291 292 /* Download the Processor Image to the processor. */ 293 if (csa_downloadimage(resp)) 294 goto err_teardown; 295 296 /* Attach the children. */ 297 298 /* PCM Audio */ 299 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 300 if (func == NULL) { 301 error = ENOMEM; 302 goto err_teardown; 303 } 304 func->varinfo = &scp->binfo; 305 func->func = SCF_PCM; 306 scp->pcm = device_add_child(dev, "pcm", -1); 307 device_set_ivars(scp->pcm, func); 308 309 /* Midi Interface */ 310 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 311 if (func == NULL) { 312 error = ENOMEM; 313 goto err_teardown; 314 } 315 func->varinfo = &scp->binfo; 316 func->func = SCF_MIDI; 317 scp->midi = device_add_child(dev, "midi", -1); 318 device_set_ivars(scp->midi, func); 319 320 bus_generic_attach(dev); 321 322 return (0); 323 324 err_teardown: 325 bus_teardown_intr(dev, resp->irq, scp->ih); 326 err_intr: 327 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 328 err_mem: 329 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 330 err_io: 331 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 332 return (error); 333 } 334 335 static int 336 csa_detach(device_t dev) 337 { 338 csa_res *resp; 339 sc_p scp; 340 int err; 341 342 scp = device_get_softc(dev); 343 resp = &scp->res; 344 345 err = 0; 346 if (scp->midi != NULL) 347 err = device_delete_child(dev, scp->midi); 348 if (err) 349 return err; 350 scp->midi = NULL; 351 352 if (scp->pcm != NULL) 353 err = device_delete_child(dev, scp->pcm); 354 if (err) 355 return err; 356 scp->pcm = NULL; 357 358 bus_teardown_intr(dev, resp->irq, scp->ih); 359 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 360 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 361 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 362 363 return bus_generic_detach(dev); 364 } 365 366 static int 367 csa_resume(device_t dev) 368 { 369 #if 0 370 /* 371 * XXX: this cannot possibly work 372 * needs to be properly implemented 373 */ 374 csa_detach(dev); 375 csa_attach(dev); 376 #endif 377 return 0; 378 } 379 380 static struct resource * 381 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 382 u_long start, u_long end, u_long count, u_int flags) 383 { 384 sc_p scp; 385 csa_res *resp; 386 struct resource *res; 387 388 scp = device_get_softc(bus); 389 resp = &scp->res; 390 switch (type) { 391 case SYS_RES_IRQ: 392 if (*rid != 0) 393 return (NULL); 394 res = resp->irq; 395 break; 396 case SYS_RES_MEMORY: 397 switch (*rid) { 398 case PCIR_BAR(0): 399 res = resp->io; 400 break; 401 case PCIR_BAR(1): 402 res = resp->mem; 403 break; 404 default: 405 return (NULL); 406 } 407 break; 408 default: 409 return (NULL); 410 } 411 412 return res; 413 } 414 415 static int 416 csa_release_resource(device_t bus, device_t child, int type, int rid, 417 struct resource *r) 418 { 419 return (0); 420 } 421 422 /* 423 * The following three functions deal with interrupt handling. 424 * An interrupt is primarily handled by the bridge driver. 425 * The bridge driver then determines the child devices to pass 426 * the interrupt. Certain information of the device can be read 427 * only once(eg the value of HISR). The bridge driver is responsible 428 * to pass such the information to the children. 429 */ 430 431 static int 432 csa_setup_intr(device_t bus, device_t child, 433 struct resource *irq, int flags, 434 driver_intr_t *intr, void *arg, void **cookiep) 435 { 436 sc_p scp; 437 csa_res *resp; 438 struct sndcard_func *func; 439 440 scp = device_get_softc(bus); 441 resp = &scp->res; 442 443 /* 444 * Look at the function code of the child to determine 445 * the appropriate hander for it. 446 */ 447 func = device_get_ivars(child); 448 if (func == NULL || irq != resp->irq) 449 return (EINVAL); 450 451 switch (func->func) { 452 case SCF_PCM: 453 scp->pcmintr = intr; 454 scp->pcmintr_arg = arg; 455 break; 456 457 case SCF_MIDI: 458 scp->midiintr = intr; 459 scp->midiintr_arg = arg; 460 break; 461 462 default: 463 return (EINVAL); 464 } 465 *cookiep = scp; 466 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 467 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 468 469 return (0); 470 } 471 472 static int 473 csa_teardown_intr(device_t bus, device_t child, 474 struct resource *irq, void *cookie) 475 { 476 sc_p scp; 477 csa_res *resp; 478 struct sndcard_func *func; 479 480 scp = device_get_softc(bus); 481 resp = &scp->res; 482 483 /* 484 * Look at the function code of the child to determine 485 * the appropriate hander for it. 486 */ 487 func = device_get_ivars(child); 488 if (func == NULL || irq != resp->irq || cookie != scp) 489 return (EINVAL); 490 491 switch (func->func) { 492 case SCF_PCM: 493 scp->pcmintr = NULL; 494 scp->pcmintr_arg = NULL; 495 break; 496 497 case SCF_MIDI: 498 scp->midiintr = NULL; 499 scp->midiintr_arg = NULL; 500 break; 501 502 default: 503 return (EINVAL); 504 } 505 506 return (0); 507 } 508 509 /* The interrupt handler */ 510 static void 511 csa_intr(void *arg) 512 { 513 sc_p scp = arg; 514 csa_res *resp; 515 u_int32_t hisr; 516 517 resp = &scp->res; 518 519 /* Is this interrupt for us? */ 520 hisr = csa_readio(resp, BA0_HISR); 521 if ((hisr & 0x7fffffff) == 0) { 522 /* Throw an eoi. */ 523 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 524 return; 525 } 526 527 /* 528 * Pass the value of HISR via struct csa_bridgeinfo. 529 * The children get access through their ivars. 530 */ 531 scp->binfo.hisr = hisr; 532 533 /* Invoke the handlers of the children. */ 534 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 535 scp->pcmintr(scp->pcmintr_arg); 536 hisr &= ~(HISR_VC0 | HISR_VC1); 537 } 538 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 539 scp->midiintr(scp->midiintr_arg); 540 hisr &= ~HISR_MIDI; 541 } 542 543 /* Throw an eoi. */ 544 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 545 } 546 547 static int 548 csa_initialize(sc_p scp) 549 { 550 int i; 551 u_int32_t acsts, acisv; 552 csa_res *resp; 553 554 resp = &scp->res; 555 556 /* 557 * First, blast the clock control register to zero so that the PLL starts 558 * out in a known state, and blast the master serial port control register 559 * to zero so that the serial ports also start out in a known state. 560 */ 561 csa_writeio(resp, BA0_CLKCR1, 0); 562 csa_writeio(resp, BA0_SERMC1, 0); 563 564 /* 565 * If we are in AC97 mode, then we must set the part to a host controlled 566 * AC-link. Otherwise, we won't be able to bring up the link. 567 */ 568 #if 1 569 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 570 #else 571 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 572 #endif /* 1 */ 573 574 /* 575 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 576 * spec) and then drive it high. This is done for non AC97 modes since 577 * there might be logic external to the CS461x that uses the ARST# line 578 * for a reset. 579 */ 580 csa_writeio(resp, BA0_ACCTL, 1); 581 DELAY(50); 582 csa_writeio(resp, BA0_ACCTL, 0); 583 DELAY(50); 584 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 585 586 /* 587 * The first thing we do here is to enable sync generation. As soon 588 * as we start receiving bit clock, we'll start producing the SYNC 589 * signal. 590 */ 591 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 592 593 /* 594 * Now wait for a short while to allow the AC97 part to start 595 * generating bit clock (so we don't try to start the PLL without an 596 * input clock). 597 */ 598 DELAY(50000); 599 600 /* 601 * Set the serial port timing configuration, so that 602 * the clock control circuit gets its clock from the correct place. 603 */ 604 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 605 DELAY(700000); 606 607 /* 608 * Write the selected clock control setup to the hardware. Do not turn on 609 * SWCE yet (if requested), so that the devices clocked by the output of 610 * PLL are not clocked until the PLL is stable. 611 */ 612 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 613 csa_writeio(resp, BA0_PLLM, 0x3a); 614 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 615 616 /* 617 * Power up the PLL. 618 */ 619 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 620 621 /* 622 * Wait until the PLL has stabilized. 623 */ 624 DELAY(5000); 625 626 /* 627 * Turn on clocking of the core so that we can setup the serial ports. 628 */ 629 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 630 631 /* 632 * Fill the serial port FIFOs with silence. 633 */ 634 csa_clearserialfifos(resp); 635 636 /* 637 * Set the serial port FIFO pointer to the first sample in the FIFO. 638 */ 639 #if notdef 640 csa_writeio(resp, BA0_SERBSP, 0); 641 #endif /* notdef */ 642 643 /* 644 * Write the serial port configuration to the part. The master 645 * enable bit is not set until all other values have been written. 646 */ 647 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 648 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 649 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 650 651 /* 652 * Wait for the codec ready signal from the AC97 codec. 653 */ 654 acsts = 0; 655 for (i = 0 ; i < 1000 ; i++) { 656 /* 657 * First, lets wait a short while to let things settle out a bit, 658 * and to prevent retrying the read too quickly. 659 */ 660 DELAY(125); 661 662 /* 663 * Read the AC97 status register to see if we've seen a CODEC READY 664 * signal from the AC97 codec. 665 */ 666 acsts = csa_readio(resp, BA0_ACSTS); 667 if ((acsts & ACSTS_CRDY) != 0) 668 break; 669 } 670 671 /* 672 * Make sure we sampled CODEC READY. 673 */ 674 if ((acsts & ACSTS_CRDY) == 0) 675 return (ENXIO); 676 677 /* 678 * Assert the vaid frame signal so that we can start sending commands 679 * to the AC97 codec. 680 */ 681 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 682 683 /* 684 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 685 * the codec is pumping ADC data across the AC-link. 686 */ 687 acisv = 0; 688 for (i = 0 ; i < 1000 ; i++) { 689 /* 690 * First, lets wait a short while to let things settle out a bit, 691 * and to prevent retrying the read too quickly. 692 */ 693 #if notdef 694 DELAY(10000000L); /* clw */ 695 #else 696 DELAY(1000); 697 #endif /* notdef */ 698 /* 699 * Read the input slot valid register and see if input slots 3 and 700 * 4 are valid yet. 701 */ 702 acisv = csa_readio(resp, BA0_ACISV); 703 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 704 break; 705 } 706 /* 707 * Make sure we sampled valid input slots 3 and 4. If not, then return 708 * an error. 709 */ 710 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 711 return (ENXIO); 712 713 /* 714 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 715 * commense the transfer of digital audio data to the AC97 codec. 716 */ 717 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 718 719 /* 720 * Power down the DAC and ADC. We will power them up (if) when we need 721 * them. 722 */ 723 #if notdef 724 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 725 #endif /* notdef */ 726 727 /* 728 * Turn off the Processor by turning off the software clock enable flag in 729 * the clock control register. 730 */ 731 #if notdef 732 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 733 csa_writeio(resp, BA0_CLKCR1, clkcr1); 734 #endif /* notdef */ 735 736 /* 737 * Enable interrupts on the part. 738 */ 739 #if 0 740 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 741 #endif /* notdef */ 742 743 return (0); 744 } 745 746 void 747 csa_clearserialfifos(csa_res *resp) 748 { 749 int i, j, pwr; 750 u_int8_t clkcr1, serbst; 751 752 /* 753 * See if the devices are powered down. If so, we must power them up first 754 * or they will not respond. 755 */ 756 pwr = 1; 757 clkcr1 = csa_readio(resp, BA0_CLKCR1); 758 if ((clkcr1 & CLKCR1_SWCE) == 0) { 759 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 760 pwr = 0; 761 } 762 763 /* 764 * We want to clear out the serial port FIFOs so we don't end up playing 765 * whatever random garbage happens to be in them. We fill the sample FIFOs 766 * with zero (silence). 767 */ 768 csa_writeio(resp, BA0_SERBWP, 0); 769 770 /* Fill all 256 sample FIFO locations. */ 771 serbst = 0; 772 for (i = 0 ; i < 256 ; i++) { 773 /* Make sure the previous FIFO write operation has completed. */ 774 for (j = 0 ; j < 5 ; j++) { 775 DELAY(100); 776 serbst = csa_readio(resp, BA0_SERBST); 777 if ((serbst & SERBST_WBSY) == 0) 778 break; 779 } 780 if ((serbst & SERBST_WBSY) != 0) { 781 if (!pwr) 782 csa_writeio(resp, BA0_CLKCR1, clkcr1); 783 } 784 /* Write the serial port FIFO index. */ 785 csa_writeio(resp, BA0_SERBAD, i); 786 /* Tell the serial port to load the new value into the FIFO location. */ 787 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 788 } 789 /* 790 * Now, if we powered up the devices, then power them back down again. 791 * This is kinda ugly, but should never happen. 792 */ 793 if (!pwr) 794 csa_writeio(resp, BA0_CLKCR1, clkcr1); 795 } 796 797 static void 798 csa_resetdsp(csa_res *resp) 799 { 800 int i; 801 802 /* 803 * Write the reset bit of the SP control register. 804 */ 805 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 806 807 /* 808 * Write the control register. 809 */ 810 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 811 812 /* 813 * Clear the trap registers. 814 */ 815 for (i = 0 ; i < 8 ; i++) { 816 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 817 csa_writemem(resp, BA1_TWPR, 0xffff); 818 } 819 csa_writemem(resp, BA1_DREG, 0); 820 821 /* 822 * Set the frame timer to reflect the number of cycles per frame. 823 */ 824 csa_writemem(resp, BA1_FRMT, 0xadf); 825 } 826 827 static int 828 csa_downloadimage(csa_res *resp) 829 { 830 int i; 831 u_int32_t tmp, src, dst, count, data; 832 833 for (i = 0; i < CLEAR__COUNT; i++) { 834 dst = ClrStat[i].BA1__DestByteOffset; 835 count = ClrStat[i].BA1__SourceSize; 836 for (tmp = 0; tmp < count; tmp += 4) 837 csa_writemem(resp, dst + tmp, 0x00000000); 838 } 839 840 for (i = 0; i < FILL__COUNT; i++) { 841 src = 0; 842 dst = FillStat[i].Offset; 843 count = FillStat[i].Size; 844 for (tmp = 0; tmp < count; tmp += 4) { 845 data = FillStat[i].pFill[src]; 846 csa_writemem(resp, dst + tmp, data); 847 src++; 848 } 849 } 850 851 return (0); 852 } 853 854 int 855 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 856 { 857 int i; 858 u_int32_t acsda, acctl, acsts; 859 860 /* 861 * Make sure that there is not data sitting around from a previous 862 * uncompleted access. ACSDA = Status Data Register = 47Ch 863 */ 864 acsda = csa_readio(resp, BA0_ACSDA); 865 866 /* 867 * Setup the AC97 control registers on the CS461x to send the 868 * appropriate command to the AC97 to perform the read. 869 * ACCAD = Command Address Register = 46Ch 870 * ACCDA = Command Data Register = 470h 871 * ACCTL = Control Register = 460h 872 * set DCV - will clear when process completed 873 * set CRW - Read command 874 * set VFRM - valid frame enabled 875 * set ESYN - ASYNC generation enabled 876 * set RSTN - ARST# inactive, AC97 codec not reset 877 */ 878 879 /* 880 * Get the actual AC97 register from the offset 881 */ 882 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 883 csa_writeio(resp, BA0_ACCDA, 0); 884 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 885 886 /* 887 * Wait for the read to occur. 888 */ 889 acctl = 0; 890 for (i = 0 ; i < 10 ; i++) { 891 /* 892 * First, we want to wait for a short time. 893 */ 894 DELAY(25); 895 896 /* 897 * Now, check to see if the read has completed. 898 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 899 */ 900 acctl = csa_readio(resp, BA0_ACCTL); 901 if ((acctl & ACCTL_DCV) == 0) 902 break; 903 } 904 905 /* 906 * Make sure the read completed. 907 */ 908 if ((acctl & ACCTL_DCV) != 0) 909 return (EAGAIN); 910 911 /* 912 * Wait for the valid status bit to go active. 913 */ 914 acsts = 0; 915 for (i = 0 ; i < 10 ; i++) { 916 /* 917 * Read the AC97 status register. 918 * ACSTS = Status Register = 464h 919 */ 920 acsts = csa_readio(resp, BA0_ACSTS); 921 /* 922 * See if we have valid status. 923 * VSTS - Valid Status 924 */ 925 if ((acsts & ACSTS_VSTS) != 0) 926 break; 927 /* 928 * Wait for a short while. 929 */ 930 DELAY(25); 931 } 932 933 /* 934 * Make sure we got valid status. 935 */ 936 if ((acsts & ACSTS_VSTS) == 0) 937 return (EAGAIN); 938 939 /* 940 * Read the data returned from the AC97 register. 941 * ACSDA = Status Data Register = 474h 942 */ 943 *data = csa_readio(resp, BA0_ACSDA); 944 945 return (0); 946 } 947 948 int 949 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 950 { 951 int i; 952 u_int32_t acctl; 953 954 /* 955 * Setup the AC97 control registers on the CS461x to send the 956 * appropriate command to the AC97 to perform the write. 957 * ACCAD = Command Address Register = 46Ch 958 * ACCDA = Command Data Register = 470h 959 * ACCTL = Control Register = 460h 960 * set DCV - will clear when process completed 961 * set VFRM - valid frame enabled 962 * set ESYN - ASYNC generation enabled 963 * set RSTN - ARST# inactive, AC97 codec not reset 964 */ 965 966 /* 967 * Get the actual AC97 register from the offset 968 */ 969 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 970 csa_writeio(resp, BA0_ACCDA, data); 971 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 972 973 /* 974 * Wait for the write to occur. 975 */ 976 acctl = 0; 977 for (i = 0 ; i < 10 ; i++) { 978 /* 979 * First, we want to wait for a short time. 980 */ 981 DELAY(25); 982 983 /* 984 * Now, check to see if the read has completed. 985 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 986 */ 987 acctl = csa_readio(resp, BA0_ACCTL); 988 if ((acctl & ACCTL_DCV) == 0) 989 break; 990 } 991 992 /* 993 * Make sure the write completed. 994 */ 995 if ((acctl & ACCTL_DCV) != 0) 996 return (EAGAIN); 997 998 return (0); 999 } 1000 1001 u_int32_t 1002 csa_readio(csa_res *resp, u_long offset) 1003 { 1004 u_int32_t ul; 1005 1006 if (offset < BA0_AC97_RESET) 1007 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1008 else { 1009 if (csa_readcodec(resp, offset, &ul)) 1010 ul = 0; 1011 return (ul); 1012 } 1013 } 1014 1015 void 1016 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1017 { 1018 if (offset < BA0_AC97_RESET) 1019 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1020 else 1021 csa_writecodec(resp, offset, data); 1022 } 1023 1024 u_int32_t 1025 csa_readmem(csa_res *resp, u_long offset) 1026 { 1027 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1028 } 1029 1030 void 1031 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1032 { 1033 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1034 } 1035 1036 static device_method_t csa_methods[] = { 1037 /* Device interface */ 1038 DEVMETHOD(device_probe, csa_probe), 1039 DEVMETHOD(device_attach, csa_attach), 1040 DEVMETHOD(device_detach, csa_detach), 1041 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1042 DEVMETHOD(device_suspend, bus_generic_suspend), 1043 DEVMETHOD(device_resume, csa_resume), 1044 1045 /* Bus interface */ 1046 DEVMETHOD(bus_print_child, bus_generic_print_child), 1047 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1048 DEVMETHOD(bus_release_resource, csa_release_resource), 1049 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1050 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1051 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1052 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1053 1054 { 0, 0 } 1055 }; 1056 1057 static driver_t csa_driver = { 1058 "csa", 1059 csa_methods, 1060 sizeof(struct csa_softc), 1061 }; 1062 1063 /* 1064 * csa can be attached to a pci bus. 1065 */ 1066 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1067 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1068 MODULE_VERSION(snd_csa, 1); 1069