1 /*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 #include <sys/soundcard.h> 41 #include <dev/sound/pcm/sound.h> 42 #include <dev/sound/chip.h> 43 #include <dev/sound/pci/csareg.h> 44 #include <dev/sound/pci/csavar.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <gnu/dev/sound/pci/csaimg.h> 50 51 SND_DECLARE_FILE("$FreeBSD$"); 52 53 /* This is the pci device id. */ 54 #define CS4610_PCI_ID 0x60011013 55 #define CS4614_PCI_ID 0x60031013 56 #define CS4615_PCI_ID 0x60041013 57 58 /* Here is the parameter structure per a device. */ 59 struct csa_softc { 60 device_t dev; /* device */ 61 csa_res res; /* resources */ 62 63 device_t pcm; /* pcm device */ 64 driver_intr_t* pcmintr; /* pcm intr */ 65 void *pcmintr_arg; /* pcm intr arg */ 66 device_t midi; /* midi device */ 67 driver_intr_t* midiintr; /* midi intr */ 68 void *midiintr_arg; /* midi intr arg */ 69 void *ih; /* cookie */ 70 71 struct csa_card *card; 72 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 73 }; 74 75 typedef struct csa_softc *sc_p; 76 77 static int csa_probe(device_t dev); 78 static int csa_attach(device_t dev); 79 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 80 u_long start, u_long end, u_long count, u_int flags); 81 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 82 struct resource *r); 83 static int csa_setup_intr(device_t bus, device_t child, 84 struct resource *irq, int flags, 85 driver_filter_t *filter, driver_intr_t *intr, 86 void *arg, void **cookiep); 87 static int csa_teardown_intr(device_t bus, device_t child, 88 struct resource *irq, void *cookie); 89 static driver_intr_t csa_intr; 90 static int csa_initialize(sc_p scp); 91 static int csa_downloadimage(csa_res *resp); 92 93 static devclass_t csa_devclass; 94 95 static void 96 amp_none(void) 97 { 98 } 99 100 static void 101 amp_voyetra(void) 102 { 103 } 104 105 static int 106 clkrun_hack(int run) 107 { 108 #ifdef __i386__ 109 devclass_t pci_devclass; 110 device_t *pci_devices, *pci_children, *busp, *childp; 111 int pci_count = 0, pci_childcount = 0; 112 int i, j, port; 113 u_int16_t control; 114 bus_space_tag_t btag; 115 116 if ((pci_devclass = devclass_find("pci")) == NULL) { 117 return ENXIO; 118 } 119 120 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 121 122 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 123 pci_childcount = 0; 124 device_get_children(*busp, &pci_children, &pci_childcount); 125 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 126 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 127 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 128 /* XXX */ 129 btag = I386_BUS_SPACE_IO; 130 131 control = bus_space_read_2(btag, 0x0, port); 132 control &= ~0x2000; 133 control |= run? 0 : 0x2000; 134 bus_space_write_2(btag, 0x0, port, control); 135 free(pci_devices, M_TEMP); 136 free(pci_children, M_TEMP); 137 return 0; 138 } 139 } 140 free(pci_children, M_TEMP); 141 } 142 143 free(pci_devices, M_TEMP); 144 return ENXIO; 145 #else 146 return 0; 147 #endif 148 } 149 150 static struct csa_card cards_4610[] = { 151 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 152 }; 153 154 static struct csa_card cards_4614[] = { 155 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 156 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 157 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 158 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 159 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 160 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 161 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 162 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 163 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 164 }; 165 166 static struct csa_card cards_4615[] = { 167 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 168 }; 169 170 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 171 172 struct card_type { 173 u_int32_t devid; 174 char *name; 175 struct csa_card *cards; 176 }; 177 178 static struct card_type cards[] = { 179 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 180 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 181 {CS4615_PCI_ID, "CS4615", cards_4615}, 182 {0, NULL, NULL}, 183 }; 184 185 static struct card_type * 186 csa_findcard(device_t dev) 187 { 188 int i; 189 190 i = 0; 191 while (cards[i].devid != 0) { 192 if (pci_get_devid(dev) == cards[i].devid) 193 return &cards[i]; 194 i++; 195 } 196 return NULL; 197 } 198 199 struct csa_card * 200 csa_findsubcard(device_t dev) 201 { 202 int i; 203 struct card_type *card; 204 struct csa_card *subcard; 205 206 card = csa_findcard(dev); 207 if (card == NULL) 208 return &nocard; 209 subcard = card->cards; 210 i = 0; 211 while (subcard[i].subvendor != 0) { 212 if (pci_get_subvendor(dev) == subcard[i].subvendor 213 && pci_get_subdevice(dev) == subcard[i].subdevice) { 214 return &subcard[i]; 215 } 216 i++; 217 } 218 return &subcard[i]; 219 } 220 221 static int 222 csa_probe(device_t dev) 223 { 224 struct card_type *card; 225 226 card = csa_findcard(dev); 227 if (card) { 228 device_set_desc(dev, card->name); 229 return BUS_PROBE_DEFAULT; 230 } 231 return ENXIO; 232 } 233 234 static int 235 csa_attach(device_t dev) 236 { 237 u_int32_t stcmd; 238 sc_p scp; 239 csa_res *resp; 240 struct sndcard_func *func; 241 int error = ENXIO; 242 243 scp = device_get_softc(dev); 244 245 /* Fill in the softc. */ 246 bzero(scp, sizeof(*scp)); 247 scp->dev = dev; 248 249 /* Wake up the device. */ 250 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 251 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 252 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 253 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 254 } 255 256 /* Allocate the resources. */ 257 resp = &scp->res; 258 scp->card = csa_findsubcard(dev); 259 scp->binfo.card = scp->card; 260 printf("csa: card is %s\n", scp->card->name); 261 resp->io_rid = PCIR_BAR(0); 262 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 263 &resp->io_rid, RF_ACTIVE); 264 if (resp->io == NULL) 265 return (ENXIO); 266 resp->mem_rid = PCIR_BAR(1); 267 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 268 &resp->mem_rid, RF_ACTIVE); 269 if (resp->mem == NULL) 270 goto err_io; 271 resp->irq_rid = 0; 272 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 273 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 274 if (resp->irq == NULL) 275 goto err_mem; 276 277 /* Enable interrupt. */ 278 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 279 goto err_intr; 280 #if 0 281 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 282 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 283 #endif 284 285 /* Initialize the chip. */ 286 if (csa_initialize(scp)) 287 goto err_teardown; 288 289 /* Reset the Processor. */ 290 csa_resetdsp(resp); 291 292 /* Download the Processor Image to the processor. */ 293 if (csa_downloadimage(resp)) 294 goto err_teardown; 295 296 /* Attach the children. */ 297 298 /* PCM Audio */ 299 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 300 if (func == NULL) { 301 error = ENOMEM; 302 goto err_teardown; 303 } 304 func->varinfo = &scp->binfo; 305 func->func = SCF_PCM; 306 scp->pcm = device_add_child(dev, "pcm", -1); 307 device_set_ivars(scp->pcm, func); 308 309 /* Midi Interface */ 310 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 311 if (func == NULL) { 312 error = ENOMEM; 313 goto err_teardown; 314 } 315 func->varinfo = &scp->binfo; 316 func->func = SCF_MIDI; 317 scp->midi = device_add_child(dev, "midi", -1); 318 device_set_ivars(scp->midi, func); 319 320 bus_generic_attach(dev); 321 322 return (0); 323 324 err_teardown: 325 bus_teardown_intr(dev, resp->irq, scp->ih); 326 err_intr: 327 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 328 err_mem: 329 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 330 err_io: 331 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 332 return (error); 333 } 334 335 static int 336 csa_detach(device_t dev) 337 { 338 csa_res *resp; 339 sc_p scp; 340 int err; 341 342 scp = device_get_softc(dev); 343 resp = &scp->res; 344 345 err = 0; 346 if (scp->midi != NULL) 347 err = device_delete_child(dev, scp->midi); 348 if (err) 349 return err; 350 scp->midi = NULL; 351 352 if (scp->pcm != NULL) 353 err = device_delete_child(dev, scp->pcm); 354 if (err) 355 return err; 356 scp->pcm = NULL; 357 358 bus_teardown_intr(dev, resp->irq, scp->ih); 359 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 360 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 361 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 362 363 return bus_generic_detach(dev); 364 } 365 366 static int 367 csa_resume(device_t dev) 368 { 369 csa_res *resp; 370 sc_p scp; 371 372 scp = device_get_softc(dev); 373 resp = &scp->res; 374 375 /* Initialize the chip. */ 376 if (csa_initialize(scp)) 377 return (ENXIO); 378 379 /* Reset the Processor. */ 380 csa_resetdsp(resp); 381 382 /* Download the Processor Image to the processor. */ 383 if (csa_downloadimage(resp)) 384 return (ENXIO); 385 386 return (bus_generic_resume(dev)); 387 } 388 389 static struct resource * 390 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 391 u_long start, u_long end, u_long count, u_int flags) 392 { 393 sc_p scp; 394 csa_res *resp; 395 struct resource *res; 396 397 scp = device_get_softc(bus); 398 resp = &scp->res; 399 switch (type) { 400 case SYS_RES_IRQ: 401 if (*rid != 0) 402 return (NULL); 403 res = resp->irq; 404 break; 405 case SYS_RES_MEMORY: 406 switch (*rid) { 407 case PCIR_BAR(0): 408 res = resp->io; 409 break; 410 case PCIR_BAR(1): 411 res = resp->mem; 412 break; 413 default: 414 return (NULL); 415 } 416 break; 417 default: 418 return (NULL); 419 } 420 421 return res; 422 } 423 424 static int 425 csa_release_resource(device_t bus, device_t child, int type, int rid, 426 struct resource *r) 427 { 428 return (0); 429 } 430 431 /* 432 * The following three functions deal with interrupt handling. 433 * An interrupt is primarily handled by the bridge driver. 434 * The bridge driver then determines the child devices to pass 435 * the interrupt. Certain information of the device can be read 436 * only once(eg the value of HISR). The bridge driver is responsible 437 * to pass such the information to the children. 438 */ 439 440 static int 441 csa_setup_intr(device_t bus, device_t child, 442 struct resource *irq, int flags, 443 driver_filter_t *filter, driver_intr_t *intr, void *arg, 444 void **cookiep) 445 { 446 sc_p scp; 447 csa_res *resp; 448 struct sndcard_func *func; 449 450 if (filter != NULL) { 451 printf("ata-csa.c: we cannot use a filter here\n"); 452 return (EINVAL); 453 } 454 scp = device_get_softc(bus); 455 resp = &scp->res; 456 457 /* 458 * Look at the function code of the child to determine 459 * the appropriate hander for it. 460 */ 461 func = device_get_ivars(child); 462 if (func == NULL || irq != resp->irq) 463 return (EINVAL); 464 465 switch (func->func) { 466 case SCF_PCM: 467 scp->pcmintr = intr; 468 scp->pcmintr_arg = arg; 469 break; 470 471 case SCF_MIDI: 472 scp->midiintr = intr; 473 scp->midiintr_arg = arg; 474 break; 475 476 default: 477 return (EINVAL); 478 } 479 *cookiep = scp; 480 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 481 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 482 483 return (0); 484 } 485 486 static int 487 csa_teardown_intr(device_t bus, device_t child, 488 struct resource *irq, void *cookie) 489 { 490 sc_p scp; 491 csa_res *resp; 492 struct sndcard_func *func; 493 494 scp = device_get_softc(bus); 495 resp = &scp->res; 496 497 /* 498 * Look at the function code of the child to determine 499 * the appropriate hander for it. 500 */ 501 func = device_get_ivars(child); 502 if (func == NULL || irq != resp->irq || cookie != scp) 503 return (EINVAL); 504 505 switch (func->func) { 506 case SCF_PCM: 507 scp->pcmintr = NULL; 508 scp->pcmintr_arg = NULL; 509 break; 510 511 case SCF_MIDI: 512 scp->midiintr = NULL; 513 scp->midiintr_arg = NULL; 514 break; 515 516 default: 517 return (EINVAL); 518 } 519 520 return (0); 521 } 522 523 /* The interrupt handler */ 524 static void 525 csa_intr(void *arg) 526 { 527 sc_p scp = arg; 528 csa_res *resp; 529 u_int32_t hisr; 530 531 resp = &scp->res; 532 533 /* Is this interrupt for us? */ 534 hisr = csa_readio(resp, BA0_HISR); 535 if ((hisr & 0x7fffffff) == 0) { 536 /* Throw an eoi. */ 537 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 538 return; 539 } 540 541 /* 542 * Pass the value of HISR via struct csa_bridgeinfo. 543 * The children get access through their ivars. 544 */ 545 scp->binfo.hisr = hisr; 546 547 /* Invoke the handlers of the children. */ 548 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 549 scp->pcmintr(scp->pcmintr_arg); 550 hisr &= ~(HISR_VC0 | HISR_VC1); 551 } 552 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 553 scp->midiintr(scp->midiintr_arg); 554 hisr &= ~HISR_MIDI; 555 } 556 557 /* Throw an eoi. */ 558 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 559 } 560 561 static int 562 csa_initialize(sc_p scp) 563 { 564 int i; 565 u_int32_t acsts, acisv; 566 csa_res *resp; 567 568 resp = &scp->res; 569 570 /* 571 * First, blast the clock control register to zero so that the PLL starts 572 * out in a known state, and blast the master serial port control register 573 * to zero so that the serial ports also start out in a known state. 574 */ 575 csa_writeio(resp, BA0_CLKCR1, 0); 576 csa_writeio(resp, BA0_SERMC1, 0); 577 578 /* 579 * If we are in AC97 mode, then we must set the part to a host controlled 580 * AC-link. Otherwise, we won't be able to bring up the link. 581 */ 582 #if 1 583 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 584 #else 585 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 586 #endif /* 1 */ 587 588 /* 589 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 590 * spec) and then drive it high. This is done for non AC97 modes since 591 * there might be logic external to the CS461x that uses the ARST# line 592 * for a reset. 593 */ 594 csa_writeio(resp, BA0_ACCTL, 1); 595 DELAY(50); 596 csa_writeio(resp, BA0_ACCTL, 0); 597 DELAY(50); 598 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 599 600 /* 601 * The first thing we do here is to enable sync generation. As soon 602 * as we start receiving bit clock, we'll start producing the SYNC 603 * signal. 604 */ 605 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 606 607 /* 608 * Now wait for a short while to allow the AC97 part to start 609 * generating bit clock (so we don't try to start the PLL without an 610 * input clock). 611 */ 612 DELAY(50000); 613 614 /* 615 * Set the serial port timing configuration, so that 616 * the clock control circuit gets its clock from the correct place. 617 */ 618 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 619 DELAY(700000); 620 621 /* 622 * Write the selected clock control setup to the hardware. Do not turn on 623 * SWCE yet (if requested), so that the devices clocked by the output of 624 * PLL are not clocked until the PLL is stable. 625 */ 626 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 627 csa_writeio(resp, BA0_PLLM, 0x3a); 628 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 629 630 /* 631 * Power up the PLL. 632 */ 633 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 634 635 /* 636 * Wait until the PLL has stabilized. 637 */ 638 DELAY(5000); 639 640 /* 641 * Turn on clocking of the core so that we can setup the serial ports. 642 */ 643 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 644 645 /* 646 * Fill the serial port FIFOs with silence. 647 */ 648 csa_clearserialfifos(resp); 649 650 /* 651 * Set the serial port FIFO pointer to the first sample in the FIFO. 652 */ 653 #ifdef notdef 654 csa_writeio(resp, BA0_SERBSP, 0); 655 #endif /* notdef */ 656 657 /* 658 * Write the serial port configuration to the part. The master 659 * enable bit is not set until all other values have been written. 660 */ 661 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 662 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 663 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 664 665 /* 666 * Wait for the codec ready signal from the AC97 codec. 667 */ 668 acsts = 0; 669 for (i = 0 ; i < 1000 ; i++) { 670 /* 671 * First, lets wait a short while to let things settle out a bit, 672 * and to prevent retrying the read too quickly. 673 */ 674 DELAY(125); 675 676 /* 677 * Read the AC97 status register to see if we've seen a CODEC READY 678 * signal from the AC97 codec. 679 */ 680 acsts = csa_readio(resp, BA0_ACSTS); 681 if ((acsts & ACSTS_CRDY) != 0) 682 break; 683 } 684 685 /* 686 * Make sure we sampled CODEC READY. 687 */ 688 if ((acsts & ACSTS_CRDY) == 0) 689 return (ENXIO); 690 691 /* 692 * Assert the vaid frame signal so that we can start sending commands 693 * to the AC97 codec. 694 */ 695 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 696 697 /* 698 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 699 * the codec is pumping ADC data across the AC-link. 700 */ 701 acisv = 0; 702 for (i = 0 ; i < 1000 ; i++) { 703 /* 704 * First, lets wait a short while to let things settle out a bit, 705 * and to prevent retrying the read too quickly. 706 */ 707 #ifdef notdef 708 DELAY(10000000L); /* clw */ 709 #else 710 DELAY(1000); 711 #endif /* notdef */ 712 /* 713 * Read the input slot valid register and see if input slots 3 and 714 * 4 are valid yet. 715 */ 716 acisv = csa_readio(resp, BA0_ACISV); 717 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 718 break; 719 } 720 /* 721 * Make sure we sampled valid input slots 3 and 4. If not, then return 722 * an error. 723 */ 724 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 725 return (ENXIO); 726 727 /* 728 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 729 * commense the transfer of digital audio data to the AC97 codec. 730 */ 731 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 732 733 /* 734 * Power down the DAC and ADC. We will power them up (if) when we need 735 * them. 736 */ 737 #ifdef notdef 738 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 739 #endif /* notdef */ 740 741 /* 742 * Turn off the Processor by turning off the software clock enable flag in 743 * the clock control register. 744 */ 745 #ifdef notdef 746 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 747 csa_writeio(resp, BA0_CLKCR1, clkcr1); 748 #endif /* notdef */ 749 750 /* 751 * Enable interrupts on the part. 752 */ 753 #if 0 754 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 755 #endif /* notdef */ 756 757 return (0); 758 } 759 760 void 761 csa_clearserialfifos(csa_res *resp) 762 { 763 int i, j, pwr; 764 u_int8_t clkcr1, serbst; 765 766 /* 767 * See if the devices are powered down. If so, we must power them up first 768 * or they will not respond. 769 */ 770 pwr = 1; 771 clkcr1 = csa_readio(resp, BA0_CLKCR1); 772 if ((clkcr1 & CLKCR1_SWCE) == 0) { 773 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 774 pwr = 0; 775 } 776 777 /* 778 * We want to clear out the serial port FIFOs so we don't end up playing 779 * whatever random garbage happens to be in them. We fill the sample FIFOs 780 * with zero (silence). 781 */ 782 csa_writeio(resp, BA0_SERBWP, 0); 783 784 /* Fill all 256 sample FIFO locations. */ 785 serbst = 0; 786 for (i = 0 ; i < 256 ; i++) { 787 /* Make sure the previous FIFO write operation has completed. */ 788 for (j = 0 ; j < 5 ; j++) { 789 DELAY(100); 790 serbst = csa_readio(resp, BA0_SERBST); 791 if ((serbst & SERBST_WBSY) == 0) 792 break; 793 } 794 if ((serbst & SERBST_WBSY) != 0) { 795 if (!pwr) 796 csa_writeio(resp, BA0_CLKCR1, clkcr1); 797 } 798 /* Write the serial port FIFO index. */ 799 csa_writeio(resp, BA0_SERBAD, i); 800 /* Tell the serial port to load the new value into the FIFO location. */ 801 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 802 } 803 /* 804 * Now, if we powered up the devices, then power them back down again. 805 * This is kinda ugly, but should never happen. 806 */ 807 if (!pwr) 808 csa_writeio(resp, BA0_CLKCR1, clkcr1); 809 } 810 811 void 812 csa_resetdsp(csa_res *resp) 813 { 814 int i; 815 816 /* 817 * Write the reset bit of the SP control register. 818 */ 819 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 820 821 /* 822 * Write the control register. 823 */ 824 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 825 826 /* 827 * Clear the trap registers. 828 */ 829 for (i = 0 ; i < 8 ; i++) { 830 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 831 csa_writemem(resp, BA1_TWPR, 0xffff); 832 } 833 csa_writemem(resp, BA1_DREG, 0); 834 835 /* 836 * Set the frame timer to reflect the number of cycles per frame. 837 */ 838 csa_writemem(resp, BA1_FRMT, 0xadf); 839 } 840 841 static int 842 csa_downloadimage(csa_res *resp) 843 { 844 int i; 845 u_int32_t tmp, src, dst, count, data; 846 847 for (i = 0; i < CLEAR__COUNT; i++) { 848 dst = ClrStat[i].BA1__DestByteOffset; 849 count = ClrStat[i].BA1__SourceSize; 850 for (tmp = 0; tmp < count; tmp += 4) 851 csa_writemem(resp, dst + tmp, 0x00000000); 852 } 853 854 for (i = 0; i < FILL__COUNT; i++) { 855 src = 0; 856 dst = FillStat[i].Offset; 857 count = FillStat[i].Size; 858 for (tmp = 0; tmp < count; tmp += 4) { 859 data = FillStat[i].pFill[src]; 860 csa_writemem(resp, dst + tmp, data); 861 src++; 862 } 863 } 864 865 return (0); 866 } 867 868 int 869 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 870 { 871 int i; 872 u_int32_t acsda, acctl, acsts; 873 874 /* 875 * Make sure that there is not data sitting around from a previous 876 * uncompleted access. ACSDA = Status Data Register = 47Ch 877 */ 878 acsda = csa_readio(resp, BA0_ACSDA); 879 880 /* 881 * Setup the AC97 control registers on the CS461x to send the 882 * appropriate command to the AC97 to perform the read. 883 * ACCAD = Command Address Register = 46Ch 884 * ACCDA = Command Data Register = 470h 885 * ACCTL = Control Register = 460h 886 * set DCV - will clear when process completed 887 * set CRW - Read command 888 * set VFRM - valid frame enabled 889 * set ESYN - ASYNC generation enabled 890 * set RSTN - ARST# inactive, AC97 codec not reset 891 */ 892 893 /* 894 * Get the actual AC97 register from the offset 895 */ 896 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 897 csa_writeio(resp, BA0_ACCDA, 0); 898 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 899 900 /* 901 * Wait for the read to occur. 902 */ 903 acctl = 0; 904 for (i = 0 ; i < 10 ; i++) { 905 /* 906 * First, we want to wait for a short time. 907 */ 908 DELAY(25); 909 910 /* 911 * Now, check to see if the read has completed. 912 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 913 */ 914 acctl = csa_readio(resp, BA0_ACCTL); 915 if ((acctl & ACCTL_DCV) == 0) 916 break; 917 } 918 919 /* 920 * Make sure the read completed. 921 */ 922 if ((acctl & ACCTL_DCV) != 0) 923 return (EAGAIN); 924 925 /* 926 * Wait for the valid status bit to go active. 927 */ 928 acsts = 0; 929 for (i = 0 ; i < 10 ; i++) { 930 /* 931 * Read the AC97 status register. 932 * ACSTS = Status Register = 464h 933 */ 934 acsts = csa_readio(resp, BA0_ACSTS); 935 /* 936 * See if we have valid status. 937 * VSTS - Valid Status 938 */ 939 if ((acsts & ACSTS_VSTS) != 0) 940 break; 941 /* 942 * Wait for a short while. 943 */ 944 DELAY(25); 945 } 946 947 /* 948 * Make sure we got valid status. 949 */ 950 if ((acsts & ACSTS_VSTS) == 0) 951 return (EAGAIN); 952 953 /* 954 * Read the data returned from the AC97 register. 955 * ACSDA = Status Data Register = 474h 956 */ 957 *data = csa_readio(resp, BA0_ACSDA); 958 959 return (0); 960 } 961 962 int 963 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 964 { 965 int i; 966 u_int32_t acctl; 967 968 /* 969 * Setup the AC97 control registers on the CS461x to send the 970 * appropriate command to the AC97 to perform the write. 971 * ACCAD = Command Address Register = 46Ch 972 * ACCDA = Command Data Register = 470h 973 * ACCTL = Control Register = 460h 974 * set DCV - will clear when process completed 975 * set VFRM - valid frame enabled 976 * set ESYN - ASYNC generation enabled 977 * set RSTN - ARST# inactive, AC97 codec not reset 978 */ 979 980 /* 981 * Get the actual AC97 register from the offset 982 */ 983 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 984 csa_writeio(resp, BA0_ACCDA, data); 985 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 986 987 /* 988 * Wait for the write to occur. 989 */ 990 acctl = 0; 991 for (i = 0 ; i < 10 ; i++) { 992 /* 993 * First, we want to wait for a short time. 994 */ 995 DELAY(25); 996 997 /* 998 * Now, check to see if the read has completed. 999 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1000 */ 1001 acctl = csa_readio(resp, BA0_ACCTL); 1002 if ((acctl & ACCTL_DCV) == 0) 1003 break; 1004 } 1005 1006 /* 1007 * Make sure the write completed. 1008 */ 1009 if ((acctl & ACCTL_DCV) != 0) 1010 return (EAGAIN); 1011 1012 return (0); 1013 } 1014 1015 u_int32_t 1016 csa_readio(csa_res *resp, u_long offset) 1017 { 1018 u_int32_t ul; 1019 1020 if (offset < BA0_AC97_RESET) 1021 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1022 else { 1023 if (csa_readcodec(resp, offset, &ul)) 1024 ul = 0; 1025 return (ul); 1026 } 1027 } 1028 1029 void 1030 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1031 { 1032 if (offset < BA0_AC97_RESET) 1033 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1034 else 1035 csa_writecodec(resp, offset, data); 1036 } 1037 1038 u_int32_t 1039 csa_readmem(csa_res *resp, u_long offset) 1040 { 1041 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1042 } 1043 1044 void 1045 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1046 { 1047 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1048 } 1049 1050 static device_method_t csa_methods[] = { 1051 /* Device interface */ 1052 DEVMETHOD(device_probe, csa_probe), 1053 DEVMETHOD(device_attach, csa_attach), 1054 DEVMETHOD(device_detach, csa_detach), 1055 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1056 DEVMETHOD(device_suspend, bus_generic_suspend), 1057 DEVMETHOD(device_resume, csa_resume), 1058 1059 /* Bus interface */ 1060 DEVMETHOD(bus_print_child, bus_generic_print_child), 1061 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1062 DEVMETHOD(bus_release_resource, csa_release_resource), 1063 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1064 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1065 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1066 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1067 1068 { 0, 0 } 1069 }; 1070 1071 static driver_t csa_driver = { 1072 "csa", 1073 csa_methods, 1074 sizeof(struct csa_softc), 1075 }; 1076 1077 /* 1078 * csa can be attached to a pci bus. 1079 */ 1080 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1081 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1082 MODULE_VERSION(snd_csa, 1); 1083