xref: /freebsd/sys/dev/sound/pci/csa.c (revision 70fe064ad7cab6c0444b91622f60ec6a462f308a)
1 /*
2  * Copyright (c) 1999 Seigo Tanimura
3  * All rights reserved.
4  *
5  * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
6  * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
7  * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  */
30 
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/bus.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <machine/resource.h>
38 #include <machine/bus.h>
39 #include <sys/rman.h>
40 #include <sys/soundcard.h>
41 #include <dev/sound/pcm/sound.h>
42 #include <dev/sound/chip.h>
43 #include <dev/sound/pci/csareg.h>
44 #include <dev/sound/pci/csavar.h>
45 
46 #include <pci/pcireg.h>
47 #include <pci/pcivar.h>
48 
49 #include <gnu/dev/sound/pci/csaimg.h>
50 
51 SND_DECLARE_FILE("$FreeBSD$");
52 
53 /* This is the pci device id. */
54 #define CS4610_PCI_ID 0x60011013
55 #define CS4614_PCI_ID 0x60031013
56 #define CS4615_PCI_ID 0x60041013
57 
58 /* Here is the parameter structure per a device. */
59 struct csa_softc {
60 	device_t dev; /* device */
61 	csa_res res; /* resources */
62 
63 	device_t pcm; /* pcm device */
64 	driver_intr_t* pcmintr; /* pcm intr */
65 	void *pcmintr_arg; /* pcm intr arg */
66 	device_t midi; /* midi device */
67 	driver_intr_t* midiintr; /* midi intr */
68 	void *midiintr_arg; /* midi intr arg */
69 	void *ih; /* cookie */
70 
71 	struct csa_card *card;
72 	struct csa_bridgeinfo binfo; /* The state of this bridge. */
73 };
74 
75 typedef struct csa_softc *sc_p;
76 
77 static int csa_probe(device_t dev);
78 static int csa_attach(device_t dev);
79 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
80 					      u_long start, u_long end, u_long count, u_int flags);
81 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
82 				   struct resource *r);
83 static int csa_setup_intr(device_t bus, device_t child,
84 			  struct resource *irq, int flags,
85 			  driver_intr_t *intr, void *arg, void **cookiep);
86 static int csa_teardown_intr(device_t bus, device_t child,
87 			     struct resource *irq, void *cookie);
88 static driver_intr_t csa_intr;
89 static int csa_initialize(sc_p scp);
90 static void csa_resetdsp(csa_res *resp);
91 static int csa_downloadimage(csa_res *resp);
92 
93 static devclass_t csa_devclass;
94 
95 static void
96 amp_none(void)
97 {
98 }
99 
100 static void
101 amp_voyetra(void)
102 {
103 }
104 
105 static int
106 clkrun_hack(int run)
107 {
108 #ifdef __i386__
109 	devclass_t		pci_devclass;
110 	device_t		*pci_devices, *pci_children, *busp, *childp;
111 	int			pci_count = 0, pci_childcount = 0;
112 	int			i, j, port;
113 	u_int16_t		control;
114 	bus_space_tag_t		btag;
115 
116 	if ((pci_devclass = devclass_find("pci")) == NULL) {
117 		return ENXIO;
118 	}
119 
120 	devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
121 
122 	for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
123 		pci_childcount = 0;
124 		device_get_children(*busp, &pci_children, &pci_childcount);
125 		for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
126 			if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
127 				port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
128 				/* XXX */
129 				btag = I386_BUS_SPACE_IO;
130 
131 				control = bus_space_read_2(btag, 0x0, port);
132 				control &= ~0x2000;
133 				control |= run? 0 : 0x2000;
134 				bus_space_write_2(btag, 0x0, port, control);
135 				free(pci_devices, M_TEMP);
136 				free(pci_children, M_TEMP);
137 				return 0;
138 			}
139 		}
140 		free(pci_children, M_TEMP);
141 	}
142 
143 	free(pci_devices, M_TEMP);
144 	return ENXIO;
145 #else
146 	return 0;
147 #endif
148 }
149 
150 static struct csa_card cards_4610[] = {
151 	{0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
152 };
153 
154 static struct csa_card cards_4614[] = {
155 	{0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
156 	{0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
157 	{0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
158 	{0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
159 	{0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
160 	{0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
161 	{0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
162 	{0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
163 	{0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
164 };
165 
166 static struct csa_card cards_4615[] = {
167 	{0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
168 };
169 
170 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
171 
172 struct card_type {
173 	u_int32_t devid;
174 	char *name;
175 	struct csa_card *cards;
176 };
177 
178 static struct card_type cards[] = {
179 	{CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
180 	{CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
181 	{CS4615_PCI_ID, "CS4615", cards_4615},
182 	{0, NULL, NULL},
183 };
184 
185 static struct card_type *
186 csa_findcard(device_t dev)
187 {
188 	int i;
189 
190 	i = 0;
191 	while (cards[i].devid != 0) {
192 		if (pci_get_devid(dev) == cards[i].devid)
193 			return &cards[i];
194 		i++;
195 	}
196 	return NULL;
197 }
198 
199 struct csa_card *
200 csa_findsubcard(device_t dev)
201 {
202 	int i;
203 	struct card_type *card;
204 	struct csa_card *subcard;
205 
206 	card = csa_findcard(dev);
207 	if (card == NULL)
208 		return &nocard;
209 	subcard = card->cards;
210 	i = 0;
211 	while (subcard[i].subvendor != 0) {
212 		if (pci_get_subvendor(dev) == subcard[i].subvendor
213 		    && pci_get_subdevice(dev) == subcard[i].subdevice) {
214 			return &subcard[i];
215 		}
216 		i++;
217 	}
218 	return &subcard[i];
219 }
220 
221 static int
222 csa_probe(device_t dev)
223 {
224 	struct card_type *card;
225 
226 	card = csa_findcard(dev);
227 	if (card) {
228 		device_set_desc(dev, card->name);
229 		return 0;
230 	}
231 	return ENXIO;
232 }
233 
234 static int
235 csa_attach(device_t dev)
236 {
237 	u_int32_t stcmd;
238 	sc_p scp;
239 	csa_res *resp;
240 	struct sndcard_func *func;
241 	int error = ENXIO;
242 
243 	scp = device_get_softc(dev);
244 
245 	/* Fill in the softc. */
246 	bzero(scp, sizeof(*scp));
247 	scp->dev = dev;
248 
249 	/* Wake up the device. */
250 	stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
251 	if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
252 		stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
253 		pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
254 	}
255 
256 	/* Allocate the resources. */
257 	resp = &scp->res;
258 	scp->card = csa_findsubcard(dev);
259 	scp->binfo.card = scp->card;
260 	printf("csa: card is %s\n", scp->card->name);
261 	resp->io_rid = PCIR_MAPS;
262 	resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, 1, RF_ACTIVE);
263 	if (resp->io == NULL)
264 		return (ENXIO);
265 	resp->mem_rid = PCIR_MAPS + 4;
266 	resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, 1, RF_ACTIVE);
267 	if (resp->mem == NULL)
268 		goto err_io;
269 	resp->irq_rid = 0;
270 	resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
271 	if (resp->irq == NULL)
272 		goto err_mem;
273 
274 	/* Enable interrupt. */
275 	if (snd_setup_intr(dev, resp->irq, INTR_MPSAFE, csa_intr, scp, &scp->ih))
276 		goto err_intr;
277 #if 0
278 	if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
279 		csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
280 #endif
281 
282 	/* Initialize the chip. */
283 	if (csa_initialize(scp))
284 		goto err_teardown;
285 
286 	/* Reset the Processor. */
287 	csa_resetdsp(resp);
288 
289 	/* Download the Processor Image to the processor. */
290 	if (csa_downloadimage(resp))
291 		goto err_teardown;
292 
293 	/* Attach the children. */
294 
295 	/* PCM Audio */
296 	func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
297 	if (func == NULL) {
298 		error = ENOMEM;
299 		goto err_teardown;
300 	}
301 	func->varinfo = &scp->binfo;
302 	func->func = SCF_PCM;
303 	scp->pcm = device_add_child(dev, "pcm", -1);
304 	device_set_ivars(scp->pcm, func);
305 
306 	/* Midi Interface */
307 	func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
308 	if (func == NULL) {
309 		error = ENOMEM;
310 		goto err_teardown;
311 	}
312 	func->varinfo = &scp->binfo;
313 	func->func = SCF_MIDI;
314 	scp->midi = device_add_child(dev, "midi", -1);
315 	device_set_ivars(scp->midi, func);
316 
317 	bus_generic_attach(dev);
318 
319 	return (0);
320 
321 err_teardown:
322 	bus_teardown_intr(dev, resp->irq, scp->ih);
323 err_intr:
324 	bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
325 err_mem:
326 	bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
327 err_io:
328 	bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
329 	return (error);
330 }
331 
332 static int
333 csa_detach(device_t dev)
334 {
335 	csa_res *resp;
336 	sc_p scp;
337 	int err;
338 
339 	scp = device_get_softc(dev);
340 	resp = &scp->res;
341 
342 	err = 0;
343 	if (scp->midi != NULL)
344 		err = device_delete_child(dev, scp->midi);
345 	if (err)
346 		return err;
347 	scp->midi = NULL;
348 
349 	if (scp->pcm != NULL)
350 		err = device_delete_child(dev, scp->pcm);
351 	if (err)
352 		return err;
353 	scp->pcm = NULL;
354 
355 	bus_teardown_intr(dev, resp->irq, scp->ih);
356 	bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
357 	bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
358 	bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
359 
360 	return bus_generic_detach(dev);
361 }
362 
363 static struct resource *
364 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
365 		      u_long start, u_long end, u_long count, u_int flags)
366 {
367 	sc_p scp;
368 	csa_res *resp;
369 	struct resource *res;
370 
371 	scp = device_get_softc(bus);
372 	resp = &scp->res;
373 	switch (type) {
374 	case SYS_RES_IRQ:
375 		if (*rid != 0)
376 			return (NULL);
377 		res = resp->irq;
378 		break;
379 	case SYS_RES_MEMORY:
380 		switch (*rid) {
381 		case PCIR_MAPS:
382 			res = resp->io;
383 			break;
384 		case PCIR_MAPS + 4:
385 			res = resp->mem;
386 			break;
387 		default:
388 			return (NULL);
389 		}
390 		break;
391 	default:
392 		return (NULL);
393 	}
394 
395 	return res;
396 }
397 
398 static int
399 csa_release_resource(device_t bus, device_t child, int type, int rid,
400 			struct resource *r)
401 {
402 	return (0);
403 }
404 
405 /*
406  * The following three functions deal with interrupt handling.
407  * An interrupt is primarily handled by the bridge driver.
408  * The bridge driver then determines the child devices to pass
409  * the interrupt. Certain information of the device can be read
410  * only once(eg the value of HISR). The bridge driver is responsible
411  * to pass such the information to the children.
412  */
413 
414 static int
415 csa_setup_intr(device_t bus, device_t child,
416 	       struct resource *irq, int flags,
417 	       driver_intr_t *intr, void *arg, void **cookiep)
418 {
419 	sc_p scp;
420 	csa_res *resp;
421 	struct sndcard_func *func;
422 
423 	scp = device_get_softc(bus);
424 	resp = &scp->res;
425 
426 	/*
427 	 * Look at the function code of the child to determine
428 	 * the appropriate hander for it.
429 	 */
430 	func = device_get_ivars(child);
431 	if (func == NULL || irq != resp->irq)
432 		return (EINVAL);
433 
434 	switch (func->func) {
435 	case SCF_PCM:
436 		scp->pcmintr = intr;
437 		scp->pcmintr_arg = arg;
438 		break;
439 
440 	case SCF_MIDI:
441 		scp->midiintr = intr;
442 		scp->midiintr_arg = arg;
443 		break;
444 
445 	default:
446 		return (EINVAL);
447 	}
448 	*cookiep = scp;
449 	if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
450 		csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
451 
452 	return (0);
453 }
454 
455 static int
456 csa_teardown_intr(device_t bus, device_t child,
457 		  struct resource *irq, void *cookie)
458 {
459 	sc_p scp;
460 	csa_res *resp;
461 	struct sndcard_func *func;
462 
463 	scp = device_get_softc(bus);
464 	resp = &scp->res;
465 
466 	/*
467 	 * Look at the function code of the child to determine
468 	 * the appropriate hander for it.
469 	 */
470 	func = device_get_ivars(child);
471 	if (func == NULL || irq != resp->irq || cookie != scp)
472 		return (EINVAL);
473 
474 	switch (func->func) {
475 	case SCF_PCM:
476 		scp->pcmintr = NULL;
477 		scp->pcmintr_arg = NULL;
478 		break;
479 
480 	case SCF_MIDI:
481 		scp->midiintr = NULL;
482 		scp->midiintr_arg = NULL;
483 		break;
484 
485 	default:
486 		return (EINVAL);
487 	}
488 
489 	return (0);
490 }
491 
492 /* The interrupt handler */
493 static void
494 csa_intr(void *arg)
495 {
496 	sc_p scp = arg;
497 	csa_res *resp;
498 	u_int32_t hisr;
499 
500 	resp = &scp->res;
501 
502 	/* Is this interrupt for us? */
503 	hisr = csa_readio(resp, BA0_HISR);
504 	if ((hisr & 0x7fffffff) == 0) {
505 		/* Throw an eoi. */
506 		csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
507 		return;
508 	}
509 
510 	/*
511 	 * Pass the value of HISR via struct csa_bridgeinfo.
512 	 * The children get access through their ivars.
513 	 */
514 	scp->binfo.hisr = hisr;
515 
516 	/* Invoke the handlers of the children. */
517 	if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
518 		scp->pcmintr(scp->pcmintr_arg);
519 		hisr &= ~(HISR_VC0 | HISR_VC1);
520 	}
521 	if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
522 		scp->midiintr(scp->midiintr_arg);
523 		hisr &= ~HISR_MIDI;
524 	}
525 
526 	/* Throw an eoi. */
527 	csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
528 }
529 
530 static int
531 csa_initialize(sc_p scp)
532 {
533 	int i;
534 	u_int32_t acsts, acisv;
535 	csa_res *resp;
536 
537 	resp = &scp->res;
538 
539 	/*
540 	 * First, blast the clock control register to zero so that the PLL starts
541 	 * out in a known state, and blast the master serial port control register
542 	 * to zero so that the serial ports also start out in a known state.
543 	 */
544 	csa_writeio(resp, BA0_CLKCR1, 0);
545 	csa_writeio(resp, BA0_SERMC1, 0);
546 
547 	/*
548 	 * If we are in AC97 mode, then we must set the part to a host controlled
549 	 * AC-link.  Otherwise, we won't be able to bring up the link.
550 	 */
551 #if 1
552 	csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
553 #else
554 	csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
555 #endif /* 1 */
556 
557 	/*
558 	 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
559 	 * spec) and then drive it high.  This is done for non AC97 modes since
560 	 * there might be logic external to the CS461x that uses the ARST# line
561 	 * for a reset.
562 	 */
563 	csa_writeio(resp, BA0_ACCTL, 1);
564 	DELAY(50);
565 	csa_writeio(resp, BA0_ACCTL, 0);
566 	DELAY(50);
567 	csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
568 
569 	/*
570 	 * The first thing we do here is to enable sync generation.  As soon
571 	 * as we start receiving bit clock, we'll start producing the SYNC
572 	 * signal.
573 	 */
574 	csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
575 
576 	/*
577 	 * Now wait for a short while to allow the AC97 part to start
578 	 * generating bit clock (so we don't try to start the PLL without an
579 	 * input clock).
580 	 */
581 	DELAY(50000);
582 
583 	/*
584 	 * Set the serial port timing configuration, so that
585 	 * the clock control circuit gets its clock from the correct place.
586 	 */
587 	csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
588 	DELAY(700000);
589 
590 	/*
591 	 * Write the selected clock control setup to the hardware.  Do not turn on
592 	 * SWCE yet (if requested), so that the devices clocked by the output of
593 	 * PLL are not clocked until the PLL is stable.
594 	 */
595 	csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
596 	csa_writeio(resp, BA0_PLLM, 0x3a);
597 	csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
598 
599 	/*
600 	 * Power up the PLL.
601 	 */
602 	csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
603 
604 	/*
605 	 * Wait until the PLL has stabilized.
606 	 */
607 	DELAY(5000);
608 
609 	/*
610 	 * Turn on clocking of the core so that we can setup the serial ports.
611 	 */
612 	csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
613 
614 	/*
615 	 * Fill the serial port FIFOs with silence.
616 	 */
617 	csa_clearserialfifos(resp);
618 
619 	/*
620 	 * Set the serial port FIFO pointer to the first sample in the FIFO.
621 	 */
622 #if notdef
623 	csa_writeio(resp, BA0_SERBSP, 0);
624 #endif /* notdef */
625 
626 	/*
627 	 *  Write the serial port configuration to the part.  The master
628 	 *  enable bit is not set until all other values have been written.
629 	 */
630 	csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
631 	csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
632 	csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
633 
634 	/*
635 	 * Wait for the codec ready signal from the AC97 codec.
636 	 */
637 	acsts = 0;
638 	for (i = 0 ; i < 1000 ; i++) {
639 		/*
640 		 * First, lets wait a short while to let things settle out a bit,
641 		 * and to prevent retrying the read too quickly.
642 		 */
643 		DELAY(125);
644 
645 		/*
646 		 * Read the AC97 status register to see if we've seen a CODEC READY
647 		 * signal from the AC97 codec.
648 		 */
649 		acsts = csa_readio(resp, BA0_ACSTS);
650 		if ((acsts & ACSTS_CRDY) != 0)
651 			break;
652 	}
653 
654 	/*
655 	 * Make sure we sampled CODEC READY.
656 	 */
657 	if ((acsts & ACSTS_CRDY) == 0)
658 		return (ENXIO);
659 
660 	/*
661 	 * Assert the vaid frame signal so that we can start sending commands
662 	 * to the AC97 codec.
663 	 */
664 	csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
665 
666 	/*
667 	 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
668 	 * the codec is pumping ADC data across the AC-link.
669 	 */
670 	acisv = 0;
671 	for (i = 0 ; i < 1000 ; i++) {
672 		/*
673 		 * First, lets wait a short while to let things settle out a bit,
674 		 * and to prevent retrying the read too quickly.
675 		 */
676 #if notdef
677 		DELAY(10000000L); /* clw */
678 #else
679 		DELAY(1000);
680 #endif /* notdef */
681 		/*
682 		 * Read the input slot valid register and see if input slots 3 and
683 		 * 4 are valid yet.
684 		 */
685 		acisv = csa_readio(resp, BA0_ACISV);
686 		if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
687 			break;
688 	}
689 	/*
690 	 * Make sure we sampled valid input slots 3 and 4.  If not, then return
691 	 * an error.
692 	 */
693 	if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
694 		return (ENXIO);
695 
696 	/*
697 	 * Now, assert valid frame and the slot 3 and 4 valid bits.  This will
698 	 * commense the transfer of digital audio data to the AC97 codec.
699 	 */
700 	csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
701 
702 	/*
703 	 * Power down the DAC and ADC.  We will power them up (if) when we need
704 	 * them.
705 	 */
706 #if notdef
707 	csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
708 #endif /* notdef */
709 
710 	/*
711 	 * Turn off the Processor by turning off the software clock enable flag in
712 	 * the clock control register.
713 	 */
714 #if notdef
715 	clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
716 	csa_writeio(resp, BA0_CLKCR1, clkcr1);
717 #endif /* notdef */
718 
719 	/*
720 	 * Enable interrupts on the part.
721 	 */
722 #if 0
723 	csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
724 #endif /* notdef */
725 
726 	return (0);
727 }
728 
729 void
730 csa_clearserialfifos(csa_res *resp)
731 {
732 	int i, j, pwr;
733 	u_int8_t clkcr1, serbst;
734 
735 	/*
736 	 * See if the devices are powered down.  If so, we must power them up first
737 	 * or they will not respond.
738 	 */
739 	pwr = 1;
740 	clkcr1 = csa_readio(resp, BA0_CLKCR1);
741 	if ((clkcr1 & CLKCR1_SWCE) == 0) {
742 		csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
743 		pwr = 0;
744 	}
745 
746 	/*
747 	 * We want to clear out the serial port FIFOs so we don't end up playing
748 	 * whatever random garbage happens to be in them.  We fill the sample FIFOs
749 	 * with zero (silence).
750 	 */
751 	csa_writeio(resp, BA0_SERBWP, 0);
752 
753 	/* Fill all 256 sample FIFO locations. */
754 	serbst = 0;
755 	for (i = 0 ; i < 256 ; i++) {
756 		/* Make sure the previous FIFO write operation has completed. */
757 		for (j = 0 ; j < 5 ; j++) {
758 			DELAY(100);
759 			serbst = csa_readio(resp, BA0_SERBST);
760 			if ((serbst & SERBST_WBSY) == 0)
761 				break;
762 		}
763 		if ((serbst & SERBST_WBSY) != 0) {
764 			if (!pwr)
765 				csa_writeio(resp, BA0_CLKCR1, clkcr1);
766 		}
767 		/* Write the serial port FIFO index. */
768 		csa_writeio(resp, BA0_SERBAD, i);
769 		/* Tell the serial port to load the new value into the FIFO location. */
770 		csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
771 	}
772 	/*
773 	 *  Now, if we powered up the devices, then power them back down again.
774 	 *  This is kinda ugly, but should never happen.
775 	 */
776 	if (!pwr)
777 		csa_writeio(resp, BA0_CLKCR1, clkcr1);
778 }
779 
780 static void
781 csa_resetdsp(csa_res *resp)
782 {
783 	int i;
784 
785 	/*
786 	 * Write the reset bit of the SP control register.
787 	 */
788 	csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
789 
790 	/*
791 	 * Write the control register.
792 	 */
793 	csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
794 
795 	/*
796 	 * Clear the trap registers.
797 	 */
798 	for (i = 0 ; i < 8 ; i++) {
799 		csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
800 		csa_writemem(resp, BA1_TWPR, 0xffff);
801 	}
802 	csa_writemem(resp, BA1_DREG, 0);
803 
804 	/*
805 	 * Set the frame timer to reflect the number of cycles per frame.
806 	 */
807 	csa_writemem(resp, BA1_FRMT, 0xadf);
808 }
809 
810 static int
811 csa_downloadimage(csa_res *resp)
812 {
813 	int i;
814 	u_int32_t tmp, src, dst, count, data;
815 
816 	for (i = 0; i < CLEAR__COUNT; i++) {
817 		dst = ClrStat[i].BA1__DestByteOffset;
818 		count = ClrStat[i].BA1__SourceSize;
819 		for (tmp = 0; tmp < count; tmp += 4)
820 			csa_writemem(resp, dst + tmp, 0x00000000);
821 	}
822 
823 	for (i = 0; i < FILL__COUNT; i++) {
824 		src = 0;
825 		dst = FillStat[i].Offset;
826 		count = FillStat[i].Size;
827 		for (tmp = 0; tmp < count; tmp += 4) {
828 			data = FillStat[i].pFill[src];
829 			csa_writemem(resp, dst + tmp, data);
830 			src++;
831 		}
832 	}
833 
834 	return (0);
835 }
836 
837 int
838 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
839 {
840 	int i;
841 	u_int32_t acsda, acctl, acsts;
842 
843 	/*
844 	 * Make sure that there is not data sitting around from a previous
845 	 * uncompleted access. ACSDA = Status Data Register = 47Ch
846 	 */
847 	acsda = csa_readio(resp, BA0_ACSDA);
848 
849 	/*
850 	 * Setup the AC97 control registers on the CS461x to send the
851 	 * appropriate command to the AC97 to perform the read.
852 	 * ACCAD = Command Address Register = 46Ch
853 	 * ACCDA = Command Data Register = 470h
854 	 * ACCTL = Control Register = 460h
855 	 * set DCV - will clear when process completed
856 	 * set CRW - Read command
857 	 * set VFRM - valid frame enabled
858 	 * set ESYN - ASYNC generation enabled
859 	 * set RSTN - ARST# inactive, AC97 codec not reset
860 	 */
861 
862 	/*
863 	 * Get the actual AC97 register from the offset
864 	 */
865 	csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
866 	csa_writeio(resp, BA0_ACCDA, 0);
867 	csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
868 
869 	/*
870 	 * Wait for the read to occur.
871 	 */
872 	acctl = 0;
873 	for (i = 0 ; i < 10 ; i++) {
874 		/*
875 		 * First, we want to wait for a short time.
876 		 */
877 		DELAY(25);
878 
879 		/*
880 		 * Now, check to see if the read has completed.
881 		 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
882 		 */
883 		acctl = csa_readio(resp, BA0_ACCTL);
884 		if ((acctl & ACCTL_DCV) == 0)
885 			break;
886 	}
887 
888 	/*
889 	 * Make sure the read completed.
890 	 */
891 	if ((acctl & ACCTL_DCV) != 0)
892 		return (EAGAIN);
893 
894 	/*
895 	 * Wait for the valid status bit to go active.
896 	 */
897 	acsts = 0;
898 	for (i = 0 ; i < 10 ; i++) {
899 		/*
900 		 * Read the AC97 status register.
901 		 * ACSTS = Status Register = 464h
902 		 */
903 		acsts = csa_readio(resp, BA0_ACSTS);
904 		/*
905 		 * See if we have valid status.
906 		 * VSTS - Valid Status
907 		 */
908 		if ((acsts & ACSTS_VSTS) != 0)
909 			break;
910 		/*
911 		 * Wait for a short while.
912 		 */
913 		 DELAY(25);
914 	}
915 
916 	/*
917 	 * Make sure we got valid status.
918 	 */
919 	if ((acsts & ACSTS_VSTS) == 0)
920 		return (EAGAIN);
921 
922 	/*
923 	 * Read the data returned from the AC97 register.
924 	 * ACSDA = Status Data Register = 474h
925 	 */
926 	*data = csa_readio(resp, BA0_ACSDA);
927 
928 	return (0);
929 }
930 
931 int
932 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
933 {
934 	int i;
935 	u_int32_t acctl;
936 
937 	/*
938 	 * Setup the AC97 control registers on the CS461x to send the
939 	 * appropriate command to the AC97 to perform the write.
940 	 * ACCAD = Command Address Register = 46Ch
941 	 * ACCDA = Command Data Register = 470h
942 	 * ACCTL = Control Register = 460h
943 	 * set DCV - will clear when process completed
944 	 * set VFRM - valid frame enabled
945 	 * set ESYN - ASYNC generation enabled
946 	 * set RSTN - ARST# inactive, AC97 codec not reset
947 	 */
948 
949 	/*
950 	 * Get the actual AC97 register from the offset
951 	 */
952 	csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
953 	csa_writeio(resp, BA0_ACCDA, data);
954 	csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
955 
956 	/*
957 	 * Wait for the write to occur.
958 	 */
959 	acctl = 0;
960 	for (i = 0 ; i < 10 ; i++) {
961 		/*
962 		 * First, we want to wait for a short time.
963 		 */
964 		DELAY(25);
965 
966 		/*
967 		 * Now, check to see if the read has completed.
968 		 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
969 		 */
970 		acctl = csa_readio(resp, BA0_ACCTL);
971 		if ((acctl & ACCTL_DCV) == 0)
972 			break;
973 	}
974 
975 	/*
976 	 * Make sure the write completed.
977 	 */
978 	if ((acctl & ACCTL_DCV) != 0)
979 		return (EAGAIN);
980 
981 	return (0);
982 }
983 
984 u_int32_t
985 csa_readio(csa_res *resp, u_long offset)
986 {
987 	u_int32_t ul;
988 
989 	if (offset < BA0_AC97_RESET)
990 		return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
991 	else {
992 		if (csa_readcodec(resp, offset, &ul))
993 			ul = 0;
994 		return (ul);
995 	}
996 }
997 
998 void
999 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1000 {
1001 	if (offset < BA0_AC97_RESET)
1002 		bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1003 	else
1004 		csa_writecodec(resp, offset, data);
1005 }
1006 
1007 u_int32_t
1008 csa_readmem(csa_res *resp, u_long offset)
1009 {
1010 	return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1011 }
1012 
1013 void
1014 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1015 {
1016 	bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1017 }
1018 
1019 static device_method_t csa_methods[] = {
1020 	/* Device interface */
1021 	DEVMETHOD(device_probe,		csa_probe),
1022 	DEVMETHOD(device_attach,	csa_attach),
1023 	DEVMETHOD(device_detach,	csa_detach),
1024 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
1025 	DEVMETHOD(device_suspend,	bus_generic_suspend),
1026 	DEVMETHOD(device_resume,	bus_generic_resume),
1027 
1028 	/* Bus interface */
1029 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
1030 	DEVMETHOD(bus_alloc_resource,	csa_alloc_resource),
1031 	DEVMETHOD(bus_release_resource,	csa_release_resource),
1032 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1033 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1034 	DEVMETHOD(bus_setup_intr,	csa_setup_intr),
1035 	DEVMETHOD(bus_teardown_intr,	csa_teardown_intr),
1036 
1037 	{ 0, 0 }
1038 };
1039 
1040 static driver_t csa_driver = {
1041 	"csa",
1042 	csa_methods,
1043 	sizeof(struct csa_softc),
1044 };
1045 
1046 /*
1047  * csa can be attached to a pci bus.
1048  */
1049 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1050 MODULE_DEPEND(snd_csa, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
1051 MODULE_VERSION(snd_csa, 1);
1052