1 /*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 41 #ifdef HAVE_KERNEL_OPTION_HEADERS 42 #include "opt_snd.h" 43 #endif 44 45 #include <dev/sound/pcm/sound.h> 46 #include <dev/sound/chip.h> 47 #include <dev/sound/pci/csareg.h> 48 #include <dev/sound/pci/csavar.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <dev/sound/pci/cs461x_dsp.h> 54 55 SND_DECLARE_FILE("$FreeBSD$"); 56 57 /* This is the pci device id. */ 58 #define CS4610_PCI_ID 0x60011013 59 #define CS4614_PCI_ID 0x60031013 60 #define CS4615_PCI_ID 0x60041013 61 62 /* Here is the parameter structure per a device. */ 63 struct csa_softc { 64 device_t dev; /* device */ 65 csa_res res; /* resources */ 66 67 device_t pcm; /* pcm device */ 68 driver_intr_t* pcmintr; /* pcm intr */ 69 void *pcmintr_arg; /* pcm intr arg */ 70 device_t midi; /* midi device */ 71 driver_intr_t* midiintr; /* midi intr */ 72 void *midiintr_arg; /* midi intr arg */ 73 void *ih; /* cookie */ 74 75 struct csa_card *card; 76 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 77 }; 78 79 typedef struct csa_softc *sc_p; 80 81 static int csa_probe(device_t dev); 82 static int csa_attach(device_t dev); 83 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 84 u_long start, u_long end, u_long count, u_int flags); 85 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 86 struct resource *r); 87 static int csa_setup_intr(device_t bus, device_t child, 88 struct resource *irq, int flags, 89 #if __FreeBSD_version >= 700031 90 driver_filter_t *filter, 91 #endif 92 driver_intr_t *intr, void *arg, void **cookiep); 93 static int csa_teardown_intr(device_t bus, device_t child, 94 struct resource *irq, void *cookie); 95 static driver_intr_t csa_intr; 96 static int csa_initialize(sc_p scp); 97 static int csa_downloadimage(csa_res *resp); 98 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len); 99 100 static devclass_t csa_devclass; 101 102 static void 103 amp_none(void) 104 { 105 } 106 107 static void 108 amp_voyetra(void) 109 { 110 } 111 112 static int 113 clkrun_hack(int run) 114 { 115 #ifdef __i386__ 116 devclass_t pci_devclass; 117 device_t *pci_devices, *pci_children, *busp, *childp; 118 int pci_count = 0, pci_childcount = 0; 119 int i, j, port; 120 u_int16_t control; 121 bus_space_tag_t btag; 122 123 if ((pci_devclass = devclass_find("pci")) == NULL) { 124 return ENXIO; 125 } 126 127 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 128 129 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 130 pci_childcount = 0; 131 if (device_get_children(*busp, &pci_children, &pci_childcount)) 132 continue; 133 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 134 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 135 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 136 /* XXX */ 137 btag = X86_BUS_SPACE_IO; 138 139 control = bus_space_read_2(btag, 0x0, port); 140 control &= ~0x2000; 141 control |= run? 0 : 0x2000; 142 bus_space_write_2(btag, 0x0, port, control); 143 free(pci_devices, M_TEMP); 144 free(pci_children, M_TEMP); 145 return 0; 146 } 147 } 148 free(pci_children, M_TEMP); 149 } 150 151 free(pci_devices, M_TEMP); 152 return ENXIO; 153 #else 154 return 0; 155 #endif 156 } 157 158 static struct csa_card cards_4610[] = { 159 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 160 }; 161 162 static struct csa_card cards_4614[] = { 163 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 164 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 165 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 166 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 167 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 168 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 169 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 170 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 171 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 172 }; 173 174 static struct csa_card cards_4615[] = { 175 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 176 }; 177 178 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 179 180 struct card_type { 181 u_int32_t devid; 182 char *name; 183 struct csa_card *cards; 184 }; 185 186 static struct card_type cards[] = { 187 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 188 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 189 {CS4615_PCI_ID, "CS4615", cards_4615}, 190 {0, NULL, NULL}, 191 }; 192 193 static struct card_type * 194 csa_findcard(device_t dev) 195 { 196 int i; 197 198 i = 0; 199 while (cards[i].devid != 0) { 200 if (pci_get_devid(dev) == cards[i].devid) 201 return &cards[i]; 202 i++; 203 } 204 return NULL; 205 } 206 207 struct csa_card * 208 csa_findsubcard(device_t dev) 209 { 210 int i; 211 struct card_type *card; 212 struct csa_card *subcard; 213 214 card = csa_findcard(dev); 215 if (card == NULL) 216 return &nocard; 217 subcard = card->cards; 218 i = 0; 219 while (subcard[i].subvendor != 0) { 220 if (pci_get_subvendor(dev) == subcard[i].subvendor 221 && pci_get_subdevice(dev) == subcard[i].subdevice) { 222 return &subcard[i]; 223 } 224 i++; 225 } 226 return &subcard[i]; 227 } 228 229 static int 230 csa_probe(device_t dev) 231 { 232 struct card_type *card; 233 234 card = csa_findcard(dev); 235 if (card) { 236 device_set_desc(dev, card->name); 237 return BUS_PROBE_DEFAULT; 238 } 239 return ENXIO; 240 } 241 242 static int 243 csa_attach(device_t dev) 244 { 245 u_int32_t stcmd; 246 sc_p scp; 247 csa_res *resp; 248 struct sndcard_func *func; 249 int error = ENXIO; 250 251 scp = device_get_softc(dev); 252 253 /* Fill in the softc. */ 254 bzero(scp, sizeof(*scp)); 255 scp->dev = dev; 256 257 /* Wake up the device. */ 258 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 259 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 260 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 261 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 262 } 263 264 /* Allocate the resources. */ 265 resp = &scp->res; 266 scp->card = csa_findsubcard(dev); 267 scp->binfo.card = scp->card; 268 printf("csa: card is %s\n", scp->card->name); 269 resp->io_rid = PCIR_BAR(0); 270 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 271 &resp->io_rid, RF_ACTIVE); 272 if (resp->io == NULL) 273 return (ENXIO); 274 resp->mem_rid = PCIR_BAR(1); 275 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 276 &resp->mem_rid, RF_ACTIVE); 277 if (resp->mem == NULL) 278 goto err_io; 279 resp->irq_rid = 0; 280 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 281 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 282 if (resp->irq == NULL) 283 goto err_mem; 284 285 /* Enable interrupt. */ 286 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 287 goto err_intr; 288 #if 0 289 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 290 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 291 #endif 292 293 /* Initialize the chip. */ 294 if (csa_initialize(scp)) 295 goto err_teardown; 296 297 /* Reset the Processor. */ 298 csa_resetdsp(resp); 299 300 /* Download the Processor Image to the processor. */ 301 if (csa_downloadimage(resp)) 302 goto err_teardown; 303 304 /* Attach the children. */ 305 306 /* PCM Audio */ 307 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 308 if (func == NULL) { 309 error = ENOMEM; 310 goto err_teardown; 311 } 312 func->varinfo = &scp->binfo; 313 func->func = SCF_PCM; 314 scp->pcm = device_add_child(dev, "pcm", -1); 315 device_set_ivars(scp->pcm, func); 316 317 /* Midi Interface */ 318 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 319 if (func == NULL) { 320 error = ENOMEM; 321 goto err_teardown; 322 } 323 func->varinfo = &scp->binfo; 324 func->func = SCF_MIDI; 325 scp->midi = device_add_child(dev, "midi", -1); 326 device_set_ivars(scp->midi, func); 327 328 bus_generic_attach(dev); 329 330 return (0); 331 332 err_teardown: 333 bus_teardown_intr(dev, resp->irq, scp->ih); 334 err_intr: 335 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 336 err_mem: 337 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 338 err_io: 339 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 340 return (error); 341 } 342 343 static int 344 csa_detach(device_t dev) 345 { 346 csa_res *resp; 347 sc_p scp; 348 struct sndcard_func *func; 349 int err; 350 351 scp = device_get_softc(dev); 352 resp = &scp->res; 353 354 if (scp->midi != NULL) { 355 func = device_get_ivars(scp->midi); 356 err = device_delete_child(dev, scp->midi); 357 if (err != 0) 358 return err; 359 if (func != NULL) 360 free(func, M_DEVBUF); 361 scp->midi = NULL; 362 } 363 364 if (scp->pcm != NULL) { 365 func = device_get_ivars(scp->pcm); 366 err = device_delete_child(dev, scp->pcm); 367 if (err != 0) 368 return err; 369 if (func != NULL) 370 free(func, M_DEVBUF); 371 scp->pcm = NULL; 372 } 373 374 bus_teardown_intr(dev, resp->irq, scp->ih); 375 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 376 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 377 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 378 379 return bus_generic_detach(dev); 380 } 381 382 static int 383 csa_resume(device_t dev) 384 { 385 csa_res *resp; 386 sc_p scp; 387 388 scp = device_get_softc(dev); 389 resp = &scp->res; 390 391 /* Initialize the chip. */ 392 if (csa_initialize(scp)) 393 return (ENXIO); 394 395 /* Reset the Processor. */ 396 csa_resetdsp(resp); 397 398 /* Download the Processor Image to the processor. */ 399 if (csa_downloadimage(resp)) 400 return (ENXIO); 401 402 return (bus_generic_resume(dev)); 403 } 404 405 static struct resource * 406 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 407 u_long start, u_long end, u_long count, u_int flags) 408 { 409 sc_p scp; 410 csa_res *resp; 411 struct resource *res; 412 413 scp = device_get_softc(bus); 414 resp = &scp->res; 415 switch (type) { 416 case SYS_RES_IRQ: 417 if (*rid != 0) 418 return (NULL); 419 res = resp->irq; 420 break; 421 case SYS_RES_MEMORY: 422 switch (*rid) { 423 case PCIR_BAR(0): 424 res = resp->io; 425 break; 426 case PCIR_BAR(1): 427 res = resp->mem; 428 break; 429 default: 430 return (NULL); 431 } 432 break; 433 default: 434 return (NULL); 435 } 436 437 return res; 438 } 439 440 static int 441 csa_release_resource(device_t bus, device_t child, int type, int rid, 442 struct resource *r) 443 { 444 return (0); 445 } 446 447 /* 448 * The following three functions deal with interrupt handling. 449 * An interrupt is primarily handled by the bridge driver. 450 * The bridge driver then determines the child devices to pass 451 * the interrupt. Certain information of the device can be read 452 * only once(eg the value of HISR). The bridge driver is responsible 453 * to pass such the information to the children. 454 */ 455 456 static int 457 csa_setup_intr(device_t bus, device_t child, 458 struct resource *irq, int flags, 459 #if __FreeBSD_version >= 700031 460 driver_filter_t *filter, 461 #endif 462 driver_intr_t *intr, void *arg, void **cookiep) 463 { 464 sc_p scp; 465 csa_res *resp; 466 struct sndcard_func *func; 467 468 #if __FreeBSD_version >= 700031 469 if (filter != NULL) { 470 printf("ata-csa.c: we cannot use a filter here\n"); 471 return (EINVAL); 472 } 473 #endif 474 scp = device_get_softc(bus); 475 resp = &scp->res; 476 477 /* 478 * Look at the function code of the child to determine 479 * the appropriate hander for it. 480 */ 481 func = device_get_ivars(child); 482 if (func == NULL || irq != resp->irq) 483 return (EINVAL); 484 485 switch (func->func) { 486 case SCF_PCM: 487 scp->pcmintr = intr; 488 scp->pcmintr_arg = arg; 489 break; 490 491 case SCF_MIDI: 492 scp->midiintr = intr; 493 scp->midiintr_arg = arg; 494 break; 495 496 default: 497 return (EINVAL); 498 } 499 *cookiep = scp; 500 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 501 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 502 503 return (0); 504 } 505 506 static int 507 csa_teardown_intr(device_t bus, device_t child, 508 struct resource *irq, void *cookie) 509 { 510 sc_p scp; 511 csa_res *resp; 512 struct sndcard_func *func; 513 514 scp = device_get_softc(bus); 515 resp = &scp->res; 516 517 /* 518 * Look at the function code of the child to determine 519 * the appropriate hander for it. 520 */ 521 func = device_get_ivars(child); 522 if (func == NULL || irq != resp->irq || cookie != scp) 523 return (EINVAL); 524 525 switch (func->func) { 526 case SCF_PCM: 527 scp->pcmintr = NULL; 528 scp->pcmintr_arg = NULL; 529 break; 530 531 case SCF_MIDI: 532 scp->midiintr = NULL; 533 scp->midiintr_arg = NULL; 534 break; 535 536 default: 537 return (EINVAL); 538 } 539 540 return (0); 541 } 542 543 /* The interrupt handler */ 544 static void 545 csa_intr(void *arg) 546 { 547 sc_p scp = arg; 548 csa_res *resp; 549 u_int32_t hisr; 550 551 resp = &scp->res; 552 553 /* Is this interrupt for us? */ 554 hisr = csa_readio(resp, BA0_HISR); 555 if ((hisr & 0x7fffffff) == 0) { 556 /* Throw an eoi. */ 557 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 558 return; 559 } 560 561 /* 562 * Pass the value of HISR via struct csa_bridgeinfo. 563 * The children get access through their ivars. 564 */ 565 scp->binfo.hisr = hisr; 566 567 /* Invoke the handlers of the children. */ 568 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 569 scp->pcmintr(scp->pcmintr_arg); 570 hisr &= ~(HISR_VC0 | HISR_VC1); 571 } 572 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 573 scp->midiintr(scp->midiintr_arg); 574 hisr &= ~HISR_MIDI; 575 } 576 577 /* Throw an eoi. */ 578 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 579 } 580 581 static int 582 csa_initialize(sc_p scp) 583 { 584 int i; 585 u_int32_t acsts, acisv; 586 csa_res *resp; 587 588 resp = &scp->res; 589 590 /* 591 * First, blast the clock control register to zero so that the PLL starts 592 * out in a known state, and blast the master serial port control register 593 * to zero so that the serial ports also start out in a known state. 594 */ 595 csa_writeio(resp, BA0_CLKCR1, 0); 596 csa_writeio(resp, BA0_SERMC1, 0); 597 598 /* 599 * If we are in AC97 mode, then we must set the part to a host controlled 600 * AC-link. Otherwise, we won't be able to bring up the link. 601 */ 602 #if 1 603 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 604 #else 605 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 606 #endif /* 1 */ 607 608 /* 609 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 610 * spec) and then drive it high. This is done for non AC97 modes since 611 * there might be logic external to the CS461x that uses the ARST# line 612 * for a reset. 613 */ 614 csa_writeio(resp, BA0_ACCTL, 1); 615 DELAY(50); 616 csa_writeio(resp, BA0_ACCTL, 0); 617 DELAY(50); 618 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 619 620 /* 621 * The first thing we do here is to enable sync generation. As soon 622 * as we start receiving bit clock, we'll start producing the SYNC 623 * signal. 624 */ 625 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 626 627 /* 628 * Now wait for a short while to allow the AC97 part to start 629 * generating bit clock (so we don't try to start the PLL without an 630 * input clock). 631 */ 632 DELAY(50000); 633 634 /* 635 * Set the serial port timing configuration, so that 636 * the clock control circuit gets its clock from the correct place. 637 */ 638 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 639 DELAY(700000); 640 641 /* 642 * Write the selected clock control setup to the hardware. Do not turn on 643 * SWCE yet (if requested), so that the devices clocked by the output of 644 * PLL are not clocked until the PLL is stable. 645 */ 646 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 647 csa_writeio(resp, BA0_PLLM, 0x3a); 648 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 649 650 /* 651 * Power up the PLL. 652 */ 653 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 654 655 /* 656 * Wait until the PLL has stabilized. 657 */ 658 DELAY(5000); 659 660 /* 661 * Turn on clocking of the core so that we can setup the serial ports. 662 */ 663 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 664 665 /* 666 * Fill the serial port FIFOs with silence. 667 */ 668 csa_clearserialfifos(resp); 669 670 /* 671 * Set the serial port FIFO pointer to the first sample in the FIFO. 672 */ 673 #ifdef notdef 674 csa_writeio(resp, BA0_SERBSP, 0); 675 #endif /* notdef */ 676 677 /* 678 * Write the serial port configuration to the part. The master 679 * enable bit is not set until all other values have been written. 680 */ 681 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 682 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 683 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 684 685 /* 686 * Wait for the codec ready signal from the AC97 codec. 687 */ 688 acsts = 0; 689 for (i = 0 ; i < 1000 ; i++) { 690 /* 691 * First, lets wait a short while to let things settle out a bit, 692 * and to prevent retrying the read too quickly. 693 */ 694 DELAY(125); 695 696 /* 697 * Read the AC97 status register to see if we've seen a CODEC READY 698 * signal from the AC97 codec. 699 */ 700 acsts = csa_readio(resp, BA0_ACSTS); 701 if ((acsts & ACSTS_CRDY) != 0) 702 break; 703 } 704 705 /* 706 * Make sure we sampled CODEC READY. 707 */ 708 if ((acsts & ACSTS_CRDY) == 0) 709 return (ENXIO); 710 711 /* 712 * Assert the vaid frame signal so that we can start sending commands 713 * to the AC97 codec. 714 */ 715 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 716 717 /* 718 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 719 * the codec is pumping ADC data across the AC-link. 720 */ 721 acisv = 0; 722 for (i = 0 ; i < 1000 ; i++) { 723 /* 724 * First, lets wait a short while to let things settle out a bit, 725 * and to prevent retrying the read too quickly. 726 */ 727 #ifdef notdef 728 DELAY(10000000L); /* clw */ 729 #else 730 DELAY(1000); 731 #endif /* notdef */ 732 /* 733 * Read the input slot valid register and see if input slots 3 and 734 * 4 are valid yet. 735 */ 736 acisv = csa_readio(resp, BA0_ACISV); 737 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 738 break; 739 } 740 /* 741 * Make sure we sampled valid input slots 3 and 4. If not, then return 742 * an error. 743 */ 744 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 745 return (ENXIO); 746 747 /* 748 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 749 * commense the transfer of digital audio data to the AC97 codec. 750 */ 751 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 752 753 /* 754 * Power down the DAC and ADC. We will power them up (if) when we need 755 * them. 756 */ 757 #ifdef notdef 758 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 759 #endif /* notdef */ 760 761 /* 762 * Turn off the Processor by turning off the software clock enable flag in 763 * the clock control register. 764 */ 765 #ifdef notdef 766 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 767 csa_writeio(resp, BA0_CLKCR1, clkcr1); 768 #endif /* notdef */ 769 770 /* 771 * Enable interrupts on the part. 772 */ 773 #if 0 774 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 775 #endif /* notdef */ 776 777 return (0); 778 } 779 780 void 781 csa_clearserialfifos(csa_res *resp) 782 { 783 int i, j, pwr; 784 u_int8_t clkcr1, serbst; 785 786 /* 787 * See if the devices are powered down. If so, we must power them up first 788 * or they will not respond. 789 */ 790 pwr = 1; 791 clkcr1 = csa_readio(resp, BA0_CLKCR1); 792 if ((clkcr1 & CLKCR1_SWCE) == 0) { 793 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 794 pwr = 0; 795 } 796 797 /* 798 * We want to clear out the serial port FIFOs so we don't end up playing 799 * whatever random garbage happens to be in them. We fill the sample FIFOs 800 * with zero (silence). 801 */ 802 csa_writeio(resp, BA0_SERBWP, 0); 803 804 /* Fill all 256 sample FIFO locations. */ 805 serbst = 0; 806 for (i = 0 ; i < 256 ; i++) { 807 /* Make sure the previous FIFO write operation has completed. */ 808 for (j = 0 ; j < 5 ; j++) { 809 DELAY(100); 810 serbst = csa_readio(resp, BA0_SERBST); 811 if ((serbst & SERBST_WBSY) == 0) 812 break; 813 } 814 if ((serbst & SERBST_WBSY) != 0) { 815 if (!pwr) 816 csa_writeio(resp, BA0_CLKCR1, clkcr1); 817 } 818 /* Write the serial port FIFO index. */ 819 csa_writeio(resp, BA0_SERBAD, i); 820 /* Tell the serial port to load the new value into the FIFO location. */ 821 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 822 } 823 /* 824 * Now, if we powered up the devices, then power them back down again. 825 * This is kinda ugly, but should never happen. 826 */ 827 if (!pwr) 828 csa_writeio(resp, BA0_CLKCR1, clkcr1); 829 } 830 831 void 832 csa_resetdsp(csa_res *resp) 833 { 834 int i; 835 836 /* 837 * Write the reset bit of the SP control register. 838 */ 839 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 840 841 /* 842 * Write the control register. 843 */ 844 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 845 846 /* 847 * Clear the trap registers. 848 */ 849 for (i = 0 ; i < 8 ; i++) { 850 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 851 csa_writemem(resp, BA1_TWPR, 0xffff); 852 } 853 csa_writemem(resp, BA1_DREG, 0); 854 855 /* 856 * Set the frame timer to reflect the number of cycles per frame. 857 */ 858 csa_writemem(resp, BA1_FRMT, 0xadf); 859 } 860 861 static int 862 csa_downloadimage(csa_res *resp) 863 { 864 int ret; 865 u_long ul, offset; 866 867 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 868 /* 869 * DMA this block from host memory to the appropriate 870 * memory on the CSDevice. 871 */ 872 ret = csa_transferimage(resp, 873 cs461x_firmware.BA1Array + offset, 874 cs461x_firmware.MemoryStat[ul].ulDestAddr, 875 cs461x_firmware.MemoryStat[ul].ulSourceSize); 876 if (ret) 877 return (ret); 878 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2; 879 } 880 return (0); 881 } 882 883 static int 884 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len) 885 { 886 u_long ul; 887 888 /* 889 * We do not allow DMAs from host memory to host memory (although the DMA 890 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 891 * in size (because that DMA can not do that). Return an error if either 892 * of these conditions exist. 893 */ 894 if ((len & 0x3) != 0) 895 return (EINVAL); 896 897 /* Check the destination address that it is a multiple of 4 */ 898 if ((dest & 0x3) != 0) 899 return (EINVAL); 900 901 /* Write the buffer out. */ 902 for (ul = 0 ; ul < len ; ul += 4) 903 csa_writemem(resp, dest + ul, src[ul >> 2]); 904 return (0); 905 } 906 907 int 908 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 909 { 910 int i; 911 u_int32_t acctl, acsts; 912 913 /* 914 * Make sure that there is not data sitting around from a previous 915 * uncompleted access. ACSDA = Status Data Register = 47Ch 916 */ 917 csa_readio(resp, BA0_ACSDA); 918 919 /* 920 * Setup the AC97 control registers on the CS461x to send the 921 * appropriate command to the AC97 to perform the read. 922 * ACCAD = Command Address Register = 46Ch 923 * ACCDA = Command Data Register = 470h 924 * ACCTL = Control Register = 460h 925 * set DCV - will clear when process completed 926 * set CRW - Read command 927 * set VFRM - valid frame enabled 928 * set ESYN - ASYNC generation enabled 929 * set RSTN - ARST# inactive, AC97 codec not reset 930 */ 931 932 /* 933 * Get the actual AC97 register from the offset 934 */ 935 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 936 csa_writeio(resp, BA0_ACCDA, 0); 937 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 938 939 /* 940 * Wait for the read to occur. 941 */ 942 acctl = 0; 943 for (i = 0 ; i < 10 ; i++) { 944 /* 945 * First, we want to wait for a short time. 946 */ 947 DELAY(25); 948 949 /* 950 * Now, check to see if the read has completed. 951 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 952 */ 953 acctl = csa_readio(resp, BA0_ACCTL); 954 if ((acctl & ACCTL_DCV) == 0) 955 break; 956 } 957 958 /* 959 * Make sure the read completed. 960 */ 961 if ((acctl & ACCTL_DCV) != 0) 962 return (EAGAIN); 963 964 /* 965 * Wait for the valid status bit to go active. 966 */ 967 acsts = 0; 968 for (i = 0 ; i < 10 ; i++) { 969 /* 970 * Read the AC97 status register. 971 * ACSTS = Status Register = 464h 972 */ 973 acsts = csa_readio(resp, BA0_ACSTS); 974 /* 975 * See if we have valid status. 976 * VSTS - Valid Status 977 */ 978 if ((acsts & ACSTS_VSTS) != 0) 979 break; 980 /* 981 * Wait for a short while. 982 */ 983 DELAY(25); 984 } 985 986 /* 987 * Make sure we got valid status. 988 */ 989 if ((acsts & ACSTS_VSTS) == 0) 990 return (EAGAIN); 991 992 /* 993 * Read the data returned from the AC97 register. 994 * ACSDA = Status Data Register = 474h 995 */ 996 *data = csa_readio(resp, BA0_ACSDA); 997 998 return (0); 999 } 1000 1001 int 1002 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 1003 { 1004 int i; 1005 u_int32_t acctl; 1006 1007 /* 1008 * Setup the AC97 control registers on the CS461x to send the 1009 * appropriate command to the AC97 to perform the write. 1010 * ACCAD = Command Address Register = 46Ch 1011 * ACCDA = Command Data Register = 470h 1012 * ACCTL = Control Register = 460h 1013 * set DCV - will clear when process completed 1014 * set VFRM - valid frame enabled 1015 * set ESYN - ASYNC generation enabled 1016 * set RSTN - ARST# inactive, AC97 codec not reset 1017 */ 1018 1019 /* 1020 * Get the actual AC97 register from the offset 1021 */ 1022 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 1023 csa_writeio(resp, BA0_ACCDA, data); 1024 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1025 1026 /* 1027 * Wait for the write to occur. 1028 */ 1029 acctl = 0; 1030 for (i = 0 ; i < 10 ; i++) { 1031 /* 1032 * First, we want to wait for a short time. 1033 */ 1034 DELAY(25); 1035 1036 /* 1037 * Now, check to see if the read has completed. 1038 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1039 */ 1040 acctl = csa_readio(resp, BA0_ACCTL); 1041 if ((acctl & ACCTL_DCV) == 0) 1042 break; 1043 } 1044 1045 /* 1046 * Make sure the write completed. 1047 */ 1048 if ((acctl & ACCTL_DCV) != 0) 1049 return (EAGAIN); 1050 1051 return (0); 1052 } 1053 1054 u_int32_t 1055 csa_readio(csa_res *resp, u_long offset) 1056 { 1057 u_int32_t ul; 1058 1059 if (offset < BA0_AC97_RESET) 1060 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1061 else { 1062 if (csa_readcodec(resp, offset, &ul)) 1063 ul = 0; 1064 return (ul); 1065 } 1066 } 1067 1068 void 1069 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1070 { 1071 if (offset < BA0_AC97_RESET) 1072 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1073 else 1074 csa_writecodec(resp, offset, data); 1075 } 1076 1077 u_int32_t 1078 csa_readmem(csa_res *resp, u_long offset) 1079 { 1080 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1081 } 1082 1083 void 1084 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1085 { 1086 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1087 } 1088 1089 static device_method_t csa_methods[] = { 1090 /* Device interface */ 1091 DEVMETHOD(device_probe, csa_probe), 1092 DEVMETHOD(device_attach, csa_attach), 1093 DEVMETHOD(device_detach, csa_detach), 1094 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1095 DEVMETHOD(device_suspend, bus_generic_suspend), 1096 DEVMETHOD(device_resume, csa_resume), 1097 1098 /* Bus interface */ 1099 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1100 DEVMETHOD(bus_release_resource, csa_release_resource), 1101 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1102 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1103 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1104 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1105 1106 DEVMETHOD_END 1107 }; 1108 1109 static driver_t csa_driver = { 1110 "csa", 1111 csa_methods, 1112 sizeof(struct csa_softc), 1113 }; 1114 1115 /* 1116 * csa can be attached to a pci bus. 1117 */ 1118 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1119 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1120 MODULE_VERSION(snd_csa, 1); 1121