1 /* 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 #include <sys/soundcard.h> 41 #include <dev/sound/pcm/sound.h> 42 #include <dev/sound/chip.h> 43 #include <dev/sound/pci/csareg.h> 44 #include <dev/sound/pci/csavar.h> 45 46 #include <pci/pcireg.h> 47 #include <pci/pcivar.h> 48 49 #include <gnu/dev/sound/pci/csaimg.h> 50 51 SND_DECLARE_FILE("$FreeBSD$"); 52 53 /* This is the pci device id. */ 54 #define CS4610_PCI_ID 0x60011013 55 #define CS4614_PCI_ID 0x60031013 56 #define CS4615_PCI_ID 0x60041013 57 58 /* Here is the parameter structure per a device. */ 59 struct csa_softc { 60 device_t dev; /* device */ 61 csa_res res; /* resources */ 62 63 device_t pcm; /* pcm device */ 64 driver_intr_t* pcmintr; /* pcm intr */ 65 void *pcmintr_arg; /* pcm intr arg */ 66 device_t midi; /* midi device */ 67 driver_intr_t* midiintr; /* midi intr */ 68 void *midiintr_arg; /* midi intr arg */ 69 void *ih; /* cookie */ 70 71 struct csa_card *card; 72 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 73 }; 74 75 typedef struct csa_softc *sc_p; 76 77 static int csa_probe(device_t dev); 78 static int csa_attach(device_t dev); 79 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 80 u_long start, u_long end, u_long count, u_int flags); 81 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 82 struct resource *r); 83 static int csa_setup_intr(device_t bus, device_t child, 84 struct resource *irq, int flags, 85 driver_intr_t *intr, void *arg, void **cookiep); 86 static int csa_teardown_intr(device_t bus, device_t child, 87 struct resource *irq, void *cookie); 88 static driver_intr_t csa_intr; 89 static int csa_initialize(sc_p scp); 90 static void csa_resetdsp(csa_res *resp); 91 static int csa_downloadimage(csa_res *resp); 92 93 static devclass_t csa_devclass; 94 95 static void 96 amp_none(void) 97 { 98 } 99 100 static void 101 amp_voyetra(void) 102 { 103 } 104 105 static int 106 clkrun_hack(int run) 107 { 108 #ifdef __i386__ 109 devclass_t pci_devclass; 110 device_t *pci_devices, *pci_children, *busp, *childp; 111 int pci_count = 0, pci_childcount = 0; 112 int i, j, port; 113 u_int16_t control; 114 bus_space_tag_t btag; 115 116 if ((pci_devclass = devclass_find("pci")) == NULL) { 117 return ENXIO; 118 } 119 120 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 121 122 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 123 pci_childcount = 0; 124 device_get_children(*busp, &pci_children, &pci_childcount); 125 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 126 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 127 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 128 /* XXX */ 129 btag = I386_BUS_SPACE_IO; 130 131 control = bus_space_read_2(btag, 0x0, port); 132 control &= ~0x2000; 133 control |= run? 0 : 0x2000; 134 bus_space_write_2(btag, 0x0, port, control); 135 free(pci_devices, M_TEMP); 136 free(pci_children, M_TEMP); 137 return 0; 138 } 139 } 140 free(pci_children, M_TEMP); 141 } 142 143 free(pci_devices, M_TEMP); 144 return ENXIO; 145 #else 146 return 0; 147 #endif 148 } 149 150 static struct csa_card cards_4610[] = { 151 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 152 }; 153 154 static struct csa_card cards_4614[] = { 155 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 156 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 157 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 158 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 159 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 160 /* Not sure if the 570 needs the clkrun hack */ 161 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, clkrun_hack, 0}, 162 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 163 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 164 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 165 }; 166 167 static struct csa_card cards_4615[] = { 168 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 169 }; 170 171 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 172 173 struct card_type { 174 u_int32_t devid; 175 char *name; 176 struct csa_card *cards; 177 }; 178 179 static struct card_type cards[] = { 180 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 181 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 182 {CS4615_PCI_ID, "CS4615", cards_4615}, 183 {0, NULL, NULL}, 184 }; 185 186 static struct card_type * 187 csa_findcard(device_t dev) 188 { 189 int i; 190 191 i = 0; 192 while (cards[i].devid != 0) { 193 if (pci_get_devid(dev) == cards[i].devid) 194 return &cards[i]; 195 i++; 196 } 197 return NULL; 198 } 199 200 struct csa_card * 201 csa_findsubcard(device_t dev) 202 { 203 int i; 204 struct card_type *card; 205 struct csa_card *subcard; 206 207 card = csa_findcard(dev); 208 if (card == NULL) 209 return &nocard; 210 subcard = card->cards; 211 i = 0; 212 while (subcard[i].subvendor != 0) { 213 if (pci_get_subvendor(dev) == subcard[i].subvendor 214 && pci_get_subdevice(dev) == subcard[i].subdevice) { 215 return &subcard[i]; 216 } 217 i++; 218 } 219 return &subcard[i]; 220 } 221 222 static int 223 csa_probe(device_t dev) 224 { 225 struct card_type *card; 226 227 card = csa_findcard(dev); 228 if (card) { 229 device_set_desc(dev, card->name); 230 return 0; 231 } 232 return ENXIO; 233 } 234 235 static int 236 csa_attach(device_t dev) 237 { 238 u_int32_t stcmd; 239 sc_p scp; 240 csa_res *resp; 241 struct sndcard_func *func; 242 int error = ENXIO; 243 244 scp = device_get_softc(dev); 245 246 /* Fill in the softc. */ 247 bzero(scp, sizeof(*scp)); 248 scp->dev = dev; 249 250 /* Wake up the device. */ 251 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 252 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 253 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 254 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 255 } 256 257 /* Allocate the resources. */ 258 resp = &scp->res; 259 scp->card = csa_findsubcard(dev); 260 scp->binfo.card = scp->card; 261 printf("csa: card is %s\n", scp->card->name); 262 resp->io_rid = PCIR_MAPS; 263 resp->io = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->io_rid, 0, ~0, 1, RF_ACTIVE); 264 if (resp->io == NULL) 265 return (ENXIO); 266 resp->mem_rid = PCIR_MAPS + 4; 267 resp->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &resp->mem_rid, 0, ~0, 1, RF_ACTIVE); 268 if (resp->mem == NULL) 269 goto err_io; 270 resp->irq_rid = 0; 271 resp->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &resp->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 272 if (resp->irq == NULL) 273 goto err_mem; 274 275 /* Enable interrupt. */ 276 if (snd_setup_intr(dev, resp->irq, INTR_MPSAFE, csa_intr, scp, &scp->ih)) 277 goto err_intr; 278 #if 0 279 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 280 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 281 #endif 282 283 /* Initialize the chip. */ 284 if (csa_initialize(scp)) 285 goto err_teardown; 286 287 /* Reset the Processor. */ 288 csa_resetdsp(resp); 289 290 /* Download the Processor Image to the processor. */ 291 if (csa_downloadimage(resp)) 292 goto err_teardown; 293 294 /* Attach the children. */ 295 296 /* PCM Audio */ 297 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 298 if (func == NULL) { 299 error = ENOMEM; 300 goto err_teardown; 301 } 302 func->varinfo = &scp->binfo; 303 func->func = SCF_PCM; 304 scp->pcm = device_add_child(dev, "pcm", -1); 305 device_set_ivars(scp->pcm, func); 306 307 /* Midi Interface */ 308 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 309 if (func == NULL) { 310 error = ENOMEM; 311 goto err_teardown; 312 } 313 func->varinfo = &scp->binfo; 314 func->func = SCF_MIDI; 315 scp->midi = device_add_child(dev, "midi", -1); 316 device_set_ivars(scp->midi, func); 317 318 bus_generic_attach(dev); 319 320 return (0); 321 322 err_teardown: 323 bus_teardown_intr(dev, resp->irq, scp->ih); 324 err_intr: 325 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 326 err_mem: 327 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 328 err_io: 329 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 330 return (error); 331 } 332 333 static int 334 csa_detach(device_t dev) 335 { 336 csa_res *resp; 337 sc_p scp; 338 int err; 339 340 scp = device_get_softc(dev); 341 resp = &scp->res; 342 343 err = 0; 344 if (scp->midi != NULL) 345 err = device_delete_child(dev, scp->midi); 346 if (err) 347 return err; 348 scp->midi = NULL; 349 350 if (scp->pcm != NULL) 351 err = device_delete_child(dev, scp->pcm); 352 if (err) 353 return err; 354 scp->pcm = NULL; 355 356 bus_teardown_intr(dev, resp->irq, scp->ih); 357 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 358 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 359 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 360 361 return bus_generic_detach(dev); 362 } 363 364 static struct resource * 365 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 366 u_long start, u_long end, u_long count, u_int flags) 367 { 368 sc_p scp; 369 csa_res *resp; 370 struct resource *res; 371 372 scp = device_get_softc(bus); 373 resp = &scp->res; 374 switch (type) { 375 case SYS_RES_IRQ: 376 if (*rid != 0) 377 return (NULL); 378 res = resp->irq; 379 break; 380 case SYS_RES_MEMORY: 381 switch (*rid) { 382 case PCIR_MAPS: 383 res = resp->io; 384 break; 385 case PCIR_MAPS + 4: 386 res = resp->mem; 387 break; 388 default: 389 return (NULL); 390 } 391 break; 392 default: 393 return (NULL); 394 } 395 396 return res; 397 } 398 399 static int 400 csa_release_resource(device_t bus, device_t child, int type, int rid, 401 struct resource *r) 402 { 403 return (0); 404 } 405 406 /* 407 * The following three functions deal with interrupt handling. 408 * An interrupt is primarily handled by the bridge driver. 409 * The bridge driver then determines the child devices to pass 410 * the interrupt. Certain information of the device can be read 411 * only once(eg the value of HISR). The bridge driver is responsible 412 * to pass such the information to the children. 413 */ 414 415 static int 416 csa_setup_intr(device_t bus, device_t child, 417 struct resource *irq, int flags, 418 driver_intr_t *intr, void *arg, void **cookiep) 419 { 420 sc_p scp; 421 csa_res *resp; 422 struct sndcard_func *func; 423 424 scp = device_get_softc(bus); 425 resp = &scp->res; 426 427 /* 428 * Look at the function code of the child to determine 429 * the appropriate hander for it. 430 */ 431 func = device_get_ivars(child); 432 if (func == NULL || irq != resp->irq) 433 return (EINVAL); 434 435 switch (func->func) { 436 case SCF_PCM: 437 scp->pcmintr = intr; 438 scp->pcmintr_arg = arg; 439 break; 440 441 case SCF_MIDI: 442 scp->midiintr = intr; 443 scp->midiintr_arg = arg; 444 break; 445 446 default: 447 return (EINVAL); 448 } 449 *cookiep = scp; 450 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 451 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 452 453 return (0); 454 } 455 456 static int 457 csa_teardown_intr(device_t bus, device_t child, 458 struct resource *irq, void *cookie) 459 { 460 sc_p scp; 461 csa_res *resp; 462 struct sndcard_func *func; 463 464 scp = device_get_softc(bus); 465 resp = &scp->res; 466 467 /* 468 * Look at the function code of the child to determine 469 * the appropriate hander for it. 470 */ 471 func = device_get_ivars(child); 472 if (func == NULL || irq != resp->irq || cookie != scp) 473 return (EINVAL); 474 475 switch (func->func) { 476 case SCF_PCM: 477 scp->pcmintr = NULL; 478 scp->pcmintr_arg = NULL; 479 break; 480 481 case SCF_MIDI: 482 scp->midiintr = NULL; 483 scp->midiintr_arg = NULL; 484 break; 485 486 default: 487 return (EINVAL); 488 } 489 490 return (0); 491 } 492 493 /* The interrupt handler */ 494 static void 495 csa_intr(void *arg) 496 { 497 sc_p scp = arg; 498 csa_res *resp; 499 u_int32_t hisr; 500 501 resp = &scp->res; 502 503 /* Is this interrupt for us? */ 504 hisr = csa_readio(resp, BA0_HISR); 505 if ((hisr & 0x7fffffff) == 0) { 506 /* Throw an eoi. */ 507 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 508 return; 509 } 510 511 /* 512 * Pass the value of HISR via struct csa_bridgeinfo. 513 * The children get access through their ivars. 514 */ 515 scp->binfo.hisr = hisr; 516 517 /* Invoke the handlers of the children. */ 518 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 519 scp->pcmintr(scp->pcmintr_arg); 520 hisr &= ~(HISR_VC0 | HISR_VC1); 521 } 522 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 523 scp->midiintr(scp->midiintr_arg); 524 hisr &= ~HISR_MIDI; 525 } 526 527 /* Throw an eoi. */ 528 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 529 } 530 531 static int 532 csa_initialize(sc_p scp) 533 { 534 int i; 535 u_int32_t acsts, acisv; 536 csa_res *resp; 537 538 resp = &scp->res; 539 540 /* 541 * First, blast the clock control register to zero so that the PLL starts 542 * out in a known state, and blast the master serial port control register 543 * to zero so that the serial ports also start out in a known state. 544 */ 545 csa_writeio(resp, BA0_CLKCR1, 0); 546 csa_writeio(resp, BA0_SERMC1, 0); 547 548 /* 549 * If we are in AC97 mode, then we must set the part to a host controlled 550 * AC-link. Otherwise, we won't be able to bring up the link. 551 */ 552 #if 1 553 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 554 #else 555 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 556 #endif /* 1 */ 557 558 /* 559 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 560 * spec) and then drive it high. This is done for non AC97 modes since 561 * there might be logic external to the CS461x that uses the ARST# line 562 * for a reset. 563 */ 564 csa_writeio(resp, BA0_ACCTL, 1); 565 DELAY(50); 566 csa_writeio(resp, BA0_ACCTL, 0); 567 DELAY(50); 568 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 569 570 /* 571 * The first thing we do here is to enable sync generation. As soon 572 * as we start receiving bit clock, we'll start producing the SYNC 573 * signal. 574 */ 575 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 576 577 /* 578 * Now wait for a short while to allow the AC97 part to start 579 * generating bit clock (so we don't try to start the PLL without an 580 * input clock). 581 */ 582 DELAY(50000); 583 584 /* 585 * Set the serial port timing configuration, so that 586 * the clock control circuit gets its clock from the correct place. 587 */ 588 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 589 DELAY(700000); 590 591 /* 592 * Write the selected clock control setup to the hardware. Do not turn on 593 * SWCE yet (if requested), so that the devices clocked by the output of 594 * PLL are not clocked until the PLL is stable. 595 */ 596 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 597 csa_writeio(resp, BA0_PLLM, 0x3a); 598 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 599 600 /* 601 * Power up the PLL. 602 */ 603 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 604 605 /* 606 * Wait until the PLL has stabilized. 607 */ 608 DELAY(5000); 609 610 /* 611 * Turn on clocking of the core so that we can setup the serial ports. 612 */ 613 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 614 615 /* 616 * Fill the serial port FIFOs with silence. 617 */ 618 csa_clearserialfifos(resp); 619 620 /* 621 * Set the serial port FIFO pointer to the first sample in the FIFO. 622 */ 623 #if notdef 624 csa_writeio(resp, BA0_SERBSP, 0); 625 #endif /* notdef */ 626 627 /* 628 * Write the serial port configuration to the part. The master 629 * enable bit is not set until all other values have been written. 630 */ 631 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 632 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 633 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 634 635 /* 636 * Wait for the codec ready signal from the AC97 codec. 637 */ 638 acsts = 0; 639 for (i = 0 ; i < 1000 ; i++) { 640 /* 641 * First, lets wait a short while to let things settle out a bit, 642 * and to prevent retrying the read too quickly. 643 */ 644 DELAY(125); 645 646 /* 647 * Read the AC97 status register to see if we've seen a CODEC READY 648 * signal from the AC97 codec. 649 */ 650 acsts = csa_readio(resp, BA0_ACSTS); 651 if ((acsts & ACSTS_CRDY) != 0) 652 break; 653 } 654 655 /* 656 * Make sure we sampled CODEC READY. 657 */ 658 if ((acsts & ACSTS_CRDY) == 0) 659 return (ENXIO); 660 661 /* 662 * Assert the vaid frame signal so that we can start sending commands 663 * to the AC97 codec. 664 */ 665 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 666 667 /* 668 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 669 * the codec is pumping ADC data across the AC-link. 670 */ 671 acisv = 0; 672 for (i = 0 ; i < 1000 ; i++) { 673 /* 674 * First, lets wait a short while to let things settle out a bit, 675 * and to prevent retrying the read too quickly. 676 */ 677 #if notdef 678 DELAY(10000000L); /* clw */ 679 #else 680 DELAY(1000); 681 #endif /* notdef */ 682 /* 683 * Read the input slot valid register and see if input slots 3 and 684 * 4 are valid yet. 685 */ 686 acisv = csa_readio(resp, BA0_ACISV); 687 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 688 break; 689 } 690 /* 691 * Make sure we sampled valid input slots 3 and 4. If not, then return 692 * an error. 693 */ 694 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 695 return (ENXIO); 696 697 /* 698 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 699 * commense the transfer of digital audio data to the AC97 codec. 700 */ 701 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 702 703 /* 704 * Power down the DAC and ADC. We will power them up (if) when we need 705 * them. 706 */ 707 #if notdef 708 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 709 #endif /* notdef */ 710 711 /* 712 * Turn off the Processor by turning off the software clock enable flag in 713 * the clock control register. 714 */ 715 #if notdef 716 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 717 csa_writeio(resp, BA0_CLKCR1, clkcr1); 718 #endif /* notdef */ 719 720 /* 721 * Enable interrupts on the part. 722 */ 723 #if 0 724 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 725 #endif /* notdef */ 726 727 return (0); 728 } 729 730 void 731 csa_clearserialfifos(csa_res *resp) 732 { 733 int i, j, pwr; 734 u_int8_t clkcr1, serbst; 735 736 /* 737 * See if the devices are powered down. If so, we must power them up first 738 * or they will not respond. 739 */ 740 pwr = 1; 741 clkcr1 = csa_readio(resp, BA0_CLKCR1); 742 if ((clkcr1 & CLKCR1_SWCE) == 0) { 743 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 744 pwr = 0; 745 } 746 747 /* 748 * We want to clear out the serial port FIFOs so we don't end up playing 749 * whatever random garbage happens to be in them. We fill the sample FIFOs 750 * with zero (silence). 751 */ 752 csa_writeio(resp, BA0_SERBWP, 0); 753 754 /* Fill all 256 sample FIFO locations. */ 755 serbst = 0; 756 for (i = 0 ; i < 256 ; i++) { 757 /* Make sure the previous FIFO write operation has completed. */ 758 for (j = 0 ; j < 5 ; j++) { 759 DELAY(100); 760 serbst = csa_readio(resp, BA0_SERBST); 761 if ((serbst & SERBST_WBSY) == 0) 762 break; 763 } 764 if ((serbst & SERBST_WBSY) != 0) { 765 if (!pwr) 766 csa_writeio(resp, BA0_CLKCR1, clkcr1); 767 } 768 /* Write the serial port FIFO index. */ 769 csa_writeio(resp, BA0_SERBAD, i); 770 /* Tell the serial port to load the new value into the FIFO location. */ 771 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 772 } 773 /* 774 * Now, if we powered up the devices, then power them back down again. 775 * This is kinda ugly, but should never happen. 776 */ 777 if (!pwr) 778 csa_writeio(resp, BA0_CLKCR1, clkcr1); 779 } 780 781 static void 782 csa_resetdsp(csa_res *resp) 783 { 784 int i; 785 786 /* 787 * Write the reset bit of the SP control register. 788 */ 789 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 790 791 /* 792 * Write the control register. 793 */ 794 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 795 796 /* 797 * Clear the trap registers. 798 */ 799 for (i = 0 ; i < 8 ; i++) { 800 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 801 csa_writemem(resp, BA1_TWPR, 0xffff); 802 } 803 csa_writemem(resp, BA1_DREG, 0); 804 805 /* 806 * Set the frame timer to reflect the number of cycles per frame. 807 */ 808 csa_writemem(resp, BA1_FRMT, 0xadf); 809 } 810 811 static int 812 csa_downloadimage(csa_res *resp) 813 { 814 int i; 815 u_int32_t tmp, src, dst, count, data; 816 817 for (i = 0; i < CLEAR__COUNT; i++) { 818 dst = ClrStat[i].BA1__DestByteOffset; 819 count = ClrStat[i].BA1__SourceSize; 820 for (tmp = 0; tmp < count; tmp += 4) 821 csa_writemem(resp, dst + tmp, 0x00000000); 822 } 823 824 for (i = 0; i < FILL__COUNT; i++) { 825 src = 0; 826 dst = FillStat[i].Offset; 827 count = FillStat[i].Size; 828 for (tmp = 0; tmp < count; tmp += 4) { 829 data = FillStat[i].pFill[src]; 830 csa_writemem(resp, dst + tmp, data); 831 src++; 832 } 833 } 834 835 return (0); 836 } 837 838 int 839 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 840 { 841 int i; 842 u_int32_t acsda, acctl, acsts; 843 844 /* 845 * Make sure that there is not data sitting around from a previous 846 * uncompleted access. ACSDA = Status Data Register = 47Ch 847 */ 848 acsda = csa_readio(resp, BA0_ACSDA); 849 850 /* 851 * Setup the AC97 control registers on the CS461x to send the 852 * appropriate command to the AC97 to perform the read. 853 * ACCAD = Command Address Register = 46Ch 854 * ACCDA = Command Data Register = 470h 855 * ACCTL = Control Register = 460h 856 * set DCV - will clear when process completed 857 * set CRW - Read command 858 * set VFRM - valid frame enabled 859 * set ESYN - ASYNC generation enabled 860 * set RSTN - ARST# inactive, AC97 codec not reset 861 */ 862 863 /* 864 * Get the actual AC97 register from the offset 865 */ 866 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 867 csa_writeio(resp, BA0_ACCDA, 0); 868 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 869 870 /* 871 * Wait for the read to occur. 872 */ 873 acctl = 0; 874 for (i = 0 ; i < 10 ; i++) { 875 /* 876 * First, we want to wait for a short time. 877 */ 878 DELAY(25); 879 880 /* 881 * Now, check to see if the read has completed. 882 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 883 */ 884 acctl = csa_readio(resp, BA0_ACCTL); 885 if ((acctl & ACCTL_DCV) == 0) 886 break; 887 } 888 889 /* 890 * Make sure the read completed. 891 */ 892 if ((acctl & ACCTL_DCV) != 0) 893 return (EAGAIN); 894 895 /* 896 * Wait for the valid status bit to go active. 897 */ 898 acsts = 0; 899 for (i = 0 ; i < 10 ; i++) { 900 /* 901 * Read the AC97 status register. 902 * ACSTS = Status Register = 464h 903 */ 904 acsts = csa_readio(resp, BA0_ACSTS); 905 /* 906 * See if we have valid status. 907 * VSTS - Valid Status 908 */ 909 if ((acsts & ACSTS_VSTS) != 0) 910 break; 911 /* 912 * Wait for a short while. 913 */ 914 DELAY(25); 915 } 916 917 /* 918 * Make sure we got valid status. 919 */ 920 if ((acsts & ACSTS_VSTS) == 0) 921 return (EAGAIN); 922 923 /* 924 * Read the data returned from the AC97 register. 925 * ACSDA = Status Data Register = 474h 926 */ 927 *data = csa_readio(resp, BA0_ACSDA); 928 929 return (0); 930 } 931 932 int 933 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 934 { 935 int i; 936 u_int32_t acctl; 937 938 /* 939 * Setup the AC97 control registers on the CS461x to send the 940 * appropriate command to the AC97 to perform the write. 941 * ACCAD = Command Address Register = 46Ch 942 * ACCDA = Command Data Register = 470h 943 * ACCTL = Control Register = 460h 944 * set DCV - will clear when process completed 945 * set VFRM - valid frame enabled 946 * set ESYN - ASYNC generation enabled 947 * set RSTN - ARST# inactive, AC97 codec not reset 948 */ 949 950 /* 951 * Get the actual AC97 register from the offset 952 */ 953 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 954 csa_writeio(resp, BA0_ACCDA, data); 955 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 956 957 /* 958 * Wait for the write to occur. 959 */ 960 acctl = 0; 961 for (i = 0 ; i < 10 ; i++) { 962 /* 963 * First, we want to wait for a short time. 964 */ 965 DELAY(25); 966 967 /* 968 * Now, check to see if the read has completed. 969 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 970 */ 971 acctl = csa_readio(resp, BA0_ACCTL); 972 if ((acctl & ACCTL_DCV) == 0) 973 break; 974 } 975 976 /* 977 * Make sure the write completed. 978 */ 979 if ((acctl & ACCTL_DCV) != 0) 980 return (EAGAIN); 981 982 return (0); 983 } 984 985 u_int32_t 986 csa_readio(csa_res *resp, u_long offset) 987 { 988 u_int32_t ul; 989 990 if (offset < BA0_AC97_RESET) 991 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 992 else { 993 if (csa_readcodec(resp, offset, &ul)) 994 ul = 0; 995 return (ul); 996 } 997 } 998 999 void 1000 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1001 { 1002 if (offset < BA0_AC97_RESET) 1003 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1004 else 1005 csa_writecodec(resp, offset, data); 1006 } 1007 1008 u_int32_t 1009 csa_readmem(csa_res *resp, u_long offset) 1010 { 1011 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1012 } 1013 1014 void 1015 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1016 { 1017 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1018 } 1019 1020 static device_method_t csa_methods[] = { 1021 /* Device interface */ 1022 DEVMETHOD(device_probe, csa_probe), 1023 DEVMETHOD(device_attach, csa_attach), 1024 DEVMETHOD(device_detach, csa_detach), 1025 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1026 DEVMETHOD(device_suspend, bus_generic_suspend), 1027 DEVMETHOD(device_resume, bus_generic_resume), 1028 1029 /* Bus interface */ 1030 DEVMETHOD(bus_print_child, bus_generic_print_child), 1031 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1032 DEVMETHOD(bus_release_resource, csa_release_resource), 1033 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1034 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1035 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1036 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1037 1038 { 0, 0 } 1039 }; 1040 1041 static driver_t csa_driver = { 1042 "csa", 1043 csa_methods, 1044 sizeof(struct csa_softc), 1045 }; 1046 1047 /* 1048 * csa can be attached to a pci bus. 1049 */ 1050 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1051 MODULE_DEPEND(snd_csa, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1052 MODULE_VERSION(snd_csa, 1); 1053