1 /*- 2 * Copyright (c) 1999 Seigo Tanimura 3 * All rights reserved. 4 * 5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <machine/resource.h> 38 #include <machine/bus.h> 39 #include <sys/rman.h> 40 #include <sys/soundcard.h> 41 #include <dev/sound/pcm/sound.h> 42 #include <dev/sound/chip.h> 43 #include <dev/sound/pci/csareg.h> 44 #include <dev/sound/pci/csavar.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <gnu/dev/sound/pci/csaimg.h> 50 51 SND_DECLARE_FILE("$FreeBSD$"); 52 53 /* This is the pci device id. */ 54 #define CS4610_PCI_ID 0x60011013 55 #define CS4614_PCI_ID 0x60031013 56 #define CS4615_PCI_ID 0x60041013 57 58 /* Here is the parameter structure per a device. */ 59 struct csa_softc { 60 device_t dev; /* device */ 61 csa_res res; /* resources */ 62 63 device_t pcm; /* pcm device */ 64 driver_intr_t* pcmintr; /* pcm intr */ 65 void *pcmintr_arg; /* pcm intr arg */ 66 device_t midi; /* midi device */ 67 driver_intr_t* midiintr; /* midi intr */ 68 void *midiintr_arg; /* midi intr arg */ 69 void *ih; /* cookie */ 70 71 struct csa_card *card; 72 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 73 }; 74 75 typedef struct csa_softc *sc_p; 76 77 static int csa_probe(device_t dev); 78 static int csa_attach(device_t dev); 79 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 80 u_long start, u_long end, u_long count, u_int flags); 81 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 82 struct resource *r); 83 static int csa_setup_intr(device_t bus, device_t child, 84 struct resource *irq, int flags, 85 #if __FreeBSD_version >= 700031 86 driver_filter_t *filter, 87 #endif 88 driver_intr_t *intr, void *arg, void **cookiep); 89 static int csa_teardown_intr(device_t bus, device_t child, 90 struct resource *irq, void *cookie); 91 static driver_intr_t csa_intr; 92 static int csa_initialize(sc_p scp); 93 static int csa_downloadimage(csa_res *resp); 94 95 static devclass_t csa_devclass; 96 97 static void 98 amp_none(void) 99 { 100 } 101 102 static void 103 amp_voyetra(void) 104 { 105 } 106 107 static int 108 clkrun_hack(int run) 109 { 110 #ifdef __i386__ 111 devclass_t pci_devclass; 112 device_t *pci_devices, *pci_children, *busp, *childp; 113 int pci_count = 0, pci_childcount = 0; 114 int i, j, port; 115 u_int16_t control; 116 bus_space_tag_t btag; 117 118 if ((pci_devclass = devclass_find("pci")) == NULL) { 119 return ENXIO; 120 } 121 122 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 123 124 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 125 pci_childcount = 0; 126 device_get_children(*busp, &pci_children, &pci_childcount); 127 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 128 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 129 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 130 /* XXX */ 131 btag = I386_BUS_SPACE_IO; 132 133 control = bus_space_read_2(btag, 0x0, port); 134 control &= ~0x2000; 135 control |= run? 0 : 0x2000; 136 bus_space_write_2(btag, 0x0, port, control); 137 free(pci_devices, M_TEMP); 138 free(pci_children, M_TEMP); 139 return 0; 140 } 141 } 142 free(pci_children, M_TEMP); 143 } 144 145 free(pci_devices, M_TEMP); 146 return ENXIO; 147 #else 148 return 0; 149 #endif 150 } 151 152 static struct csa_card cards_4610[] = { 153 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 154 }; 155 156 static struct csa_card cards_4614[] = { 157 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 158 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 159 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 160 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 161 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 162 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 163 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 164 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 165 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 166 }; 167 168 static struct csa_card cards_4615[] = { 169 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 170 }; 171 172 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 173 174 struct card_type { 175 u_int32_t devid; 176 char *name; 177 struct csa_card *cards; 178 }; 179 180 static struct card_type cards[] = { 181 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 182 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 183 {CS4615_PCI_ID, "CS4615", cards_4615}, 184 {0, NULL, NULL}, 185 }; 186 187 static struct card_type * 188 csa_findcard(device_t dev) 189 { 190 int i; 191 192 i = 0; 193 while (cards[i].devid != 0) { 194 if (pci_get_devid(dev) == cards[i].devid) 195 return &cards[i]; 196 i++; 197 } 198 return NULL; 199 } 200 201 struct csa_card * 202 csa_findsubcard(device_t dev) 203 { 204 int i; 205 struct card_type *card; 206 struct csa_card *subcard; 207 208 card = csa_findcard(dev); 209 if (card == NULL) 210 return &nocard; 211 subcard = card->cards; 212 i = 0; 213 while (subcard[i].subvendor != 0) { 214 if (pci_get_subvendor(dev) == subcard[i].subvendor 215 && pci_get_subdevice(dev) == subcard[i].subdevice) { 216 return &subcard[i]; 217 } 218 i++; 219 } 220 return &subcard[i]; 221 } 222 223 static int 224 csa_probe(device_t dev) 225 { 226 struct card_type *card; 227 228 card = csa_findcard(dev); 229 if (card) { 230 device_set_desc(dev, card->name); 231 return BUS_PROBE_DEFAULT; 232 } 233 return ENXIO; 234 } 235 236 static int 237 csa_attach(device_t dev) 238 { 239 u_int32_t stcmd; 240 sc_p scp; 241 csa_res *resp; 242 struct sndcard_func *func; 243 int error = ENXIO; 244 245 scp = device_get_softc(dev); 246 247 /* Fill in the softc. */ 248 bzero(scp, sizeof(*scp)); 249 scp->dev = dev; 250 251 /* Wake up the device. */ 252 stcmd = pci_read_config(dev, PCIR_COMMAND, 2); 253 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) { 254 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 255 pci_write_config(dev, PCIR_COMMAND, stcmd, 2); 256 } 257 258 /* Allocate the resources. */ 259 resp = &scp->res; 260 scp->card = csa_findsubcard(dev); 261 scp->binfo.card = scp->card; 262 printf("csa: card is %s\n", scp->card->name); 263 resp->io_rid = PCIR_BAR(0); 264 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 265 &resp->io_rid, RF_ACTIVE); 266 if (resp->io == NULL) 267 return (ENXIO); 268 resp->mem_rid = PCIR_BAR(1); 269 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 270 &resp->mem_rid, RF_ACTIVE); 271 if (resp->mem == NULL) 272 goto err_io; 273 resp->irq_rid = 0; 274 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 275 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 276 if (resp->irq == NULL) 277 goto err_mem; 278 279 /* Enable interrupt. */ 280 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 281 goto err_intr; 282 #if 0 283 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 284 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 285 #endif 286 287 /* Initialize the chip. */ 288 if (csa_initialize(scp)) 289 goto err_teardown; 290 291 /* Reset the Processor. */ 292 csa_resetdsp(resp); 293 294 /* Download the Processor Image to the processor. */ 295 if (csa_downloadimage(resp)) 296 goto err_teardown; 297 298 /* Attach the children. */ 299 300 /* PCM Audio */ 301 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 302 if (func == NULL) { 303 error = ENOMEM; 304 goto err_teardown; 305 } 306 func->varinfo = &scp->binfo; 307 func->func = SCF_PCM; 308 scp->pcm = device_add_child(dev, "pcm", -1); 309 device_set_ivars(scp->pcm, func); 310 311 /* Midi Interface */ 312 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 313 if (func == NULL) { 314 error = ENOMEM; 315 goto err_teardown; 316 } 317 func->varinfo = &scp->binfo; 318 func->func = SCF_MIDI; 319 scp->midi = device_add_child(dev, "midi", -1); 320 device_set_ivars(scp->midi, func); 321 322 bus_generic_attach(dev); 323 324 return (0); 325 326 err_teardown: 327 bus_teardown_intr(dev, resp->irq, scp->ih); 328 err_intr: 329 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 330 err_mem: 331 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 332 err_io: 333 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 334 return (error); 335 } 336 337 static int 338 csa_detach(device_t dev) 339 { 340 csa_res *resp; 341 sc_p scp; 342 int err; 343 344 scp = device_get_softc(dev); 345 resp = &scp->res; 346 347 err = 0; 348 if (scp->midi != NULL) 349 err = device_delete_child(dev, scp->midi); 350 if (err) 351 return err; 352 scp->midi = NULL; 353 354 if (scp->pcm != NULL) 355 err = device_delete_child(dev, scp->pcm); 356 if (err) 357 return err; 358 scp->pcm = NULL; 359 360 bus_teardown_intr(dev, resp->irq, scp->ih); 361 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 362 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 363 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 364 365 return bus_generic_detach(dev); 366 } 367 368 static int 369 csa_resume(device_t dev) 370 { 371 csa_res *resp; 372 sc_p scp; 373 374 scp = device_get_softc(dev); 375 resp = &scp->res; 376 377 /* Initialize the chip. */ 378 if (csa_initialize(scp)) 379 return (ENXIO); 380 381 /* Reset the Processor. */ 382 csa_resetdsp(resp); 383 384 /* Download the Processor Image to the processor. */ 385 if (csa_downloadimage(resp)) 386 return (ENXIO); 387 388 return (bus_generic_resume(dev)); 389 } 390 391 static struct resource * 392 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 393 u_long start, u_long end, u_long count, u_int flags) 394 { 395 sc_p scp; 396 csa_res *resp; 397 struct resource *res; 398 399 scp = device_get_softc(bus); 400 resp = &scp->res; 401 switch (type) { 402 case SYS_RES_IRQ: 403 if (*rid != 0) 404 return (NULL); 405 res = resp->irq; 406 break; 407 case SYS_RES_MEMORY: 408 switch (*rid) { 409 case PCIR_BAR(0): 410 res = resp->io; 411 break; 412 case PCIR_BAR(1): 413 res = resp->mem; 414 break; 415 default: 416 return (NULL); 417 } 418 break; 419 default: 420 return (NULL); 421 } 422 423 return res; 424 } 425 426 static int 427 csa_release_resource(device_t bus, device_t child, int type, int rid, 428 struct resource *r) 429 { 430 return (0); 431 } 432 433 /* 434 * The following three functions deal with interrupt handling. 435 * An interrupt is primarily handled by the bridge driver. 436 * The bridge driver then determines the child devices to pass 437 * the interrupt. Certain information of the device can be read 438 * only once(eg the value of HISR). The bridge driver is responsible 439 * to pass such the information to the children. 440 */ 441 442 static int 443 csa_setup_intr(device_t bus, device_t child, 444 struct resource *irq, int flags, 445 #if __FreeBSD_version >= 700031 446 driver_filter_t *filter, 447 #endif 448 driver_intr_t *intr, void *arg, void **cookiep) 449 { 450 sc_p scp; 451 csa_res *resp; 452 struct sndcard_func *func; 453 454 #if __FreeBSD_version >= 700031 455 if (filter != NULL) { 456 printf("ata-csa.c: we cannot use a filter here\n"); 457 return (EINVAL); 458 } 459 #endif 460 scp = device_get_softc(bus); 461 resp = &scp->res; 462 463 /* 464 * Look at the function code of the child to determine 465 * the appropriate hander for it. 466 */ 467 func = device_get_ivars(child); 468 if (func == NULL || irq != resp->irq) 469 return (EINVAL); 470 471 switch (func->func) { 472 case SCF_PCM: 473 scp->pcmintr = intr; 474 scp->pcmintr_arg = arg; 475 break; 476 477 case SCF_MIDI: 478 scp->midiintr = intr; 479 scp->midiintr_arg = arg; 480 break; 481 482 default: 483 return (EINVAL); 484 } 485 *cookiep = scp; 486 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 487 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 488 489 return (0); 490 } 491 492 static int 493 csa_teardown_intr(device_t bus, device_t child, 494 struct resource *irq, void *cookie) 495 { 496 sc_p scp; 497 csa_res *resp; 498 struct sndcard_func *func; 499 500 scp = device_get_softc(bus); 501 resp = &scp->res; 502 503 /* 504 * Look at the function code of the child to determine 505 * the appropriate hander for it. 506 */ 507 func = device_get_ivars(child); 508 if (func == NULL || irq != resp->irq || cookie != scp) 509 return (EINVAL); 510 511 switch (func->func) { 512 case SCF_PCM: 513 scp->pcmintr = NULL; 514 scp->pcmintr_arg = NULL; 515 break; 516 517 case SCF_MIDI: 518 scp->midiintr = NULL; 519 scp->midiintr_arg = NULL; 520 break; 521 522 default: 523 return (EINVAL); 524 } 525 526 return (0); 527 } 528 529 /* The interrupt handler */ 530 static void 531 csa_intr(void *arg) 532 { 533 sc_p scp = arg; 534 csa_res *resp; 535 u_int32_t hisr; 536 537 resp = &scp->res; 538 539 /* Is this interrupt for us? */ 540 hisr = csa_readio(resp, BA0_HISR); 541 if ((hisr & 0x7fffffff) == 0) { 542 /* Throw an eoi. */ 543 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 544 return; 545 } 546 547 /* 548 * Pass the value of HISR via struct csa_bridgeinfo. 549 * The children get access through their ivars. 550 */ 551 scp->binfo.hisr = hisr; 552 553 /* Invoke the handlers of the children. */ 554 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 555 scp->pcmintr(scp->pcmintr_arg); 556 hisr &= ~(HISR_VC0 | HISR_VC1); 557 } 558 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 559 scp->midiintr(scp->midiintr_arg); 560 hisr &= ~HISR_MIDI; 561 } 562 563 /* Throw an eoi. */ 564 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 565 } 566 567 static int 568 csa_initialize(sc_p scp) 569 { 570 int i; 571 u_int32_t acsts, acisv; 572 csa_res *resp; 573 574 resp = &scp->res; 575 576 /* 577 * First, blast the clock control register to zero so that the PLL starts 578 * out in a known state, and blast the master serial port control register 579 * to zero so that the serial ports also start out in a known state. 580 */ 581 csa_writeio(resp, BA0_CLKCR1, 0); 582 csa_writeio(resp, BA0_SERMC1, 0); 583 584 /* 585 * If we are in AC97 mode, then we must set the part to a host controlled 586 * AC-link. Otherwise, we won't be able to bring up the link. 587 */ 588 #if 1 589 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 590 #else 591 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 592 #endif /* 1 */ 593 594 /* 595 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 596 * spec) and then drive it high. This is done for non AC97 modes since 597 * there might be logic external to the CS461x that uses the ARST# line 598 * for a reset. 599 */ 600 csa_writeio(resp, BA0_ACCTL, 1); 601 DELAY(50); 602 csa_writeio(resp, BA0_ACCTL, 0); 603 DELAY(50); 604 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 605 606 /* 607 * The first thing we do here is to enable sync generation. As soon 608 * as we start receiving bit clock, we'll start producing the SYNC 609 * signal. 610 */ 611 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 612 613 /* 614 * Now wait for a short while to allow the AC97 part to start 615 * generating bit clock (so we don't try to start the PLL without an 616 * input clock). 617 */ 618 DELAY(50000); 619 620 /* 621 * Set the serial port timing configuration, so that 622 * the clock control circuit gets its clock from the correct place. 623 */ 624 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 625 DELAY(700000); 626 627 /* 628 * Write the selected clock control setup to the hardware. Do not turn on 629 * SWCE yet (if requested), so that the devices clocked by the output of 630 * PLL are not clocked until the PLL is stable. 631 */ 632 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 633 csa_writeio(resp, BA0_PLLM, 0x3a); 634 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 635 636 /* 637 * Power up the PLL. 638 */ 639 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 640 641 /* 642 * Wait until the PLL has stabilized. 643 */ 644 DELAY(5000); 645 646 /* 647 * Turn on clocking of the core so that we can setup the serial ports. 648 */ 649 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 650 651 /* 652 * Fill the serial port FIFOs with silence. 653 */ 654 csa_clearserialfifos(resp); 655 656 /* 657 * Set the serial port FIFO pointer to the first sample in the FIFO. 658 */ 659 #ifdef notdef 660 csa_writeio(resp, BA0_SERBSP, 0); 661 #endif /* notdef */ 662 663 /* 664 * Write the serial port configuration to the part. The master 665 * enable bit is not set until all other values have been written. 666 */ 667 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 668 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 669 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 670 671 /* 672 * Wait for the codec ready signal from the AC97 codec. 673 */ 674 acsts = 0; 675 for (i = 0 ; i < 1000 ; i++) { 676 /* 677 * First, lets wait a short while to let things settle out a bit, 678 * and to prevent retrying the read too quickly. 679 */ 680 DELAY(125); 681 682 /* 683 * Read the AC97 status register to see if we've seen a CODEC READY 684 * signal from the AC97 codec. 685 */ 686 acsts = csa_readio(resp, BA0_ACSTS); 687 if ((acsts & ACSTS_CRDY) != 0) 688 break; 689 } 690 691 /* 692 * Make sure we sampled CODEC READY. 693 */ 694 if ((acsts & ACSTS_CRDY) == 0) 695 return (ENXIO); 696 697 /* 698 * Assert the vaid frame signal so that we can start sending commands 699 * to the AC97 codec. 700 */ 701 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 702 703 /* 704 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 705 * the codec is pumping ADC data across the AC-link. 706 */ 707 acisv = 0; 708 for (i = 0 ; i < 1000 ; i++) { 709 /* 710 * First, lets wait a short while to let things settle out a bit, 711 * and to prevent retrying the read too quickly. 712 */ 713 #ifdef notdef 714 DELAY(10000000L); /* clw */ 715 #else 716 DELAY(1000); 717 #endif /* notdef */ 718 /* 719 * Read the input slot valid register and see if input slots 3 and 720 * 4 are valid yet. 721 */ 722 acisv = csa_readio(resp, BA0_ACISV); 723 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 724 break; 725 } 726 /* 727 * Make sure we sampled valid input slots 3 and 4. If not, then return 728 * an error. 729 */ 730 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 731 return (ENXIO); 732 733 /* 734 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 735 * commense the transfer of digital audio data to the AC97 codec. 736 */ 737 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 738 739 /* 740 * Power down the DAC and ADC. We will power them up (if) when we need 741 * them. 742 */ 743 #ifdef notdef 744 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 745 #endif /* notdef */ 746 747 /* 748 * Turn off the Processor by turning off the software clock enable flag in 749 * the clock control register. 750 */ 751 #ifdef notdef 752 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 753 csa_writeio(resp, BA0_CLKCR1, clkcr1); 754 #endif /* notdef */ 755 756 /* 757 * Enable interrupts on the part. 758 */ 759 #if 0 760 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 761 #endif /* notdef */ 762 763 return (0); 764 } 765 766 void 767 csa_clearserialfifos(csa_res *resp) 768 { 769 int i, j, pwr; 770 u_int8_t clkcr1, serbst; 771 772 /* 773 * See if the devices are powered down. If so, we must power them up first 774 * or they will not respond. 775 */ 776 pwr = 1; 777 clkcr1 = csa_readio(resp, BA0_CLKCR1); 778 if ((clkcr1 & CLKCR1_SWCE) == 0) { 779 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 780 pwr = 0; 781 } 782 783 /* 784 * We want to clear out the serial port FIFOs so we don't end up playing 785 * whatever random garbage happens to be in them. We fill the sample FIFOs 786 * with zero (silence). 787 */ 788 csa_writeio(resp, BA0_SERBWP, 0); 789 790 /* Fill all 256 sample FIFO locations. */ 791 serbst = 0; 792 for (i = 0 ; i < 256 ; i++) { 793 /* Make sure the previous FIFO write operation has completed. */ 794 for (j = 0 ; j < 5 ; j++) { 795 DELAY(100); 796 serbst = csa_readio(resp, BA0_SERBST); 797 if ((serbst & SERBST_WBSY) == 0) 798 break; 799 } 800 if ((serbst & SERBST_WBSY) != 0) { 801 if (!pwr) 802 csa_writeio(resp, BA0_CLKCR1, clkcr1); 803 } 804 /* Write the serial port FIFO index. */ 805 csa_writeio(resp, BA0_SERBAD, i); 806 /* Tell the serial port to load the new value into the FIFO location. */ 807 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 808 } 809 /* 810 * Now, if we powered up the devices, then power them back down again. 811 * This is kinda ugly, but should never happen. 812 */ 813 if (!pwr) 814 csa_writeio(resp, BA0_CLKCR1, clkcr1); 815 } 816 817 void 818 csa_resetdsp(csa_res *resp) 819 { 820 int i; 821 822 /* 823 * Write the reset bit of the SP control register. 824 */ 825 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 826 827 /* 828 * Write the control register. 829 */ 830 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 831 832 /* 833 * Clear the trap registers. 834 */ 835 for (i = 0 ; i < 8 ; i++) { 836 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 837 csa_writemem(resp, BA1_TWPR, 0xffff); 838 } 839 csa_writemem(resp, BA1_DREG, 0); 840 841 /* 842 * Set the frame timer to reflect the number of cycles per frame. 843 */ 844 csa_writemem(resp, BA1_FRMT, 0xadf); 845 } 846 847 static int 848 csa_downloadimage(csa_res *resp) 849 { 850 int i; 851 u_int32_t tmp, src, dst, count, data; 852 853 for (i = 0; i < CLEAR__COUNT; i++) { 854 dst = ClrStat[i].BA1__DestByteOffset; 855 count = ClrStat[i].BA1__SourceSize; 856 for (tmp = 0; tmp < count; tmp += 4) 857 csa_writemem(resp, dst + tmp, 0x00000000); 858 } 859 860 for (i = 0; i < FILL__COUNT; i++) { 861 src = 0; 862 dst = FillStat[i].Offset; 863 count = FillStat[i].Size; 864 for (tmp = 0; tmp < count; tmp += 4) { 865 data = FillStat[i].pFill[src]; 866 csa_writemem(resp, dst + tmp, data); 867 src++; 868 } 869 } 870 871 return (0); 872 } 873 874 int 875 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 876 { 877 int i; 878 u_int32_t acsda, acctl, acsts; 879 880 /* 881 * Make sure that there is not data sitting around from a previous 882 * uncompleted access. ACSDA = Status Data Register = 47Ch 883 */ 884 acsda = csa_readio(resp, BA0_ACSDA); 885 886 /* 887 * Setup the AC97 control registers on the CS461x to send the 888 * appropriate command to the AC97 to perform the read. 889 * ACCAD = Command Address Register = 46Ch 890 * ACCDA = Command Data Register = 470h 891 * ACCTL = Control Register = 460h 892 * set DCV - will clear when process completed 893 * set CRW - Read command 894 * set VFRM - valid frame enabled 895 * set ESYN - ASYNC generation enabled 896 * set RSTN - ARST# inactive, AC97 codec not reset 897 */ 898 899 /* 900 * Get the actual AC97 register from the offset 901 */ 902 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 903 csa_writeio(resp, BA0_ACCDA, 0); 904 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 905 906 /* 907 * Wait for the read to occur. 908 */ 909 acctl = 0; 910 for (i = 0 ; i < 10 ; i++) { 911 /* 912 * First, we want to wait for a short time. 913 */ 914 DELAY(25); 915 916 /* 917 * Now, check to see if the read has completed. 918 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 919 */ 920 acctl = csa_readio(resp, BA0_ACCTL); 921 if ((acctl & ACCTL_DCV) == 0) 922 break; 923 } 924 925 /* 926 * Make sure the read completed. 927 */ 928 if ((acctl & ACCTL_DCV) != 0) 929 return (EAGAIN); 930 931 /* 932 * Wait for the valid status bit to go active. 933 */ 934 acsts = 0; 935 for (i = 0 ; i < 10 ; i++) { 936 /* 937 * Read the AC97 status register. 938 * ACSTS = Status Register = 464h 939 */ 940 acsts = csa_readio(resp, BA0_ACSTS); 941 /* 942 * See if we have valid status. 943 * VSTS - Valid Status 944 */ 945 if ((acsts & ACSTS_VSTS) != 0) 946 break; 947 /* 948 * Wait for a short while. 949 */ 950 DELAY(25); 951 } 952 953 /* 954 * Make sure we got valid status. 955 */ 956 if ((acsts & ACSTS_VSTS) == 0) 957 return (EAGAIN); 958 959 /* 960 * Read the data returned from the AC97 register. 961 * ACSDA = Status Data Register = 474h 962 */ 963 *data = csa_readio(resp, BA0_ACSDA); 964 965 return (0); 966 } 967 968 int 969 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 970 { 971 int i; 972 u_int32_t acctl; 973 974 /* 975 * Setup the AC97 control registers on the CS461x to send the 976 * appropriate command to the AC97 to perform the write. 977 * ACCAD = Command Address Register = 46Ch 978 * ACCDA = Command Data Register = 470h 979 * ACCTL = Control Register = 460h 980 * set DCV - will clear when process completed 981 * set VFRM - valid frame enabled 982 * set ESYN - ASYNC generation enabled 983 * set RSTN - ARST# inactive, AC97 codec not reset 984 */ 985 986 /* 987 * Get the actual AC97 register from the offset 988 */ 989 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 990 csa_writeio(resp, BA0_ACCDA, data); 991 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 992 993 /* 994 * Wait for the write to occur. 995 */ 996 acctl = 0; 997 for (i = 0 ; i < 10 ; i++) { 998 /* 999 * First, we want to wait for a short time. 1000 */ 1001 DELAY(25); 1002 1003 /* 1004 * Now, check to see if the read has completed. 1005 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1006 */ 1007 acctl = csa_readio(resp, BA0_ACCTL); 1008 if ((acctl & ACCTL_DCV) == 0) 1009 break; 1010 } 1011 1012 /* 1013 * Make sure the write completed. 1014 */ 1015 if ((acctl & ACCTL_DCV) != 0) 1016 return (EAGAIN); 1017 1018 return (0); 1019 } 1020 1021 u_int32_t 1022 csa_readio(csa_res *resp, u_long offset) 1023 { 1024 u_int32_t ul; 1025 1026 if (offset < BA0_AC97_RESET) 1027 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1028 else { 1029 if (csa_readcodec(resp, offset, &ul)) 1030 ul = 0; 1031 return (ul); 1032 } 1033 } 1034 1035 void 1036 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1037 { 1038 if (offset < BA0_AC97_RESET) 1039 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1040 else 1041 csa_writecodec(resp, offset, data); 1042 } 1043 1044 u_int32_t 1045 csa_readmem(csa_res *resp, u_long offset) 1046 { 1047 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1048 } 1049 1050 void 1051 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1052 { 1053 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1054 } 1055 1056 static device_method_t csa_methods[] = { 1057 /* Device interface */ 1058 DEVMETHOD(device_probe, csa_probe), 1059 DEVMETHOD(device_attach, csa_attach), 1060 DEVMETHOD(device_detach, csa_detach), 1061 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1062 DEVMETHOD(device_suspend, bus_generic_suspend), 1063 DEVMETHOD(device_resume, csa_resume), 1064 1065 /* Bus interface */ 1066 DEVMETHOD(bus_print_child, bus_generic_print_child), 1067 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1068 DEVMETHOD(bus_release_resource, csa_release_resource), 1069 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1070 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1071 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1072 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1073 1074 { 0, 0 } 1075 }; 1076 1077 static driver_t csa_driver = { 1078 "csa", 1079 csa_methods, 1080 sizeof(struct csa_softc), 1081 }; 1082 1083 /* 1084 * csa can be attached to a pci bus. 1085 */ 1086 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1087 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1088 MODULE_VERSION(snd_csa, 1); 1089