xref: /freebsd/sys/dev/sound/pci/csa.c (revision 1e413cf93298b5b97441a21d9a50fdcd0ee9945e)
1 /*-
2  * Copyright (c) 1999 Seigo Tanimura
3  * All rights reserved.
4  *
5  * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
6  * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
7  * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  */
30 
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/bus.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <machine/resource.h>
38 #include <machine/bus.h>
39 #include <sys/rman.h>
40 #include <sys/soundcard.h>
41 #include <dev/sound/pcm/sound.h>
42 #include <dev/sound/chip.h>
43 #include <dev/sound/pci/csareg.h>
44 #include <dev/sound/pci/csavar.h>
45 
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48 
49 #include <gnu/dev/sound/pci/csaimg.h>
50 
51 SND_DECLARE_FILE("$FreeBSD$");
52 
53 /* This is the pci device id. */
54 #define CS4610_PCI_ID 0x60011013
55 #define CS4614_PCI_ID 0x60031013
56 #define CS4615_PCI_ID 0x60041013
57 
58 /* Here is the parameter structure per a device. */
59 struct csa_softc {
60 	device_t dev; /* device */
61 	csa_res res; /* resources */
62 
63 	device_t pcm; /* pcm device */
64 	driver_intr_t* pcmintr; /* pcm intr */
65 	void *pcmintr_arg; /* pcm intr arg */
66 	device_t midi; /* midi device */
67 	driver_intr_t* midiintr; /* midi intr */
68 	void *midiintr_arg; /* midi intr arg */
69 	void *ih; /* cookie */
70 
71 	struct csa_card *card;
72 	struct csa_bridgeinfo binfo; /* The state of this bridge. */
73 };
74 
75 typedef struct csa_softc *sc_p;
76 
77 static int csa_probe(device_t dev);
78 static int csa_attach(device_t dev);
79 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
80 					      u_long start, u_long end, u_long count, u_int flags);
81 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
82 				   struct resource *r);
83 static int csa_setup_intr(device_t bus, device_t child,
84 			  struct resource *irq, int flags,
85 #if __FreeBSD_version >= 700031
86 			  driver_filter_t *filter,
87 #endif
88 			  driver_intr_t *intr,  void *arg, void **cookiep);
89 static int csa_teardown_intr(device_t bus, device_t child,
90 			     struct resource *irq, void *cookie);
91 static driver_intr_t csa_intr;
92 static int csa_initialize(sc_p scp);
93 static int csa_downloadimage(csa_res *resp);
94 
95 static devclass_t csa_devclass;
96 
97 static void
98 amp_none(void)
99 {
100 }
101 
102 static void
103 amp_voyetra(void)
104 {
105 }
106 
107 static int
108 clkrun_hack(int run)
109 {
110 #ifdef __i386__
111 	devclass_t		pci_devclass;
112 	device_t		*pci_devices, *pci_children, *busp, *childp;
113 	int			pci_count = 0, pci_childcount = 0;
114 	int			i, j, port;
115 	u_int16_t		control;
116 	bus_space_tag_t		btag;
117 
118 	if ((pci_devclass = devclass_find("pci")) == NULL) {
119 		return ENXIO;
120 	}
121 
122 	devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
123 
124 	for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
125 		pci_childcount = 0;
126 		device_get_children(*busp, &pci_children, &pci_childcount);
127 		for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
128 			if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
129 				port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
130 				/* XXX */
131 				btag = I386_BUS_SPACE_IO;
132 
133 				control = bus_space_read_2(btag, 0x0, port);
134 				control &= ~0x2000;
135 				control |= run? 0 : 0x2000;
136 				bus_space_write_2(btag, 0x0, port, control);
137 				free(pci_devices, M_TEMP);
138 				free(pci_children, M_TEMP);
139 				return 0;
140 			}
141 		}
142 		free(pci_children, M_TEMP);
143 	}
144 
145 	free(pci_devices, M_TEMP);
146 	return ENXIO;
147 #else
148 	return 0;
149 #endif
150 }
151 
152 static struct csa_card cards_4610[] = {
153 	{0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
154 };
155 
156 static struct csa_card cards_4614[] = {
157 	{0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
158 	{0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
159 	{0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
160 	{0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
161 	{0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
162 	{0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
163 	{0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
164 	{0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
165 	{0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
166 };
167 
168 static struct csa_card cards_4615[] = {
169 	{0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
170 };
171 
172 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
173 
174 struct card_type {
175 	u_int32_t devid;
176 	char *name;
177 	struct csa_card *cards;
178 };
179 
180 static struct card_type cards[] = {
181 	{CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
182 	{CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
183 	{CS4615_PCI_ID, "CS4615", cards_4615},
184 	{0, NULL, NULL},
185 };
186 
187 static struct card_type *
188 csa_findcard(device_t dev)
189 {
190 	int i;
191 
192 	i = 0;
193 	while (cards[i].devid != 0) {
194 		if (pci_get_devid(dev) == cards[i].devid)
195 			return &cards[i];
196 		i++;
197 	}
198 	return NULL;
199 }
200 
201 struct csa_card *
202 csa_findsubcard(device_t dev)
203 {
204 	int i;
205 	struct card_type *card;
206 	struct csa_card *subcard;
207 
208 	card = csa_findcard(dev);
209 	if (card == NULL)
210 		return &nocard;
211 	subcard = card->cards;
212 	i = 0;
213 	while (subcard[i].subvendor != 0) {
214 		if (pci_get_subvendor(dev) == subcard[i].subvendor
215 		    && pci_get_subdevice(dev) == subcard[i].subdevice) {
216 			return &subcard[i];
217 		}
218 		i++;
219 	}
220 	return &subcard[i];
221 }
222 
223 static int
224 csa_probe(device_t dev)
225 {
226 	struct card_type *card;
227 
228 	card = csa_findcard(dev);
229 	if (card) {
230 		device_set_desc(dev, card->name);
231 		return BUS_PROBE_DEFAULT;
232 	}
233 	return ENXIO;
234 }
235 
236 static int
237 csa_attach(device_t dev)
238 {
239 	u_int32_t stcmd;
240 	sc_p scp;
241 	csa_res *resp;
242 	struct sndcard_func *func;
243 	int error = ENXIO;
244 
245 	scp = device_get_softc(dev);
246 
247 	/* Fill in the softc. */
248 	bzero(scp, sizeof(*scp));
249 	scp->dev = dev;
250 
251 	/* Wake up the device. */
252 	stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
253 	if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
254 		stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
255 		pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
256 	}
257 
258 	/* Allocate the resources. */
259 	resp = &scp->res;
260 	scp->card = csa_findsubcard(dev);
261 	scp->binfo.card = scp->card;
262 	printf("csa: card is %s\n", scp->card->name);
263 	resp->io_rid = PCIR_BAR(0);
264 	resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
265 		&resp->io_rid, RF_ACTIVE);
266 	if (resp->io == NULL)
267 		return (ENXIO);
268 	resp->mem_rid = PCIR_BAR(1);
269 	resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
270 		&resp->mem_rid, RF_ACTIVE);
271 	if (resp->mem == NULL)
272 		goto err_io;
273 	resp->irq_rid = 0;
274 	resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
275 		&resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
276 	if (resp->irq == NULL)
277 		goto err_mem;
278 
279 	/* Enable interrupt. */
280 	if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
281 		goto err_intr;
282 #if 0
283 	if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
284 		csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
285 #endif
286 
287 	/* Initialize the chip. */
288 	if (csa_initialize(scp))
289 		goto err_teardown;
290 
291 	/* Reset the Processor. */
292 	csa_resetdsp(resp);
293 
294 	/* Download the Processor Image to the processor. */
295 	if (csa_downloadimage(resp))
296 		goto err_teardown;
297 
298 	/* Attach the children. */
299 
300 	/* PCM Audio */
301 	func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
302 	if (func == NULL) {
303 		error = ENOMEM;
304 		goto err_teardown;
305 	}
306 	func->varinfo = &scp->binfo;
307 	func->func = SCF_PCM;
308 	scp->pcm = device_add_child(dev, "pcm", -1);
309 	device_set_ivars(scp->pcm, func);
310 
311 	/* Midi Interface */
312 	func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
313 	if (func == NULL) {
314 		error = ENOMEM;
315 		goto err_teardown;
316 	}
317 	func->varinfo = &scp->binfo;
318 	func->func = SCF_MIDI;
319 	scp->midi = device_add_child(dev, "midi", -1);
320 	device_set_ivars(scp->midi, func);
321 
322 	bus_generic_attach(dev);
323 
324 	return (0);
325 
326 err_teardown:
327 	bus_teardown_intr(dev, resp->irq, scp->ih);
328 err_intr:
329 	bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
330 err_mem:
331 	bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
332 err_io:
333 	bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
334 	return (error);
335 }
336 
337 static int
338 csa_detach(device_t dev)
339 {
340 	csa_res *resp;
341 	sc_p scp;
342 	struct sndcard_func *func;
343 	int err;
344 
345 	scp = device_get_softc(dev);
346 	resp = &scp->res;
347 
348 	if (scp->midi != NULL) {
349 		func = device_get_ivars(scp->midi);
350 		err = device_delete_child(dev, scp->midi);
351 		if (err != 0)
352 			return err;
353 		if (func != NULL)
354 			free(func, M_DEVBUF);
355 		scp->midi = NULL;
356 	}
357 
358 	if (scp->pcm != NULL) {
359 		func = device_get_ivars(scp->pcm);
360 		err = device_delete_child(dev, scp->pcm);
361 		if (err != 0)
362 			return err;
363 		if (func != NULL)
364 			free(func, M_DEVBUF);
365 		scp->pcm = NULL;
366 	}
367 
368 	bus_teardown_intr(dev, resp->irq, scp->ih);
369 	bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
370 	bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
371 	bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
372 
373 	return bus_generic_detach(dev);
374 }
375 
376 static int
377 csa_resume(device_t dev)
378 {
379 	csa_res *resp;
380 	sc_p scp;
381 
382 	scp = device_get_softc(dev);
383 	resp = &scp->res;
384 
385 	/* Initialize the chip. */
386 	if (csa_initialize(scp))
387 		return (ENXIO);
388 
389 	/* Reset the Processor. */
390 	csa_resetdsp(resp);
391 
392 	/* Download the Processor Image to the processor. */
393 	if (csa_downloadimage(resp))
394 		return (ENXIO);
395 
396 	return (bus_generic_resume(dev));
397 }
398 
399 static struct resource *
400 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
401 		      u_long start, u_long end, u_long count, u_int flags)
402 {
403 	sc_p scp;
404 	csa_res *resp;
405 	struct resource *res;
406 
407 	scp = device_get_softc(bus);
408 	resp = &scp->res;
409 	switch (type) {
410 	case SYS_RES_IRQ:
411 		if (*rid != 0)
412 			return (NULL);
413 		res = resp->irq;
414 		break;
415 	case SYS_RES_MEMORY:
416 		switch (*rid) {
417 		case PCIR_BAR(0):
418 			res = resp->io;
419 			break;
420 		case PCIR_BAR(1):
421 			res = resp->mem;
422 			break;
423 		default:
424 			return (NULL);
425 		}
426 		break;
427 	default:
428 		return (NULL);
429 	}
430 
431 	return res;
432 }
433 
434 static int
435 csa_release_resource(device_t bus, device_t child, int type, int rid,
436 			struct resource *r)
437 {
438 	return (0);
439 }
440 
441 /*
442  * The following three functions deal with interrupt handling.
443  * An interrupt is primarily handled by the bridge driver.
444  * The bridge driver then determines the child devices to pass
445  * the interrupt. Certain information of the device can be read
446  * only once(eg the value of HISR). The bridge driver is responsible
447  * to pass such the information to the children.
448  */
449 
450 static int
451 csa_setup_intr(device_t bus, device_t child,
452 	       struct resource *irq, int flags,
453 #if __FreeBSD_version >= 700031
454 	       driver_filter_t *filter,
455 #endif
456 	       driver_intr_t *intr, void *arg, void **cookiep)
457 {
458 	sc_p scp;
459 	csa_res *resp;
460 	struct sndcard_func *func;
461 
462 #if __FreeBSD_version >= 700031
463 	if (filter != NULL) {
464 		printf("ata-csa.c: we cannot use a filter here\n");
465 		return (EINVAL);
466 	}
467 #endif
468 	scp = device_get_softc(bus);
469 	resp = &scp->res;
470 
471 	/*
472 	 * Look at the function code of the child to determine
473 	 * the appropriate hander for it.
474 	 */
475 	func = device_get_ivars(child);
476 	if (func == NULL || irq != resp->irq)
477 		return (EINVAL);
478 
479 	switch (func->func) {
480 	case SCF_PCM:
481 		scp->pcmintr = intr;
482 		scp->pcmintr_arg = arg;
483 		break;
484 
485 	case SCF_MIDI:
486 		scp->midiintr = intr;
487 		scp->midiintr_arg = arg;
488 		break;
489 
490 	default:
491 		return (EINVAL);
492 	}
493 	*cookiep = scp;
494 	if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
495 		csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
496 
497 	return (0);
498 }
499 
500 static int
501 csa_teardown_intr(device_t bus, device_t child,
502 		  struct resource *irq, void *cookie)
503 {
504 	sc_p scp;
505 	csa_res *resp;
506 	struct sndcard_func *func;
507 
508 	scp = device_get_softc(bus);
509 	resp = &scp->res;
510 
511 	/*
512 	 * Look at the function code of the child to determine
513 	 * the appropriate hander for it.
514 	 */
515 	func = device_get_ivars(child);
516 	if (func == NULL || irq != resp->irq || cookie != scp)
517 		return (EINVAL);
518 
519 	switch (func->func) {
520 	case SCF_PCM:
521 		scp->pcmintr = NULL;
522 		scp->pcmintr_arg = NULL;
523 		break;
524 
525 	case SCF_MIDI:
526 		scp->midiintr = NULL;
527 		scp->midiintr_arg = NULL;
528 		break;
529 
530 	default:
531 		return (EINVAL);
532 	}
533 
534 	return (0);
535 }
536 
537 /* The interrupt handler */
538 static void
539 csa_intr(void *arg)
540 {
541 	sc_p scp = arg;
542 	csa_res *resp;
543 	u_int32_t hisr;
544 
545 	resp = &scp->res;
546 
547 	/* Is this interrupt for us? */
548 	hisr = csa_readio(resp, BA0_HISR);
549 	if ((hisr & 0x7fffffff) == 0) {
550 		/* Throw an eoi. */
551 		csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
552 		return;
553 	}
554 
555 	/*
556 	 * Pass the value of HISR via struct csa_bridgeinfo.
557 	 * The children get access through their ivars.
558 	 */
559 	scp->binfo.hisr = hisr;
560 
561 	/* Invoke the handlers of the children. */
562 	if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
563 		scp->pcmintr(scp->pcmintr_arg);
564 		hisr &= ~(HISR_VC0 | HISR_VC1);
565 	}
566 	if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
567 		scp->midiintr(scp->midiintr_arg);
568 		hisr &= ~HISR_MIDI;
569 	}
570 
571 	/* Throw an eoi. */
572 	csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
573 }
574 
575 static int
576 csa_initialize(sc_p scp)
577 {
578 	int i;
579 	u_int32_t acsts, acisv;
580 	csa_res *resp;
581 
582 	resp = &scp->res;
583 
584 	/*
585 	 * First, blast the clock control register to zero so that the PLL starts
586 	 * out in a known state, and blast the master serial port control register
587 	 * to zero so that the serial ports also start out in a known state.
588 	 */
589 	csa_writeio(resp, BA0_CLKCR1, 0);
590 	csa_writeio(resp, BA0_SERMC1, 0);
591 
592 	/*
593 	 * If we are in AC97 mode, then we must set the part to a host controlled
594 	 * AC-link.  Otherwise, we won't be able to bring up the link.
595 	 */
596 #if 1
597 	csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
598 #else
599 	csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
600 #endif /* 1 */
601 
602 	/*
603 	 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
604 	 * spec) and then drive it high.  This is done for non AC97 modes since
605 	 * there might be logic external to the CS461x that uses the ARST# line
606 	 * for a reset.
607 	 */
608 	csa_writeio(resp, BA0_ACCTL, 1);
609 	DELAY(50);
610 	csa_writeio(resp, BA0_ACCTL, 0);
611 	DELAY(50);
612 	csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
613 
614 	/*
615 	 * The first thing we do here is to enable sync generation.  As soon
616 	 * as we start receiving bit clock, we'll start producing the SYNC
617 	 * signal.
618 	 */
619 	csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
620 
621 	/*
622 	 * Now wait for a short while to allow the AC97 part to start
623 	 * generating bit clock (so we don't try to start the PLL without an
624 	 * input clock).
625 	 */
626 	DELAY(50000);
627 
628 	/*
629 	 * Set the serial port timing configuration, so that
630 	 * the clock control circuit gets its clock from the correct place.
631 	 */
632 	csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
633 	DELAY(700000);
634 
635 	/*
636 	 * Write the selected clock control setup to the hardware.  Do not turn on
637 	 * SWCE yet (if requested), so that the devices clocked by the output of
638 	 * PLL are not clocked until the PLL is stable.
639 	 */
640 	csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
641 	csa_writeio(resp, BA0_PLLM, 0x3a);
642 	csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
643 
644 	/*
645 	 * Power up the PLL.
646 	 */
647 	csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
648 
649 	/*
650 	 * Wait until the PLL has stabilized.
651 	 */
652 	DELAY(5000);
653 
654 	/*
655 	 * Turn on clocking of the core so that we can setup the serial ports.
656 	 */
657 	csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
658 
659 	/*
660 	 * Fill the serial port FIFOs with silence.
661 	 */
662 	csa_clearserialfifos(resp);
663 
664 	/*
665 	 * Set the serial port FIFO pointer to the first sample in the FIFO.
666 	 */
667 #ifdef notdef
668 	csa_writeio(resp, BA0_SERBSP, 0);
669 #endif /* notdef */
670 
671 	/*
672 	 *  Write the serial port configuration to the part.  The master
673 	 *  enable bit is not set until all other values have been written.
674 	 */
675 	csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
676 	csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
677 	csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
678 
679 	/*
680 	 * Wait for the codec ready signal from the AC97 codec.
681 	 */
682 	acsts = 0;
683 	for (i = 0 ; i < 1000 ; i++) {
684 		/*
685 		 * First, lets wait a short while to let things settle out a bit,
686 		 * and to prevent retrying the read too quickly.
687 		 */
688 		DELAY(125);
689 
690 		/*
691 		 * Read the AC97 status register to see if we've seen a CODEC READY
692 		 * signal from the AC97 codec.
693 		 */
694 		acsts = csa_readio(resp, BA0_ACSTS);
695 		if ((acsts & ACSTS_CRDY) != 0)
696 			break;
697 	}
698 
699 	/*
700 	 * Make sure we sampled CODEC READY.
701 	 */
702 	if ((acsts & ACSTS_CRDY) == 0)
703 		return (ENXIO);
704 
705 	/*
706 	 * Assert the vaid frame signal so that we can start sending commands
707 	 * to the AC97 codec.
708 	 */
709 	csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
710 
711 	/*
712 	 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
713 	 * the codec is pumping ADC data across the AC-link.
714 	 */
715 	acisv = 0;
716 	for (i = 0 ; i < 1000 ; i++) {
717 		/*
718 		 * First, lets wait a short while to let things settle out a bit,
719 		 * and to prevent retrying the read too quickly.
720 		 */
721 #ifdef notdef
722 		DELAY(10000000L); /* clw */
723 #else
724 		DELAY(1000);
725 #endif /* notdef */
726 		/*
727 		 * Read the input slot valid register and see if input slots 3 and
728 		 * 4 are valid yet.
729 		 */
730 		acisv = csa_readio(resp, BA0_ACISV);
731 		if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
732 			break;
733 	}
734 	/*
735 	 * Make sure we sampled valid input slots 3 and 4.  If not, then return
736 	 * an error.
737 	 */
738 	if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
739 		return (ENXIO);
740 
741 	/*
742 	 * Now, assert valid frame and the slot 3 and 4 valid bits.  This will
743 	 * commense the transfer of digital audio data to the AC97 codec.
744 	 */
745 	csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
746 
747 	/*
748 	 * Power down the DAC and ADC.  We will power them up (if) when we need
749 	 * them.
750 	 */
751 #ifdef notdef
752 	csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
753 #endif /* notdef */
754 
755 	/*
756 	 * Turn off the Processor by turning off the software clock enable flag in
757 	 * the clock control register.
758 	 */
759 #ifdef notdef
760 	clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
761 	csa_writeio(resp, BA0_CLKCR1, clkcr1);
762 #endif /* notdef */
763 
764 	/*
765 	 * Enable interrupts on the part.
766 	 */
767 #if 0
768 	csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
769 #endif /* notdef */
770 
771 	return (0);
772 }
773 
774 void
775 csa_clearserialfifos(csa_res *resp)
776 {
777 	int i, j, pwr;
778 	u_int8_t clkcr1, serbst;
779 
780 	/*
781 	 * See if the devices are powered down.  If so, we must power them up first
782 	 * or they will not respond.
783 	 */
784 	pwr = 1;
785 	clkcr1 = csa_readio(resp, BA0_CLKCR1);
786 	if ((clkcr1 & CLKCR1_SWCE) == 0) {
787 		csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
788 		pwr = 0;
789 	}
790 
791 	/*
792 	 * We want to clear out the serial port FIFOs so we don't end up playing
793 	 * whatever random garbage happens to be in them.  We fill the sample FIFOs
794 	 * with zero (silence).
795 	 */
796 	csa_writeio(resp, BA0_SERBWP, 0);
797 
798 	/* Fill all 256 sample FIFO locations. */
799 	serbst = 0;
800 	for (i = 0 ; i < 256 ; i++) {
801 		/* Make sure the previous FIFO write operation has completed. */
802 		for (j = 0 ; j < 5 ; j++) {
803 			DELAY(100);
804 			serbst = csa_readio(resp, BA0_SERBST);
805 			if ((serbst & SERBST_WBSY) == 0)
806 				break;
807 		}
808 		if ((serbst & SERBST_WBSY) != 0) {
809 			if (!pwr)
810 				csa_writeio(resp, BA0_CLKCR1, clkcr1);
811 		}
812 		/* Write the serial port FIFO index. */
813 		csa_writeio(resp, BA0_SERBAD, i);
814 		/* Tell the serial port to load the new value into the FIFO location. */
815 		csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
816 	}
817 	/*
818 	 *  Now, if we powered up the devices, then power them back down again.
819 	 *  This is kinda ugly, but should never happen.
820 	 */
821 	if (!pwr)
822 		csa_writeio(resp, BA0_CLKCR1, clkcr1);
823 }
824 
825 void
826 csa_resetdsp(csa_res *resp)
827 {
828 	int i;
829 
830 	/*
831 	 * Write the reset bit of the SP control register.
832 	 */
833 	csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
834 
835 	/*
836 	 * Write the control register.
837 	 */
838 	csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
839 
840 	/*
841 	 * Clear the trap registers.
842 	 */
843 	for (i = 0 ; i < 8 ; i++) {
844 		csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
845 		csa_writemem(resp, BA1_TWPR, 0xffff);
846 	}
847 	csa_writemem(resp, BA1_DREG, 0);
848 
849 	/*
850 	 * Set the frame timer to reflect the number of cycles per frame.
851 	 */
852 	csa_writemem(resp, BA1_FRMT, 0xadf);
853 }
854 
855 static int
856 csa_downloadimage(csa_res *resp)
857 {
858 	int i;
859 	u_int32_t tmp, src, dst, count, data;
860 
861 	for (i = 0; i < CLEAR__COUNT; i++) {
862 		dst = ClrStat[i].BA1__DestByteOffset;
863 		count = ClrStat[i].BA1__SourceSize;
864 		for (tmp = 0; tmp < count; tmp += 4)
865 			csa_writemem(resp, dst + tmp, 0x00000000);
866 	}
867 
868 	for (i = 0; i < FILL__COUNT; i++) {
869 		src = 0;
870 		dst = FillStat[i].Offset;
871 		count = FillStat[i].Size;
872 		for (tmp = 0; tmp < count; tmp += 4) {
873 			data = FillStat[i].pFill[src];
874 			csa_writemem(resp, dst + tmp, data);
875 			src++;
876 		}
877 	}
878 
879 	return (0);
880 }
881 
882 int
883 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
884 {
885 	int i;
886 	u_int32_t acsda, acctl, acsts;
887 
888 	/*
889 	 * Make sure that there is not data sitting around from a previous
890 	 * uncompleted access. ACSDA = Status Data Register = 47Ch
891 	 */
892 	acsda = csa_readio(resp, BA0_ACSDA);
893 
894 	/*
895 	 * Setup the AC97 control registers on the CS461x to send the
896 	 * appropriate command to the AC97 to perform the read.
897 	 * ACCAD = Command Address Register = 46Ch
898 	 * ACCDA = Command Data Register = 470h
899 	 * ACCTL = Control Register = 460h
900 	 * set DCV - will clear when process completed
901 	 * set CRW - Read command
902 	 * set VFRM - valid frame enabled
903 	 * set ESYN - ASYNC generation enabled
904 	 * set RSTN - ARST# inactive, AC97 codec not reset
905 	 */
906 
907 	/*
908 	 * Get the actual AC97 register from the offset
909 	 */
910 	csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
911 	csa_writeio(resp, BA0_ACCDA, 0);
912 	csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
913 
914 	/*
915 	 * Wait for the read to occur.
916 	 */
917 	acctl = 0;
918 	for (i = 0 ; i < 10 ; i++) {
919 		/*
920 		 * First, we want to wait for a short time.
921 		 */
922 		DELAY(25);
923 
924 		/*
925 		 * Now, check to see if the read has completed.
926 		 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
927 		 */
928 		acctl = csa_readio(resp, BA0_ACCTL);
929 		if ((acctl & ACCTL_DCV) == 0)
930 			break;
931 	}
932 
933 	/*
934 	 * Make sure the read completed.
935 	 */
936 	if ((acctl & ACCTL_DCV) != 0)
937 		return (EAGAIN);
938 
939 	/*
940 	 * Wait for the valid status bit to go active.
941 	 */
942 	acsts = 0;
943 	for (i = 0 ; i < 10 ; i++) {
944 		/*
945 		 * Read the AC97 status register.
946 		 * ACSTS = Status Register = 464h
947 		 */
948 		acsts = csa_readio(resp, BA0_ACSTS);
949 		/*
950 		 * See if we have valid status.
951 		 * VSTS - Valid Status
952 		 */
953 		if ((acsts & ACSTS_VSTS) != 0)
954 			break;
955 		/*
956 		 * Wait for a short while.
957 		 */
958 		 DELAY(25);
959 	}
960 
961 	/*
962 	 * Make sure we got valid status.
963 	 */
964 	if ((acsts & ACSTS_VSTS) == 0)
965 		return (EAGAIN);
966 
967 	/*
968 	 * Read the data returned from the AC97 register.
969 	 * ACSDA = Status Data Register = 474h
970 	 */
971 	*data = csa_readio(resp, BA0_ACSDA);
972 
973 	return (0);
974 }
975 
976 int
977 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
978 {
979 	int i;
980 	u_int32_t acctl;
981 
982 	/*
983 	 * Setup the AC97 control registers on the CS461x to send the
984 	 * appropriate command to the AC97 to perform the write.
985 	 * ACCAD = Command Address Register = 46Ch
986 	 * ACCDA = Command Data Register = 470h
987 	 * ACCTL = Control Register = 460h
988 	 * set DCV - will clear when process completed
989 	 * set VFRM - valid frame enabled
990 	 * set ESYN - ASYNC generation enabled
991 	 * set RSTN - ARST# inactive, AC97 codec not reset
992 	 */
993 
994 	/*
995 	 * Get the actual AC97 register from the offset
996 	 */
997 	csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
998 	csa_writeio(resp, BA0_ACCDA, data);
999 	csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
1000 
1001 	/*
1002 	 * Wait for the write to occur.
1003 	 */
1004 	acctl = 0;
1005 	for (i = 0 ; i < 10 ; i++) {
1006 		/*
1007 		 * First, we want to wait for a short time.
1008 		 */
1009 		DELAY(25);
1010 
1011 		/*
1012 		 * Now, check to see if the read has completed.
1013 		 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
1014 		 */
1015 		acctl = csa_readio(resp, BA0_ACCTL);
1016 		if ((acctl & ACCTL_DCV) == 0)
1017 			break;
1018 	}
1019 
1020 	/*
1021 	 * Make sure the write completed.
1022 	 */
1023 	if ((acctl & ACCTL_DCV) != 0)
1024 		return (EAGAIN);
1025 
1026 	return (0);
1027 }
1028 
1029 u_int32_t
1030 csa_readio(csa_res *resp, u_long offset)
1031 {
1032 	u_int32_t ul;
1033 
1034 	if (offset < BA0_AC97_RESET)
1035 		return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1036 	else {
1037 		if (csa_readcodec(resp, offset, &ul))
1038 			ul = 0;
1039 		return (ul);
1040 	}
1041 }
1042 
1043 void
1044 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1045 {
1046 	if (offset < BA0_AC97_RESET)
1047 		bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1048 	else
1049 		csa_writecodec(resp, offset, data);
1050 }
1051 
1052 u_int32_t
1053 csa_readmem(csa_res *resp, u_long offset)
1054 {
1055 	return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1056 }
1057 
1058 void
1059 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1060 {
1061 	bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1062 }
1063 
1064 static device_method_t csa_methods[] = {
1065 	/* Device interface */
1066 	DEVMETHOD(device_probe,		csa_probe),
1067 	DEVMETHOD(device_attach,	csa_attach),
1068 	DEVMETHOD(device_detach,	csa_detach),
1069 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
1070 	DEVMETHOD(device_suspend,	bus_generic_suspend),
1071 	DEVMETHOD(device_resume,	csa_resume),
1072 
1073 	/* Bus interface */
1074 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
1075 	DEVMETHOD(bus_alloc_resource,	csa_alloc_resource),
1076 	DEVMETHOD(bus_release_resource,	csa_release_resource),
1077 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1078 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1079 	DEVMETHOD(bus_setup_intr,	csa_setup_intr),
1080 	DEVMETHOD(bus_teardown_intr,	csa_teardown_intr),
1081 
1082 	{ 0, 0 }
1083 };
1084 
1085 static driver_t csa_driver = {
1086 	"csa",
1087 	csa_methods,
1088 	sizeof(struct csa_softc),
1089 };
1090 
1091 /*
1092  * csa can be attached to a pci bus.
1093  */
1094 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1095 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1096 MODULE_VERSION(snd_csa, 1);
1097