1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1999 Seigo Tanimura 5 * All rights reserved. 6 * 7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 43 #ifdef HAVE_KERNEL_OPTION_HEADERS 44 #include "opt_snd.h" 45 #endif 46 47 #include <dev/sound/pcm/sound.h> 48 #include <dev/sound/chip.h> 49 #include <dev/sound/pci/csareg.h> 50 #include <dev/sound/pci/csavar.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 55 #include <dev/sound/pci/cs461x_dsp.h> 56 57 SND_DECLARE_FILE("$FreeBSD$"); 58 59 /* This is the pci device id. */ 60 #define CS4610_PCI_ID 0x60011013 61 #define CS4614_PCI_ID 0x60031013 62 #define CS4615_PCI_ID 0x60041013 63 64 /* Here is the parameter structure per a device. */ 65 struct csa_softc { 66 device_t dev; /* device */ 67 csa_res res; /* resources */ 68 69 device_t pcm; /* pcm device */ 70 driver_intr_t* pcmintr; /* pcm intr */ 71 void *pcmintr_arg; /* pcm intr arg */ 72 device_t midi; /* midi device */ 73 driver_intr_t* midiintr; /* midi intr */ 74 void *midiintr_arg; /* midi intr arg */ 75 void *ih; /* cookie */ 76 77 struct csa_card *card; 78 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 79 }; 80 81 typedef struct csa_softc *sc_p; 82 83 static int csa_probe(device_t dev); 84 static int csa_attach(device_t dev); 85 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 86 rman_res_t start, rman_res_t end, 87 rman_res_t count, u_int flags); 88 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 89 struct resource *r); 90 static int csa_setup_intr(device_t bus, device_t child, 91 struct resource *irq, int flags, 92 driver_filter_t *filter, 93 driver_intr_t *intr, void *arg, void **cookiep); 94 static int csa_teardown_intr(device_t bus, device_t child, 95 struct resource *irq, void *cookie); 96 static driver_intr_t csa_intr; 97 static int csa_initialize(sc_p scp); 98 static int csa_downloadimage(csa_res *resp); 99 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len); 100 101 static devclass_t csa_devclass; 102 103 static void 104 amp_none(void) 105 { 106 } 107 108 static void 109 amp_voyetra(void) 110 { 111 } 112 113 static int 114 clkrun_hack(int run) 115 { 116 #ifdef __i386__ 117 devclass_t pci_devclass; 118 device_t *pci_devices, *pci_children, *busp, *childp; 119 int pci_count = 0, pci_childcount = 0; 120 int i, j, port; 121 u_int16_t control; 122 bus_space_tag_t btag; 123 124 if ((pci_devclass = devclass_find("pci")) == NULL) { 125 return ENXIO; 126 } 127 128 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 129 130 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 131 pci_childcount = 0; 132 if (device_get_children(*busp, &pci_children, &pci_childcount)) 133 continue; 134 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 135 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 136 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 137 /* XXX */ 138 btag = X86_BUS_SPACE_IO; 139 140 control = bus_space_read_2(btag, 0x0, port); 141 control &= ~0x2000; 142 control |= run? 0 : 0x2000; 143 bus_space_write_2(btag, 0x0, port, control); 144 free(pci_devices, M_TEMP); 145 free(pci_children, M_TEMP); 146 return 0; 147 } 148 } 149 free(pci_children, M_TEMP); 150 } 151 152 free(pci_devices, M_TEMP); 153 return ENXIO; 154 #else 155 return 0; 156 #endif 157 } 158 159 static struct csa_card cards_4610[] = { 160 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 161 }; 162 163 static struct csa_card cards_4614[] = { 164 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 165 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 166 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 167 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 168 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 169 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 170 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 171 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 172 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 173 }; 174 175 static struct csa_card cards_4615[] = { 176 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 177 }; 178 179 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 180 181 struct card_type { 182 u_int32_t devid; 183 char *name; 184 struct csa_card *cards; 185 }; 186 187 static struct card_type cards[] = { 188 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 189 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 190 {CS4615_PCI_ID, "CS4615", cards_4615}, 191 {0, NULL, NULL}, 192 }; 193 194 static struct card_type * 195 csa_findcard(device_t dev) 196 { 197 int i; 198 199 i = 0; 200 while (cards[i].devid != 0) { 201 if (pci_get_devid(dev) == cards[i].devid) 202 return &cards[i]; 203 i++; 204 } 205 return NULL; 206 } 207 208 struct csa_card * 209 csa_findsubcard(device_t dev) 210 { 211 int i; 212 struct card_type *card; 213 struct csa_card *subcard; 214 215 card = csa_findcard(dev); 216 if (card == NULL) 217 return &nocard; 218 subcard = card->cards; 219 i = 0; 220 while (subcard[i].subvendor != 0) { 221 if (pci_get_subvendor(dev) == subcard[i].subvendor 222 && pci_get_subdevice(dev) == subcard[i].subdevice) { 223 return &subcard[i]; 224 } 225 i++; 226 } 227 return &subcard[i]; 228 } 229 230 static int 231 csa_probe(device_t dev) 232 { 233 struct card_type *card; 234 235 card = csa_findcard(dev); 236 if (card) { 237 device_set_desc(dev, card->name); 238 return BUS_PROBE_DEFAULT; 239 } 240 return ENXIO; 241 } 242 243 static int 244 csa_attach(device_t dev) 245 { 246 sc_p scp; 247 csa_res *resp; 248 struct sndcard_func *func; 249 int error = ENXIO; 250 251 scp = device_get_softc(dev); 252 253 /* Fill in the softc. */ 254 bzero(scp, sizeof(*scp)); 255 scp->dev = dev; 256 257 pci_enable_busmaster(dev); 258 259 /* Allocate the resources. */ 260 resp = &scp->res; 261 scp->card = csa_findsubcard(dev); 262 scp->binfo.card = scp->card; 263 printf("csa: card is %s\n", scp->card->name); 264 resp->io_rid = PCIR_BAR(0); 265 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 266 &resp->io_rid, RF_ACTIVE); 267 if (resp->io == NULL) 268 return (ENXIO); 269 resp->mem_rid = PCIR_BAR(1); 270 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 271 &resp->mem_rid, RF_ACTIVE); 272 if (resp->mem == NULL) 273 goto err_io; 274 resp->irq_rid = 0; 275 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 276 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 277 if (resp->irq == NULL) 278 goto err_mem; 279 280 /* Enable interrupt. */ 281 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 282 goto err_intr; 283 #if 0 284 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 285 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 286 #endif 287 288 /* Initialize the chip. */ 289 if (csa_initialize(scp)) 290 goto err_teardown; 291 292 /* Reset the Processor. */ 293 csa_resetdsp(resp); 294 295 /* Download the Processor Image to the processor. */ 296 if (csa_downloadimage(resp)) 297 goto err_teardown; 298 299 /* Attach the children. */ 300 301 /* PCM Audio */ 302 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 303 if (func == NULL) { 304 error = ENOMEM; 305 goto err_teardown; 306 } 307 func->varinfo = &scp->binfo; 308 func->func = SCF_PCM; 309 scp->pcm = device_add_child(dev, "pcm", -1); 310 device_set_ivars(scp->pcm, func); 311 312 /* Midi Interface */ 313 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 314 if (func == NULL) { 315 error = ENOMEM; 316 goto err_teardown; 317 } 318 func->varinfo = &scp->binfo; 319 func->func = SCF_MIDI; 320 scp->midi = device_add_child(dev, "midi", -1); 321 device_set_ivars(scp->midi, func); 322 323 bus_generic_attach(dev); 324 325 return (0); 326 327 err_teardown: 328 bus_teardown_intr(dev, resp->irq, scp->ih); 329 err_intr: 330 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 331 err_mem: 332 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 333 err_io: 334 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 335 return (error); 336 } 337 338 static int 339 csa_detach(device_t dev) 340 { 341 csa_res *resp; 342 sc_p scp; 343 struct sndcard_func *func; 344 int err; 345 346 scp = device_get_softc(dev); 347 resp = &scp->res; 348 349 if (scp->midi != NULL) { 350 func = device_get_ivars(scp->midi); 351 err = device_delete_child(dev, scp->midi); 352 if (err != 0) 353 return err; 354 if (func != NULL) 355 free(func, M_DEVBUF); 356 scp->midi = NULL; 357 } 358 359 if (scp->pcm != NULL) { 360 func = device_get_ivars(scp->pcm); 361 err = device_delete_child(dev, scp->pcm); 362 if (err != 0) 363 return err; 364 if (func != NULL) 365 free(func, M_DEVBUF); 366 scp->pcm = NULL; 367 } 368 369 bus_teardown_intr(dev, resp->irq, scp->ih); 370 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 371 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 372 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 373 374 return bus_generic_detach(dev); 375 } 376 377 static int 378 csa_resume(device_t dev) 379 { 380 csa_res *resp; 381 sc_p scp; 382 383 scp = device_get_softc(dev); 384 resp = &scp->res; 385 386 /* Initialize the chip. */ 387 if (csa_initialize(scp)) 388 return (ENXIO); 389 390 /* Reset the Processor. */ 391 csa_resetdsp(resp); 392 393 /* Download the Processor Image to the processor. */ 394 if (csa_downloadimage(resp)) 395 return (ENXIO); 396 397 return (bus_generic_resume(dev)); 398 } 399 400 static struct resource * 401 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 402 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 403 { 404 sc_p scp; 405 csa_res *resp; 406 struct resource *res; 407 408 scp = device_get_softc(bus); 409 resp = &scp->res; 410 switch (type) { 411 case SYS_RES_IRQ: 412 if (*rid != 0) 413 return (NULL); 414 res = resp->irq; 415 break; 416 case SYS_RES_MEMORY: 417 switch (*rid) { 418 case PCIR_BAR(0): 419 res = resp->io; 420 break; 421 case PCIR_BAR(1): 422 res = resp->mem; 423 break; 424 default: 425 return (NULL); 426 } 427 break; 428 default: 429 return (NULL); 430 } 431 432 return res; 433 } 434 435 static int 436 csa_release_resource(device_t bus, device_t child, int type, int rid, 437 struct resource *r) 438 { 439 return (0); 440 } 441 442 /* 443 * The following three functions deal with interrupt handling. 444 * An interrupt is primarily handled by the bridge driver. 445 * The bridge driver then determines the child devices to pass 446 * the interrupt. Certain information of the device can be read 447 * only once(eg the value of HISR). The bridge driver is responsible 448 * to pass such the information to the children. 449 */ 450 451 static int 452 csa_setup_intr(device_t bus, device_t child, 453 struct resource *irq, int flags, 454 driver_filter_t *filter, 455 driver_intr_t *intr, void *arg, void **cookiep) 456 { 457 sc_p scp; 458 csa_res *resp; 459 struct sndcard_func *func; 460 461 if (filter != NULL) { 462 printf("ata-csa.c: we cannot use a filter here\n"); 463 return (EINVAL); 464 } 465 scp = device_get_softc(bus); 466 resp = &scp->res; 467 468 /* 469 * Look at the function code of the child to determine 470 * the appropriate hander for it. 471 */ 472 func = device_get_ivars(child); 473 if (func == NULL || irq != resp->irq) 474 return (EINVAL); 475 476 switch (func->func) { 477 case SCF_PCM: 478 scp->pcmintr = intr; 479 scp->pcmintr_arg = arg; 480 break; 481 482 case SCF_MIDI: 483 scp->midiintr = intr; 484 scp->midiintr_arg = arg; 485 break; 486 487 default: 488 return (EINVAL); 489 } 490 *cookiep = scp; 491 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 492 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 493 494 return (0); 495 } 496 497 static int 498 csa_teardown_intr(device_t bus, device_t child, 499 struct resource *irq, void *cookie) 500 { 501 sc_p scp; 502 csa_res *resp; 503 struct sndcard_func *func; 504 505 scp = device_get_softc(bus); 506 resp = &scp->res; 507 508 /* 509 * Look at the function code of the child to determine 510 * the appropriate hander for it. 511 */ 512 func = device_get_ivars(child); 513 if (func == NULL || irq != resp->irq || cookie != scp) 514 return (EINVAL); 515 516 switch (func->func) { 517 case SCF_PCM: 518 scp->pcmintr = NULL; 519 scp->pcmintr_arg = NULL; 520 break; 521 522 case SCF_MIDI: 523 scp->midiintr = NULL; 524 scp->midiintr_arg = NULL; 525 break; 526 527 default: 528 return (EINVAL); 529 } 530 531 return (0); 532 } 533 534 /* The interrupt handler */ 535 static void 536 csa_intr(void *arg) 537 { 538 sc_p scp = arg; 539 csa_res *resp; 540 u_int32_t hisr; 541 542 resp = &scp->res; 543 544 /* Is this interrupt for us? */ 545 hisr = csa_readio(resp, BA0_HISR); 546 if ((hisr & 0x7fffffff) == 0) { 547 /* Throw an eoi. */ 548 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 549 return; 550 } 551 552 /* 553 * Pass the value of HISR via struct csa_bridgeinfo. 554 * The children get access through their ivars. 555 */ 556 scp->binfo.hisr = hisr; 557 558 /* Invoke the handlers of the children. */ 559 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 560 scp->pcmintr(scp->pcmintr_arg); 561 hisr &= ~(HISR_VC0 | HISR_VC1); 562 } 563 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 564 scp->midiintr(scp->midiintr_arg); 565 hisr &= ~HISR_MIDI; 566 } 567 568 /* Throw an eoi. */ 569 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 570 } 571 572 static int 573 csa_initialize(sc_p scp) 574 { 575 int i; 576 u_int32_t acsts, acisv; 577 csa_res *resp; 578 579 resp = &scp->res; 580 581 /* 582 * First, blast the clock control register to zero so that the PLL starts 583 * out in a known state, and blast the master serial port control register 584 * to zero so that the serial ports also start out in a known state. 585 */ 586 csa_writeio(resp, BA0_CLKCR1, 0); 587 csa_writeio(resp, BA0_SERMC1, 0); 588 589 /* 590 * If we are in AC97 mode, then we must set the part to a host controlled 591 * AC-link. Otherwise, we won't be able to bring up the link. 592 */ 593 #if 1 594 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 595 #else 596 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 597 #endif /* 1 */ 598 599 /* 600 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 601 * spec) and then drive it high. This is done for non AC97 modes since 602 * there might be logic external to the CS461x that uses the ARST# line 603 * for a reset. 604 */ 605 csa_writeio(resp, BA0_ACCTL, 1); 606 DELAY(50); 607 csa_writeio(resp, BA0_ACCTL, 0); 608 DELAY(50); 609 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 610 611 /* 612 * The first thing we do here is to enable sync generation. As soon 613 * as we start receiving bit clock, we'll start producing the SYNC 614 * signal. 615 */ 616 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 617 618 /* 619 * Now wait for a short while to allow the AC97 part to start 620 * generating bit clock (so we don't try to start the PLL without an 621 * input clock). 622 */ 623 DELAY(50000); 624 625 /* 626 * Set the serial port timing configuration, so that 627 * the clock control circuit gets its clock from the correct place. 628 */ 629 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 630 DELAY(700000); 631 632 /* 633 * Write the selected clock control setup to the hardware. Do not turn on 634 * SWCE yet (if requested), so that the devices clocked by the output of 635 * PLL are not clocked until the PLL is stable. 636 */ 637 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 638 csa_writeio(resp, BA0_PLLM, 0x3a); 639 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 640 641 /* 642 * Power up the PLL. 643 */ 644 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 645 646 /* 647 * Wait until the PLL has stabilized. 648 */ 649 DELAY(5000); 650 651 /* 652 * Turn on clocking of the core so that we can setup the serial ports. 653 */ 654 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 655 656 /* 657 * Fill the serial port FIFOs with silence. 658 */ 659 csa_clearserialfifos(resp); 660 661 /* 662 * Set the serial port FIFO pointer to the first sample in the FIFO. 663 */ 664 #ifdef notdef 665 csa_writeio(resp, BA0_SERBSP, 0); 666 #endif /* notdef */ 667 668 /* 669 * Write the serial port configuration to the part. The master 670 * enable bit is not set until all other values have been written. 671 */ 672 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 673 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 674 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 675 676 /* 677 * Wait for the codec ready signal from the AC97 codec. 678 */ 679 acsts = 0; 680 for (i = 0 ; i < 1000 ; i++) { 681 /* 682 * First, lets wait a short while to let things settle out a bit, 683 * and to prevent retrying the read too quickly. 684 */ 685 DELAY(125); 686 687 /* 688 * Read the AC97 status register to see if we've seen a CODEC READY 689 * signal from the AC97 codec. 690 */ 691 acsts = csa_readio(resp, BA0_ACSTS); 692 if ((acsts & ACSTS_CRDY) != 0) 693 break; 694 } 695 696 /* 697 * Make sure we sampled CODEC READY. 698 */ 699 if ((acsts & ACSTS_CRDY) == 0) 700 return (ENXIO); 701 702 /* 703 * Assert the vaid frame signal so that we can start sending commands 704 * to the AC97 codec. 705 */ 706 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 707 708 /* 709 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 710 * the codec is pumping ADC data across the AC-link. 711 */ 712 acisv = 0; 713 for (i = 0 ; i < 1000 ; i++) { 714 /* 715 * First, lets wait a short while to let things settle out a bit, 716 * and to prevent retrying the read too quickly. 717 */ 718 #ifdef notdef 719 DELAY(10000000L); /* clw */ 720 #else 721 DELAY(1000); 722 #endif /* notdef */ 723 /* 724 * Read the input slot valid register and see if input slots 3 and 725 * 4 are valid yet. 726 */ 727 acisv = csa_readio(resp, BA0_ACISV); 728 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 729 break; 730 } 731 /* 732 * Make sure we sampled valid input slots 3 and 4. If not, then return 733 * an error. 734 */ 735 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 736 return (ENXIO); 737 738 /* 739 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 740 * commense the transfer of digital audio data to the AC97 codec. 741 */ 742 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 743 744 /* 745 * Power down the DAC and ADC. We will power them up (if) when we need 746 * them. 747 */ 748 #ifdef notdef 749 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 750 #endif /* notdef */ 751 752 /* 753 * Turn off the Processor by turning off the software clock enable flag in 754 * the clock control register. 755 */ 756 #ifdef notdef 757 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 758 csa_writeio(resp, BA0_CLKCR1, clkcr1); 759 #endif /* notdef */ 760 761 /* 762 * Enable interrupts on the part. 763 */ 764 #if 0 765 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 766 #endif /* notdef */ 767 768 return (0); 769 } 770 771 void 772 csa_clearserialfifos(csa_res *resp) 773 { 774 int i, j, pwr; 775 u_int8_t clkcr1, serbst; 776 777 /* 778 * See if the devices are powered down. If so, we must power them up first 779 * or they will not respond. 780 */ 781 pwr = 1; 782 clkcr1 = csa_readio(resp, BA0_CLKCR1); 783 if ((clkcr1 & CLKCR1_SWCE) == 0) { 784 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 785 pwr = 0; 786 } 787 788 /* 789 * We want to clear out the serial port FIFOs so we don't end up playing 790 * whatever random garbage happens to be in them. We fill the sample FIFOs 791 * with zero (silence). 792 */ 793 csa_writeio(resp, BA0_SERBWP, 0); 794 795 /* Fill all 256 sample FIFO locations. */ 796 serbst = 0; 797 for (i = 0 ; i < 256 ; i++) { 798 /* Make sure the previous FIFO write operation has completed. */ 799 for (j = 0 ; j < 5 ; j++) { 800 DELAY(100); 801 serbst = csa_readio(resp, BA0_SERBST); 802 if ((serbst & SERBST_WBSY) == 0) 803 break; 804 } 805 if ((serbst & SERBST_WBSY) != 0) { 806 if (!pwr) 807 csa_writeio(resp, BA0_CLKCR1, clkcr1); 808 } 809 /* Write the serial port FIFO index. */ 810 csa_writeio(resp, BA0_SERBAD, i); 811 /* Tell the serial port to load the new value into the FIFO location. */ 812 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 813 } 814 /* 815 * Now, if we powered up the devices, then power them back down again. 816 * This is kinda ugly, but should never happen. 817 */ 818 if (!pwr) 819 csa_writeio(resp, BA0_CLKCR1, clkcr1); 820 } 821 822 void 823 csa_resetdsp(csa_res *resp) 824 { 825 int i; 826 827 /* 828 * Write the reset bit of the SP control register. 829 */ 830 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 831 832 /* 833 * Write the control register. 834 */ 835 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 836 837 /* 838 * Clear the trap registers. 839 */ 840 for (i = 0 ; i < 8 ; i++) { 841 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 842 csa_writemem(resp, BA1_TWPR, 0xffff); 843 } 844 csa_writemem(resp, BA1_DREG, 0); 845 846 /* 847 * Set the frame timer to reflect the number of cycles per frame. 848 */ 849 csa_writemem(resp, BA1_FRMT, 0xadf); 850 } 851 852 static int 853 csa_downloadimage(csa_res *resp) 854 { 855 int ret; 856 u_long ul, offset; 857 858 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 859 /* 860 * DMA this block from host memory to the appropriate 861 * memory on the CSDevice. 862 */ 863 ret = csa_transferimage(resp, 864 cs461x_firmware.BA1Array + offset, 865 cs461x_firmware.MemoryStat[ul].ulDestAddr, 866 cs461x_firmware.MemoryStat[ul].ulSourceSize); 867 if (ret) 868 return (ret); 869 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2; 870 } 871 return (0); 872 } 873 874 static int 875 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len) 876 { 877 u_long ul; 878 879 /* 880 * We do not allow DMAs from host memory to host memory (although the DMA 881 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 882 * in size (because that DMA can not do that). Return an error if either 883 * of these conditions exist. 884 */ 885 if ((len & 0x3) != 0) 886 return (EINVAL); 887 888 /* Check the destination address that it is a multiple of 4 */ 889 if ((dest & 0x3) != 0) 890 return (EINVAL); 891 892 /* Write the buffer out. */ 893 for (ul = 0 ; ul < len ; ul += 4) 894 csa_writemem(resp, dest + ul, src[ul >> 2]); 895 return (0); 896 } 897 898 int 899 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 900 { 901 int i; 902 u_int32_t acctl, acsts; 903 904 /* 905 * Make sure that there is not data sitting around from a previous 906 * uncompleted access. ACSDA = Status Data Register = 47Ch 907 */ 908 csa_readio(resp, BA0_ACSDA); 909 910 /* 911 * Setup the AC97 control registers on the CS461x to send the 912 * appropriate command to the AC97 to perform the read. 913 * ACCAD = Command Address Register = 46Ch 914 * ACCDA = Command Data Register = 470h 915 * ACCTL = Control Register = 460h 916 * set DCV - will clear when process completed 917 * set CRW - Read command 918 * set VFRM - valid frame enabled 919 * set ESYN - ASYNC generation enabled 920 * set RSTN - ARST# inactive, AC97 codec not reset 921 */ 922 923 /* 924 * Get the actual AC97 register from the offset 925 */ 926 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 927 csa_writeio(resp, BA0_ACCDA, 0); 928 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 929 930 /* 931 * Wait for the read to occur. 932 */ 933 acctl = 0; 934 for (i = 0 ; i < 10 ; i++) { 935 /* 936 * First, we want to wait for a short time. 937 */ 938 DELAY(25); 939 940 /* 941 * Now, check to see if the read has completed. 942 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 943 */ 944 acctl = csa_readio(resp, BA0_ACCTL); 945 if ((acctl & ACCTL_DCV) == 0) 946 break; 947 } 948 949 /* 950 * Make sure the read completed. 951 */ 952 if ((acctl & ACCTL_DCV) != 0) 953 return (EAGAIN); 954 955 /* 956 * Wait for the valid status bit to go active. 957 */ 958 acsts = 0; 959 for (i = 0 ; i < 10 ; i++) { 960 /* 961 * Read the AC97 status register. 962 * ACSTS = Status Register = 464h 963 */ 964 acsts = csa_readio(resp, BA0_ACSTS); 965 /* 966 * See if we have valid status. 967 * VSTS - Valid Status 968 */ 969 if ((acsts & ACSTS_VSTS) != 0) 970 break; 971 /* 972 * Wait for a short while. 973 */ 974 DELAY(25); 975 } 976 977 /* 978 * Make sure we got valid status. 979 */ 980 if ((acsts & ACSTS_VSTS) == 0) 981 return (EAGAIN); 982 983 /* 984 * Read the data returned from the AC97 register. 985 * ACSDA = Status Data Register = 474h 986 */ 987 *data = csa_readio(resp, BA0_ACSDA); 988 989 return (0); 990 } 991 992 int 993 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 994 { 995 int i; 996 u_int32_t acctl; 997 998 /* 999 * Setup the AC97 control registers on the CS461x to send the 1000 * appropriate command to the AC97 to perform the write. 1001 * ACCAD = Command Address Register = 46Ch 1002 * ACCDA = Command Data Register = 470h 1003 * ACCTL = Control Register = 460h 1004 * set DCV - will clear when process completed 1005 * set VFRM - valid frame enabled 1006 * set ESYN - ASYNC generation enabled 1007 * set RSTN - ARST# inactive, AC97 codec not reset 1008 */ 1009 1010 /* 1011 * Get the actual AC97 register from the offset 1012 */ 1013 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 1014 csa_writeio(resp, BA0_ACCDA, data); 1015 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1016 1017 /* 1018 * Wait for the write to occur. 1019 */ 1020 acctl = 0; 1021 for (i = 0 ; i < 10 ; i++) { 1022 /* 1023 * First, we want to wait for a short time. 1024 */ 1025 DELAY(25); 1026 1027 /* 1028 * Now, check to see if the read has completed. 1029 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1030 */ 1031 acctl = csa_readio(resp, BA0_ACCTL); 1032 if ((acctl & ACCTL_DCV) == 0) 1033 break; 1034 } 1035 1036 /* 1037 * Make sure the write completed. 1038 */ 1039 if ((acctl & ACCTL_DCV) != 0) 1040 return (EAGAIN); 1041 1042 return (0); 1043 } 1044 1045 u_int32_t 1046 csa_readio(csa_res *resp, u_long offset) 1047 { 1048 u_int32_t ul; 1049 1050 if (offset < BA0_AC97_RESET) 1051 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1052 else { 1053 if (csa_readcodec(resp, offset, &ul)) 1054 ul = 0; 1055 return (ul); 1056 } 1057 } 1058 1059 void 1060 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1061 { 1062 if (offset < BA0_AC97_RESET) 1063 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1064 else 1065 csa_writecodec(resp, offset, data); 1066 } 1067 1068 u_int32_t 1069 csa_readmem(csa_res *resp, u_long offset) 1070 { 1071 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1072 } 1073 1074 void 1075 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1076 { 1077 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1078 } 1079 1080 static device_method_t csa_methods[] = { 1081 /* Device interface */ 1082 DEVMETHOD(device_probe, csa_probe), 1083 DEVMETHOD(device_attach, csa_attach), 1084 DEVMETHOD(device_detach, csa_detach), 1085 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1086 DEVMETHOD(device_suspend, bus_generic_suspend), 1087 DEVMETHOD(device_resume, csa_resume), 1088 1089 /* Bus interface */ 1090 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1091 DEVMETHOD(bus_release_resource, csa_release_resource), 1092 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1093 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1094 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1095 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1096 1097 DEVMETHOD_END 1098 }; 1099 1100 static driver_t csa_driver = { 1101 "csa", 1102 csa_methods, 1103 sizeof(struct csa_softc), 1104 }; 1105 1106 /* 1107 * csa can be attached to a pci bus. 1108 */ 1109 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0); 1110 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1111 MODULE_VERSION(snd_csa, 1); 1112