1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1999 Seigo Tanimura 5 * All rights reserved. 6 * 7 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in 8 * cwcealdr1.zip, the sample sources by Crystal Semiconductor. 9 * Copyright (c) 1996-1998 Crystal Semiconductor Corp. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <machine/resource.h> 40 #include <machine/bus.h> 41 #include <sys/rman.h> 42 43 #ifdef HAVE_KERNEL_OPTION_HEADERS 44 #include "opt_snd.h" 45 #endif 46 47 #include <dev/sound/pcm/sound.h> 48 #include <dev/sound/chip.h> 49 #include <dev/sound/pci/csareg.h> 50 #include <dev/sound/pci/csavar.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 55 #include <dev/sound/pci/cs461x_dsp.h> 56 57 SND_DECLARE_FILE("$FreeBSD$"); 58 59 /* This is the pci device id. */ 60 #define CS4610_PCI_ID 0x60011013 61 #define CS4614_PCI_ID 0x60031013 62 #define CS4615_PCI_ID 0x60041013 63 64 /* Here is the parameter structure per a device. */ 65 struct csa_softc { 66 device_t dev; /* device */ 67 csa_res res; /* resources */ 68 69 device_t pcm; /* pcm device */ 70 driver_intr_t* pcmintr; /* pcm intr */ 71 void *pcmintr_arg; /* pcm intr arg */ 72 device_t midi; /* midi device */ 73 driver_intr_t* midiintr; /* midi intr */ 74 void *midiintr_arg; /* midi intr arg */ 75 void *ih; /* cookie */ 76 77 struct csa_card *card; 78 struct csa_bridgeinfo binfo; /* The state of this bridge. */ 79 }; 80 81 typedef struct csa_softc *sc_p; 82 83 static int csa_probe(device_t dev); 84 static int csa_attach(device_t dev); 85 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 86 rman_res_t start, rman_res_t end, 87 rman_res_t count, u_int flags); 88 static int csa_release_resource(device_t bus, device_t child, int type, int rid, 89 struct resource *r); 90 static int csa_setup_intr(device_t bus, device_t child, 91 struct resource *irq, int flags, 92 driver_filter_t *filter, 93 driver_intr_t *intr, void *arg, void **cookiep); 94 static int csa_teardown_intr(device_t bus, device_t child, 95 struct resource *irq, void *cookie); 96 static driver_intr_t csa_intr; 97 static int csa_initialize(sc_p scp); 98 static int csa_downloadimage(csa_res *resp); 99 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len); 100 101 static void 102 amp_none(void) 103 { 104 } 105 106 static void 107 amp_voyetra(void) 108 { 109 } 110 111 static int 112 clkrun_hack(int run) 113 { 114 #ifdef __i386__ 115 devclass_t pci_devclass; 116 device_t *pci_devices, *pci_children, *busp, *childp; 117 int pci_count = 0, pci_childcount = 0; 118 int i, j, port; 119 u_int16_t control; 120 bus_space_tag_t btag; 121 122 if ((pci_devclass = devclass_find("pci")) == NULL) { 123 return ENXIO; 124 } 125 126 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 127 128 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 129 pci_childcount = 0; 130 if (device_get_children(*busp, &pci_children, &pci_childcount)) 131 continue; 132 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 133 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) { 134 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10; 135 /* XXX */ 136 btag = X86_BUS_SPACE_IO; 137 138 control = bus_space_read_2(btag, 0x0, port); 139 control &= ~0x2000; 140 control |= run? 0 : 0x2000; 141 bus_space_write_2(btag, 0x0, port, control); 142 free(pci_devices, M_TEMP); 143 free(pci_children, M_TEMP); 144 return 0; 145 } 146 } 147 free(pci_children, M_TEMP); 148 } 149 150 free(pci_devices, M_TEMP); 151 return ENXIO; 152 #else 153 return 0; 154 #endif 155 } 156 157 static struct csa_card cards_4610[] = { 158 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0}, 159 }; 160 161 static struct csa_card cards_4614[] = { 162 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0}, 163 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1}, 164 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0}, 165 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 166 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0}, 167 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0}, 168 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0}, 169 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0}, 170 {0x153b, 0x1136, "Terratec SiXPack 5.1+", NULL, NULL, NULL, 0}, 171 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0}, 172 }; 173 174 static struct csa_card cards_4615[] = { 175 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0}, 176 }; 177 178 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0}; 179 180 struct card_type { 181 u_int32_t devid; 182 char *name; 183 struct csa_card *cards; 184 }; 185 186 static struct card_type cards[] = { 187 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610}, 188 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614}, 189 {CS4615_PCI_ID, "CS4615", cards_4615}, 190 {0, NULL, NULL}, 191 }; 192 193 static struct card_type * 194 csa_findcard(device_t dev) 195 { 196 int i; 197 198 i = 0; 199 while (cards[i].devid != 0) { 200 if (pci_get_devid(dev) == cards[i].devid) 201 return &cards[i]; 202 i++; 203 } 204 return NULL; 205 } 206 207 struct csa_card * 208 csa_findsubcard(device_t dev) 209 { 210 int i; 211 struct card_type *card; 212 struct csa_card *subcard; 213 214 card = csa_findcard(dev); 215 if (card == NULL) 216 return &nocard; 217 subcard = card->cards; 218 i = 0; 219 while (subcard[i].subvendor != 0) { 220 if (pci_get_subvendor(dev) == subcard[i].subvendor 221 && pci_get_subdevice(dev) == subcard[i].subdevice) { 222 return &subcard[i]; 223 } 224 i++; 225 } 226 return &subcard[i]; 227 } 228 229 static int 230 csa_probe(device_t dev) 231 { 232 struct card_type *card; 233 234 card = csa_findcard(dev); 235 if (card) { 236 device_set_desc(dev, card->name); 237 return BUS_PROBE_DEFAULT; 238 } 239 return ENXIO; 240 } 241 242 static int 243 csa_attach(device_t dev) 244 { 245 sc_p scp; 246 csa_res *resp; 247 struct sndcard_func *func; 248 int error = ENXIO; 249 250 scp = device_get_softc(dev); 251 252 /* Fill in the softc. */ 253 bzero(scp, sizeof(*scp)); 254 scp->dev = dev; 255 256 pci_enable_busmaster(dev); 257 258 /* Allocate the resources. */ 259 resp = &scp->res; 260 scp->card = csa_findsubcard(dev); 261 scp->binfo.card = scp->card; 262 printf("csa: card is %s\n", scp->card->name); 263 resp->io_rid = PCIR_BAR(0); 264 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 265 &resp->io_rid, RF_ACTIVE); 266 if (resp->io == NULL) 267 return (ENXIO); 268 resp->mem_rid = PCIR_BAR(1); 269 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 270 &resp->mem_rid, RF_ACTIVE); 271 if (resp->mem == NULL) 272 goto err_io; 273 resp->irq_rid = 0; 274 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 275 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE); 276 if (resp->irq == NULL) 277 goto err_mem; 278 279 /* Enable interrupt. */ 280 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih)) 281 goto err_intr; 282 #if 0 283 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 284 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 285 #endif 286 287 /* Initialize the chip. */ 288 if (csa_initialize(scp)) 289 goto err_teardown; 290 291 /* Reset the Processor. */ 292 csa_resetdsp(resp); 293 294 /* Download the Processor Image to the processor. */ 295 if (csa_downloadimage(resp)) 296 goto err_teardown; 297 298 /* Attach the children. */ 299 300 /* PCM Audio */ 301 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 302 if (func == NULL) { 303 error = ENOMEM; 304 goto err_teardown; 305 } 306 func->varinfo = &scp->binfo; 307 func->func = SCF_PCM; 308 scp->pcm = device_add_child(dev, "pcm", -1); 309 device_set_ivars(scp->pcm, func); 310 311 /* Midi Interface */ 312 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO); 313 if (func == NULL) { 314 error = ENOMEM; 315 goto err_teardown; 316 } 317 func->varinfo = &scp->binfo; 318 func->func = SCF_MIDI; 319 scp->midi = device_add_child(dev, "midi", -1); 320 device_set_ivars(scp->midi, func); 321 322 bus_generic_attach(dev); 323 324 return (0); 325 326 err_teardown: 327 bus_teardown_intr(dev, resp->irq, scp->ih); 328 err_intr: 329 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 330 err_mem: 331 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 332 err_io: 333 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 334 return (error); 335 } 336 337 static int 338 csa_detach(device_t dev) 339 { 340 csa_res *resp; 341 sc_p scp; 342 struct sndcard_func *func; 343 int err; 344 345 scp = device_get_softc(dev); 346 resp = &scp->res; 347 348 if (scp->midi != NULL) { 349 func = device_get_ivars(scp->midi); 350 err = device_delete_child(dev, scp->midi); 351 if (err != 0) 352 return err; 353 if (func != NULL) 354 free(func, M_DEVBUF); 355 scp->midi = NULL; 356 } 357 358 if (scp->pcm != NULL) { 359 func = device_get_ivars(scp->pcm); 360 err = device_delete_child(dev, scp->pcm); 361 if (err != 0) 362 return err; 363 if (func != NULL) 364 free(func, M_DEVBUF); 365 scp->pcm = NULL; 366 } 367 368 bus_teardown_intr(dev, resp->irq, scp->ih); 369 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq); 370 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem); 371 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io); 372 373 return bus_generic_detach(dev); 374 } 375 376 static int 377 csa_resume(device_t dev) 378 { 379 csa_res *resp; 380 sc_p scp; 381 382 scp = device_get_softc(dev); 383 resp = &scp->res; 384 385 /* Initialize the chip. */ 386 if (csa_initialize(scp)) 387 return (ENXIO); 388 389 /* Reset the Processor. */ 390 csa_resetdsp(resp); 391 392 /* Download the Processor Image to the processor. */ 393 if (csa_downloadimage(resp)) 394 return (ENXIO); 395 396 return (bus_generic_resume(dev)); 397 } 398 399 static struct resource * 400 csa_alloc_resource(device_t bus, device_t child, int type, int *rid, 401 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 402 { 403 sc_p scp; 404 csa_res *resp; 405 struct resource *res; 406 407 scp = device_get_softc(bus); 408 resp = &scp->res; 409 switch (type) { 410 case SYS_RES_IRQ: 411 if (*rid != 0) 412 return (NULL); 413 res = resp->irq; 414 break; 415 case SYS_RES_MEMORY: 416 switch (*rid) { 417 case PCIR_BAR(0): 418 res = resp->io; 419 break; 420 case PCIR_BAR(1): 421 res = resp->mem; 422 break; 423 default: 424 return (NULL); 425 } 426 break; 427 default: 428 return (NULL); 429 } 430 431 return res; 432 } 433 434 static int 435 csa_release_resource(device_t bus, device_t child, int type, int rid, 436 struct resource *r) 437 { 438 return (0); 439 } 440 441 /* 442 * The following three functions deal with interrupt handling. 443 * An interrupt is primarily handled by the bridge driver. 444 * The bridge driver then determines the child devices to pass 445 * the interrupt. Certain information of the device can be read 446 * only once(eg the value of HISR). The bridge driver is responsible 447 * to pass such the information to the children. 448 */ 449 450 static int 451 csa_setup_intr(device_t bus, device_t child, 452 struct resource *irq, int flags, 453 driver_filter_t *filter, 454 driver_intr_t *intr, void *arg, void **cookiep) 455 { 456 sc_p scp; 457 csa_res *resp; 458 struct sndcard_func *func; 459 460 if (filter != NULL) { 461 printf("ata-csa.c: we cannot use a filter here\n"); 462 return (EINVAL); 463 } 464 scp = device_get_softc(bus); 465 resp = &scp->res; 466 467 /* 468 * Look at the function code of the child to determine 469 * the appropriate handler for it. 470 */ 471 func = device_get_ivars(child); 472 if (func == NULL || irq != resp->irq) 473 return (EINVAL); 474 475 switch (func->func) { 476 case SCF_PCM: 477 scp->pcmintr = intr; 478 scp->pcmintr_arg = arg; 479 break; 480 481 case SCF_MIDI: 482 scp->midiintr = intr; 483 scp->midiintr_arg = arg; 484 break; 485 486 default: 487 return (EINVAL); 488 } 489 *cookiep = scp; 490 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0) 491 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 492 493 return (0); 494 } 495 496 static int 497 csa_teardown_intr(device_t bus, device_t child, 498 struct resource *irq, void *cookie) 499 { 500 sc_p scp; 501 csa_res *resp; 502 struct sndcard_func *func; 503 504 scp = device_get_softc(bus); 505 resp = &scp->res; 506 507 /* 508 * Look at the function code of the child to determine 509 * the appropriate handler for it. 510 */ 511 func = device_get_ivars(child); 512 if (func == NULL || irq != resp->irq || cookie != scp) 513 return (EINVAL); 514 515 switch (func->func) { 516 case SCF_PCM: 517 scp->pcmintr = NULL; 518 scp->pcmintr_arg = NULL; 519 break; 520 521 case SCF_MIDI: 522 scp->midiintr = NULL; 523 scp->midiintr_arg = NULL; 524 break; 525 526 default: 527 return (EINVAL); 528 } 529 530 return (0); 531 } 532 533 /* The interrupt handler */ 534 static void 535 csa_intr(void *arg) 536 { 537 sc_p scp = arg; 538 csa_res *resp; 539 u_int32_t hisr; 540 541 resp = &scp->res; 542 543 /* Is this interrupt for us? */ 544 hisr = csa_readio(resp, BA0_HISR); 545 if ((hisr & 0x7fffffff) == 0) { 546 /* Throw an eoi. */ 547 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 548 return; 549 } 550 551 /* 552 * Pass the value of HISR via struct csa_bridgeinfo. 553 * The children get access through their ivars. 554 */ 555 scp->binfo.hisr = hisr; 556 557 /* Invoke the handlers of the children. */ 558 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) { 559 scp->pcmintr(scp->pcmintr_arg); 560 hisr &= ~(HISR_VC0 | HISR_VC1); 561 } 562 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) { 563 scp->midiintr(scp->midiintr_arg); 564 hisr &= ~HISR_MIDI; 565 } 566 567 /* Throw an eoi. */ 568 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 569 } 570 571 static int 572 csa_initialize(sc_p scp) 573 { 574 int i; 575 u_int32_t acsts, acisv; 576 csa_res *resp; 577 578 resp = &scp->res; 579 580 /* 581 * First, blast the clock control register to zero so that the PLL starts 582 * out in a known state, and blast the master serial port control register 583 * to zero so that the serial ports also start out in a known state. 584 */ 585 csa_writeio(resp, BA0_CLKCR1, 0); 586 csa_writeio(resp, BA0_SERMC1, 0); 587 588 /* 589 * If we are in AC97 mode, then we must set the part to a host controlled 590 * AC-link. Otherwise, we won't be able to bring up the link. 591 */ 592 #if 1 593 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */ 594 #else 595 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */ 596 #endif /* 1 */ 597 598 /* 599 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 600 * spec) and then drive it high. This is done for non AC97 modes since 601 * there might be logic external to the CS461x that uses the ARST# line 602 * for a reset. 603 */ 604 csa_writeio(resp, BA0_ACCTL, 1); 605 DELAY(50); 606 csa_writeio(resp, BA0_ACCTL, 0); 607 DELAY(50); 608 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN); 609 610 /* 611 * The first thing we do here is to enable sync generation. As soon 612 * as we start receiving bit clock, we'll start producing the SYNC 613 * signal. 614 */ 615 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 616 617 /* 618 * Now wait for a short while to allow the AC97 part to start 619 * generating bit clock (so we don't try to start the PLL without an 620 * input clock). 621 */ 622 DELAY(50000); 623 624 /* 625 * Set the serial port timing configuration, so that 626 * the clock control circuit gets its clock from the correct place. 627 */ 628 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97); 629 DELAY(700000); 630 631 /* 632 * Write the selected clock control setup to the hardware. Do not turn on 633 * SWCE yet (if requested), so that the devices clocked by the output of 634 * PLL are not clocked until the PLL is stable. 635 */ 636 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 637 csa_writeio(resp, BA0_PLLM, 0x3a); 638 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8); 639 640 /* 641 * Power up the PLL. 642 */ 643 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP); 644 645 /* 646 * Wait until the PLL has stabilized. 647 */ 648 DELAY(5000); 649 650 /* 651 * Turn on clocking of the core so that we can setup the serial ports. 652 */ 653 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE); 654 655 /* 656 * Fill the serial port FIFOs with silence. 657 */ 658 csa_clearserialfifos(resp); 659 660 /* 661 * Set the serial port FIFO pointer to the first sample in the FIFO. 662 */ 663 #ifdef notdef 664 csa_writeio(resp, BA0_SERBSP, 0); 665 #endif /* notdef */ 666 667 /* 668 * Write the serial port configuration to the part. The master 669 * enable bit is not set until all other values have been written. 670 */ 671 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 672 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 673 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 674 675 /* 676 * Wait for the codec ready signal from the AC97 codec. 677 */ 678 acsts = 0; 679 for (i = 0 ; i < 1000 ; i++) { 680 /* 681 * First, lets wait a short while to let things settle out a bit, 682 * and to prevent retrying the read too quickly. 683 */ 684 DELAY(125); 685 686 /* 687 * Read the AC97 status register to see if we've seen a CODEC READY 688 * signal from the AC97 codec. 689 */ 690 acsts = csa_readio(resp, BA0_ACSTS); 691 if ((acsts & ACSTS_CRDY) != 0) 692 break; 693 } 694 695 /* 696 * Make sure we sampled CODEC READY. 697 */ 698 if ((acsts & ACSTS_CRDY) == 0) 699 return (ENXIO); 700 701 /* 702 * Assert the vaid frame signal so that we can start sending commands 703 * to the AC97 codec. 704 */ 705 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 706 707 /* 708 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 709 * the codec is pumping ADC data across the AC-link. 710 */ 711 acisv = 0; 712 for (i = 0 ; i < 2000 ; i++) { 713 /* 714 * First, lets wait a short while to let things settle out a bit, 715 * and to prevent retrying the read too quickly. 716 */ 717 #ifdef notdef 718 DELAY(10000000L); /* clw */ 719 #else 720 DELAY(1000); 721 #endif /* notdef */ 722 /* 723 * Read the input slot valid register and see if input slots 3 and 724 * 4 are valid yet. 725 */ 726 acisv = csa_readio(resp, BA0_ACISV); 727 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 728 break; 729 } 730 /* 731 * Make sure we sampled valid input slots 3 and 4. If not, then return 732 * an error. 733 */ 734 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4)) 735 return (ENXIO); 736 737 /* 738 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 739 * commense the transfer of digital audio data to the AC97 codec. 740 */ 741 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 742 743 /* 744 * Power down the DAC and ADC. We will power them up (if) when we need 745 * them. 746 */ 747 #ifdef notdef 748 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300); 749 #endif /* notdef */ 750 751 /* 752 * Turn off the Processor by turning off the software clock enable flag in 753 * the clock control register. 754 */ 755 #ifdef notdef 756 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE; 757 csa_writeio(resp, BA0_CLKCR1, clkcr1); 758 #endif /* notdef */ 759 760 /* 761 * Enable interrupts on the part. 762 */ 763 #if 0 764 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM); 765 #endif /* notdef */ 766 767 return (0); 768 } 769 770 void 771 csa_clearserialfifos(csa_res *resp) 772 { 773 int i, j, pwr; 774 u_int8_t clkcr1, serbst; 775 776 /* 777 * See if the devices are powered down. If so, we must power them up first 778 * or they will not respond. 779 */ 780 pwr = 1; 781 clkcr1 = csa_readio(resp, BA0_CLKCR1); 782 if ((clkcr1 & CLKCR1_SWCE) == 0) { 783 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE); 784 pwr = 0; 785 } 786 787 /* 788 * We want to clear out the serial port FIFOs so we don't end up playing 789 * whatever random garbage happens to be in them. We fill the sample FIFOs 790 * with zero (silence). 791 */ 792 csa_writeio(resp, BA0_SERBWP, 0); 793 794 /* Fill all 256 sample FIFO locations. */ 795 serbst = 0; 796 for (i = 0 ; i < 256 ; i++) { 797 /* Make sure the previous FIFO write operation has completed. */ 798 for (j = 0 ; j < 5 ; j++) { 799 DELAY(100); 800 serbst = csa_readio(resp, BA0_SERBST); 801 if ((serbst & SERBST_WBSY) == 0) 802 break; 803 } 804 if ((serbst & SERBST_WBSY) != 0) { 805 if (!pwr) 806 csa_writeio(resp, BA0_CLKCR1, clkcr1); 807 } 808 /* Write the serial port FIFO index. */ 809 csa_writeio(resp, BA0_SERBAD, i); 810 /* Tell the serial port to load the new value into the FIFO location. */ 811 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC); 812 } 813 /* 814 * Now, if we powered up the devices, then power them back down again. 815 * This is kinda ugly, but should never happen. 816 */ 817 if (!pwr) 818 csa_writeio(resp, BA0_CLKCR1, clkcr1); 819 } 820 821 void 822 csa_resetdsp(csa_res *resp) 823 { 824 int i; 825 826 /* 827 * Write the reset bit of the SP control register. 828 */ 829 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP); 830 831 /* 832 * Write the control register. 833 */ 834 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN); 835 836 /* 837 * Clear the trap registers. 838 */ 839 for (i = 0 ; i < 8 ; i++) { 840 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i); 841 csa_writemem(resp, BA1_TWPR, 0xffff); 842 } 843 csa_writemem(resp, BA1_DREG, 0); 844 845 /* 846 * Set the frame timer to reflect the number of cycles per frame. 847 */ 848 csa_writemem(resp, BA1_FRMT, 0xadf); 849 } 850 851 static int 852 csa_downloadimage(csa_res *resp) 853 { 854 int ret; 855 u_long ul, offset; 856 857 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) { 858 /* 859 * DMA this block from host memory to the appropriate 860 * memory on the CSDevice. 861 */ 862 ret = csa_transferimage(resp, 863 cs461x_firmware.BA1Array + offset, 864 cs461x_firmware.MemoryStat[ul].ulDestAddr, 865 cs461x_firmware.MemoryStat[ul].ulSourceSize); 866 if (ret) 867 return (ret); 868 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2; 869 } 870 return (0); 871 } 872 873 static int 874 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len) 875 { 876 u_long ul; 877 878 /* 879 * We do not allow DMAs from host memory to host memory (although the DMA 880 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes 881 * in size (because that DMA can not do that). Return an error if either 882 * of these conditions exist. 883 */ 884 if ((len & 0x3) != 0) 885 return (EINVAL); 886 887 /* Check the destination address that it is a multiple of 4 */ 888 if ((dest & 0x3) != 0) 889 return (EINVAL); 890 891 /* Write the buffer out. */ 892 for (ul = 0 ; ul < len ; ul += 4) 893 csa_writemem(resp, dest + ul, src[ul >> 2]); 894 return (0); 895 } 896 897 int 898 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data) 899 { 900 int i; 901 u_int32_t acctl, acsts; 902 903 /* 904 * Make sure that there is not data sitting around from a previous 905 * uncompleted access. ACSDA = Status Data Register = 47Ch 906 */ 907 csa_readio(resp, BA0_ACSDA); 908 909 /* 910 * Setup the AC97 control registers on the CS461x to send the 911 * appropriate command to the AC97 to perform the read. 912 * ACCAD = Command Address Register = 46Ch 913 * ACCDA = Command Data Register = 470h 914 * ACCTL = Control Register = 460h 915 * set DCV - will clear when process completed 916 * set CRW - Read command 917 * set VFRM - valid frame enabled 918 * set ESYN - ASYNC generation enabled 919 * set RSTN - ARST# inactive, AC97 codec not reset 920 */ 921 922 /* 923 * Get the actual AC97 register from the offset 924 */ 925 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 926 csa_writeio(resp, BA0_ACCDA, 0); 927 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 928 929 /* 930 * Wait for the read to occur. 931 */ 932 acctl = 0; 933 for (i = 0 ; i < 10 ; i++) { 934 /* 935 * First, we want to wait for a short time. 936 */ 937 DELAY(25); 938 939 /* 940 * Now, check to see if the read has completed. 941 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 942 */ 943 acctl = csa_readio(resp, BA0_ACCTL); 944 if ((acctl & ACCTL_DCV) == 0) 945 break; 946 } 947 948 /* 949 * Make sure the read completed. 950 */ 951 if ((acctl & ACCTL_DCV) != 0) 952 return (EAGAIN); 953 954 /* 955 * Wait for the valid status bit to go active. 956 */ 957 acsts = 0; 958 for (i = 0 ; i < 10 ; i++) { 959 /* 960 * Read the AC97 status register. 961 * ACSTS = Status Register = 464h 962 */ 963 acsts = csa_readio(resp, BA0_ACSTS); 964 /* 965 * See if we have valid status. 966 * VSTS - Valid Status 967 */ 968 if ((acsts & ACSTS_VSTS) != 0) 969 break; 970 /* 971 * Wait for a short while. 972 */ 973 DELAY(25); 974 } 975 976 /* 977 * Make sure we got valid status. 978 */ 979 if ((acsts & ACSTS_VSTS) == 0) 980 return (EAGAIN); 981 982 /* 983 * Read the data returned from the AC97 register. 984 * ACSDA = Status Data Register = 474h 985 */ 986 *data = csa_readio(resp, BA0_ACSDA); 987 988 return (0); 989 } 990 991 int 992 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data) 993 { 994 int i; 995 u_int32_t acctl; 996 997 /* 998 * Setup the AC97 control registers on the CS461x to send the 999 * appropriate command to the AC97 to perform the write. 1000 * ACCAD = Command Address Register = 46Ch 1001 * ACCDA = Command Data Register = 470h 1002 * ACCTL = Control Register = 460h 1003 * set DCV - will clear when process completed 1004 * set VFRM - valid frame enabled 1005 * set ESYN - ASYNC generation enabled 1006 * set RSTN - ARST# inactive, AC97 codec not reset 1007 */ 1008 1009 /* 1010 * Get the actual AC97 register from the offset 1011 */ 1012 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET); 1013 csa_writeio(resp, BA0_ACCDA, data); 1014 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1015 1016 /* 1017 * Wait for the write to occur. 1018 */ 1019 acctl = 0; 1020 for (i = 0 ; i < 10 ; i++) { 1021 /* 1022 * First, we want to wait for a short time. 1023 */ 1024 DELAY(25); 1025 1026 /* 1027 * Now, check to see if the read has completed. 1028 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 1029 */ 1030 acctl = csa_readio(resp, BA0_ACCTL); 1031 if ((acctl & ACCTL_DCV) == 0) 1032 break; 1033 } 1034 1035 /* 1036 * Make sure the write completed. 1037 */ 1038 if ((acctl & ACCTL_DCV) != 0) 1039 return (EAGAIN); 1040 1041 return (0); 1042 } 1043 1044 u_int32_t 1045 csa_readio(csa_res *resp, u_long offset) 1046 { 1047 u_int32_t ul; 1048 1049 if (offset < BA0_AC97_RESET) 1050 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff; 1051 else { 1052 if (csa_readcodec(resp, offset, &ul)) 1053 ul = 0; 1054 return (ul); 1055 } 1056 } 1057 1058 void 1059 csa_writeio(csa_res *resp, u_long offset, u_int32_t data) 1060 { 1061 if (offset < BA0_AC97_RESET) 1062 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data); 1063 else 1064 csa_writecodec(resp, offset, data); 1065 } 1066 1067 u_int32_t 1068 csa_readmem(csa_res *resp, u_long offset) 1069 { 1070 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset); 1071 } 1072 1073 void 1074 csa_writemem(csa_res *resp, u_long offset, u_int32_t data) 1075 { 1076 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data); 1077 } 1078 1079 static device_method_t csa_methods[] = { 1080 /* Device interface */ 1081 DEVMETHOD(device_probe, csa_probe), 1082 DEVMETHOD(device_attach, csa_attach), 1083 DEVMETHOD(device_detach, csa_detach), 1084 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1085 DEVMETHOD(device_suspend, bus_generic_suspend), 1086 DEVMETHOD(device_resume, csa_resume), 1087 1088 /* Bus interface */ 1089 DEVMETHOD(bus_alloc_resource, csa_alloc_resource), 1090 DEVMETHOD(bus_release_resource, csa_release_resource), 1091 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1092 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1093 DEVMETHOD(bus_setup_intr, csa_setup_intr), 1094 DEVMETHOD(bus_teardown_intr, csa_teardown_intr), 1095 1096 DEVMETHOD_END 1097 }; 1098 1099 static driver_t csa_driver = { 1100 "csa", 1101 csa_methods, 1102 sizeof(struct csa_softc), 1103 }; 1104 1105 /* 1106 * csa can be attached to a pci bus. 1107 */ 1108 DRIVER_MODULE(snd_csa, pci, csa_driver, 0, 0); 1109 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1110 MODULE_VERSION(snd_csa, 1); 1111