xref: /freebsd/sys/dev/sound/pci/cs4281.c (revision 1e413cf93298b5b97441a21d9a50fdcd0ee9945e)
1 /*-
2  * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * The order of pokes in the initiation sequence is based on Linux
27  * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
28  * woller (twoller@crystal.cirrus.com).  Shingo Watanabe (nabe@nabechan.org)
29  * contributed towards power management.
30  */
31 
32 #include <dev/sound/pcm/sound.h>
33 #include <dev/sound/pcm/ac97.h>
34 
35 #include <dev/pci/pcireg.h>
36 #include <dev/pci/pcivar.h>
37 
38 #include <dev/sound/pci/cs4281.h>
39 
40 SND_DECLARE_FILE("$FreeBSD$");
41 
42 #define CS4281_DEFAULT_BUFSZ 16384
43 
44 /* Max fifo size for full duplex is 64 */
45 #define CS4281_FIFO_SIZE 15
46 
47 /* DMA Engine Indices */
48 #define CS4281_DMA_PLAY 0
49 #define CS4281_DMA_REC  1
50 
51 /* Misc */
52 
53 #define inline __inline
54 
55 #ifndef DEB
56 #define DEB(x) /* x */
57 #endif /* DEB */
58 
59 /* ------------------------------------------------------------------------- */
60 /* Structures */
61 
62 struct sc_info;
63 
64 /* channel registers */
65 struct sc_chinfo {
66     struct sc_info *parent;
67 
68     struct snd_dbuf *buffer;
69     struct pcm_channel *channel;
70 
71     u_int32_t spd, fmt, bps, blksz;
72 
73     int dma_setup, dma_active, dma_chan;
74 };
75 
76 /* device private data */
77 struct sc_info {
78     device_t dev;
79     u_int32_t type;
80 
81     bus_space_tag_t st;
82     bus_space_handle_t sh;
83     bus_dma_tag_t parent_dmat;
84 
85     struct resource *reg, *irq, *mem;
86     int regtype, regid, irqid, memid;
87     void *ih;
88 
89     int power;
90     unsigned long bufsz;
91     struct sc_chinfo pch;
92     struct sc_chinfo rch;
93 };
94 
95 /* -------------------------------------------------------------------- */
96 /* prototypes */
97 
98 /* ADC/DAC control */
99 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
100 static void      adcdac_prog(struct sc_chinfo *ch);
101 
102 /* power management and interrupt control */
103 static void      cs4281_intr(void *);
104 static int       cs4281_power(struct sc_info *, int);
105 static int       cs4281_init(struct sc_info *);
106 
107 /* talk to the card */
108 static u_int32_t cs4281_rd(struct sc_info *, int);
109 static void 	 cs4281_wr(struct sc_info *, int, u_int32_t);
110 
111 /* misc */
112 static u_int8_t  cs4281_rate_to_rv(u_int32_t);
113 static u_int32_t cs4281_format_to_dmr(u_int32_t);
114 static u_int32_t cs4281_format_to_bps(u_int32_t);
115 
116 /* -------------------------------------------------------------------- */
117 /* formats (do not add formats without editing cs_fmt_tab)              */
118 
119 static u_int32_t cs4281_fmts[] = {
120     AFMT_U8,
121     AFMT_U8 | AFMT_STEREO,
122     AFMT_S8,
123     AFMT_S8 | AFMT_STEREO,
124     AFMT_S16_LE,
125     AFMT_S16_LE | AFMT_STEREO,
126     AFMT_U16_LE,
127     AFMT_U16_LE | AFMT_STEREO,
128     AFMT_S16_BE,
129     AFMT_S16_BE | AFMT_STEREO,
130     AFMT_U16_BE,
131     AFMT_U16_BE | AFMT_STEREO,
132     0
133 };
134 
135 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
136 
137 /* -------------------------------------------------------------------- */
138 /* Hardware */
139 
140 static inline u_int32_t
141 cs4281_rd(struct sc_info *sc, int regno)
142 {
143     return bus_space_read_4(sc->st, sc->sh, regno);
144 }
145 
146 static inline void
147 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
148 {
149     bus_space_write_4(sc->st, sc->sh, regno, data);
150     DELAY(100);
151 }
152 
153 static inline void
154 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
155 {
156     u_int32_t r;
157     r = cs4281_rd(sc, regno);
158     cs4281_wr(sc, regno, r & ~mask);
159 }
160 
161 static inline void
162 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
163 {
164     u_int32_t v;
165     v = cs4281_rd(sc, regno);
166     cs4281_wr(sc, regno, v | mask);
167 }
168 
169 static int
170 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
171 {
172     u_int32_t v;
173 
174     while(tries > 0) {
175 	DELAY(100);
176 	v = cs4281_rd(sc, regno);
177 	if ((v & mask) == mask) break;
178 	tries --;
179     }
180     return tries;
181 }
182 
183 static int
184 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
185 {
186     u_int32_t v;
187 
188     while(tries > 0) {
189 	DELAY(100);
190 	v = ~ cs4281_rd(sc, regno);
191 	if (v & mask) break;
192 	tries --;
193     }
194     return tries;
195 }
196 
197 /* ------------------------------------------------------------------------- */
198 /* Register value mapping functions */
199 
200 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
201 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
202 
203 static u_int8_t
204 cs4281_rate_to_rv(u_int32_t rate)
205 {
206     u_int32_t v;
207 
208     for (v = 0; v < CS4281_NUM_RATES; v++) {
209 	if (rate == cs4281_rates[v]) return v;
210     }
211 
212     v = 1536000 / rate;
213     if (v > 255 || v < 32) v = 5; /* default to 8k */
214     return v;
215 }
216 
217 static u_int32_t
218 cs4281_rv_to_rate(u_int8_t rv)
219 {
220     u_int32_t r;
221 
222     if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
223     r = 1536000 / rv;
224     return r;
225 }
226 
227 static inline u_int32_t
228 cs4281_format_to_dmr(u_int32_t format)
229 {
230     u_int32_t dmr = 0;
231     if (AFMT_8BIT & format)      dmr |= CS4281PCI_DMR_SIZE8;
232     if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO;
233     if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND;
234     if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
235     return dmr;
236 }
237 
238 static inline u_int32_t
239 cs4281_format_to_bps(u_int32_t format)
240 {
241     return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1);
242 }
243 
244 /* -------------------------------------------------------------------- */
245 /* ac97 codec */
246 
247 static u_int32_t
248 cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
249 {
250     struct sc_info *sc = (struct sc_info *)devinfo;
251     int codecno;
252 
253     codecno = regno >> 8;
254     regno &= 0xff;
255 
256     /* Remove old state */
257     cs4281_rd(sc, CS4281PCI_ACSDA);
258 
259     /* Fill in AC97 register value request form */
260     cs4281_wr(sc, CS4281PCI_ACCAD, regno);
261     cs4281_wr(sc, CS4281PCI_ACCDA, 0);
262     cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
263 	      CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV |
264 	      CS4281PCI_ACCTL_CRW);
265 
266     /* Wait for read to complete */
267     if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
268 	device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
269 	return 0xffffffff;
270     }
271 
272     /* Wait for valid status */
273     if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) {
274 	device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
275 	return 0xffffffff;
276     }
277 
278     return cs4281_rd(sc, CS4281PCI_ACSDA);
279 }
280 
281 static void
282 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
283 {
284     struct sc_info *sc = (struct sc_info *)devinfo;
285     int codecno;
286 
287     codecno = regno >> 8;
288     regno &= 0xff;
289 
290     cs4281_wr(sc, CS4281PCI_ACCAD, regno);
291     cs4281_wr(sc, CS4281PCI_ACCDA, data);
292     cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
293 	      CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV);
294 
295     if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
296 	device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
297     }
298 }
299 
300 static kobj_method_t cs4281_ac97_methods[] = {
301         KOBJMETHOD(ac97_read,           cs4281_rdcd),
302         KOBJMETHOD(ac97_write,          cs4281_wrcd),
303         { 0, 0 }
304 };
305 AC97_DECLARE(cs4281_ac97);
306 
307 /* ------------------------------------------------------------------------- */
308 /* shared rec/play channel interface */
309 
310 static void *
311 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
312 {
313     struct sc_info *sc = devinfo;
314     struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
315 
316     ch->buffer = b;
317     if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
318 	return NULL;
319     }
320     ch->parent = sc;
321     ch->channel = c;
322 
323     ch->fmt = AFMT_U8;
324     ch->spd = DSP_DEFAULT_SPEED;
325     ch->bps = 1;
326     ch->blksz = sndbuf_getsize(ch->buffer);
327 
328     ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC;
329     ch->dma_setup = 0;
330 
331     adcdac_go(ch, 0);
332     adcdac_prog(ch);
333 
334     return ch;
335 }
336 
337 static int
338 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
339 {
340     struct sc_chinfo *ch = data;
341     struct sc_info *sc = ch->parent;
342     u_int32_t go;
343 
344     go = adcdac_go(ch, 0);
345 
346     /* 2 interrupts are possible and used in buffer (half-empty,empty),
347      * hence factor of 2. */
348     ch->blksz = MIN(blocksize, sc->bufsz / 2);
349     sndbuf_resize(ch->buffer, 2, ch->blksz);
350     ch->dma_setup = 0;
351     adcdac_prog(ch);
352     adcdac_go(ch, go);
353 
354     DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz));
355 
356     return ch->blksz;
357 }
358 
359 static int
360 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
361 {
362     struct sc_chinfo *ch = data;
363     struct sc_info *sc = ch->parent;
364     u_int32_t go, v, r;
365 
366     go = adcdac_go(ch, 0); /* pause */
367     r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR;
368     v = cs4281_rate_to_rv(speed);
369     cs4281_wr(sc, r, v);
370     adcdac_go(ch, go); /* unpause */
371 
372     ch->spd = cs4281_rv_to_rate(v);
373     return ch->spd;
374 }
375 
376 static int
377 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
378 {
379     struct sc_chinfo *ch = data;
380     struct sc_info *sc = ch->parent;
381     u_int32_t v, go;
382 
383     go = adcdac_go(ch, 0); /* pause */
384 
385     if (ch->dma_chan == CS4281_DMA_PLAY)
386 	v = CS4281PCI_DMR_TR_PLAY;
387     else
388 	v = CS4281PCI_DMR_TR_REC;
389     v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO;
390     v |= cs4281_format_to_dmr(format);
391     cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v);
392 
393     adcdac_go(ch, go); /* unpause */
394 
395     ch->fmt = format;
396     ch->bps = cs4281_format_to_bps(format);
397     ch->dma_setup = 0;
398 
399     return 0;
400 }
401 
402 static int
403 cs4281chan_getptr(kobj_t obj, void *data)
404 {
405     struct sc_chinfo *ch = data;
406     struct sc_info *sc = ch->parent;
407     u_int32_t  dba, dca, ptr;
408     int sz;
409 
410     sz  = sndbuf_getsize(ch->buffer);
411     dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
412     dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
413     ptr = (dca - dba + sz) % sz;
414 
415     return ptr;
416 }
417 
418 static int
419 cs4281chan_trigger(kobj_t obj, void *data, int go)
420 {
421     struct sc_chinfo *ch = data;
422 
423     switch(go) {
424     case PCMTRIG_START:
425 	adcdac_prog(ch);
426 	adcdac_go(ch, 1);
427 	break;
428     case PCMTRIG_STOP:
429     case PCMTRIG_ABORT:
430 	adcdac_go(ch, 0);
431 	break;
432     default:
433 	break;
434     }
435 
436     /* return 0 if ok */
437     return 0;
438 }
439 
440 static struct pcmchan_caps *
441 cs4281chan_getcaps(kobj_t obj, void *data)
442 {
443     return &cs4281_caps;
444 }
445 
446 static kobj_method_t cs4281chan_methods[] = {
447     	KOBJMETHOD(channel_init,		cs4281chan_init),
448     	KOBJMETHOD(channel_setformat,		cs4281chan_setformat),
449     	KOBJMETHOD(channel_setspeed,		cs4281chan_setspeed),
450     	KOBJMETHOD(channel_setblocksize,	cs4281chan_setblocksize),
451     	KOBJMETHOD(channel_trigger,		cs4281chan_trigger),
452     	KOBJMETHOD(channel_getptr,		cs4281chan_getptr),
453     	KOBJMETHOD(channel_getcaps,		cs4281chan_getcaps),
454 	{ 0, 0 }
455 };
456 CHANNEL_DECLARE(cs4281chan);
457 
458 /* -------------------------------------------------------------------- */
459 /* ADC/DAC control */
460 
461 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
462  * active before call */
463 
464 static u_int32_t
465 adcdac_go(struct sc_chinfo *ch, u_int32_t go)
466 {
467     struct sc_info *sc = ch->parent;
468     u_int32_t going;
469 
470     going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK);
471 
472     if (go)
473 	cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
474     else
475 	cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
476 
477     cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
478 
479     return going;
480 }
481 
482 static void
483 adcdac_prog(struct sc_chinfo *ch)
484 {
485     struct sc_info *sc = ch->parent;
486     u_int32_t go;
487 
488     if (!ch->dma_setup) {
489 	go = adcdac_go(ch, 0);
490 	cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan),
491 		  sndbuf_getbufaddr(ch->buffer));
492 	cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan),
493 		  sndbuf_getsize(ch->buffer) / ch->bps - 1);
494 	ch->dma_setup = 1;
495 	adcdac_go(ch, go);
496     }
497 }
498 
499 /* -------------------------------------------------------------------- */
500 /* The interrupt handler */
501 
502 static void
503 cs4281_intr(void *p)
504 {
505     struct sc_info *sc = (struct sc_info *)p;
506     u_int32_t hisr;
507 
508     hisr = cs4281_rd(sc, CS4281PCI_HISR);
509 
510     if (hisr == 0) return;
511 
512     if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) {
513 	chn_intr(sc->pch.channel);
514 	cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
515     }
516 
517     if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) {
518 	chn_intr(sc->rch.channel);
519 	cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
520     }
521 
522     /* Signal End-of-Interrupt */
523     cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
524 }
525 
526 /* -------------------------------------------------------------------- */
527 /* power management related */
528 
529 static int
530 cs4281_power(struct sc_info *sc, int state)
531 {
532 
533     switch (state) {
534     case 0:
535         /* Permit r/w access to all BA0 registers */
536         cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC);
537         /* Power on */
538         cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
539         break;
540     case 3:
541     	/* Power off card and codec */
542     	cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
543     	cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
544         break;
545     }
546 
547     DEB(printf("cs4281_power %d -> %d\n", sc->power, state));
548     sc->power = state;
549 
550     return 0;
551 }
552 
553 static int
554 cs4281_init(struct sc_info *sc)
555 {
556     u_int32_t i, v;
557 
558     /* (0) Blast clock register and serial port */
559     cs4281_wr(sc, CS4281PCI_CLKCR1, 0);
560     cs4281_wr(sc, CS4281PCI_SERMC,  0);
561 
562     /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
563     cs4281_wr(sc, CS4281PCI_ACCTL, 0);
564     DELAY(50);
565 
566     /* (2) Effect Reset */
567     cs4281_wr(sc, CS4281PCI_SPMC, 0);
568     DELAY(100);
569     cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
570     /* Wait 50ms for ABITCLK to become stable */
571     DELAY(50000);
572 
573     /* (3) Enable Sound System Clocks */
574     cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);
575     DELAY(50000); /* Wait for PLL to stabilize */
576     cs4281_wr(sc, CS4281PCI_CLKCR1,
577 	      CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);
578 
579     /* (4) Power Up - this combination is essential. */
580     cs4281_set4(sc, CS4281PCI_SSPM,
581 		CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |
582 		CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);
583 
584     /* (5) Wait for clock stabilization */
585     if (cs4281_waitset(sc,
586 		       CS4281PCI_CLKCR1,
587 		       CS4281PCI_CLKCR1_DLLRDY,
588 		       250) == 0) {
589 	device_printf(sc->dev, "Clock stabilization failed\n");
590 	return -1;
591     }
592 
593     /* (6) Enable ASYNC generation. */
594     cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);
595 
596     /* Wait to allow AC97 to start generating clock bit */
597     DELAY(50000);
598 
599     /* Set AC97 timing */
600     cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
601 
602     /* (7) Wait for AC97 ready signal */
603     if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {
604 	device_printf(sc->dev, "codec did not avail\n");
605 	return -1;
606     }
607 
608     /* (8) Assert valid frame signal to begin sending commands to
609      *     AC97 codec */
610     cs4281_wr(sc,
611 	      CS4281PCI_ACCTL,
612 	      CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);
613 
614     /* (9) Wait for codec calibration */
615     for(i = 0 ; i < 1000; i++) {
616 	DELAY(10000);
617 	v = cs4281_rdcd(0, sc, AC97_REG_POWER);
618 	if ((v & 0x0f) == 0x0f) {
619 	    break;
620 	}
621     }
622     if (i == 1000) {
623 	device_printf(sc->dev, "codec failed to calibrate\n");
624 	return -1;
625     }
626 
627     /* (10) Set AC97 timing */
628     cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
629 
630     /* (11) Wait for valid data to arrive */
631     if (cs4281_waitset(sc,
632 		       CS4281PCI_ACISV,
633 		       CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),
634 		       10000) == 0) {
635 	device_printf(sc->dev, "cs4281 never got valid data\n");
636 	return -1;
637     }
638 
639     /* (12) Start digital data transfer of audio data to codec */
640     cs4281_wr(sc,
641 	      CS4281PCI_ACOSV,
642 	      CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));
643 
644     /* Set Master and headphone to max */
645     cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0);
646     cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
647 
648     /* Power on the DAC */
649     v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
650     cs4281_wrcd(0, sc, AC97_REG_POWER, v);
651 
652     /* Wait until DAC state ready */
653     for(i = 0; i < 320; i++) {
654 	DELAY(100);
655 	v = cs4281_rdcd(0, sc, AC97_REG_POWER);
656 	if (v & 0x02) break;
657     }
658 
659     /* Power on the ADC */
660     v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
661     cs4281_wrcd(0, sc, AC97_REG_POWER, v);
662 
663     /* Wait until ADC state ready */
664     for(i = 0; i < 320; i++) {
665 	DELAY(100);
666 	v = cs4281_rdcd(0, sc, AC97_REG_POWER);
667 	if (v & 0x01) break;
668     }
669 
670     /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
671     /* Play FIFO */
672 
673     v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) |
674 	CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) |
675 	CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
676 	CS4281PCI_FCR_OF(0);
677     cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v);
678 
679     cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN);
680 
681     /* Record FIFO */
682     v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) |
683 	CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) |
684 	CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
685 	CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1);
686     cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH);
687     cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN);
688 
689     /* Match AC97 slots to FIFOs */
690     v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) |
691 	CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) |
692 	CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) |
693 	CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT);
694     cs4281_wr(sc, CS4281PCI_SRCSA, v);
695 
696     /* Set Auto-Initialize and set directions */
697     cs4281_wr(sc,
698 	      CS4281PCI_DMR(CS4281_DMA_PLAY),
699 	      CS4281PCI_DMR_DMA  |
700 	      CS4281PCI_DMR_AUTO |
701 	      CS4281PCI_DMR_TR_PLAY);
702     cs4281_wr(sc,
703 	      CS4281PCI_DMR(CS4281_DMA_REC),
704 	      CS4281PCI_DMR_DMA  |
705 	      CS4281PCI_DMR_AUTO |
706 	      CS4281PCI_DMR_TR_REC);
707 
708     /* Enable half and empty buffer interrupts keeping DMA paused */
709     cs4281_wr(sc,
710 	      CS4281PCI_DCR(CS4281_DMA_PLAY),
711 	      CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
712     cs4281_wr(sc,
713 	      CS4281PCI_DCR(CS4281_DMA_REC),
714 	      CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
715 
716     /* Enable Interrupts */
717     cs4281_clr4(sc,
718 		CS4281PCI_HIMR,
719 		CS4281PCI_HIMR_DMAI |
720 		CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) |
721 		CS4281PCI_HIMR_DMA(CS4281_DMA_REC));
722 
723     /* Set playback volume */
724     cs4281_wr(sc, CS4281PCI_PPLVC, 7);
725     cs4281_wr(sc, CS4281PCI_PPRVC, 7);
726 
727     return 0;
728 }
729 
730 /* -------------------------------------------------------------------- */
731 /* Probe and attach the card */
732 
733 static int
734 cs4281_pci_probe(device_t dev)
735 {
736     char *s = NULL;
737 
738     switch (pci_get_devid(dev)) {
739     case CS4281_PCI_ID:
740 	s = "Crystal Semiconductor CS4281";
741 	break;
742     }
743 
744     if (s)
745 	device_set_desc(dev, s);
746     return s ? BUS_PROBE_DEFAULT : ENXIO;
747 }
748 
749 static int
750 cs4281_pci_attach(device_t dev)
751 {
752     struct sc_info *sc;
753     struct ac97_info *codec = NULL;
754     u_int32_t data;
755     char status[SND_STATUSLEN];
756 
757     sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
758     sc->dev = dev;
759     sc->type = pci_get_devid(dev);
760 
761     data = pci_read_config(dev, PCIR_COMMAND, 2);
762     data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
763     pci_write_config(dev, PCIR_COMMAND, data, 2);
764 
765 #if __FreeBSD_version > 500000
766     if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
767 	/* Reset the power state. */
768 	device_printf(dev, "chip is in D%d power mode "
769 		      "-- setting to D0\n", pci_get_powerstate(dev));
770 
771 	pci_set_powerstate(dev, PCI_POWERSTATE_D0);
772     }
773 #else
774     data = pci_read_config(dev, CS4281PCI_PMCS_OFFSET, 4);
775     if (data & CS4281PCI_PMCS_PS_MASK) {
776 	    /* Reset the power state. */
777 	    device_printf(dev, "chip is in D%d power mode "
778 			  "-- setting to D0\n",
779 			  data & CS4281PCI_PMCS_PS_MASK);
780 	    pci_write_config(dev, CS4281PCI_PMCS_OFFSET,
781 			     data & ~CS4281PCI_PMCS_PS_MASK, 4);
782     }
783 #endif
784 
785     sc->regid   = PCIR_BAR(0);
786     sc->regtype = SYS_RES_MEMORY;
787     sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
788 				 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
789     if (!sc->reg) {
790 	sc->regtype = SYS_RES_IOPORT;
791 	sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
792 				     0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
793 	if (!sc->reg) {
794 	    device_printf(dev, "unable to allocate register space\n");
795 	    goto bad;
796 	}
797     }
798     sc->st = rman_get_bustag(sc->reg);
799     sc->sh = rman_get_bushandle(sc->reg);
800 
801     sc->memid = PCIR_BAR(1);
802     sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0,
803 				 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE);
804     if (sc->mem == NULL) {
805 	device_printf(dev, "unable to allocate fifo space\n");
806 	goto bad;
807     }
808 
809     sc->irqid = 0;
810     sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
811 				     RF_ACTIVE | RF_SHAREABLE);
812     if (!sc->irq) {
813 	device_printf(dev, "unable to allocate interrupt\n");
814 	goto bad;
815     }
816 
817     if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) {
818 	device_printf(dev, "unable to setup interrupt\n");
819 	goto bad;
820     }
821 
822     sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536);
823 
824     if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
825 			   /*boundary*/0,
826 			   /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
827 			   /*highaddr*/BUS_SPACE_MAXADDR,
828 			   /*filter*/NULL, /*filterarg*/NULL,
829 			   /*maxsize*/sc->bufsz, /*nsegments*/1,
830 			   /*maxsegz*/0x3ffff,
831 			   /*flags*/0, /*lockfunc*/busdma_lock_mutex,
832 			   /*lockarg*/&Giant, &sc->parent_dmat) != 0) {
833 	device_printf(dev, "unable to create dma tag\n");
834 	goto bad;
835     }
836 
837     /* power up */
838     cs4281_power(sc, 0);
839 
840     /* init chip */
841     if (cs4281_init(sc) == -1) {
842 	device_printf(dev, "unable to initialize the card\n");
843 	goto bad;
844     }
845 
846     /* create/init mixer */
847     codec = AC97_CREATE(dev, sc, cs4281_ac97);
848     if (codec == NULL)
849         goto bad;
850 
851     mixer_init(dev, ac97_getmixerclass(), codec);
852 
853     if (pcm_register(dev, sc, 1, 1))
854 	goto bad;
855 
856     pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
857     pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
858 
859     snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
860 	     (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
861 	     rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281));
862     pcm_setstatus(dev, status);
863 
864     return 0;
865 
866  bad:
867     if (codec)
868 	ac97_destroy(codec);
869     if (sc->reg)
870 	bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
871     if (sc->mem)
872 	bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
873     if (sc->ih)
874 	bus_teardown_intr(dev, sc->irq, sc->ih);
875     if (sc->irq)
876 	bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
877     if (sc->parent_dmat)
878 	bus_dma_tag_destroy(sc->parent_dmat);
879     free(sc, M_DEVBUF);
880 
881     return ENXIO;
882 }
883 
884 static int
885 cs4281_pci_detach(device_t dev)
886 {
887     int r;
888     struct sc_info *sc;
889 
890     r = pcm_unregister(dev);
891     if (r)
892 	return r;
893 
894     sc = pcm_getdevinfo(dev);
895 
896     /* power off */
897     cs4281_power(sc, 3);
898 
899     bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
900     bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
901     bus_teardown_intr(dev, sc->irq, sc->ih);
902     bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
903     bus_dma_tag_destroy(sc->parent_dmat);
904     free(sc, M_DEVBUF);
905 
906     return 0;
907 }
908 
909 static int
910 cs4281_pci_suspend(device_t dev)
911 {
912     struct sc_info *sc;
913 
914     sc = pcm_getdevinfo(dev);
915 
916     sc->rch.dma_active = adcdac_go(&sc->rch, 0);
917     sc->pch.dma_active = adcdac_go(&sc->pch, 0);
918 
919     cs4281_power(sc, 3);
920 
921     return 0;
922 }
923 
924 static int
925 cs4281_pci_resume(device_t dev)
926 {
927     struct sc_info *sc;
928 
929     sc = pcm_getdevinfo(dev);
930 
931     /* power up */
932     cs4281_power(sc, 0);
933 
934     /* initialize chip */
935     if (cs4281_init(sc) == -1) {
936         device_printf(dev, "unable to reinitialize the card\n");
937         return ENXIO;
938     }
939 
940     /* restore mixer state */
941     if (mixer_reinit(dev) == -1) {
942 	device_printf(dev, "unable to reinitialize the mixer\n");
943 	return ENXIO;
944     }
945 
946     /* restore chip state */
947     cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd);
948     cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz);
949     cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt);
950     adcdac_go(&sc->rch, sc->rch.dma_active);
951 
952     cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd);
953     cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz);
954     cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt);
955     adcdac_go(&sc->pch, sc->pch.dma_active);
956 
957     return 0;
958 }
959 
960 static device_method_t cs4281_methods[] = {
961     /* Device interface */
962     DEVMETHOD(device_probe,		cs4281_pci_probe),
963     DEVMETHOD(device_attach,		cs4281_pci_attach),
964     DEVMETHOD(device_detach,		cs4281_pci_detach),
965     DEVMETHOD(device_suspend,		cs4281_pci_suspend),
966     DEVMETHOD(device_resume,		cs4281_pci_resume),
967     { 0, 0 }
968 };
969 
970 static driver_t cs4281_driver = {
971     "pcm",
972     cs4281_methods,
973     PCM_SOFTC_SIZE,
974 };
975 
976 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0);
977 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
978 MODULE_VERSION(snd_cs4281, 1);
979