1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * The order of pokes in the initiation sequence is based on Linux 31 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom 32 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org) 33 * contributed towards power management. 34 */ 35 36 #ifdef HAVE_KERNEL_OPTION_HEADERS 37 #include "opt_snd.h" 38 #endif 39 40 #include <dev/sound/pcm/sound.h> 41 #include <dev/sound/pcm/ac97.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/sound/pci/cs4281.h> 47 48 SND_DECLARE_FILE("$FreeBSD$"); 49 50 #define CS4281_DEFAULT_BUFSZ 16384 51 52 /* Max fifo size for full duplex is 64 */ 53 #define CS4281_FIFO_SIZE 15 54 55 /* DMA Engine Indices */ 56 #define CS4281_DMA_PLAY 0 57 #define CS4281_DMA_REC 1 58 59 /* Misc */ 60 61 #define inline __inline 62 63 #ifndef DEB 64 #define DEB(x) /* x */ 65 #endif /* DEB */ 66 67 /* ------------------------------------------------------------------------- */ 68 /* Structures */ 69 70 struct sc_info; 71 72 /* channel registers */ 73 struct sc_chinfo { 74 struct sc_info *parent; 75 76 struct snd_dbuf *buffer; 77 struct pcm_channel *channel; 78 79 u_int32_t spd, fmt, bps, blksz; 80 81 int dma_setup, dma_active, dma_chan; 82 }; 83 84 /* device private data */ 85 struct sc_info { 86 device_t dev; 87 u_int32_t type; 88 89 bus_space_tag_t st; 90 bus_space_handle_t sh; 91 bus_dma_tag_t parent_dmat; 92 93 struct resource *reg, *irq, *mem; 94 int regtype, regid, irqid, memid; 95 void *ih; 96 97 int power; 98 unsigned long bufsz; 99 struct sc_chinfo pch; 100 struct sc_chinfo rch; 101 }; 102 103 /* -------------------------------------------------------------------- */ 104 /* prototypes */ 105 106 /* ADC/DAC control */ 107 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go); 108 static void adcdac_prog(struct sc_chinfo *ch); 109 110 /* power management and interrupt control */ 111 static void cs4281_intr(void *); 112 static int cs4281_power(struct sc_info *, int); 113 static int cs4281_init(struct sc_info *); 114 115 /* talk to the card */ 116 static u_int32_t cs4281_rd(struct sc_info *, int); 117 static void cs4281_wr(struct sc_info *, int, u_int32_t); 118 119 /* misc */ 120 static u_int8_t cs4281_rate_to_rv(u_int32_t); 121 static u_int32_t cs4281_format_to_dmr(u_int32_t); 122 static u_int32_t cs4281_format_to_bps(u_int32_t); 123 124 /* -------------------------------------------------------------------- */ 125 /* formats (do not add formats without editing cs_fmt_tab) */ 126 127 static u_int32_t cs4281_fmts[] = { 128 SND_FORMAT(AFMT_U8, 1, 0), 129 SND_FORMAT(AFMT_U8, 2, 0), 130 SND_FORMAT(AFMT_S8, 1, 0), 131 SND_FORMAT(AFMT_S8, 2, 0), 132 SND_FORMAT(AFMT_S16_LE, 1, 0), 133 SND_FORMAT(AFMT_S16_LE, 2, 0), 134 SND_FORMAT(AFMT_U16_LE, 1, 0), 135 SND_FORMAT(AFMT_U16_LE, 2, 0), 136 SND_FORMAT(AFMT_S16_BE, 1, 0), 137 SND_FORMAT(AFMT_S16_BE, 2, 0), 138 SND_FORMAT(AFMT_U16_BE, 1, 0), 139 SND_FORMAT(AFMT_U16_BE, 2, 0), 140 0 141 }; 142 143 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0}; 144 145 /* -------------------------------------------------------------------- */ 146 /* Hardware */ 147 148 static inline u_int32_t 149 cs4281_rd(struct sc_info *sc, int regno) 150 { 151 return bus_space_read_4(sc->st, sc->sh, regno); 152 } 153 154 static inline void 155 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data) 156 { 157 bus_space_write_4(sc->st, sc->sh, regno, data); 158 DELAY(100); 159 } 160 161 static inline void 162 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask) 163 { 164 u_int32_t r; 165 r = cs4281_rd(sc, regno); 166 cs4281_wr(sc, regno, r & ~mask); 167 } 168 169 static inline void 170 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask) 171 { 172 u_int32_t v; 173 v = cs4281_rd(sc, regno); 174 cs4281_wr(sc, regno, v | mask); 175 } 176 177 static int 178 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries) 179 { 180 u_int32_t v; 181 182 while (tries > 0) { 183 DELAY(100); 184 v = cs4281_rd(sc, regno); 185 if ((v & mask) == mask) break; 186 tries --; 187 } 188 return tries; 189 } 190 191 static int 192 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries) 193 { 194 u_int32_t v; 195 196 while (tries > 0) { 197 DELAY(100); 198 v = ~ cs4281_rd(sc, regno); 199 if (v & mask) break; 200 tries --; 201 } 202 return tries; 203 } 204 205 /* ------------------------------------------------------------------------- */ 206 /* Register value mapping functions */ 207 208 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000}; 209 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0]) 210 211 static u_int8_t 212 cs4281_rate_to_rv(u_int32_t rate) 213 { 214 u_int32_t v; 215 216 for (v = 0; v < CS4281_NUM_RATES; v++) { 217 if (rate == cs4281_rates[v]) return v; 218 } 219 220 v = 1536000 / rate; 221 if (v > 255 || v < 32) v = 5; /* default to 8k */ 222 return v; 223 } 224 225 static u_int32_t 226 cs4281_rv_to_rate(u_int8_t rv) 227 { 228 u_int32_t r; 229 230 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv]; 231 r = 1536000 / rv; 232 return r; 233 } 234 235 static inline u_int32_t 236 cs4281_format_to_dmr(u_int32_t format) 237 { 238 u_int32_t dmr = 0; 239 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8; 240 if (AFMT_CHANNEL(format) < 2) dmr |= CS4281PCI_DMR_MONO; 241 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND; 242 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN; 243 return dmr; 244 } 245 246 static inline u_int32_t 247 cs4281_format_to_bps(u_int32_t format) 248 { 249 return ((AFMT_8BIT & format) ? 1 : 2) * 250 ((AFMT_CHANNEL(format) > 1) ? 2 : 1); 251 } 252 253 /* -------------------------------------------------------------------- */ 254 /* ac97 codec */ 255 256 static int 257 cs4281_rdcd(kobj_t obj, void *devinfo, int regno) 258 { 259 struct sc_info *sc = (struct sc_info *)devinfo; 260 261 regno &= 0xff; 262 263 /* Remove old state */ 264 cs4281_rd(sc, CS4281PCI_ACSDA); 265 266 /* Fill in AC97 register value request form */ 267 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 268 cs4281_wr(sc, CS4281PCI_ACCDA, 0); 269 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 270 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV | 271 CS4281PCI_ACCTL_CRW); 272 273 /* Wait for read to complete */ 274 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 275 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n"); 276 return -1; 277 } 278 279 /* Wait for valid status */ 280 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) { 281 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n"); 282 return -1; 283 } 284 285 return cs4281_rd(sc, CS4281PCI_ACSDA); 286 } 287 288 static int 289 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 290 { 291 struct sc_info *sc = (struct sc_info *)devinfo; 292 293 regno &= 0xff; 294 295 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 296 cs4281_wr(sc, CS4281PCI_ACCDA, data); 297 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 298 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV); 299 300 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 301 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n"); 302 } 303 304 return 0; 305 } 306 307 static kobj_method_t cs4281_ac97_methods[] = { 308 KOBJMETHOD(ac97_read, cs4281_rdcd), 309 KOBJMETHOD(ac97_write, cs4281_wrcd), 310 KOBJMETHOD_END 311 }; 312 AC97_DECLARE(cs4281_ac97); 313 314 /* ------------------------------------------------------------------------- */ 315 /* shared rec/play channel interface */ 316 317 static void * 318 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 319 { 320 struct sc_info *sc = devinfo; 321 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 322 323 ch->buffer = b; 324 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 325 return NULL; 326 } 327 ch->parent = sc; 328 ch->channel = c; 329 330 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 331 ch->spd = DSP_DEFAULT_SPEED; 332 ch->bps = 1; 333 ch->blksz = sndbuf_getsize(ch->buffer); 334 335 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC; 336 ch->dma_setup = 0; 337 338 adcdac_go(ch, 0); 339 adcdac_prog(ch); 340 341 return ch; 342 } 343 344 static u_int32_t 345 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 346 { 347 struct sc_chinfo *ch = data; 348 struct sc_info *sc = ch->parent; 349 u_int32_t go; 350 351 go = adcdac_go(ch, 0); 352 353 /* 2 interrupts are possible and used in buffer (half-empty,empty), 354 * hence factor of 2. */ 355 ch->blksz = MIN(blocksize, sc->bufsz / 2); 356 sndbuf_resize(ch->buffer, 2, ch->blksz); 357 ch->dma_setup = 0; 358 adcdac_prog(ch); 359 adcdac_go(ch, go); 360 361 DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz)); 362 363 return ch->blksz; 364 } 365 366 static u_int32_t 367 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed) 368 { 369 struct sc_chinfo *ch = data; 370 struct sc_info *sc = ch->parent; 371 u_int32_t go, v, r; 372 373 go = adcdac_go(ch, 0); /* pause */ 374 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR; 375 v = cs4281_rate_to_rv(speed); 376 cs4281_wr(sc, r, v); 377 adcdac_go(ch, go); /* unpause */ 378 379 ch->spd = cs4281_rv_to_rate(v); 380 return ch->spd; 381 } 382 383 static int 384 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format) 385 { 386 struct sc_chinfo *ch = data; 387 struct sc_info *sc = ch->parent; 388 u_int32_t v, go; 389 390 go = adcdac_go(ch, 0); /* pause */ 391 392 if (ch->dma_chan == CS4281_DMA_PLAY) 393 v = CS4281PCI_DMR_TR_PLAY; 394 else 395 v = CS4281PCI_DMR_TR_REC; 396 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO; 397 v |= cs4281_format_to_dmr(format); 398 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v); 399 400 adcdac_go(ch, go); /* unpause */ 401 402 ch->fmt = format; 403 ch->bps = cs4281_format_to_bps(format); 404 ch->dma_setup = 0; 405 406 return 0; 407 } 408 409 static u_int32_t 410 cs4281chan_getptr(kobj_t obj, void *data) 411 { 412 struct sc_chinfo *ch = data; 413 struct sc_info *sc = ch->parent; 414 u_int32_t dba, dca, ptr; 415 int sz; 416 417 sz = sndbuf_getsize(ch->buffer); 418 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan)); 419 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan)); 420 ptr = (dca - dba + sz) % sz; 421 422 return ptr; 423 } 424 425 static int 426 cs4281chan_trigger(kobj_t obj, void *data, int go) 427 { 428 struct sc_chinfo *ch = data; 429 430 switch(go) { 431 case PCMTRIG_START: 432 adcdac_prog(ch); 433 adcdac_go(ch, 1); 434 break; 435 case PCMTRIG_STOP: 436 case PCMTRIG_ABORT: 437 adcdac_go(ch, 0); 438 break; 439 default: 440 break; 441 } 442 443 /* return 0 if ok */ 444 return 0; 445 } 446 447 static struct pcmchan_caps * 448 cs4281chan_getcaps(kobj_t obj, void *data) 449 { 450 return &cs4281_caps; 451 } 452 453 static kobj_method_t cs4281chan_methods[] = { 454 KOBJMETHOD(channel_init, cs4281chan_init), 455 KOBJMETHOD(channel_setformat, cs4281chan_setformat), 456 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed), 457 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize), 458 KOBJMETHOD(channel_trigger, cs4281chan_trigger), 459 KOBJMETHOD(channel_getptr, cs4281chan_getptr), 460 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps), 461 KOBJMETHOD_END 462 }; 463 CHANNEL_DECLARE(cs4281chan); 464 465 /* -------------------------------------------------------------------- */ 466 /* ADC/DAC control */ 467 468 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was 469 * active before call */ 470 471 static u_int32_t 472 adcdac_go(struct sc_chinfo *ch, u_int32_t go) 473 { 474 struct sc_info *sc = ch->parent; 475 u_int32_t going; 476 477 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK); 478 479 if (go) 480 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 481 else 482 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 483 484 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 485 486 return going; 487 } 488 489 static void 490 adcdac_prog(struct sc_chinfo *ch) 491 { 492 struct sc_info *sc = ch->parent; 493 u_int32_t go; 494 495 if (!ch->dma_setup) { 496 go = adcdac_go(ch, 0); 497 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan), 498 sndbuf_getbufaddr(ch->buffer)); 499 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan), 500 sndbuf_getsize(ch->buffer) / ch->bps - 1); 501 ch->dma_setup = 1; 502 adcdac_go(ch, go); 503 } 504 } 505 506 /* -------------------------------------------------------------------- */ 507 /* The interrupt handler */ 508 509 static void 510 cs4281_intr(void *p) 511 { 512 struct sc_info *sc = (struct sc_info *)p; 513 u_int32_t hisr; 514 515 hisr = cs4281_rd(sc, CS4281PCI_HISR); 516 517 if (hisr == 0) return; 518 519 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) { 520 chn_intr(sc->pch.channel); 521 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */ 522 } 523 524 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) { 525 chn_intr(sc->rch.channel); 526 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */ 527 } 528 529 /* Signal End-of-Interrupt */ 530 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 531 } 532 533 /* -------------------------------------------------------------------- */ 534 /* power management related */ 535 536 static int 537 cs4281_power(struct sc_info *sc, int state) 538 { 539 540 switch (state) { 541 case 0: 542 /* Permit r/w access to all BA0 registers */ 543 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC); 544 /* Power on */ 545 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 546 break; 547 case 3: 548 /* Power off card and codec */ 549 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 550 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 551 break; 552 } 553 554 DEB(printf("cs4281_power %d -> %d\n", sc->power, state)); 555 sc->power = state; 556 557 return 0; 558 } 559 560 static int 561 cs4281_init(struct sc_info *sc) 562 { 563 u_int32_t i, v; 564 565 /* (0) Blast clock register and serial port */ 566 cs4281_wr(sc, CS4281PCI_CLKCR1, 0); 567 cs4281_wr(sc, CS4281PCI_SERMC, 0); 568 569 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */ 570 cs4281_wr(sc, CS4281PCI_ACCTL, 0); 571 DELAY(50); 572 573 /* (2) Effect Reset */ 574 cs4281_wr(sc, CS4281PCI_SPMC, 0); 575 DELAY(100); 576 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 577 /* Wait 50ms for ABITCLK to become stable */ 578 DELAY(50000); 579 580 /* (3) Enable Sound System Clocks */ 581 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP); 582 DELAY(50000); /* Wait for PLL to stabilize */ 583 cs4281_wr(sc, CS4281PCI_CLKCR1, 584 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE); 585 586 /* (4) Power Up - this combination is essential. */ 587 cs4281_set4(sc, CS4281PCI_SSPM, 588 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN | 589 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN); 590 591 /* (5) Wait for clock stabilization */ 592 if (cs4281_waitset(sc, 593 CS4281PCI_CLKCR1, 594 CS4281PCI_CLKCR1_DLLRDY, 595 250) == 0) { 596 device_printf(sc->dev, "Clock stabilization failed\n"); 597 return -1; 598 } 599 600 /* (6) Enable ASYNC generation. */ 601 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN); 602 603 /* Wait to allow AC97 to start generating clock bit */ 604 DELAY(50000); 605 606 /* Set AC97 timing */ 607 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 608 609 /* (7) Wait for AC97 ready signal */ 610 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) { 611 device_printf(sc->dev, "codec did not avail\n"); 612 return -1; 613 } 614 615 /* (8) Assert valid frame signal to begin sending commands to 616 * AC97 codec */ 617 cs4281_wr(sc, 618 CS4281PCI_ACCTL, 619 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN); 620 621 /* (9) Wait for codec calibration */ 622 for(i = 0 ; i < 1000; i++) { 623 DELAY(10000); 624 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 625 if ((v & 0x0f) == 0x0f) { 626 break; 627 } 628 } 629 if (i == 1000) { 630 device_printf(sc->dev, "codec failed to calibrate\n"); 631 return -1; 632 } 633 634 /* (10) Set AC97 timing */ 635 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 636 637 /* (11) Wait for valid data to arrive */ 638 if (cs4281_waitset(sc, 639 CS4281PCI_ACISV, 640 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4), 641 10000) == 0) { 642 device_printf(sc->dev, "cs4281 never got valid data\n"); 643 return -1; 644 } 645 646 /* (12) Start digital data transfer of audio data to codec */ 647 cs4281_wr(sc, 648 CS4281PCI_ACOSV, 649 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4)); 650 651 /* Set Master and headphone to max */ 652 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0); 653 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0); 654 655 /* Power on the DAC */ 656 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff; 657 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 658 659 /* Wait until DAC state ready */ 660 for(i = 0; i < 320; i++) { 661 DELAY(100); 662 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 663 if (v & 0x02) break; 664 } 665 666 /* Power on the ADC */ 667 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff; 668 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 669 670 /* Wait until ADC state ready */ 671 for(i = 0; i < 320; i++) { 672 DELAY(100); 673 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 674 if (v & 0x01) break; 675 } 676 677 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */ 678 /* Play FIFO */ 679 680 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) | 681 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) | 682 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 683 CS4281PCI_FCR_OF(0); 684 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v); 685 686 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN); 687 688 /* Record FIFO */ 689 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) | 690 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) | 691 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 692 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1); 693 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH); 694 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN); 695 696 /* Match AC97 slots to FIFOs */ 697 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) | 698 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) | 699 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) | 700 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT); 701 cs4281_wr(sc, CS4281PCI_SRCSA, v); 702 703 /* Set Auto-Initialize and set directions */ 704 cs4281_wr(sc, 705 CS4281PCI_DMR(CS4281_DMA_PLAY), 706 CS4281PCI_DMR_DMA | 707 CS4281PCI_DMR_AUTO | 708 CS4281PCI_DMR_TR_PLAY); 709 cs4281_wr(sc, 710 CS4281PCI_DMR(CS4281_DMA_REC), 711 CS4281PCI_DMR_DMA | 712 CS4281PCI_DMR_AUTO | 713 CS4281PCI_DMR_TR_REC); 714 715 /* Enable half and empty buffer interrupts keeping DMA paused */ 716 cs4281_wr(sc, 717 CS4281PCI_DCR(CS4281_DMA_PLAY), 718 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 719 cs4281_wr(sc, 720 CS4281PCI_DCR(CS4281_DMA_REC), 721 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 722 723 /* Enable Interrupts */ 724 cs4281_clr4(sc, 725 CS4281PCI_HIMR, 726 CS4281PCI_HIMR_DMAI | 727 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) | 728 CS4281PCI_HIMR_DMA(CS4281_DMA_REC)); 729 730 /* Set playback volume */ 731 cs4281_wr(sc, CS4281PCI_PPLVC, 7); 732 cs4281_wr(sc, CS4281PCI_PPRVC, 7); 733 734 return 0; 735 } 736 737 /* -------------------------------------------------------------------- */ 738 /* Probe and attach the card */ 739 740 static int 741 cs4281_pci_probe(device_t dev) 742 { 743 char *s = NULL; 744 745 switch (pci_get_devid(dev)) { 746 case CS4281_PCI_ID: 747 s = "Crystal Semiconductor CS4281"; 748 break; 749 } 750 751 if (s) 752 device_set_desc(dev, s); 753 return s ? BUS_PROBE_DEFAULT : ENXIO; 754 } 755 756 static int 757 cs4281_pci_attach(device_t dev) 758 { 759 struct sc_info *sc; 760 struct ac97_info *codec = NULL; 761 char status[SND_STATUSLEN]; 762 763 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 764 sc->dev = dev; 765 sc->type = pci_get_devid(dev); 766 767 pci_enable_busmaster(dev); 768 769 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 770 /* Reset the power state. */ 771 device_printf(dev, "chip is in D%d power mode " 772 "-- setting to D0\n", pci_get_powerstate(dev)); 773 774 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 775 } 776 777 sc->regid = PCIR_BAR(0); 778 sc->regtype = SYS_RES_MEMORY; 779 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, RF_ACTIVE); 780 if (!sc->reg) { 781 sc->regtype = SYS_RES_IOPORT; 782 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 783 RF_ACTIVE); 784 if (!sc->reg) { 785 device_printf(dev, "unable to allocate register space\n"); 786 goto bad; 787 } 788 } 789 sc->st = rman_get_bustag(sc->reg); 790 sc->sh = rman_get_bushandle(sc->reg); 791 792 sc->memid = PCIR_BAR(1); 793 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->memid, 794 RF_ACTIVE); 795 if (sc->mem == NULL) { 796 device_printf(dev, "unable to allocate fifo space\n"); 797 goto bad; 798 } 799 800 sc->irqid = 0; 801 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 802 RF_ACTIVE | RF_SHAREABLE); 803 if (!sc->irq) { 804 device_printf(dev, "unable to allocate interrupt\n"); 805 goto bad; 806 } 807 808 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) { 809 device_printf(dev, "unable to setup interrupt\n"); 810 goto bad; 811 } 812 813 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536); 814 815 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 816 /*boundary*/0, 817 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 818 /*highaddr*/BUS_SPACE_MAXADDR, 819 /*filter*/NULL, /*filterarg*/NULL, 820 /*maxsize*/sc->bufsz, /*nsegments*/1, 821 /*maxsegz*/0x3ffff, 822 /*flags*/0, /*lockfunc*/NULL, /*lockarg*/NULL, 823 &sc->parent_dmat) != 0) { 824 device_printf(dev, "unable to create dma tag\n"); 825 goto bad; 826 } 827 828 /* power up */ 829 cs4281_power(sc, 0); 830 831 /* init chip */ 832 if (cs4281_init(sc) == -1) { 833 device_printf(dev, "unable to initialize the card\n"); 834 goto bad; 835 } 836 837 /* create/init mixer */ 838 codec = AC97_CREATE(dev, sc, cs4281_ac97); 839 if (codec == NULL) 840 goto bad; 841 842 mixer_init(dev, ac97_getmixerclass(), codec); 843 844 if (pcm_register(dev, sc, 1, 1)) 845 goto bad; 846 847 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc); 848 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc); 849 850 snprintf(status, SND_STATUSLEN, "at %s 0x%jx irq %jd %s", 851 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 852 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281)); 853 pcm_setstatus(dev, status); 854 855 return 0; 856 857 bad: 858 if (codec) 859 ac97_destroy(codec); 860 if (sc->reg) 861 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 862 if (sc->mem) 863 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 864 if (sc->ih) 865 bus_teardown_intr(dev, sc->irq, sc->ih); 866 if (sc->irq) 867 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 868 if (sc->parent_dmat) 869 bus_dma_tag_destroy(sc->parent_dmat); 870 free(sc, M_DEVBUF); 871 872 return ENXIO; 873 } 874 875 static int 876 cs4281_pci_detach(device_t dev) 877 { 878 int r; 879 struct sc_info *sc; 880 881 r = pcm_unregister(dev); 882 if (r) 883 return r; 884 885 sc = pcm_getdevinfo(dev); 886 887 /* power off */ 888 cs4281_power(sc, 3); 889 890 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 891 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 892 bus_teardown_intr(dev, sc->irq, sc->ih); 893 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 894 bus_dma_tag_destroy(sc->parent_dmat); 895 free(sc, M_DEVBUF); 896 897 return 0; 898 } 899 900 static int 901 cs4281_pci_suspend(device_t dev) 902 { 903 struct sc_info *sc; 904 905 sc = pcm_getdevinfo(dev); 906 907 sc->rch.dma_active = adcdac_go(&sc->rch, 0); 908 sc->pch.dma_active = adcdac_go(&sc->pch, 0); 909 910 cs4281_power(sc, 3); 911 912 return 0; 913 } 914 915 static int 916 cs4281_pci_resume(device_t dev) 917 { 918 struct sc_info *sc; 919 920 sc = pcm_getdevinfo(dev); 921 922 /* power up */ 923 cs4281_power(sc, 0); 924 925 /* initialize chip */ 926 if (cs4281_init(sc) == -1) { 927 device_printf(dev, "unable to reinitialize the card\n"); 928 return ENXIO; 929 } 930 931 /* restore mixer state */ 932 if (mixer_reinit(dev) == -1) { 933 device_printf(dev, "unable to reinitialize the mixer\n"); 934 return ENXIO; 935 } 936 937 /* restore chip state */ 938 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd); 939 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz); 940 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt); 941 adcdac_go(&sc->rch, sc->rch.dma_active); 942 943 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd); 944 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz); 945 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt); 946 adcdac_go(&sc->pch, sc->pch.dma_active); 947 948 return 0; 949 } 950 951 static device_method_t cs4281_methods[] = { 952 /* Device interface */ 953 DEVMETHOD(device_probe, cs4281_pci_probe), 954 DEVMETHOD(device_attach, cs4281_pci_attach), 955 DEVMETHOD(device_detach, cs4281_pci_detach), 956 DEVMETHOD(device_suspend, cs4281_pci_suspend), 957 DEVMETHOD(device_resume, cs4281_pci_resume), 958 { 0, 0 } 959 }; 960 961 static driver_t cs4281_driver = { 962 "pcm", 963 cs4281_methods, 964 PCM_SOFTC_SIZE, 965 }; 966 967 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, 0, 0); 968 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 969 MODULE_VERSION(snd_cs4281, 1); 970