1 /* 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * This driver exists largely as a result of other people's efforts. 27 * Much of register handling is based on NetBSD CMI8x38 audio driver 28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 30 * registers and the 8738 mixer devices. His Linux was driver a also 31 * useful reference point. 32 * 33 * TODO: MIDI / suspend / resume 34 * 35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 36 * 37 * $FreeBSD$ 38 */ 39 40 #include <dev/sound/pcm/sound.h> 41 #include <dev/sound/pci/cmireg.h> 42 #include <dev/sound/isa/sb.h> 43 44 #include <pci/pcireg.h> 45 #include <pci/pcivar.h> 46 47 #include "mixer_if.h" 48 49 /* Supported chip ID's */ 50 #define CMI8338A_PCI_ID 0x010013f6 51 #define CMI8338B_PCI_ID 0x010113f6 52 #define CMI8738_PCI_ID 0x011113f6 53 #define CMI8738B_PCI_ID 0x011213f6 54 55 /* Buffer size max is 64k for permitted DMA boundaries */ 56 #define CMI_BUFFER_SIZE 16384 57 58 /* Interrupts per length of buffer */ 59 #define CMI_INTR_PER_BUFFER 2 60 61 /* Clarify meaning of named defines in cmireg.h */ 62 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 63 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 64 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 65 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 66 67 /* Our indication of custom mixer control */ 68 #define CMPCI_NON_SB16_CONTROL 0xff 69 70 /* Debugging macro's */ 71 #ifndef DEB 72 #define DEB(x) /* x */ 73 #endif /* DEB */ 74 75 #ifndef DEBMIX 76 #define DEBMIX(x) /* x */ 77 #endif /* DEBMIX */ 78 79 /* ------------------------------------------------------------------------- */ 80 /* Structures */ 81 82 struct cmi_info; 83 84 struct cmi_chinfo { 85 struct cmi_info *parent; 86 pcm_channel *channel; 87 snd_dbuf *buffer; 88 int dir; 89 int bps; /* bytes per sample */ 90 u_int32_t fmt, spd, phys_buf; 91 u_int32_t dma_configured; 92 }; 93 94 struct cmi_info { 95 device_t dev; 96 u_int32_t type, rev; 97 98 bus_space_tag_t st; 99 bus_space_handle_t sh; 100 bus_dma_tag_t parent_dmat; 101 struct resource *reg, *irq; 102 int regid, irqid; 103 void *ih; 104 105 struct cmi_chinfo pch, rch; 106 }; 107 108 /* Channel caps */ 109 110 static u_int32_t cmi_fmt[] = { 111 AFMT_U8, 112 AFMT_STEREO | AFMT_U8, 113 AFMT_S16_LE, 114 AFMT_STEREO | AFMT_S16_LE, 115 0 116 }; 117 118 static pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 119 120 /* ------------------------------------------------------------------------- */ 121 /* Register Utilities */ 122 123 static u_int32_t 124 cmi_rd(struct cmi_info *cmi, int regno, int size) 125 { 126 switch (size) { 127 case 1: 128 return bus_space_read_1(cmi->st, cmi->sh, regno); 129 case 2: 130 return bus_space_read_2(cmi->st, cmi->sh, regno); 131 case 4: 132 return bus_space_read_4(cmi->st, cmi->sh, regno); 133 default: 134 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 135 return 0xFFFFFFFF; 136 } 137 } 138 139 static void 140 cmi_wr(struct cmi_info *cmi, int regno, u_int32_t data, int size) 141 { 142 switch (size) { 143 case 1: 144 bus_space_write_1(cmi->st, cmi->sh, regno, data); 145 break; 146 case 2: 147 bus_space_write_2(cmi->st, cmi->sh, regno, data); 148 break; 149 case 4: 150 bus_space_write_4(cmi->st, cmi->sh, regno, data); 151 break; 152 } 153 DELAY(10); 154 } 155 156 static void 157 cmi_partial_wr4(struct cmi_info *cmi, 158 int reg, int shift, u_int32_t mask, u_int32_t val) 159 { 160 u_int32_t r; 161 162 r = cmi_rd(cmi, reg, 4); 163 r &= ~(mask << shift); 164 r |= val << shift; 165 cmi_wr(cmi, reg, r, 4); 166 } 167 168 static void 169 cmi_clr4(struct cmi_info *cmi, int reg, u_int32_t mask) 170 { 171 u_int32_t r; 172 173 r = cmi_rd(cmi, reg, 4); 174 r &= ~mask; 175 cmi_wr(cmi, reg, r, 4); 176 } 177 178 static void 179 cmi_set4(struct cmi_info *cmi, int reg, u_int32_t mask) 180 { 181 u_int32_t r; 182 183 r = cmi_rd(cmi, reg, 4); 184 r |= mask; 185 cmi_wr(cmi, reg, r, 4); 186 } 187 188 /* ------------------------------------------------------------------------- */ 189 /* Rate Mapping */ 190 191 static int cmi_rates[] = {5512, 8000, 11025, 16000, 192 22050, 32000, 44100, 48000}; 193 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 194 195 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 196 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 197 198 static u_int32_t 199 cmpci_rate_to_regvalue(int rate) 200 { 201 int i, r; 202 203 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 204 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 205 break; 206 } 207 } 208 209 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 210 211 r = ((i >> 1) | (i << 2)) & 0x07; 212 return r; 213 } 214 215 static int 216 cmpci_regvalue_to_rate(u_int32_t r) 217 { 218 int i; 219 220 i = ((r << 1) | (r >> 2)) & 0x07; 221 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 222 return cmi_rates[i]; 223 } 224 225 /* ------------------------------------------------------------------------- */ 226 /* ADC/DAC control */ 227 228 static void 229 cmi_dac_start(struct cmi_info *cmi, struct cmi_chinfo *ch) 230 { 231 if (ch->dma_configured == 0) { 232 u_int32_t s, i, sz; 233 ch->phys_buf = vtophys(sndbuf_getbuf(ch->buffer)); 234 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 235 s = (sz + 1) / ch->bps - 1; 236 i = (sz + 1) / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 237 cmi_wr(cmi, CMPCI_REG_DMA0_BASE, ch->phys_buf, 4); 238 cmi_wr(cmi, CMPCI_REG_DMA0_MAX_SAMPLES, s, 2); 239 cmi_wr(cmi, CMPCI_REG_DMA0_INTR_SAMPLES, i, 2); 240 ch->dma_configured = 1; 241 DEB(printf("cmi_dac_start: dma prog\n")); 242 } 243 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 244 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_PAUSE); 245 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 246 cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 247 } 248 249 static void 250 cmi_dac_stop(struct cmi_info *cmi) 251 { 252 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 253 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 254 } 255 256 static void 257 cmi_dac_reset(struct cmi_info *cmi, struct cmi_chinfo *ch) 258 { 259 cmi_dac_stop(cmi); 260 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 261 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 262 ch->dma_configured = 0; 263 DEB(printf("cmi_dac_reset\n")); 264 } 265 266 static void 267 cmi_adc_start(struct cmi_info *cmi, struct cmi_chinfo *ch) 268 { 269 if (ch->dma_configured == 0) { 270 u_int32_t s, i, sz; 271 ch->phys_buf = vtophys(sndbuf_getbuf(ch->buffer)); 272 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 273 s = (sz + 1) / ch->bps - 1; 274 i = (sz + 1) / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 275 276 cmi_wr(cmi, CMPCI_REG_DMA1_BASE, ch->phys_buf, 4); 277 cmi_wr(cmi, CMPCI_REG_DMA1_MAX_SAMPLES, s, 2); 278 cmi_wr(cmi, CMPCI_REG_DMA1_INTR_SAMPLES, i, 2); 279 ch->dma_configured = 1; 280 DEB(printf("cmi_adc_start: dma prog\n")); 281 } 282 283 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 284 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_PAUSE); 285 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 286 cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 287 } 288 289 static void 290 cmi_adc_stop(struct cmi_info *cmi) 291 { 292 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 293 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 294 } 295 296 static void 297 cmi_adc_reset(struct cmi_info *cmi, struct cmi_chinfo *ch) 298 { 299 cmi_adc_stop(cmi); 300 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 301 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 302 ch->dma_configured = 0; 303 DEB(printf("cmi_adc_reset\n")); 304 } 305 306 static void 307 cmi_spdif_speed(struct cmi_info *cmi, int speed) { 308 u_int32_t fcr1, lcr, mcr; 309 310 mcr = 0; 311 312 if (speed >= 44100) { 313 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 314 lcr = CMPCI_REG_XSPDIF_ENABLE; 315 mcr = (speed == 48000) ? 316 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 317 } else { 318 fcr1 = mcr = lcr = 0; 319 } 320 321 cmi_partial_wr4(cmi, CMPCI_REG_FUNC_1, 0, 322 CMPCI_REG_SPDIF0_ENABLE, fcr1); 323 cmi_partial_wr4(cmi, CMPCI_REG_MISC, 0, 324 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 325 cmi_partial_wr4(cmi, CMPCI_REG_LEGACY_CTRL, 0, 326 CMPCI_REG_XSPDIF_ENABLE, lcr); 327 } 328 329 /* ------------------------------------------------------------------------- */ 330 /* Channel Interface implementation */ 331 332 static void * 333 cmichan_init(kobj_t obj, void *devinfo, snd_dbuf *b, pcm_channel *c, int dir) 334 { 335 struct cmi_info *cmi = devinfo; 336 struct cmi_chinfo *ch = (dir == PCMDIR_PLAY) ? &cmi->pch : &cmi->rch; 337 338 ch->parent = cmi; 339 ch->channel = c; 340 ch->bps = 1; 341 ch->fmt = AFMT_U8; 342 ch->spd = DSP_DEFAULT_SPEED; 343 ch->dma_configured = 0; 344 ch->buffer = b; 345 if (sndbuf_alloc(ch->buffer, cmi->parent_dmat, CMI_BUFFER_SIZE) != 0) { 346 DEB(printf("cmichan_init failed\n")); 347 return NULL; 348 } 349 350 ch->dir = dir; 351 if (dir == PCMDIR_PLAY) { 352 cmi_clr4(ch->parent, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 353 } else { 354 cmi_set4(ch->parent, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 355 } 356 357 return ch; 358 } 359 360 static int 361 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 362 { 363 struct cmi_chinfo *ch = data; 364 u_int32_t f; 365 366 if (format & AFMT_S16_LE) { 367 f = CMPCI_REG_FORMAT_16BIT; 368 ch->bps = 2; 369 } else { 370 f = CMPCI_REG_FORMAT_8BIT; 371 ch->bps = 1; 372 } 373 374 if (format & AFMT_STEREO) { 375 f |= CMPCI_REG_FORMAT_STEREO; 376 ch->bps *= 2; 377 } else { 378 f |= CMPCI_REG_FORMAT_MONO; 379 } 380 381 if (ch->dir == PCMDIR_PLAY) { 382 cmi_partial_wr4(ch->parent, 383 CMPCI_REG_CHANNEL_FORMAT, 384 CMPCI_REG_CH0_FORMAT_SHIFT, 385 CMPCI_REG_CH0_FORMAT_MASK, 386 f); 387 } else { 388 cmi_partial_wr4(ch->parent, 389 CMPCI_REG_CHANNEL_FORMAT, 390 CMPCI_REG_CH1_FORMAT_SHIFT, 391 CMPCI_REG_CH1_FORMAT_MASK, 392 f); 393 } 394 ch->fmt = format; 395 ch->dma_configured = 0; 396 397 return 0; 398 } 399 400 static int 401 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 402 { 403 struct cmi_chinfo *ch = data; 404 u_int32_t r, rsp; 405 406 r = cmpci_rate_to_regvalue(speed); 407 if (ch->dir == PCMDIR_PLAY) { 408 if (speed < 44100) /* disable if req before rate change */ 409 cmi_spdif_speed(ch->parent, speed); 410 cmi_partial_wr4(ch->parent, 411 CMPCI_REG_FUNC_1, 412 CMPCI_REG_DAC_FS_SHIFT, 413 CMPCI_REG_DAC_FS_MASK, 414 r); 415 if (speed >= 44100) /* enable if req after rate change */ 416 cmi_spdif_speed(ch->parent, speed); 417 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 418 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 419 rsp &= CMPCI_REG_DAC_FS_MASK; 420 } else { 421 cmi_partial_wr4(ch->parent, 422 CMPCI_REG_FUNC_1, 423 CMPCI_REG_ADC_FS_SHIFT, 424 CMPCI_REG_ADC_FS_MASK, 425 r); 426 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 427 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 428 rsp &= CMPCI_REG_ADC_FS_MASK; 429 } 430 ch->spd = cmpci_regvalue_to_rate(r); 431 432 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 433 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 434 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 435 436 return ch->spd; 437 } 438 439 static int 440 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 441 { 442 struct cmi_chinfo *ch = data; 443 444 /* user has requested interrupts every blocksize bytes */ 445 if (blocksize > CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER) { 446 blocksize = CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER; 447 } 448 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 449 450 ch->dma_configured = 0; 451 return sndbuf_getsize(ch->buffer); 452 } 453 454 static int 455 cmichan_trigger(kobj_t obj, void *data, int go) 456 { 457 struct cmi_chinfo *ch = data; 458 struct cmi_info *cmi = ch->parent; 459 460 if (ch->dir == PCMDIR_PLAY) { 461 switch(go) { 462 case PCMTRIG_START: 463 cmi_dac_start(cmi, ch); 464 break; 465 case PCMTRIG_ABORT: 466 cmi_dac_reset(cmi, ch); 467 break; 468 } 469 } else { 470 switch(go) { 471 case PCMTRIG_START: 472 cmi_adc_start(cmi, ch); 473 break; 474 case PCMTRIG_ABORT: 475 cmi_adc_reset(cmi, ch); 476 break; 477 } 478 } 479 return 0; 480 } 481 482 static int 483 cmichan_getptr(kobj_t obj, void *data) 484 { 485 struct cmi_chinfo *ch = data; 486 struct cmi_info *cmi = ch->parent; 487 u_int32_t physptr, bufptr, sz; 488 489 if (ch->dir == PCMDIR_PLAY) { 490 physptr = cmi_rd(cmi, CMPCI_REG_DMA0_BASE, 4); 491 } else { 492 physptr = cmi_rd(cmi, CMPCI_REG_DMA1_BASE, 4); 493 } 494 495 sz = sndbuf_getsize(ch->buffer); 496 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 497 498 return bufptr; 499 } 500 501 static void 502 cmi_intr(void *data) 503 { 504 struct cmi_info *cmi = data; 505 u_int32_t intrstat; 506 507 intrstat = cmi_rd(cmi, CMPCI_REG_INTR_STATUS, 4); 508 if ((intrstat & CMPCI_REG_ANY_INTR) == 0) { 509 return; 510 } 511 512 /* Disable interrupts */ 513 if (intrstat & CMPCI_REG_CH0_INTR) { 514 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 515 } 516 517 if (intrstat & CMPCI_REG_CH1_INTR) { 518 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 519 } 520 521 DEB(printf("cmi_intr - play %d rec %d\n", 522 intrstat & CMPCI_REG_CH0_INTR, 523 (intrstat & CMPCI_REG_CH1_INTR)>>1)); 524 525 /* Signal interrupts to channel */ 526 if (intrstat & CMPCI_REG_CH0_INTR) { 527 chn_intr(cmi->pch.channel); 528 } 529 530 if (intrstat & CMPCI_REG_CH1_INTR) { 531 chn_intr(cmi->rch.channel); 532 } 533 534 /* Enable interrupts */ 535 if (intrstat & CMPCI_REG_CH0_INTR) { 536 cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 537 } 538 539 if (intrstat & CMPCI_REG_CH1_INTR) { 540 cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 541 } 542 543 return; 544 } 545 546 static pcmchan_caps * 547 cmichan_getcaps(kobj_t obj, void *data) 548 { 549 return &cmi_caps; 550 } 551 552 static kobj_method_t cmichan_methods[] = { 553 KOBJMETHOD(channel_init, cmichan_init), 554 KOBJMETHOD(channel_setformat, cmichan_setformat), 555 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 556 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 557 KOBJMETHOD(channel_trigger, cmichan_trigger), 558 KOBJMETHOD(channel_getptr, cmichan_getptr), 559 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 560 { 0, 0 } 561 }; 562 CHANNEL_DECLARE(cmichan); 563 564 /* ------------------------------------------------------------------------- */ 565 /* Mixer - sb16 with kinks */ 566 567 static void 568 cmimix_wr(struct cmi_info *cmi, u_int8_t port, u_int8_t val) 569 { 570 cmi_wr(cmi, CMPCI_REG_SBADDR, port, 1); 571 cmi_wr(cmi, CMPCI_REG_SBDATA, val, 1); 572 } 573 574 static u_int8_t 575 cmimix_rd(struct cmi_info *cmi, u_int8_t port) 576 { 577 cmi_wr(cmi, CMPCI_REG_SBADDR, port, 1); 578 return (u_int8_t)cmi_rd(cmi, CMPCI_REG_SBDATA, 1); 579 } 580 581 struct sb16props { 582 u_int8_t rreg; /* right reg chan register */ 583 u_int8_t stereo:1; /* (no explanation needed, honest) */ 584 u_int8_t rec:1; /* recording source */ 585 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 586 u_int8_t oselect; /* output select mask */ 587 u_int8_t iselect; /* right input select mask */ 588 } static const cmt[SOUND_MIXER_NRDEVICES] = { 589 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 590 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 591 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 592 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 593 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 594 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 595 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 596 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 597 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 598 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 599 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 600 /* These controls are not implemented in CMI8738, but maybe at a 601 future date. They are not documented in C-Media documentation, 602 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 603 */ 604 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 605 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 606 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 607 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 608 /* The mic pre-amp is implemented with non-SB16 compatible registers. */ 609 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 610 }; 611 612 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 613 614 static int 615 cmimix_init(snd_mixer *m) 616 { 617 struct cmi_info *cmi = mix_getdevinfo(m); 618 u_int32_t i,v; 619 620 v = 0; 621 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 622 if (cmt[i].bits) v |= 1 << i; 623 } 624 mix_setdevs(m, v); 625 v = 0; 626 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 627 if (cmt[i].rec) v |= 1 << i; 628 } 629 mix_setrecdevs(m, v); 630 631 cmimix_wr(cmi, CMPCI_SB16_MIXER_RESET, 0); 632 cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_L, 0); 633 cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_R, 0); 634 cmimix_wr(cmi, CMPCI_SB16_MIXER_OUTMIX, 635 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 636 return 0; 637 } 638 639 static int 640 cmimix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right) 641 { 642 struct cmi_info *cmi = mix_getdevinfo(m); 643 u_int32_t r, l, max; 644 u_int8_t v; 645 646 max = (1 << cmt[dev].bits) - 1; 647 648 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 649 /* For time being this can only be one thing (mic in mic/aux reg) */ 650 u_int8_t v; 651 v = cmi_rd(cmi, CMPCI_REG_AUX_MIC, 1) & 0xf0; 652 l = left * max / 100; 653 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value*/ 654 v |= ((l << 1) | (~l >> 3)) & 0x0f; 655 cmi_wr(cmi, CMPCI_REG_AUX_MIC, v, 1); 656 return 0; 657 } 658 659 l = (left * max / 100) << (8 - cmt[dev].bits); 660 if (cmt[dev].stereo) { 661 r = (right * max / 100) << (8 - cmt[dev].bits); 662 cmimix_wr(cmi, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 663 cmimix_wr(cmi, cmt[dev].rreg, r); 664 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 665 "value 0x%02x:0x%02x\n", 666 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 667 } else { 668 r = l; 669 cmimix_wr(cmi, cmt[dev].rreg, l); 670 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 671 "value 0x%02x:0x%02x\n", 672 dev, cmt[dev].rreg, l, l)); 673 } 674 675 /* Zero gain does not mute channel from output, but this does... */ 676 v = cmimix_rd(cmi, CMPCI_SB16_MIXER_OUTMIX); 677 if (l == 0 && r == 0) { 678 v &= ~cmt[dev].oselect; 679 } else { 680 v |= cmt[dev].oselect; 681 } 682 cmimix_wr(cmi, CMPCI_SB16_MIXER_OUTMIX, v); 683 684 return 0; 685 } 686 687 static int 688 cmimix_setrecsrc(snd_mixer *m, u_int32_t src) 689 { 690 struct cmi_info *cmi = mix_getdevinfo(m); 691 u_int32_t i, ml, sl; 692 693 ml = sl = 0; 694 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 695 if ((1<<i) & src) { 696 if (cmt[i].stereo) { 697 sl |= cmt[i].iselect; 698 } else { 699 ml |= cmt[i].iselect; 700 } 701 } 702 } 703 cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 704 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 705 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 706 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 707 cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 708 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 709 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 710 711 return src; 712 } 713 714 static kobj_method_t cmi_mixer_methods[] = { 715 KOBJMETHOD(mixer_init, cmimix_init), 716 KOBJMETHOD(mixer_set, cmimix_set), 717 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 718 { 0, 0 } 719 }; 720 MIXER_DECLARE(cmi_mixer); 721 722 /* ------------------------------------------------------------------------- */ 723 /* Power and reset */ 724 725 static void 726 cmi_power(struct cmi_info *cmi, int state) 727 { 728 switch (state) { 729 case 0: /* full power */ 730 cmi_clr4(cmi, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 731 break; 732 default: 733 /* power off */ 734 cmi_set4(cmi, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 735 break; 736 } 737 } 738 739 /* ------------------------------------------------------------------------- */ 740 /* Bus and device registration */ 741 static int 742 cmi_probe(device_t dev) 743 { 744 switch(pci_get_devid(dev)) { 745 case CMI8338A_PCI_ID: 746 device_set_desc(dev, "CMedia CMI8338A"); 747 return 0; 748 case CMI8338B_PCI_ID: 749 device_set_desc(dev, "CMedia CMI8338B"); 750 return 0; 751 case CMI8738_PCI_ID: 752 device_set_desc(dev, "CMedia CMI8738"); 753 return 0; 754 case CMI8738B_PCI_ID: 755 device_set_desc(dev, "CMedia CMI8738B"); 756 return 0; 757 default: 758 return ENXIO; 759 } 760 } 761 762 static int 763 cmi_attach(device_t dev) 764 { 765 snddev_info *d; 766 struct cmi_info *cmi; 767 u_int32_t data; 768 char status[SND_STATUSLEN]; 769 770 d = device_get_softc(dev); 771 772 if ((cmi = malloc(sizeof(struct cmi_info), M_DEVBUF, M_NOWAIT)) == NULL) { 773 device_printf(dev, "cannot allocate softc\n"); 774 return ENXIO; 775 } 776 777 bzero(cmi, sizeof(*cmi)); 778 779 data = pci_read_config(dev, PCIR_COMMAND, 2); 780 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 781 pci_write_config(dev, PCIR_COMMAND, data, 2); 782 data = pci_read_config(dev, PCIR_COMMAND, 2); 783 784 cmi->regid = PCIR_MAPS; 785 cmi->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &cmi->regid, 786 0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE); 787 if (!cmi->reg) { 788 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 789 goto bad; 790 } 791 cmi->st = rman_get_bustag(cmi->reg); 792 cmi->sh = rman_get_bushandle(cmi->reg); 793 794 cmi->irqid = 0; 795 cmi->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &cmi->irqid, 796 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 797 if (!cmi->irq || 798 bus_setup_intr(dev, cmi->irq, INTR_TYPE_TTY, cmi_intr, cmi, &cmi->ih)){ 799 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 800 goto bad; 801 } 802 803 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 804 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 805 /*highaddr*/BUS_SPACE_MAXADDR, 806 /*filter*/NULL, /*filterarg*/NULL, 807 /*maxsize*/CMI_BUFFER_SIZE, /*nsegments*/1, 808 /*maxsegz*/0x3ffff, /*flags*/0, 809 &cmi->parent_dmat) != 0) { 810 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 811 goto bad; 812 } 813 814 cmi_power(cmi, 0); 815 /* Disable interrupts and channels */ 816 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, 817 CMPCI_REG_CH0_INTR_ENABLE | 818 CMPCI_REG_CH1_INTR_ENABLE | 819 CMPCI_REG_TDMA_INTR_ENABLE); 820 cmi_clr4(cmi, CMPCI_REG_FUNC_0, 821 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 822 823 mixer_init(dev, &cmi_mixer_class, cmi); 824 825 if (pcm_register(dev, cmi, 1, 1)) 826 goto bad; 827 828 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, cmi); 829 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, cmi); 830 831 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld", 832 rman_get_start(cmi->reg), rman_get_start(cmi->irq)); 833 pcm_setstatus(dev, status); 834 835 DEB(printf("cmi_attach: succeeded\n")); 836 return 0; 837 838 bad: 839 if (cmi->parent_dmat) bus_dma_tag_destroy(cmi->parent_dmat); 840 if (cmi->ih) bus_teardown_intr(dev, cmi->irq, cmi->ih); 841 if (cmi->irq) bus_release_resource(dev, SYS_RES_IRQ, cmi->irqid, cmi->irq); 842 if (cmi->reg) bus_release_resource(dev, SYS_RES_IOPORT, 843 cmi->regid, cmi->reg); 844 if (cmi) free(cmi, M_DEVBUF); 845 846 return ENXIO; 847 } 848 849 static int 850 cmi_detach(device_t dev) 851 { 852 struct cmi_info *cmi; 853 int r; 854 855 r = pcm_unregister(dev); 856 if (r) return r; 857 858 cmi = pcm_getdevinfo(dev); 859 cmi_power(cmi, 3); 860 bus_dma_tag_destroy(cmi->parent_dmat); 861 bus_teardown_intr(dev, cmi->irq, cmi->ih); 862 bus_release_resource(dev, SYS_RES_IRQ, cmi->irqid, cmi->irq); 863 bus_release_resource(dev, SYS_RES_IOPORT, cmi->regid, cmi->reg); 864 free(cmi, M_DEVBUF); 865 866 return 0; 867 } 868 869 static device_method_t cmi_methods[] = { 870 DEVMETHOD(device_probe, cmi_probe), 871 DEVMETHOD(device_attach, cmi_attach), 872 DEVMETHOD(device_detach, cmi_detach), 873 DEVMETHOD(device_resume, bus_generic_resume), 874 DEVMETHOD(device_suspend, bus_generic_suspend), 875 { 0, 0 } 876 }; 877 878 static driver_t cmi_driver = { 879 "pcm", 880 cmi_methods, 881 sizeof(snddev_info) 882 }; 883 884 static devclass_t pcm_devclass; 885 DRIVER_MODULE(snd_cmipci, pci, cmi_driver, pcm_devclass, 0, 0); 886 MODULE_DEPEND(snd_cmipci, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 887 MODULE_VERSION(snd_cmipci, 1); 888