1 /*- 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This driver exists largely as a result of other people's efforts. 29 * Much of register handling is based on NetBSD CMI8x38 audio driver 30 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 31 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 32 * registers and the 8738 mixer devices. His Linux driver was also a 33 * useful reference point. 34 * 35 * TODO: MIDI 36 * 37 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 38 * 39 * This card/code does not always manage to sample at 44100 - actual 40 * rate drifts slightly between recordings (usually 0-3%). No 41 * differences visible in register dumps between times that work and 42 * those that don't. 43 */ 44 45 #ifdef HAVE_KERNEL_OPTION_HEADERS 46 #include "opt_snd.h" 47 #endif 48 49 #include <dev/sound/pcm/sound.h> 50 #include <dev/sound/pci/cmireg.h> 51 #include <dev/sound/isa/sb.h> 52 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcivar.h> 55 56 #include <sys/sysctl.h> 57 #include <dev/sound/midi/mpu401.h> 58 59 #include "mixer_if.h" 60 #include "mpufoi_if.h" 61 62 SND_DECLARE_FILE("$FreeBSD$"); 63 64 /* Supported chip ID's */ 65 #define CMI8338A_PCI_ID 0x010013f6 66 #define CMI8338B_PCI_ID 0x010113f6 67 #define CMI8738_PCI_ID 0x011113f6 68 #define CMI8738B_PCI_ID 0x011213f6 69 #define CMI120_USB_ID 0x01030d8c 70 71 /* Buffer size max is 64k for permitted DMA boundaries */ 72 #define CMI_DEFAULT_BUFSZ 16384 73 74 /* Interrupts per length of buffer */ 75 #define CMI_INTR_PER_BUFFER 2 76 77 /* Clarify meaning of named defines in cmireg.h */ 78 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 79 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 80 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 81 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 82 83 /* Our indication of custom mixer control */ 84 #define CMPCI_NON_SB16_CONTROL 0xff 85 86 /* Debugging macro's */ 87 #undef DEB 88 #ifndef DEB 89 #define DEB(x) /* x */ 90 #endif /* DEB */ 91 92 #ifndef DEBMIX 93 #define DEBMIX(x) /* x */ 94 #endif /* DEBMIX */ 95 96 /* ------------------------------------------------------------------------- */ 97 /* Structures */ 98 99 struct sc_info; 100 101 struct sc_chinfo { 102 struct sc_info *parent; 103 struct pcm_channel *channel; 104 struct snd_dbuf *buffer; 105 u_int32_t fmt, spd, phys_buf, bps; 106 u_int32_t dma_active:1, dma_was_active:1; 107 int dir; 108 }; 109 110 struct sc_info { 111 device_t dev; 112 113 bus_space_tag_t st; 114 bus_space_handle_t sh; 115 bus_dma_tag_t parent_dmat; 116 struct resource *reg, *irq; 117 int regid, irqid; 118 void *ih; 119 struct mtx *lock; 120 121 int spdif_enabled; 122 unsigned int bufsz; 123 struct sc_chinfo pch, rch; 124 125 struct mpu401 *mpu; 126 mpu401_intr_t *mpu_intr; 127 struct resource *mpu_reg; 128 int mpu_regid; 129 bus_space_tag_t mpu_bt; 130 bus_space_handle_t mpu_bh; 131 }; 132 133 /* Channel caps */ 134 135 static u_int32_t cmi_fmt[] = { 136 SND_FORMAT(AFMT_U8, 1, 0), 137 SND_FORMAT(AFMT_U8, 2, 0), 138 SND_FORMAT(AFMT_S16_LE, 1, 0), 139 SND_FORMAT(AFMT_S16_LE, 2, 0), 140 0 141 }; 142 143 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 144 145 /* ------------------------------------------------------------------------- */ 146 /* Register Utilities */ 147 148 static u_int32_t 149 cmi_rd(struct sc_info *sc, int regno, int size) 150 { 151 switch (size) { 152 case 1: 153 return bus_space_read_1(sc->st, sc->sh, regno); 154 case 2: 155 return bus_space_read_2(sc->st, sc->sh, regno); 156 case 4: 157 return bus_space_read_4(sc->st, sc->sh, regno); 158 default: 159 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 160 return 0xFFFFFFFF; 161 } 162 } 163 164 static void 165 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 166 { 167 switch (size) { 168 case 1: 169 bus_space_write_1(sc->st, sc->sh, regno, data); 170 break; 171 case 2: 172 bus_space_write_2(sc->st, sc->sh, regno, data); 173 break; 174 case 4: 175 bus_space_write_4(sc->st, sc->sh, regno, data); 176 break; 177 } 178 } 179 180 static void 181 cmi_partial_wr4(struct sc_info *sc, 182 int reg, int shift, u_int32_t mask, u_int32_t val) 183 { 184 u_int32_t r; 185 186 r = cmi_rd(sc, reg, 4); 187 r &= ~(mask << shift); 188 r |= val << shift; 189 cmi_wr(sc, reg, r, 4); 190 } 191 192 static void 193 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 194 { 195 u_int32_t r; 196 197 r = cmi_rd(sc, reg, 4); 198 r &= ~mask; 199 cmi_wr(sc, reg, r, 4); 200 } 201 202 static void 203 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 204 { 205 u_int32_t r; 206 207 r = cmi_rd(sc, reg, 4); 208 r |= mask; 209 cmi_wr(sc, reg, r, 4); 210 } 211 212 /* ------------------------------------------------------------------------- */ 213 /* Rate Mapping */ 214 215 static int cmi_rates[] = {5512, 8000, 11025, 16000, 216 22050, 32000, 44100, 48000}; 217 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 218 219 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 220 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 221 222 static u_int32_t 223 cmpci_rate_to_regvalue(int rate) 224 { 225 int i, r; 226 227 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 228 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 229 break; 230 } 231 } 232 233 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 234 235 r = ((i >> 1) | (i << 2)) & 0x07; 236 return r; 237 } 238 239 static int 240 cmpci_regvalue_to_rate(u_int32_t r) 241 { 242 int i; 243 244 i = ((r << 1) | (r >> 2)) & 0x07; 245 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 246 return cmi_rates[i]; 247 } 248 249 /* ------------------------------------------------------------------------- */ 250 /* ADC/DAC control - there are 2 dma channels on 8738, either can be 251 * playback or capture. We use ch0 for playback and ch1 for capture. */ 252 253 static void 254 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 255 { 256 u_int32_t s, i, sz; 257 258 ch->phys_buf = sndbuf_getbufaddr(ch->buffer); 259 260 cmi_wr(sc, base, ch->phys_buf, 4); 261 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 262 263 s = sz / ch->bps - 1; 264 cmi_wr(sc, base + 4, s, 2); 265 266 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 267 cmi_wr(sc, base + 6, i, 2); 268 } 269 270 271 static void 272 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 273 { 274 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 275 276 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 277 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 278 CMPCI_REG_CH0_INTR_ENABLE); 279 280 ch->dma_active = 1; 281 } 282 283 static u_int32_t 284 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 285 { 286 u_int32_t r = ch->dma_active; 287 288 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 289 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 290 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 291 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 292 ch->dma_active = 0; 293 return r; 294 } 295 296 static void 297 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 298 { 299 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 300 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 301 /* Enable Interrupts */ 302 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 303 CMPCI_REG_CH1_INTR_ENABLE); 304 DEB(printf("cmi_ch1_start: dma prog\n")); 305 ch->dma_active = 1; 306 } 307 308 static u_int32_t 309 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 310 { 311 u_int32_t r = ch->dma_active; 312 313 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 314 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 315 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 316 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 317 ch->dma_active = 0; 318 return r; 319 } 320 321 static void 322 cmi_spdif_speed(struct sc_info *sc, int speed) { 323 u_int32_t fcr1, lcr, mcr; 324 325 if (speed >= 44100) { 326 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 327 lcr = CMPCI_REG_XSPDIF_ENABLE; 328 mcr = (speed == 48000) ? 329 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 330 } else { 331 fcr1 = mcr = lcr = 0; 332 } 333 334 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 335 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 336 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 337 CMPCI_REG_SPDIF0_ENABLE, fcr1); 338 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 339 CMPCI_REG_XSPDIF_ENABLE, lcr); 340 } 341 342 /* ------------------------------------------------------------------------- */ 343 /* Channel Interface implementation */ 344 345 static void * 346 cmichan_init(kobj_t obj, void *devinfo, 347 struct snd_dbuf *b, struct pcm_channel *c, int dir) 348 { 349 struct sc_info *sc = devinfo; 350 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 351 352 ch->parent = sc; 353 ch->channel = c; 354 ch->bps = 1; 355 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 356 ch->spd = DSP_DEFAULT_SPEED; 357 ch->buffer = b; 358 ch->dma_active = 0; 359 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 360 DEB(printf("cmichan_init failed\n")); 361 return NULL; 362 } 363 364 ch->dir = dir; 365 snd_mtxlock(sc->lock); 366 if (ch->dir == PCMDIR_PLAY) { 367 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 368 } else { 369 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 370 } 371 snd_mtxunlock(sc->lock); 372 373 return ch; 374 } 375 376 static int 377 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 378 { 379 struct sc_chinfo *ch = data; 380 struct sc_info *sc = ch->parent; 381 u_int32_t f; 382 383 if (format & AFMT_S16_LE) { 384 f = CMPCI_REG_FORMAT_16BIT; 385 ch->bps = 2; 386 } else { 387 f = CMPCI_REG_FORMAT_8BIT; 388 ch->bps = 1; 389 } 390 391 if (AFMT_CHANNEL(format) > 1) { 392 f |= CMPCI_REG_FORMAT_STEREO; 393 ch->bps *= 2; 394 } else { 395 f |= CMPCI_REG_FORMAT_MONO; 396 } 397 398 snd_mtxlock(sc->lock); 399 if (ch->dir == PCMDIR_PLAY) { 400 cmi_partial_wr4(ch->parent, 401 CMPCI_REG_CHANNEL_FORMAT, 402 CMPCI_REG_CH0_FORMAT_SHIFT, 403 CMPCI_REG_CH0_FORMAT_MASK, 404 f); 405 } else { 406 cmi_partial_wr4(ch->parent, 407 CMPCI_REG_CHANNEL_FORMAT, 408 CMPCI_REG_CH1_FORMAT_SHIFT, 409 CMPCI_REG_CH1_FORMAT_MASK, 410 f); 411 } 412 snd_mtxunlock(sc->lock); 413 ch->fmt = format; 414 415 return 0; 416 } 417 418 static u_int32_t 419 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 420 { 421 struct sc_chinfo *ch = data; 422 struct sc_info *sc = ch->parent; 423 u_int32_t r, rsp; 424 425 r = cmpci_rate_to_regvalue(speed); 426 snd_mtxlock(sc->lock); 427 if (ch->dir == PCMDIR_PLAY) { 428 if (speed < 44100) { 429 /* disable if req before rate change */ 430 cmi_spdif_speed(ch->parent, speed); 431 } 432 cmi_partial_wr4(ch->parent, 433 CMPCI_REG_FUNC_1, 434 CMPCI_REG_DAC_FS_SHIFT, 435 CMPCI_REG_DAC_FS_MASK, 436 r); 437 if (speed >= 44100 && ch->parent->spdif_enabled) { 438 /* enable if req after rate change */ 439 cmi_spdif_speed(ch->parent, speed); 440 } 441 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 442 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 443 rsp &= CMPCI_REG_DAC_FS_MASK; 444 } else { 445 cmi_partial_wr4(ch->parent, 446 CMPCI_REG_FUNC_1, 447 CMPCI_REG_ADC_FS_SHIFT, 448 CMPCI_REG_ADC_FS_MASK, 449 r); 450 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 451 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 452 rsp &= CMPCI_REG_ADC_FS_MASK; 453 } 454 snd_mtxunlock(sc->lock); 455 ch->spd = cmpci_regvalue_to_rate(r); 456 457 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 458 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 459 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 460 461 return ch->spd; 462 } 463 464 static u_int32_t 465 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 466 { 467 struct sc_chinfo *ch = data; 468 struct sc_info *sc = ch->parent; 469 470 /* user has requested interrupts every blocksize bytes */ 471 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 472 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 473 } 474 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 475 476 return blocksize; 477 } 478 479 static int 480 cmichan_trigger(kobj_t obj, void *data, int go) 481 { 482 struct sc_chinfo *ch = data; 483 struct sc_info *sc = ch->parent; 484 485 if (!PCMTRIG_COMMON(go)) 486 return 0; 487 488 snd_mtxlock(sc->lock); 489 if (ch->dir == PCMDIR_PLAY) { 490 switch(go) { 491 case PCMTRIG_START: 492 cmi_ch0_start(sc, ch); 493 break; 494 case PCMTRIG_STOP: 495 case PCMTRIG_ABORT: 496 cmi_ch0_stop(sc, ch); 497 break; 498 } 499 } else { 500 switch(go) { 501 case PCMTRIG_START: 502 cmi_ch1_start(sc, ch); 503 break; 504 case PCMTRIG_STOP: 505 case PCMTRIG_ABORT: 506 cmi_ch1_stop(sc, ch); 507 break; 508 } 509 } 510 snd_mtxunlock(sc->lock); 511 return 0; 512 } 513 514 static u_int32_t 515 cmichan_getptr(kobj_t obj, void *data) 516 { 517 struct sc_chinfo *ch = data; 518 struct sc_info *sc = ch->parent; 519 u_int32_t physptr, bufptr, sz; 520 521 snd_mtxlock(sc->lock); 522 if (ch->dir == PCMDIR_PLAY) { 523 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 524 } else { 525 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 526 } 527 snd_mtxunlock(sc->lock); 528 529 sz = sndbuf_getsize(ch->buffer); 530 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 531 532 return bufptr; 533 } 534 535 static void 536 cmi_intr(void *data) 537 { 538 struct sc_info *sc = data; 539 u_int32_t intrstat; 540 u_int32_t toclear; 541 542 snd_mtxlock(sc->lock); 543 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 544 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) { 545 546 toclear = 0; 547 if (intrstat & CMPCI_REG_CH0_INTR) { 548 toclear |= CMPCI_REG_CH0_INTR_ENABLE; 549 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 550 } 551 552 if (intrstat & CMPCI_REG_CH1_INTR) { 553 toclear |= CMPCI_REG_CH1_INTR_ENABLE; 554 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 555 } 556 557 if (toclear) { 558 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear); 559 snd_mtxunlock(sc->lock); 560 561 /* Signal interrupts to channel */ 562 if (intrstat & CMPCI_REG_CH0_INTR) { 563 chn_intr(sc->pch.channel); 564 } 565 566 if (intrstat & CMPCI_REG_CH1_INTR) { 567 chn_intr(sc->rch.channel); 568 } 569 570 snd_mtxlock(sc->lock); 571 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear); 572 573 } 574 } 575 if(sc->mpu_intr) { 576 (sc->mpu_intr)(sc->mpu); 577 } 578 snd_mtxunlock(sc->lock); 579 return; 580 } 581 582 static struct pcmchan_caps * 583 cmichan_getcaps(kobj_t obj, void *data) 584 { 585 return &cmi_caps; 586 } 587 588 static kobj_method_t cmichan_methods[] = { 589 KOBJMETHOD(channel_init, cmichan_init), 590 KOBJMETHOD(channel_setformat, cmichan_setformat), 591 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 592 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 593 KOBJMETHOD(channel_trigger, cmichan_trigger), 594 KOBJMETHOD(channel_getptr, cmichan_getptr), 595 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 596 KOBJMETHOD_END 597 }; 598 CHANNEL_DECLARE(cmichan); 599 600 /* ------------------------------------------------------------------------- */ 601 /* Mixer - sb16 with kinks */ 602 603 static void 604 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 605 { 606 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 607 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 608 } 609 610 static u_int8_t 611 cmimix_rd(struct sc_info *sc, u_int8_t port) 612 { 613 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 614 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 615 } 616 617 struct sb16props { 618 u_int8_t rreg; /* right reg chan register */ 619 u_int8_t stereo:1; /* (no explanation needed, honest) */ 620 u_int8_t rec:1; /* recording source */ 621 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 622 u_int8_t oselect; /* output select mask */ 623 u_int8_t iselect; /* right input select mask */ 624 } static const cmt[SOUND_MIXER_NRDEVICES] = { 625 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 626 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 627 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 628 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 629 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 630 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 631 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 632 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 633 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 634 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 635 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 636 /* These controls are not implemented in CMI8738, but maybe at a 637 future date. They are not documented in C-Media documentation, 638 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 639 */ 640 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 641 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 642 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 643 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 644 /* The mic pre-amp is implemented with non-SB16 compatible 645 registers. */ 646 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 647 }; 648 649 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 650 651 static int 652 cmimix_init(struct snd_mixer *m) 653 { 654 struct sc_info *sc = mix_getdevinfo(m); 655 u_int32_t i,v; 656 657 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 658 if (cmt[i].bits) v |= 1 << i; 659 } 660 mix_setdevs(m, v); 661 662 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 663 if (cmt[i].rec) v |= 1 << i; 664 } 665 mix_setrecdevs(m, v); 666 667 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 668 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 669 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 670 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 671 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 672 return 0; 673 } 674 675 static int 676 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 677 { 678 struct sc_info *sc = mix_getdevinfo(m); 679 u_int32_t r, l, max; 680 u_int8_t v; 681 682 max = (1 << cmt[dev].bits) - 1; 683 684 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 685 /* For time being this can only be one thing (mic in 686 * mic/aux reg) */ 687 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 688 l = left * max / 100; 689 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 690 v |= ((l << 1) | (~l >> 3)) & 0x0f; 691 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 692 return 0; 693 } 694 695 l = (left * max / 100) << (8 - cmt[dev].bits); 696 if (cmt[dev].stereo) { 697 r = (right * max / 100) << (8 - cmt[dev].bits); 698 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 699 cmimix_wr(sc, cmt[dev].rreg, r); 700 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 701 "value 0x%02x:0x%02x\n", 702 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 703 } else { 704 r = l; 705 cmimix_wr(sc, cmt[dev].rreg, l); 706 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 707 "value 0x%02x:0x%02x\n", 708 dev, cmt[dev].rreg, l, l)); 709 } 710 711 /* Zero gain does not mute channel from output, but this does... */ 712 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 713 if (l == 0 && r == 0) { 714 v &= ~cmt[dev].oselect; 715 } else { 716 v |= cmt[dev].oselect; 717 } 718 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 719 720 return 0; 721 } 722 723 static u_int32_t 724 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 725 { 726 struct sc_info *sc = mix_getdevinfo(m); 727 u_int32_t i, ml, sl; 728 729 ml = sl = 0; 730 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 731 if ((1<<i) & src) { 732 if (cmt[i].stereo) { 733 sl |= cmt[i].iselect; 734 } else { 735 ml |= cmt[i].iselect; 736 } 737 } 738 } 739 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 740 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 741 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 742 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 743 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 744 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 745 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 746 747 return src; 748 } 749 750 /* Optional SPDIF support. */ 751 752 static int 753 cmi_initsys(struct sc_info* sc) 754 { 755 /* XXX: an user should be able to set this with a control tool, 756 if not done before 7.0-RELEASE, this needs to be converted 757 to a device specific sysctl "dev.pcm.X.yyy" via 758 device_get_sysctl_*() as discussed on multimedia@ in msg-id 759 <861wujij2q.fsf@xps.des.no> */ 760 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 761 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 762 OID_AUTO, "spdif_enabled", CTLFLAG_RW, 763 &sc->spdif_enabled, 0, 764 "enable SPDIF output at 44.1 kHz and above"); 765 766 return 0; 767 } 768 769 /* ------------------------------------------------------------------------- */ 770 static kobj_method_t cmi_mixer_methods[] = { 771 KOBJMETHOD(mixer_init, cmimix_init), 772 KOBJMETHOD(mixer_set, cmimix_set), 773 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 774 KOBJMETHOD_END 775 }; 776 MIXER_DECLARE(cmi_mixer); 777 778 /* 779 * mpu401 functions 780 */ 781 782 static unsigned char 783 cmi_mread(struct mpu401 *arg, void *sc, int reg) 784 { 785 unsigned int d; 786 787 d = bus_space_read_1(0,0, 0x330 + reg); 788 /* printf("cmi_mread: reg %x %x\n",reg, d); 789 */ 790 return d; 791 } 792 793 static void 794 cmi_mwrite(struct mpu401 *arg, void *sc, int reg, unsigned char b) 795 { 796 797 bus_space_write_1(0,0,0x330 + reg , b); 798 } 799 800 static int 801 cmi_muninit(struct mpu401 *arg, void *cookie) 802 { 803 struct sc_info *sc = cookie; 804 805 snd_mtxlock(sc->lock); 806 sc->mpu_intr = 0; 807 sc->mpu = 0; 808 snd_mtxunlock(sc->lock); 809 810 return 0; 811 } 812 813 static kobj_method_t cmi_mpu_methods[] = { 814 KOBJMETHOD(mpufoi_read, cmi_mread), 815 KOBJMETHOD(mpufoi_write, cmi_mwrite), 816 KOBJMETHOD(mpufoi_uninit, cmi_muninit), 817 KOBJMETHOD_END 818 }; 819 820 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0); 821 822 static void 823 cmi_midiattach(struct sc_info *sc) { 824 /* 825 const struct { 826 int port,bits; 827 } *p, ports[] = { 828 {0x330,0}, 829 {0x320,1}, 830 {0x310,2}, 831 {0x300,3}, 832 {0,0} } ; 833 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does 834 anyone know how to bus_space tag? 835 */ 836 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 837 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL, 838 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT); 839 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL, 840 0 << CMPCI_REG_VMPUSEL_SHIFT ); 841 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 842 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr); 843 } 844 845 846 847 /* ------------------------------------------------------------------------- */ 848 /* Power and reset */ 849 850 static void 851 cmi_power(struct sc_info *sc, int state) 852 { 853 switch (state) { 854 case 0: /* full power */ 855 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 856 break; 857 default: 858 /* power off */ 859 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 860 break; 861 } 862 } 863 864 static int 865 cmi_init(struct sc_info *sc) 866 { 867 /* Effect reset */ 868 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 869 DELAY(100); 870 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 871 872 /* Disable interrupts and channels */ 873 cmi_clr4(sc, CMPCI_REG_FUNC_0, 874 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 875 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 876 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 877 878 /* Configure DMA channels, ch0 = play, ch1 = capture */ 879 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 880 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 881 882 /* Attempt to enable 4 Channel output */ 883 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 884 885 /* Disable SPDIF1 - not compatible with config */ 886 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 887 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 888 889 return 0; 890 } 891 892 static void 893 cmi_uninit(struct sc_info *sc) 894 { 895 /* Disable interrupts and channels */ 896 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 897 CMPCI_REG_CH0_INTR_ENABLE | 898 CMPCI_REG_CH1_INTR_ENABLE | 899 CMPCI_REG_TDMA_INTR_ENABLE); 900 cmi_clr4(sc, CMPCI_REG_FUNC_0, 901 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 902 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 903 904 if( sc->mpu ) 905 sc->mpu_intr = 0; 906 } 907 908 /* ------------------------------------------------------------------------- */ 909 /* Bus and device registration */ 910 static int 911 cmi_probe(device_t dev) 912 { 913 switch(pci_get_devid(dev)) { 914 case CMI8338A_PCI_ID: 915 device_set_desc(dev, "CMedia CMI8338A"); 916 return BUS_PROBE_DEFAULT; 917 case CMI8338B_PCI_ID: 918 device_set_desc(dev, "CMedia CMI8338B"); 919 return BUS_PROBE_DEFAULT; 920 case CMI8738_PCI_ID: 921 device_set_desc(dev, "CMedia CMI8738"); 922 return BUS_PROBE_DEFAULT; 923 case CMI8738B_PCI_ID: 924 device_set_desc(dev, "CMedia CMI8738B"); 925 return BUS_PROBE_DEFAULT; 926 case CMI120_USB_ID: 927 device_set_desc(dev, "CMedia CMI120"); 928 return BUS_PROBE_DEFAULT; 929 default: 930 return ENXIO; 931 } 932 } 933 934 static int 935 cmi_attach(device_t dev) 936 { 937 struct sc_info *sc; 938 u_int32_t data; 939 char status[SND_STATUSLEN]; 940 941 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 942 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc"); 943 data = pci_read_config(dev, PCIR_COMMAND, 2); 944 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 945 pci_write_config(dev, PCIR_COMMAND, data, 2); 946 data = pci_read_config(dev, PCIR_COMMAND, 2); 947 948 sc->dev = dev; 949 sc->regid = PCIR_BAR(0); 950 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid, 951 RF_ACTIVE); 952 if (!sc->reg) { 953 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 954 goto bad; 955 } 956 sc->st = rman_get_bustag(sc->reg); 957 sc->sh = rman_get_bushandle(sc->reg); 958 959 if (0) 960 cmi_midiattach(sc); 961 962 sc->irqid = 0; 963 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 964 RF_ACTIVE | RF_SHAREABLE); 965 if (!sc->irq || 966 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 967 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 968 goto bad; 969 } 970 971 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 972 973 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 974 /*boundary*/0, 975 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 976 /*highaddr*/BUS_SPACE_MAXADDR, 977 /*filter*/NULL, /*filterarg*/NULL, 978 /*maxsize*/sc->bufsz, /*nsegments*/1, 979 /*maxsegz*/0x3ffff, /*flags*/0, 980 /*lockfunc*/NULL, 981 /*lockfunc*/NULL, 982 &sc->parent_dmat) != 0) { 983 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 984 goto bad; 985 } 986 987 cmi_power(sc, 0); 988 if (cmi_init(sc)) 989 goto bad; 990 991 if (mixer_init(dev, &cmi_mixer_class, sc)) 992 goto bad; 993 994 if (pcm_register(dev, sc, 1, 1)) 995 goto bad; 996 997 cmi_initsys(sc); 998 999 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 1000 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 1001 1002 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 1003 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi)); 1004 pcm_setstatus(dev, status); 1005 1006 DEB(printf("cmi_attach: succeeded\n")); 1007 return 0; 1008 1009 bad: 1010 if (sc->parent_dmat) 1011 bus_dma_tag_destroy(sc->parent_dmat); 1012 if (sc->ih) 1013 bus_teardown_intr(dev, sc->irq, sc->ih); 1014 if (sc->irq) 1015 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1016 if (sc->reg) 1017 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1018 if (sc->lock) 1019 snd_mtxfree(sc->lock); 1020 if (sc) 1021 free(sc, M_DEVBUF); 1022 1023 return ENXIO; 1024 } 1025 1026 static int 1027 cmi_detach(device_t dev) 1028 { 1029 struct sc_info *sc; 1030 int r; 1031 1032 r = pcm_unregister(dev); 1033 if (r) return r; 1034 1035 sc = pcm_getdevinfo(dev); 1036 cmi_uninit(sc); 1037 cmi_power(sc, 3); 1038 1039 bus_dma_tag_destroy(sc->parent_dmat); 1040 bus_teardown_intr(dev, sc->irq, sc->ih); 1041 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1042 if(sc->mpu) 1043 mpu401_uninit(sc->mpu); 1044 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1045 if (sc->mpu_reg) 1046 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg); 1047 1048 snd_mtxfree(sc->lock); 1049 free(sc, M_DEVBUF); 1050 1051 return 0; 1052 } 1053 1054 static int 1055 cmi_suspend(device_t dev) 1056 { 1057 struct sc_info *sc = pcm_getdevinfo(dev); 1058 1059 snd_mtxlock(sc->lock); 1060 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 1061 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 1062 cmi_power(sc, 3); 1063 snd_mtxunlock(sc->lock); 1064 return 0; 1065 } 1066 1067 static int 1068 cmi_resume(device_t dev) 1069 { 1070 struct sc_info *sc = pcm_getdevinfo(dev); 1071 1072 snd_mtxlock(sc->lock); 1073 cmi_power(sc, 0); 1074 if (cmi_init(sc) != 0) { 1075 device_printf(dev, "unable to reinitialize the card\n"); 1076 snd_mtxunlock(sc->lock); 1077 return ENXIO; 1078 } 1079 1080 if (mixer_reinit(dev) == -1) { 1081 device_printf(dev, "unable to reinitialize the mixer\n"); 1082 snd_mtxunlock(sc->lock); 1083 return ENXIO; 1084 } 1085 1086 if (sc->pch.dma_was_active) { 1087 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 1088 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 1089 cmi_ch0_start(sc, &sc->pch); 1090 } 1091 1092 if (sc->rch.dma_was_active) { 1093 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 1094 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 1095 cmi_ch1_start(sc, &sc->rch); 1096 } 1097 snd_mtxunlock(sc->lock); 1098 return 0; 1099 } 1100 1101 static device_method_t cmi_methods[] = { 1102 DEVMETHOD(device_probe, cmi_probe), 1103 DEVMETHOD(device_attach, cmi_attach), 1104 DEVMETHOD(device_detach, cmi_detach), 1105 DEVMETHOD(device_resume, cmi_resume), 1106 DEVMETHOD(device_suspend, cmi_suspend), 1107 { 0, 0 } 1108 }; 1109 1110 static driver_t cmi_driver = { 1111 "pcm", 1112 cmi_methods, 1113 PCM_SOFTC_SIZE 1114 }; 1115 1116 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0); 1117 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1118 MODULE_DEPEND(snd_cmi, midi, 1,1,1); 1119 MODULE_VERSION(snd_cmi, 1); 1120