1 /* 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * This driver exists largely as a result of other people's efforts. 27 * Much of register handling is based on NetBSD CMI8x38 audio driver 28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 30 * registers and the 8738 mixer devices. His Linux was driver a also 31 * useful reference point. 32 * 33 * TODO: MIDI 34 * 35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 36 * 37 * This card/code does not always manage to sample at 44100 - actual 38 * rate drifts slightly between recordings (usually 0-3%). No 39 * differences visible in register dumps between times that work and 40 * those that don't. 41 */ 42 43 #include <dev/sound/pcm/sound.h> 44 #include <dev/sound/pci/cmireg.h> 45 #include <dev/sound/isa/sb.h> 46 47 #include <pci/pcireg.h> 48 #include <pci/pcivar.h> 49 50 #include <sys/sysctl.h> 51 52 #include "mixer_if.h" 53 54 SND_DECLARE_FILE("$FreeBSD$"); 55 56 /* Supported chip ID's */ 57 #define CMI8338A_PCI_ID 0x010013f6 58 #define CMI8338B_PCI_ID 0x010113f6 59 #define CMI8738_PCI_ID 0x011113f6 60 #define CMI8738B_PCI_ID 0x011213f6 61 62 /* Buffer size max is 64k for permitted DMA boundaries */ 63 #define CMI_BUFFER_SIZE 16384 64 65 /* Interrupts per length of buffer */ 66 #define CMI_INTR_PER_BUFFER 2 67 68 /* Clarify meaning of named defines in cmireg.h */ 69 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 70 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 71 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 72 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 73 74 /* Our indication of custom mixer control */ 75 #define CMPCI_NON_SB16_CONTROL 0xff 76 77 /* Debugging macro's */ 78 #undef DEB 79 #ifndef DEB 80 #define DEB(x) /* x */ 81 #endif /* DEB */ 82 83 #ifndef DEBMIX 84 #define DEBMIX(x) /* x */ 85 #endif /* DEBMIX */ 86 87 /* ------------------------------------------------------------------------- */ 88 /* Structures */ 89 90 struct sc_info; 91 92 struct sc_chinfo { 93 struct sc_info *parent; 94 struct pcm_channel *channel; 95 struct snd_dbuf *buffer; 96 u_int32_t fmt, spd, phys_buf, bps; 97 u_int32_t dma_active:1, dma_was_active:1; 98 int dir; 99 }; 100 101 struct sc_info { 102 device_t dev; 103 104 bus_space_tag_t st; 105 bus_space_handle_t sh; 106 bus_dma_tag_t parent_dmat; 107 struct resource *reg, *irq; 108 int regid, irqid; 109 void *ih; 110 void *lock; 111 112 struct sc_chinfo pch, rch; 113 }; 114 115 /* Channel caps */ 116 117 static u_int32_t cmi_fmt[] = { 118 AFMT_U8, 119 AFMT_STEREO | AFMT_U8, 120 AFMT_S16_LE, 121 AFMT_STEREO | AFMT_S16_LE, 122 0 123 }; 124 125 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 126 127 /* ------------------------------------------------------------------------- */ 128 /* Register Utilities */ 129 130 static u_int32_t 131 cmi_rd(struct sc_info *sc, int regno, int size) 132 { 133 switch (size) { 134 case 1: 135 return bus_space_read_1(sc->st, sc->sh, regno); 136 case 2: 137 return bus_space_read_2(sc->st, sc->sh, regno); 138 case 4: 139 return bus_space_read_4(sc->st, sc->sh, regno); 140 default: 141 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 142 return 0xFFFFFFFF; 143 } 144 } 145 146 static void 147 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 148 { 149 switch (size) { 150 case 1: 151 bus_space_write_1(sc->st, sc->sh, regno, data); 152 break; 153 case 2: 154 bus_space_write_2(sc->st, sc->sh, regno, data); 155 break; 156 case 4: 157 bus_space_write_4(sc->st, sc->sh, regno, data); 158 break; 159 } 160 } 161 162 static void 163 cmi_partial_wr4(struct sc_info *sc, 164 int reg, int shift, u_int32_t mask, u_int32_t val) 165 { 166 u_int32_t r; 167 168 r = cmi_rd(sc, reg, 4); 169 r &= ~(mask << shift); 170 r |= val << shift; 171 cmi_wr(sc, reg, r, 4); 172 } 173 174 static void 175 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 176 { 177 u_int32_t r; 178 179 r = cmi_rd(sc, reg, 4); 180 r &= ~mask; 181 cmi_wr(sc, reg, r, 4); 182 } 183 184 static void 185 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 186 { 187 u_int32_t r; 188 189 r = cmi_rd(sc, reg, 4); 190 r |= mask; 191 cmi_wr(sc, reg, r, 4); 192 } 193 194 /* ------------------------------------------------------------------------- */ 195 /* Rate Mapping */ 196 197 static int cmi_rates[] = {5512, 8000, 11025, 16000, 198 22050, 32000, 44100, 48000}; 199 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 200 201 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 202 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 203 204 static u_int32_t 205 cmpci_rate_to_regvalue(int rate) 206 { 207 int i, r; 208 209 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 210 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 211 break; 212 } 213 } 214 215 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 216 217 r = ((i >> 1) | (i << 2)) & 0x07; 218 return r; 219 } 220 221 static int 222 cmpci_regvalue_to_rate(u_int32_t r) 223 { 224 int i; 225 226 i = ((r << 1) | (r >> 2)) & 0x07; 227 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 228 return cmi_rates[i]; 229 } 230 231 /* ------------------------------------------------------------------------- */ 232 /* ADC/DAC control - there are 2 dma channels on 8738, either can be 233 * playback or capture. We use ch0 for playback and ch1 for capture. */ 234 235 static void 236 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 237 { 238 u_int32_t s, i, sz, physbuf; 239 240 physbuf = vtophys(sndbuf_getbuf(ch->buffer)); 241 242 cmi_wr(sc, base, physbuf, 4); 243 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 244 245 s = sz / ch->bps - 1; 246 cmi_wr(sc, base + 4, s, 2); 247 248 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 249 cmi_wr(sc, base + 6, i, 2); 250 } 251 252 253 static void 254 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 255 { 256 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 257 258 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 259 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 260 CMPCI_REG_CH0_INTR_ENABLE); 261 262 ch->dma_active = 1; 263 } 264 265 static u_int32_t 266 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 267 { 268 u_int32_t r = ch->dma_active; 269 270 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 271 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 272 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 273 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 274 ch->dma_active = 0; 275 return r; 276 } 277 278 static void 279 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 280 { 281 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 282 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 283 /* Enable Interrupts */ 284 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 285 CMPCI_REG_CH1_INTR_ENABLE); 286 DEB(printf("cmi_ch1_start: dma prog\n")); 287 ch->dma_active = 1; 288 } 289 290 static u_int32_t 291 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 292 { 293 u_int32_t r = ch->dma_active; 294 295 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 296 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 297 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 298 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 299 ch->dma_active = 0; 300 return r; 301 } 302 303 static void 304 cmi_spdif_speed(struct sc_info *sc, int speed) { 305 u_int32_t fcr1, lcr, mcr; 306 307 if (speed >= 44100) { 308 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 309 lcr = CMPCI_REG_XSPDIF_ENABLE; 310 mcr = (speed == 48000) ? 311 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 312 } else { 313 fcr1 = mcr = lcr = 0; 314 } 315 316 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 317 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 318 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 319 CMPCI_REG_SPDIF0_ENABLE, fcr1); 320 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 321 CMPCI_REG_XSPDIF_ENABLE, lcr); 322 } 323 324 /* ------------------------------------------------------------------------- */ 325 /* Channel Interface implementation */ 326 327 static void * 328 cmichan_init(kobj_t obj, void *devinfo, 329 struct snd_dbuf *b, struct pcm_channel *c, int dir) 330 { 331 struct sc_info *sc = devinfo; 332 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 333 334 ch->parent = sc; 335 ch->channel = c; 336 ch->bps = 1; 337 ch->fmt = AFMT_U8; 338 ch->spd = DSP_DEFAULT_SPEED; 339 ch->buffer = b; 340 ch->dma_active = 0; 341 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, CMI_BUFFER_SIZE) != 0) { 342 DEB(printf("cmichan_init failed\n")); 343 return NULL; 344 } 345 346 ch->dir = dir; 347 snd_mtxlock(sc->lock); 348 if (ch->dir == PCMDIR_PLAY) { 349 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 350 } else { 351 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 352 } 353 snd_mtxunlock(sc->lock); 354 355 return ch; 356 } 357 358 static int 359 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 360 { 361 struct sc_chinfo *ch = data; 362 struct sc_info *sc = ch->parent; 363 u_int32_t f; 364 365 if (format & AFMT_S16_LE) { 366 f = CMPCI_REG_FORMAT_16BIT; 367 ch->bps = 2; 368 } else { 369 f = CMPCI_REG_FORMAT_8BIT; 370 ch->bps = 1; 371 } 372 373 if (format & AFMT_STEREO) { 374 f |= CMPCI_REG_FORMAT_STEREO; 375 ch->bps *= 2; 376 } else { 377 f |= CMPCI_REG_FORMAT_MONO; 378 } 379 380 snd_mtxlock(sc->lock); 381 if (ch->dir == PCMDIR_PLAY) { 382 cmi_partial_wr4(ch->parent, 383 CMPCI_REG_CHANNEL_FORMAT, 384 CMPCI_REG_CH0_FORMAT_SHIFT, 385 CMPCI_REG_CH0_FORMAT_MASK, 386 f); 387 } else { 388 cmi_partial_wr4(ch->parent, 389 CMPCI_REG_CHANNEL_FORMAT, 390 CMPCI_REG_CH1_FORMAT_SHIFT, 391 CMPCI_REG_CH1_FORMAT_MASK, 392 f); 393 } 394 snd_mtxunlock(sc->lock); 395 ch->fmt = format; 396 397 return 0; 398 } 399 400 static int 401 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 402 { 403 struct sc_chinfo *ch = data; 404 struct sc_info *sc = ch->parent; 405 u_int32_t r, rsp; 406 407 r = cmpci_rate_to_regvalue(speed); 408 snd_mtxlock(sc->lock); 409 if (ch->dir == PCMDIR_PLAY) { 410 if (speed < 44100) /* disable if req before rate change */ 411 cmi_spdif_speed(ch->parent, speed); 412 cmi_partial_wr4(ch->parent, 413 CMPCI_REG_FUNC_1, 414 CMPCI_REG_DAC_FS_SHIFT, 415 CMPCI_REG_DAC_FS_MASK, 416 r); 417 if (speed >= 44100) /* enable if req after rate change */ 418 cmi_spdif_speed(ch->parent, speed); 419 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 420 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 421 rsp &= CMPCI_REG_DAC_FS_MASK; 422 } else { 423 cmi_partial_wr4(ch->parent, 424 CMPCI_REG_FUNC_1, 425 CMPCI_REG_ADC_FS_SHIFT, 426 CMPCI_REG_ADC_FS_MASK, 427 r); 428 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 429 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 430 rsp &= CMPCI_REG_ADC_FS_MASK; 431 } 432 snd_mtxunlock(sc->lock); 433 ch->spd = cmpci_regvalue_to_rate(r); 434 435 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 436 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 437 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 438 439 return ch->spd; 440 } 441 442 static int 443 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 444 { 445 struct sc_chinfo *ch = data; 446 447 /* user has requested interrupts every blocksize bytes */ 448 if (blocksize > CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER) { 449 blocksize = CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER; 450 } 451 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 452 453 return blocksize; 454 } 455 456 static int 457 cmichan_trigger(kobj_t obj, void *data, int go) 458 { 459 struct sc_chinfo *ch = data; 460 struct sc_info *sc = ch->parent; 461 462 snd_mtxlock(sc->lock); 463 if (ch->dir == PCMDIR_PLAY) { 464 switch(go) { 465 case PCMTRIG_START: 466 cmi_ch0_start(sc, ch); 467 break; 468 case PCMTRIG_ABORT: 469 cmi_ch0_stop(sc, ch); 470 break; 471 } 472 } else { 473 switch(go) { 474 case PCMTRIG_START: 475 cmi_ch1_start(sc, ch); 476 break; 477 case PCMTRIG_ABORT: 478 cmi_ch1_stop(sc, ch); 479 break; 480 } 481 } 482 snd_mtxunlock(sc->lock); 483 return 0; 484 } 485 486 static int 487 cmichan_getptr(kobj_t obj, void *data) 488 { 489 struct sc_chinfo *ch = data; 490 struct sc_info *sc = ch->parent; 491 u_int32_t physptr, bufptr, sz; 492 493 snd_mtxlock(sc->lock); 494 if (ch->dir == PCMDIR_PLAY) { 495 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 496 } else { 497 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 498 } 499 snd_mtxunlock(sc->lock); 500 501 sz = sndbuf_getsize(ch->buffer); 502 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 503 504 return bufptr; 505 } 506 507 static void 508 cmi_intr(void *data) 509 { 510 struct sc_info *sc = data; 511 u_int32_t intrstat; 512 513 snd_mtxlock(sc->lock); 514 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 515 if ((intrstat & CMPCI_REG_ANY_INTR) == 0) { 516 goto out; 517 } 518 519 /* Disable interrupts */ 520 if (intrstat & CMPCI_REG_CH0_INTR) { 521 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 522 } 523 524 if (intrstat & CMPCI_REG_CH1_INTR) { 525 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 526 } 527 528 /* Signal interrupts to channel */ 529 if (intrstat & CMPCI_REG_CH0_INTR) { 530 chn_intr(sc->pch.channel); 531 } 532 533 if (intrstat & CMPCI_REG_CH1_INTR) { 534 chn_intr(sc->rch.channel); 535 } 536 537 /* Enable interrupts */ 538 if (intrstat & CMPCI_REG_CH0_INTR) { 539 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 540 } 541 542 if (intrstat & CMPCI_REG_CH1_INTR) { 543 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 544 } 545 546 out: 547 snd_mtxunlock(sc->lock); 548 return; 549 } 550 551 static struct pcmchan_caps * 552 cmichan_getcaps(kobj_t obj, void *data) 553 { 554 return &cmi_caps; 555 } 556 557 static kobj_method_t cmichan_methods[] = { 558 KOBJMETHOD(channel_init, cmichan_init), 559 KOBJMETHOD(channel_setformat, cmichan_setformat), 560 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 561 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 562 KOBJMETHOD(channel_trigger, cmichan_trigger), 563 KOBJMETHOD(channel_getptr, cmichan_getptr), 564 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 565 { 0, 0 } 566 }; 567 CHANNEL_DECLARE(cmichan); 568 569 /* ------------------------------------------------------------------------- */ 570 /* Mixer - sb16 with kinks */ 571 572 static void 573 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 574 { 575 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 576 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 577 } 578 579 static u_int8_t 580 cmimix_rd(struct sc_info *sc, u_int8_t port) 581 { 582 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 583 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 584 } 585 586 struct sb16props { 587 u_int8_t rreg; /* right reg chan register */ 588 u_int8_t stereo:1; /* (no explanation needed, honest) */ 589 u_int8_t rec:1; /* recording source */ 590 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 591 u_int8_t oselect; /* output select mask */ 592 u_int8_t iselect; /* right input select mask */ 593 } static const cmt[SOUND_MIXER_NRDEVICES] = { 594 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 595 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 596 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 597 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 598 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 599 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 600 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 601 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 602 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 603 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 604 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 605 /* These controls are not implemented in CMI8738, but maybe at a 606 future date. They are not documented in C-Media documentation, 607 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 608 */ 609 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 610 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 611 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 612 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 613 /* The mic pre-amp is implemented with non-SB16 compatible 614 registers. */ 615 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 616 }; 617 618 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 619 620 static int 621 cmimix_init(struct snd_mixer *m) 622 { 623 struct sc_info *sc = mix_getdevinfo(m); 624 u_int32_t i,v; 625 626 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 627 if (cmt[i].bits) v |= 1 << i; 628 } 629 mix_setdevs(m, v); 630 631 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 632 if (cmt[i].rec) v |= 1 << i; 633 } 634 mix_setrecdevs(m, v); 635 636 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 637 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 638 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 639 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 640 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 641 return 0; 642 } 643 644 static int 645 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 646 { 647 struct sc_info *sc = mix_getdevinfo(m); 648 u_int32_t r, l, max; 649 u_int8_t v; 650 651 max = (1 << cmt[dev].bits) - 1; 652 653 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 654 /* For time being this can only be one thing (mic in 655 * mic/aux reg) */ 656 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 657 l = left * max / 100; 658 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 659 v |= ((l << 1) | (~l >> 3)) & 0x0f; 660 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 661 return 0; 662 } 663 664 l = (left * max / 100) << (8 - cmt[dev].bits); 665 if (cmt[dev].stereo) { 666 r = (right * max / 100) << (8 - cmt[dev].bits); 667 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 668 cmimix_wr(sc, cmt[dev].rreg, r); 669 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 670 "value 0x%02x:0x%02x\n", 671 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 672 } else { 673 r = l; 674 cmimix_wr(sc, cmt[dev].rreg, l); 675 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 676 "value 0x%02x:0x%02x\n", 677 dev, cmt[dev].rreg, l, l)); 678 } 679 680 /* Zero gain does not mute channel from output, but this does... */ 681 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 682 if (l == 0 && r == 0) { 683 v &= ~cmt[dev].oselect; 684 } else { 685 v |= cmt[dev].oselect; 686 } 687 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 688 689 return 0; 690 } 691 692 static int 693 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 694 { 695 struct sc_info *sc = mix_getdevinfo(m); 696 u_int32_t i, ml, sl; 697 698 ml = sl = 0; 699 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 700 if ((1<<i) & src) { 701 if (cmt[i].stereo) { 702 sl |= cmt[i].iselect; 703 } else { 704 ml |= cmt[i].iselect; 705 } 706 } 707 } 708 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 709 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 710 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 711 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 712 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 713 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 714 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 715 716 return src; 717 } 718 719 static kobj_method_t cmi_mixer_methods[] = { 720 KOBJMETHOD(mixer_init, cmimix_init), 721 KOBJMETHOD(mixer_set, cmimix_set), 722 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 723 { 0, 0 } 724 }; 725 MIXER_DECLARE(cmi_mixer); 726 727 /* ------------------------------------------------------------------------- */ 728 /* Power and reset */ 729 730 static void 731 cmi_power(struct sc_info *sc, int state) 732 { 733 switch (state) { 734 case 0: /* full power */ 735 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 736 break; 737 default: 738 /* power off */ 739 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 740 break; 741 } 742 } 743 744 static int 745 cmi_init(struct sc_info *sc) 746 { 747 /* Effect reset */ 748 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 749 DELAY(100); 750 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 751 752 /* Disable interrupts and channels */ 753 cmi_clr4(sc, CMPCI_REG_FUNC_0, 754 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 755 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 756 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 757 758 /* Configure DMA channels, ch0 = play, ch1 = capture */ 759 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 760 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 761 762 /* Attempt to enable 4 Channel output */ 763 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 764 765 /* Disable SPDIF1 - not compatible with config */ 766 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 767 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 768 769 return 0; 770 } 771 772 static void 773 cmi_uninit(struct sc_info *sc) 774 { 775 /* Disable interrupts and channels */ 776 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 777 CMPCI_REG_CH0_INTR_ENABLE | 778 CMPCI_REG_CH1_INTR_ENABLE | 779 CMPCI_REG_TDMA_INTR_ENABLE); 780 cmi_clr4(sc, CMPCI_REG_FUNC_0, 781 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 782 } 783 784 /* ------------------------------------------------------------------------- */ 785 /* Bus and device registration */ 786 static int 787 cmi_probe(device_t dev) 788 { 789 switch(pci_get_devid(dev)) { 790 case CMI8338A_PCI_ID: 791 device_set_desc(dev, "CMedia CMI8338A"); 792 return 0; 793 case CMI8338B_PCI_ID: 794 device_set_desc(dev, "CMedia CMI8338B"); 795 return 0; 796 case CMI8738_PCI_ID: 797 device_set_desc(dev, "CMedia CMI8738"); 798 return 0; 799 case CMI8738B_PCI_ID: 800 device_set_desc(dev, "CMedia CMI8738B"); 801 return 0; 802 default: 803 return ENXIO; 804 } 805 } 806 807 static int 808 cmi_attach(device_t dev) 809 { 810 struct snddev_info *d; 811 struct sc_info *sc; 812 u_int32_t data; 813 char status[SND_STATUSLEN]; 814 815 d = device_get_softc(dev); 816 sc = malloc(sizeof(struct sc_info), M_DEVBUF, M_NOWAIT | M_ZERO); 817 if (sc == NULL) { 818 device_printf(dev, "cannot allocate softc\n"); 819 return ENXIO; 820 } 821 822 sc->lock = snd_mtxcreate(device_get_nameunit(dev)); 823 data = pci_read_config(dev, PCIR_COMMAND, 2); 824 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 825 pci_write_config(dev, PCIR_COMMAND, data, 2); 826 data = pci_read_config(dev, PCIR_COMMAND, 2); 827 828 sc->regid = PCIR_MAPS; 829 sc->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->regid, 830 0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE); 831 if (!sc->reg) { 832 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 833 goto bad; 834 } 835 sc->st = rman_get_bustag(sc->reg); 836 sc->sh = rman_get_bushandle(sc->reg); 837 838 sc->irqid = 0; 839 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 840 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 841 if (!sc->irq || 842 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 843 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 844 goto bad; 845 } 846 847 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 848 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 849 /*highaddr*/BUS_SPACE_MAXADDR, 850 /*filter*/NULL, /*filterarg*/NULL, 851 /*maxsize*/CMI_BUFFER_SIZE, /*nsegments*/1, 852 /*maxsegz*/0x3ffff, /*flags*/0, 853 &sc->parent_dmat) != 0) { 854 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 855 goto bad; 856 } 857 858 cmi_power(sc, 0); 859 if (cmi_init(sc)) 860 goto bad; 861 862 if (mixer_init(dev, &cmi_mixer_class, sc)) 863 goto bad; 864 865 if (pcm_register(dev, sc, 1, 1)) 866 goto bad; 867 868 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 869 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 870 871 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld", 872 rman_get_start(sc->reg), rman_get_start(sc->irq)); 873 pcm_setstatus(dev, status); 874 875 DEB(printf("cmi_attach: succeeded\n")); 876 return 0; 877 878 bad: 879 if (sc->parent_dmat) 880 bus_dma_tag_destroy(sc->parent_dmat); 881 if (sc->ih) 882 bus_teardown_intr(dev, sc->irq, sc->ih); 883 if (sc->irq) 884 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 885 if (sc->reg) 886 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 887 if (sc->lock) 888 snd_mtxfree(sc->lock); 889 if (sc) 890 free(sc, M_DEVBUF); 891 892 return ENXIO; 893 } 894 895 static int 896 cmi_detach(device_t dev) 897 { 898 struct sc_info *sc; 899 int r; 900 901 r = pcm_unregister(dev); 902 if (r) return r; 903 904 sc = pcm_getdevinfo(dev); 905 cmi_uninit(sc); 906 cmi_power(sc, 3); 907 908 bus_dma_tag_destroy(sc->parent_dmat); 909 bus_teardown_intr(dev, sc->irq, sc->ih); 910 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 911 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 912 snd_mtxfree(sc->lock); 913 free(sc, M_DEVBUF); 914 915 return 0; 916 } 917 918 static int 919 cmi_suspend(device_t dev) 920 { 921 struct sc_info *sc = pcm_getdevinfo(dev); 922 923 snd_mtxlock(sc->lock); 924 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 925 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 926 cmi_power(sc, 3); 927 snd_mtxunlock(sc->lock); 928 return 0; 929 } 930 931 static int 932 cmi_resume(device_t dev) 933 { 934 struct sc_info *sc = pcm_getdevinfo(dev); 935 936 snd_mtxlock(sc->lock); 937 cmi_power(sc, 0); 938 if (cmi_init(sc) != 0) { 939 device_printf(dev, "unable to reinitialize the card\n"); 940 snd_mtxunlock(sc->lock); 941 return ENXIO; 942 } 943 944 if (mixer_reinit(dev) == -1) { 945 device_printf(dev, "unable to reinitialize the mixer\n"); 946 snd_mtxunlock(sc->lock); 947 return ENXIO; 948 } 949 950 if (sc->pch.dma_was_active) { 951 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 952 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 953 cmi_ch0_start(sc, &sc->pch); 954 } 955 956 if (sc->rch.dma_was_active) { 957 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 958 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 959 cmi_ch1_start(sc, &sc->rch); 960 } 961 snd_mtxunlock(sc->lock); 962 return 0; 963 } 964 965 static device_method_t cmi_methods[] = { 966 DEVMETHOD(device_probe, cmi_probe), 967 DEVMETHOD(device_attach, cmi_attach), 968 DEVMETHOD(device_detach, cmi_detach), 969 DEVMETHOD(device_resume, cmi_resume), 970 DEVMETHOD(device_suspend, cmi_suspend), 971 { 0, 0 } 972 }; 973 974 static driver_t cmi_driver = { 975 "pcm", 976 cmi_methods, 977 PCM_SOFTC_SIZE 978 }; 979 980 DRIVER_MODULE(snd_cmipci, pci, cmi_driver, pcm_devclass, 0, 0); 981 MODULE_DEPEND(snd_cmipci, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 982 MODULE_VERSION(snd_cmipci, 1); 983