1 /* 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * This driver exists largely as a result of other people's efforts. 27 * Much of register handling is based on NetBSD CMI8x38 audio driver 28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 30 * registers and the 8738 mixer devices. His Linux was driver a also 31 * useful reference point. 32 * 33 * TODO: MIDI 34 * 35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 36 * 37 * This card/code does not always manage to sample at 44100 - actual 38 * rate drifts slightly between recordings (usually 0-3%). No 39 * differences visible in register dumps between times that work and 40 * those that don't. 41 */ 42 43 #include <dev/sound/pcm/sound.h> 44 #include <dev/sound/pci/cmireg.h> 45 #include <dev/sound/isa/sb.h> 46 47 #include <pci/pcireg.h> 48 #include <pci/pcivar.h> 49 50 #include <sys/sysctl.h> 51 52 #include "mixer_if.h" 53 54 SND_DECLARE_FILE("$FreeBSD$"); 55 56 /* Supported chip ID's */ 57 #define CMI8338A_PCI_ID 0x010013f6 58 #define CMI8338B_PCI_ID 0x010113f6 59 #define CMI8738_PCI_ID 0x011113f6 60 #define CMI8738B_PCI_ID 0x011213f6 61 62 /* Buffer size max is 64k for permitted DMA boundaries */ 63 #define CMI_DEFAULT_BUFSZ 16384 64 65 /* Interrupts per length of buffer */ 66 #define CMI_INTR_PER_BUFFER 2 67 68 /* Clarify meaning of named defines in cmireg.h */ 69 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 70 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 71 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 72 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 73 74 /* Our indication of custom mixer control */ 75 #define CMPCI_NON_SB16_CONTROL 0xff 76 77 /* Debugging macro's */ 78 #undef DEB 79 #ifndef DEB 80 #define DEB(x) /* x */ 81 #endif /* DEB */ 82 83 #ifndef DEBMIX 84 #define DEBMIX(x) /* x */ 85 #endif /* DEBMIX */ 86 87 /* ------------------------------------------------------------------------- */ 88 /* Structures */ 89 90 struct sc_info; 91 92 struct sc_chinfo { 93 struct sc_info *parent; 94 struct pcm_channel *channel; 95 struct snd_dbuf *buffer; 96 u_int32_t fmt, spd, phys_buf, bps; 97 u_int32_t dma_active:1, dma_was_active:1; 98 int dir; 99 }; 100 101 struct sc_info { 102 device_t dev; 103 104 bus_space_tag_t st; 105 bus_space_handle_t sh; 106 bus_dma_tag_t parent_dmat; 107 struct resource *reg, *irq; 108 int regid, irqid; 109 void *ih; 110 void *lock; 111 112 unsigned int bufsz; 113 struct sc_chinfo pch, rch; 114 }; 115 116 /* Channel caps */ 117 118 static u_int32_t cmi_fmt[] = { 119 AFMT_U8, 120 AFMT_STEREO | AFMT_U8, 121 AFMT_S16_LE, 122 AFMT_STEREO | AFMT_S16_LE, 123 0 124 }; 125 126 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 127 128 /* ------------------------------------------------------------------------- */ 129 /* Register Utilities */ 130 131 static u_int32_t 132 cmi_rd(struct sc_info *sc, int regno, int size) 133 { 134 switch (size) { 135 case 1: 136 return bus_space_read_1(sc->st, sc->sh, regno); 137 case 2: 138 return bus_space_read_2(sc->st, sc->sh, regno); 139 case 4: 140 return bus_space_read_4(sc->st, sc->sh, regno); 141 default: 142 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 143 return 0xFFFFFFFF; 144 } 145 } 146 147 static void 148 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 149 { 150 switch (size) { 151 case 1: 152 bus_space_write_1(sc->st, sc->sh, regno, data); 153 break; 154 case 2: 155 bus_space_write_2(sc->st, sc->sh, regno, data); 156 break; 157 case 4: 158 bus_space_write_4(sc->st, sc->sh, regno, data); 159 break; 160 } 161 } 162 163 static void 164 cmi_partial_wr4(struct sc_info *sc, 165 int reg, int shift, u_int32_t mask, u_int32_t val) 166 { 167 u_int32_t r; 168 169 r = cmi_rd(sc, reg, 4); 170 r &= ~(mask << shift); 171 r |= val << shift; 172 cmi_wr(sc, reg, r, 4); 173 } 174 175 static void 176 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 177 { 178 u_int32_t r; 179 180 r = cmi_rd(sc, reg, 4); 181 r &= ~mask; 182 cmi_wr(sc, reg, r, 4); 183 } 184 185 static void 186 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 187 { 188 u_int32_t r; 189 190 r = cmi_rd(sc, reg, 4); 191 r |= mask; 192 cmi_wr(sc, reg, r, 4); 193 } 194 195 /* ------------------------------------------------------------------------- */ 196 /* Rate Mapping */ 197 198 static int cmi_rates[] = {5512, 8000, 11025, 16000, 199 22050, 32000, 44100, 48000}; 200 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 201 202 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 203 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 204 205 static u_int32_t 206 cmpci_rate_to_regvalue(int rate) 207 { 208 int i, r; 209 210 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 211 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 212 break; 213 } 214 } 215 216 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 217 218 r = ((i >> 1) | (i << 2)) & 0x07; 219 return r; 220 } 221 222 static int 223 cmpci_regvalue_to_rate(u_int32_t r) 224 { 225 int i; 226 227 i = ((r << 1) | (r >> 2)) & 0x07; 228 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 229 return cmi_rates[i]; 230 } 231 232 /* ------------------------------------------------------------------------- */ 233 /* ADC/DAC control - there are 2 dma channels on 8738, either can be 234 * playback or capture. We use ch0 for playback and ch1 for capture. */ 235 236 static void 237 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 238 { 239 u_int32_t s, i, sz, physbuf; 240 241 physbuf = vtophys(sndbuf_getbuf(ch->buffer)); 242 243 cmi_wr(sc, base, physbuf, 4); 244 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 245 246 s = sz / ch->bps - 1; 247 cmi_wr(sc, base + 4, s, 2); 248 249 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 250 cmi_wr(sc, base + 6, i, 2); 251 } 252 253 254 static void 255 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 256 { 257 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 258 259 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 260 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 261 CMPCI_REG_CH0_INTR_ENABLE); 262 263 ch->dma_active = 1; 264 } 265 266 static u_int32_t 267 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 268 { 269 u_int32_t r = ch->dma_active; 270 271 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 272 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 273 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 274 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 275 ch->dma_active = 0; 276 return r; 277 } 278 279 static void 280 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 281 { 282 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 283 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 284 /* Enable Interrupts */ 285 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 286 CMPCI_REG_CH1_INTR_ENABLE); 287 DEB(printf("cmi_ch1_start: dma prog\n")); 288 ch->dma_active = 1; 289 } 290 291 static u_int32_t 292 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 293 { 294 u_int32_t r = ch->dma_active; 295 296 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 297 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 298 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 299 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 300 ch->dma_active = 0; 301 return r; 302 } 303 304 static void 305 cmi_spdif_speed(struct sc_info *sc, int speed) { 306 u_int32_t fcr1, lcr, mcr; 307 308 if (speed >= 44100) { 309 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 310 lcr = CMPCI_REG_XSPDIF_ENABLE; 311 mcr = (speed == 48000) ? 312 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 313 } else { 314 fcr1 = mcr = lcr = 0; 315 } 316 317 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 318 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 319 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 320 CMPCI_REG_SPDIF0_ENABLE, fcr1); 321 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 322 CMPCI_REG_XSPDIF_ENABLE, lcr); 323 } 324 325 /* ------------------------------------------------------------------------- */ 326 /* Channel Interface implementation */ 327 328 static void * 329 cmichan_init(kobj_t obj, void *devinfo, 330 struct snd_dbuf *b, struct pcm_channel *c, int dir) 331 { 332 struct sc_info *sc = devinfo; 333 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 334 335 ch->parent = sc; 336 ch->channel = c; 337 ch->bps = 1; 338 ch->fmt = AFMT_U8; 339 ch->spd = DSP_DEFAULT_SPEED; 340 ch->buffer = b; 341 ch->dma_active = 0; 342 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) { 343 DEB(printf("cmichan_init failed\n")); 344 return NULL; 345 } 346 347 ch->dir = dir; 348 snd_mtxlock(sc->lock); 349 if (ch->dir == PCMDIR_PLAY) { 350 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 351 } else { 352 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 353 } 354 snd_mtxunlock(sc->lock); 355 356 return ch; 357 } 358 359 static int 360 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 361 { 362 struct sc_chinfo *ch = data; 363 struct sc_info *sc = ch->parent; 364 u_int32_t f; 365 366 if (format & AFMT_S16_LE) { 367 f = CMPCI_REG_FORMAT_16BIT; 368 ch->bps = 2; 369 } else { 370 f = CMPCI_REG_FORMAT_8BIT; 371 ch->bps = 1; 372 } 373 374 if (format & AFMT_STEREO) { 375 f |= CMPCI_REG_FORMAT_STEREO; 376 ch->bps *= 2; 377 } else { 378 f |= CMPCI_REG_FORMAT_MONO; 379 } 380 381 snd_mtxlock(sc->lock); 382 if (ch->dir == PCMDIR_PLAY) { 383 cmi_partial_wr4(ch->parent, 384 CMPCI_REG_CHANNEL_FORMAT, 385 CMPCI_REG_CH0_FORMAT_SHIFT, 386 CMPCI_REG_CH0_FORMAT_MASK, 387 f); 388 } else { 389 cmi_partial_wr4(ch->parent, 390 CMPCI_REG_CHANNEL_FORMAT, 391 CMPCI_REG_CH1_FORMAT_SHIFT, 392 CMPCI_REG_CH1_FORMAT_MASK, 393 f); 394 } 395 snd_mtxunlock(sc->lock); 396 ch->fmt = format; 397 398 return 0; 399 } 400 401 static int 402 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 403 { 404 struct sc_chinfo *ch = data; 405 struct sc_info *sc = ch->parent; 406 u_int32_t r, rsp; 407 408 r = cmpci_rate_to_regvalue(speed); 409 snd_mtxlock(sc->lock); 410 if (ch->dir == PCMDIR_PLAY) { 411 if (speed < 44100) /* disable if req before rate change */ 412 cmi_spdif_speed(ch->parent, speed); 413 cmi_partial_wr4(ch->parent, 414 CMPCI_REG_FUNC_1, 415 CMPCI_REG_DAC_FS_SHIFT, 416 CMPCI_REG_DAC_FS_MASK, 417 r); 418 if (speed >= 44100) /* enable if req after rate change */ 419 cmi_spdif_speed(ch->parent, speed); 420 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 421 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 422 rsp &= CMPCI_REG_DAC_FS_MASK; 423 } else { 424 cmi_partial_wr4(ch->parent, 425 CMPCI_REG_FUNC_1, 426 CMPCI_REG_ADC_FS_SHIFT, 427 CMPCI_REG_ADC_FS_MASK, 428 r); 429 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 430 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 431 rsp &= CMPCI_REG_ADC_FS_MASK; 432 } 433 snd_mtxunlock(sc->lock); 434 ch->spd = cmpci_regvalue_to_rate(r); 435 436 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 437 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 438 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 439 440 return ch->spd; 441 } 442 443 static int 444 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 445 { 446 struct sc_chinfo *ch = data; 447 struct sc_info *sc = ch->parent; 448 449 /* user has requested interrupts every blocksize bytes */ 450 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 451 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 452 } 453 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 454 455 return blocksize; 456 } 457 458 static int 459 cmichan_trigger(kobj_t obj, void *data, int go) 460 { 461 struct sc_chinfo *ch = data; 462 struct sc_info *sc = ch->parent; 463 464 snd_mtxlock(sc->lock); 465 if (ch->dir == PCMDIR_PLAY) { 466 switch(go) { 467 case PCMTRIG_START: 468 cmi_ch0_start(sc, ch); 469 break; 470 case PCMTRIG_ABORT: 471 cmi_ch0_stop(sc, ch); 472 break; 473 } 474 } else { 475 switch(go) { 476 case PCMTRIG_START: 477 cmi_ch1_start(sc, ch); 478 break; 479 case PCMTRIG_ABORT: 480 cmi_ch1_stop(sc, ch); 481 break; 482 } 483 } 484 snd_mtxunlock(sc->lock); 485 return 0; 486 } 487 488 static int 489 cmichan_getptr(kobj_t obj, void *data) 490 { 491 struct sc_chinfo *ch = data; 492 struct sc_info *sc = ch->parent; 493 u_int32_t physptr, bufptr, sz; 494 495 snd_mtxlock(sc->lock); 496 if (ch->dir == PCMDIR_PLAY) { 497 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 498 } else { 499 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 500 } 501 snd_mtxunlock(sc->lock); 502 503 sz = sndbuf_getsize(ch->buffer); 504 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 505 506 return bufptr; 507 } 508 509 static void 510 cmi_intr(void *data) 511 { 512 struct sc_info *sc = data; 513 u_int32_t intrstat; 514 515 snd_mtxlock(sc->lock); 516 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 517 if ((intrstat & CMPCI_REG_ANY_INTR) == 0) { 518 goto out; 519 } 520 521 /* Disable interrupts */ 522 if (intrstat & CMPCI_REG_CH0_INTR) { 523 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 524 } 525 526 if (intrstat & CMPCI_REG_CH1_INTR) { 527 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 528 } 529 530 /* Signal interrupts to channel */ 531 if (intrstat & CMPCI_REG_CH0_INTR) { 532 chn_intr(sc->pch.channel); 533 } 534 535 if (intrstat & CMPCI_REG_CH1_INTR) { 536 chn_intr(sc->rch.channel); 537 } 538 539 /* Enable interrupts */ 540 if (intrstat & CMPCI_REG_CH0_INTR) { 541 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 542 } 543 544 if (intrstat & CMPCI_REG_CH1_INTR) { 545 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 546 } 547 548 out: 549 snd_mtxunlock(sc->lock); 550 return; 551 } 552 553 static struct pcmchan_caps * 554 cmichan_getcaps(kobj_t obj, void *data) 555 { 556 return &cmi_caps; 557 } 558 559 static kobj_method_t cmichan_methods[] = { 560 KOBJMETHOD(channel_init, cmichan_init), 561 KOBJMETHOD(channel_setformat, cmichan_setformat), 562 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 563 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 564 KOBJMETHOD(channel_trigger, cmichan_trigger), 565 KOBJMETHOD(channel_getptr, cmichan_getptr), 566 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 567 { 0, 0 } 568 }; 569 CHANNEL_DECLARE(cmichan); 570 571 /* ------------------------------------------------------------------------- */ 572 /* Mixer - sb16 with kinks */ 573 574 static void 575 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 576 { 577 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 578 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 579 } 580 581 static u_int8_t 582 cmimix_rd(struct sc_info *sc, u_int8_t port) 583 { 584 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 585 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 586 } 587 588 struct sb16props { 589 u_int8_t rreg; /* right reg chan register */ 590 u_int8_t stereo:1; /* (no explanation needed, honest) */ 591 u_int8_t rec:1; /* recording source */ 592 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 593 u_int8_t oselect; /* output select mask */ 594 u_int8_t iselect; /* right input select mask */ 595 } static const cmt[SOUND_MIXER_NRDEVICES] = { 596 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 597 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 598 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 599 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 600 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 601 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 602 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 603 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 604 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 605 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 606 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 607 /* These controls are not implemented in CMI8738, but maybe at a 608 future date. They are not documented in C-Media documentation, 609 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 610 */ 611 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 612 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 613 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 614 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 615 /* The mic pre-amp is implemented with non-SB16 compatible 616 registers. */ 617 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 618 }; 619 620 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 621 622 static int 623 cmimix_init(struct snd_mixer *m) 624 { 625 struct sc_info *sc = mix_getdevinfo(m); 626 u_int32_t i,v; 627 628 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 629 if (cmt[i].bits) v |= 1 << i; 630 } 631 mix_setdevs(m, v); 632 633 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 634 if (cmt[i].rec) v |= 1 << i; 635 } 636 mix_setrecdevs(m, v); 637 638 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 639 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 640 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 641 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 642 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 643 return 0; 644 } 645 646 static int 647 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 648 { 649 struct sc_info *sc = mix_getdevinfo(m); 650 u_int32_t r, l, max; 651 u_int8_t v; 652 653 max = (1 << cmt[dev].bits) - 1; 654 655 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 656 /* For time being this can only be one thing (mic in 657 * mic/aux reg) */ 658 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 659 l = left * max / 100; 660 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 661 v |= ((l << 1) | (~l >> 3)) & 0x0f; 662 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 663 return 0; 664 } 665 666 l = (left * max / 100) << (8 - cmt[dev].bits); 667 if (cmt[dev].stereo) { 668 r = (right * max / 100) << (8 - cmt[dev].bits); 669 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 670 cmimix_wr(sc, cmt[dev].rreg, r); 671 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 672 "value 0x%02x:0x%02x\n", 673 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 674 } else { 675 r = l; 676 cmimix_wr(sc, cmt[dev].rreg, l); 677 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 678 "value 0x%02x:0x%02x\n", 679 dev, cmt[dev].rreg, l, l)); 680 } 681 682 /* Zero gain does not mute channel from output, but this does... */ 683 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 684 if (l == 0 && r == 0) { 685 v &= ~cmt[dev].oselect; 686 } else { 687 v |= cmt[dev].oselect; 688 } 689 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 690 691 return 0; 692 } 693 694 static int 695 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 696 { 697 struct sc_info *sc = mix_getdevinfo(m); 698 u_int32_t i, ml, sl; 699 700 ml = sl = 0; 701 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 702 if ((1<<i) & src) { 703 if (cmt[i].stereo) { 704 sl |= cmt[i].iselect; 705 } else { 706 ml |= cmt[i].iselect; 707 } 708 } 709 } 710 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 711 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 712 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 713 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 714 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 715 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 716 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 717 718 return src; 719 } 720 721 static kobj_method_t cmi_mixer_methods[] = { 722 KOBJMETHOD(mixer_init, cmimix_init), 723 KOBJMETHOD(mixer_set, cmimix_set), 724 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 725 { 0, 0 } 726 }; 727 MIXER_DECLARE(cmi_mixer); 728 729 /* ------------------------------------------------------------------------- */ 730 /* Power and reset */ 731 732 static void 733 cmi_power(struct sc_info *sc, int state) 734 { 735 switch (state) { 736 case 0: /* full power */ 737 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 738 break; 739 default: 740 /* power off */ 741 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 742 break; 743 } 744 } 745 746 static int 747 cmi_init(struct sc_info *sc) 748 { 749 /* Effect reset */ 750 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 751 DELAY(100); 752 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 753 754 /* Disable interrupts and channels */ 755 cmi_clr4(sc, CMPCI_REG_FUNC_0, 756 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 757 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 758 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 759 760 /* Configure DMA channels, ch0 = play, ch1 = capture */ 761 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 762 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 763 764 /* Attempt to enable 4 Channel output */ 765 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 766 767 /* Disable SPDIF1 - not compatible with config */ 768 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 769 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 770 771 return 0; 772 } 773 774 static void 775 cmi_uninit(struct sc_info *sc) 776 { 777 /* Disable interrupts and channels */ 778 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 779 CMPCI_REG_CH0_INTR_ENABLE | 780 CMPCI_REG_CH1_INTR_ENABLE | 781 CMPCI_REG_TDMA_INTR_ENABLE); 782 cmi_clr4(sc, CMPCI_REG_FUNC_0, 783 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 784 } 785 786 /* ------------------------------------------------------------------------- */ 787 /* Bus and device registration */ 788 static int 789 cmi_probe(device_t dev) 790 { 791 switch(pci_get_devid(dev)) { 792 case CMI8338A_PCI_ID: 793 device_set_desc(dev, "CMedia CMI8338A"); 794 return 0; 795 case CMI8338B_PCI_ID: 796 device_set_desc(dev, "CMedia CMI8338B"); 797 return 0; 798 case CMI8738_PCI_ID: 799 device_set_desc(dev, "CMedia CMI8738"); 800 return 0; 801 case CMI8738B_PCI_ID: 802 device_set_desc(dev, "CMedia CMI8738B"); 803 return 0; 804 default: 805 return ENXIO; 806 } 807 } 808 809 static int 810 cmi_attach(device_t dev) 811 { 812 struct snddev_info *d; 813 struct sc_info *sc; 814 u_int32_t data; 815 char status[SND_STATUSLEN]; 816 817 d = device_get_softc(dev); 818 sc = malloc(sizeof(struct sc_info), M_DEVBUF, M_NOWAIT | M_ZERO); 819 if (sc == NULL) { 820 device_printf(dev, "cannot allocate softc\n"); 821 return ENXIO; 822 } 823 824 sc->lock = snd_mtxcreate(device_get_nameunit(dev)); 825 data = pci_read_config(dev, PCIR_COMMAND, 2); 826 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 827 pci_write_config(dev, PCIR_COMMAND, data, 2); 828 data = pci_read_config(dev, PCIR_COMMAND, 2); 829 830 sc->regid = PCIR_MAPS; 831 sc->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->regid, 832 0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE); 833 if (!sc->reg) { 834 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 835 goto bad; 836 } 837 sc->st = rman_get_bustag(sc->reg); 838 sc->sh = rman_get_bushandle(sc->reg); 839 840 sc->irqid = 0; 841 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 842 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 843 if (!sc->irq || 844 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 845 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 846 goto bad; 847 } 848 849 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 850 851 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 852 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 853 /*highaddr*/BUS_SPACE_MAXADDR, 854 /*filter*/NULL, /*filterarg*/NULL, 855 /*maxsize*/sc->bufsz, /*nsegments*/1, 856 /*maxsegz*/0x3ffff, /*flags*/0, 857 &sc->parent_dmat) != 0) { 858 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 859 goto bad; 860 } 861 862 cmi_power(sc, 0); 863 if (cmi_init(sc)) 864 goto bad; 865 866 if (mixer_init(dev, &cmi_mixer_class, sc)) 867 goto bad; 868 869 if (pcm_register(dev, sc, 1, 1)) 870 goto bad; 871 872 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 873 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 874 875 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld", 876 rman_get_start(sc->reg), rman_get_start(sc->irq)); 877 pcm_setstatus(dev, status); 878 879 DEB(printf("cmi_attach: succeeded\n")); 880 return 0; 881 882 bad: 883 if (sc->parent_dmat) 884 bus_dma_tag_destroy(sc->parent_dmat); 885 if (sc->ih) 886 bus_teardown_intr(dev, sc->irq, sc->ih); 887 if (sc->irq) 888 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 889 if (sc->reg) 890 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 891 if (sc->lock) 892 snd_mtxfree(sc->lock); 893 if (sc) 894 free(sc, M_DEVBUF); 895 896 return ENXIO; 897 } 898 899 static int 900 cmi_detach(device_t dev) 901 { 902 struct sc_info *sc; 903 int r; 904 905 r = pcm_unregister(dev); 906 if (r) return r; 907 908 sc = pcm_getdevinfo(dev); 909 cmi_uninit(sc); 910 cmi_power(sc, 3); 911 912 bus_dma_tag_destroy(sc->parent_dmat); 913 bus_teardown_intr(dev, sc->irq, sc->ih); 914 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 915 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 916 snd_mtxfree(sc->lock); 917 free(sc, M_DEVBUF); 918 919 return 0; 920 } 921 922 static int 923 cmi_suspend(device_t dev) 924 { 925 struct sc_info *sc = pcm_getdevinfo(dev); 926 927 snd_mtxlock(sc->lock); 928 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 929 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 930 cmi_power(sc, 3); 931 snd_mtxunlock(sc->lock); 932 return 0; 933 } 934 935 static int 936 cmi_resume(device_t dev) 937 { 938 struct sc_info *sc = pcm_getdevinfo(dev); 939 940 snd_mtxlock(sc->lock); 941 cmi_power(sc, 0); 942 if (cmi_init(sc) != 0) { 943 device_printf(dev, "unable to reinitialize the card\n"); 944 snd_mtxunlock(sc->lock); 945 return ENXIO; 946 } 947 948 if (mixer_reinit(dev) == -1) { 949 device_printf(dev, "unable to reinitialize the mixer\n"); 950 snd_mtxunlock(sc->lock); 951 return ENXIO; 952 } 953 954 if (sc->pch.dma_was_active) { 955 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 956 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 957 cmi_ch0_start(sc, &sc->pch); 958 } 959 960 if (sc->rch.dma_was_active) { 961 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 962 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 963 cmi_ch1_start(sc, &sc->rch); 964 } 965 snd_mtxunlock(sc->lock); 966 return 0; 967 } 968 969 static device_method_t cmi_methods[] = { 970 DEVMETHOD(device_probe, cmi_probe), 971 DEVMETHOD(device_attach, cmi_attach), 972 DEVMETHOD(device_detach, cmi_detach), 973 DEVMETHOD(device_resume, cmi_resume), 974 DEVMETHOD(device_suspend, cmi_suspend), 975 { 0, 0 } 976 }; 977 978 static driver_t cmi_driver = { 979 "pcm", 980 cmi_methods, 981 PCM_SOFTC_SIZE 982 }; 983 984 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0); 985 MODULE_DEPEND(snd_cmi, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 986 MODULE_VERSION(snd_cmi, 1); 987