1 /*- 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * This driver exists largely as a result of other people's efforts. 27 * Much of register handling is based on NetBSD CMI8x38 audio driver 28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 30 * registers and the 8738 mixer devices. His Linux driver was also a 31 * useful reference point. 32 * 33 * TODO: MIDI 34 * 35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 36 * 37 * This card/code does not always manage to sample at 44100 - actual 38 * rate drifts slightly between recordings (usually 0-3%). No 39 * differences visible in register dumps between times that work and 40 * those that don't. 41 */ 42 43 #include <dev/sound/pcm/sound.h> 44 #include <dev/sound/pci/cmireg.h> 45 #include <dev/sound/isa/sb.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <sys/sysctl.h> 51 #include <dev/sound/midi/mpu401.h> 52 53 #include "mixer_if.h" 54 #include "mpufoi_if.h" 55 56 SND_DECLARE_FILE("$FreeBSD$"); 57 58 /* Supported chip ID's */ 59 #define CMI8338A_PCI_ID 0x010013f6 60 #define CMI8338B_PCI_ID 0x010113f6 61 #define CMI8738_PCI_ID 0x011113f6 62 #define CMI8738B_PCI_ID 0x011213f6 63 64 /* Buffer size max is 64k for permitted DMA boundaries */ 65 #define CMI_DEFAULT_BUFSZ 16384 66 67 /* Interrupts per length of buffer */ 68 #define CMI_INTR_PER_BUFFER 2 69 70 /* Clarify meaning of named defines in cmireg.h */ 71 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 72 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 73 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 74 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 75 76 /* Our indication of custom mixer control */ 77 #define CMPCI_NON_SB16_CONTROL 0xff 78 79 /* Debugging macro's */ 80 #undef DEB 81 #ifndef DEB 82 #define DEB(x) /* x */ 83 #endif /* DEB */ 84 85 #ifndef DEBMIX 86 #define DEBMIX(x) /* x */ 87 #endif /* DEBMIX */ 88 89 /* ------------------------------------------------------------------------- */ 90 /* Structures */ 91 92 struct sc_info; 93 94 struct sc_chinfo { 95 struct sc_info *parent; 96 struct pcm_channel *channel; 97 struct snd_dbuf *buffer; 98 u_int32_t fmt, spd, phys_buf, bps; 99 u_int32_t dma_active:1, dma_was_active:1; 100 int dir; 101 }; 102 103 struct sc_info { 104 device_t dev; 105 106 bus_space_tag_t st; 107 bus_space_handle_t sh; 108 bus_dma_tag_t parent_dmat; 109 struct resource *reg, *irq; 110 int regid, irqid; 111 void *ih; 112 struct mtx *lock; 113 114 int spdif_enabled; 115 unsigned int bufsz; 116 struct sc_chinfo pch, rch; 117 118 struct mpu401 *mpu; 119 mpu401_intr_t *mpu_intr; 120 struct resource *mpu_reg; 121 int mpu_regid; 122 bus_space_tag_t mpu_bt; 123 bus_space_handle_t mpu_bh; 124 }; 125 126 /* Channel caps */ 127 128 static u_int32_t cmi_fmt[] = { 129 AFMT_U8, 130 AFMT_STEREO | AFMT_U8, 131 AFMT_S16_LE, 132 AFMT_STEREO | AFMT_S16_LE, 133 0 134 }; 135 136 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 137 138 /* ------------------------------------------------------------------------- */ 139 /* Register Utilities */ 140 141 static u_int32_t 142 cmi_rd(struct sc_info *sc, int regno, int size) 143 { 144 switch (size) { 145 case 1: 146 return bus_space_read_1(sc->st, sc->sh, regno); 147 case 2: 148 return bus_space_read_2(sc->st, sc->sh, regno); 149 case 4: 150 return bus_space_read_4(sc->st, sc->sh, regno); 151 default: 152 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 153 return 0xFFFFFFFF; 154 } 155 } 156 157 static void 158 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 159 { 160 switch (size) { 161 case 1: 162 bus_space_write_1(sc->st, sc->sh, regno, data); 163 break; 164 case 2: 165 bus_space_write_2(sc->st, sc->sh, regno, data); 166 break; 167 case 4: 168 bus_space_write_4(sc->st, sc->sh, regno, data); 169 break; 170 } 171 } 172 173 static void 174 cmi_partial_wr4(struct sc_info *sc, 175 int reg, int shift, u_int32_t mask, u_int32_t val) 176 { 177 u_int32_t r; 178 179 r = cmi_rd(sc, reg, 4); 180 r &= ~(mask << shift); 181 r |= val << shift; 182 cmi_wr(sc, reg, r, 4); 183 } 184 185 static void 186 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 187 { 188 u_int32_t r; 189 190 r = cmi_rd(sc, reg, 4); 191 r &= ~mask; 192 cmi_wr(sc, reg, r, 4); 193 } 194 195 static void 196 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 197 { 198 u_int32_t r; 199 200 r = cmi_rd(sc, reg, 4); 201 r |= mask; 202 cmi_wr(sc, reg, r, 4); 203 } 204 205 /* ------------------------------------------------------------------------- */ 206 /* Rate Mapping */ 207 208 static int cmi_rates[] = {5512, 8000, 11025, 16000, 209 22050, 32000, 44100, 48000}; 210 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 211 212 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 213 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 214 215 static u_int32_t 216 cmpci_rate_to_regvalue(int rate) 217 { 218 int i, r; 219 220 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 221 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 222 break; 223 } 224 } 225 226 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 227 228 r = ((i >> 1) | (i << 2)) & 0x07; 229 return r; 230 } 231 232 static int 233 cmpci_regvalue_to_rate(u_int32_t r) 234 { 235 int i; 236 237 i = ((r << 1) | (r >> 2)) & 0x07; 238 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 239 return cmi_rates[i]; 240 } 241 242 /* ------------------------------------------------------------------------- */ 243 /* ADC/DAC control - there are 2 dma channels on 8738, either can be 244 * playback or capture. We use ch0 for playback and ch1 for capture. */ 245 246 static void 247 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 248 { 249 u_int32_t s, i, sz; 250 251 ch->phys_buf = sndbuf_getbufaddr(ch->buffer); 252 253 cmi_wr(sc, base, ch->phys_buf, 4); 254 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 255 256 s = sz / ch->bps - 1; 257 cmi_wr(sc, base + 4, s, 2); 258 259 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 260 cmi_wr(sc, base + 6, i, 2); 261 } 262 263 264 static void 265 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 266 { 267 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 268 269 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 270 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 271 CMPCI_REG_CH0_INTR_ENABLE); 272 273 ch->dma_active = 1; 274 } 275 276 static u_int32_t 277 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 278 { 279 u_int32_t r = ch->dma_active; 280 281 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 282 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 283 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 284 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 285 ch->dma_active = 0; 286 return r; 287 } 288 289 static void 290 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 291 { 292 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 293 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 294 /* Enable Interrupts */ 295 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 296 CMPCI_REG_CH1_INTR_ENABLE); 297 DEB(printf("cmi_ch1_start: dma prog\n")); 298 ch->dma_active = 1; 299 } 300 301 static u_int32_t 302 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 303 { 304 u_int32_t r = ch->dma_active; 305 306 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 307 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 308 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 309 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 310 ch->dma_active = 0; 311 return r; 312 } 313 314 static void 315 cmi_spdif_speed(struct sc_info *sc, int speed) { 316 u_int32_t fcr1, lcr, mcr; 317 318 if (speed >= 44100) { 319 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 320 lcr = CMPCI_REG_XSPDIF_ENABLE; 321 mcr = (speed == 48000) ? 322 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 323 } else { 324 fcr1 = mcr = lcr = 0; 325 } 326 327 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 328 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 329 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 330 CMPCI_REG_SPDIF0_ENABLE, fcr1); 331 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 332 CMPCI_REG_XSPDIF_ENABLE, lcr); 333 } 334 335 /* ------------------------------------------------------------------------- */ 336 /* Channel Interface implementation */ 337 338 static void * 339 cmichan_init(kobj_t obj, void *devinfo, 340 struct snd_dbuf *b, struct pcm_channel *c, int dir) 341 { 342 struct sc_info *sc = devinfo; 343 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 344 345 ch->parent = sc; 346 ch->channel = c; 347 ch->bps = 1; 348 ch->fmt = AFMT_U8; 349 ch->spd = DSP_DEFAULT_SPEED; 350 ch->buffer = b; 351 ch->dma_active = 0; 352 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 353 DEB(printf("cmichan_init failed\n")); 354 return NULL; 355 } 356 357 ch->dir = dir; 358 snd_mtxlock(sc->lock); 359 if (ch->dir == PCMDIR_PLAY) { 360 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 361 } else { 362 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 363 } 364 snd_mtxunlock(sc->lock); 365 366 return ch; 367 } 368 369 static int 370 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 371 { 372 struct sc_chinfo *ch = data; 373 struct sc_info *sc = ch->parent; 374 u_int32_t f; 375 376 if (format & AFMT_S16_LE) { 377 f = CMPCI_REG_FORMAT_16BIT; 378 ch->bps = 2; 379 } else { 380 f = CMPCI_REG_FORMAT_8BIT; 381 ch->bps = 1; 382 } 383 384 if (format & AFMT_STEREO) { 385 f |= CMPCI_REG_FORMAT_STEREO; 386 ch->bps *= 2; 387 } else { 388 f |= CMPCI_REG_FORMAT_MONO; 389 } 390 391 snd_mtxlock(sc->lock); 392 if (ch->dir == PCMDIR_PLAY) { 393 cmi_partial_wr4(ch->parent, 394 CMPCI_REG_CHANNEL_FORMAT, 395 CMPCI_REG_CH0_FORMAT_SHIFT, 396 CMPCI_REG_CH0_FORMAT_MASK, 397 f); 398 } else { 399 cmi_partial_wr4(ch->parent, 400 CMPCI_REG_CHANNEL_FORMAT, 401 CMPCI_REG_CH1_FORMAT_SHIFT, 402 CMPCI_REG_CH1_FORMAT_MASK, 403 f); 404 } 405 snd_mtxunlock(sc->lock); 406 ch->fmt = format; 407 408 return 0; 409 } 410 411 static int 412 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 413 { 414 struct sc_chinfo *ch = data; 415 struct sc_info *sc = ch->parent; 416 u_int32_t r, rsp; 417 418 r = cmpci_rate_to_regvalue(speed); 419 snd_mtxlock(sc->lock); 420 if (ch->dir == PCMDIR_PLAY) { 421 if (speed < 44100) { 422 /* disable if req before rate change */ 423 cmi_spdif_speed(ch->parent, speed); 424 } 425 cmi_partial_wr4(ch->parent, 426 CMPCI_REG_FUNC_1, 427 CMPCI_REG_DAC_FS_SHIFT, 428 CMPCI_REG_DAC_FS_MASK, 429 r); 430 if (speed >= 44100 && ch->parent->spdif_enabled) { 431 /* enable if req after rate change */ 432 cmi_spdif_speed(ch->parent, speed); 433 } 434 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 435 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 436 rsp &= CMPCI_REG_DAC_FS_MASK; 437 } else { 438 cmi_partial_wr4(ch->parent, 439 CMPCI_REG_FUNC_1, 440 CMPCI_REG_ADC_FS_SHIFT, 441 CMPCI_REG_ADC_FS_MASK, 442 r); 443 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 444 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 445 rsp &= CMPCI_REG_ADC_FS_MASK; 446 } 447 snd_mtxunlock(sc->lock); 448 ch->spd = cmpci_regvalue_to_rate(r); 449 450 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 451 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 452 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 453 454 return ch->spd; 455 } 456 457 static int 458 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 459 { 460 struct sc_chinfo *ch = data; 461 struct sc_info *sc = ch->parent; 462 463 /* user has requested interrupts every blocksize bytes */ 464 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 465 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 466 } 467 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 468 469 return blocksize; 470 } 471 472 static int 473 cmichan_trigger(kobj_t obj, void *data, int go) 474 { 475 struct sc_chinfo *ch = data; 476 struct sc_info *sc = ch->parent; 477 478 if (!PCMTRIG_COMMON(go)) 479 return 0; 480 481 snd_mtxlock(sc->lock); 482 if (ch->dir == PCMDIR_PLAY) { 483 switch(go) { 484 case PCMTRIG_START: 485 cmi_ch0_start(sc, ch); 486 break; 487 case PCMTRIG_STOP: 488 case PCMTRIG_ABORT: 489 cmi_ch0_stop(sc, ch); 490 break; 491 } 492 } else { 493 switch(go) { 494 case PCMTRIG_START: 495 cmi_ch1_start(sc, ch); 496 break; 497 case PCMTRIG_STOP: 498 case PCMTRIG_ABORT: 499 cmi_ch1_stop(sc, ch); 500 break; 501 } 502 } 503 snd_mtxunlock(sc->lock); 504 return 0; 505 } 506 507 static int 508 cmichan_getptr(kobj_t obj, void *data) 509 { 510 struct sc_chinfo *ch = data; 511 struct sc_info *sc = ch->parent; 512 u_int32_t physptr, bufptr, sz; 513 514 snd_mtxlock(sc->lock); 515 if (ch->dir == PCMDIR_PLAY) { 516 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 517 } else { 518 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 519 } 520 snd_mtxunlock(sc->lock); 521 522 sz = sndbuf_getsize(ch->buffer); 523 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 524 525 return bufptr; 526 } 527 528 static void 529 cmi_intr(void *data) 530 { 531 struct sc_info *sc = data; 532 u_int32_t intrstat; 533 u_int32_t toclear; 534 535 snd_mtxlock(sc->lock); 536 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 537 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) { 538 539 toclear = 0; 540 if (intrstat & CMPCI_REG_CH0_INTR) { 541 toclear |= CMPCI_REG_CH0_INTR_ENABLE; 542 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 543 } 544 545 if (intrstat & CMPCI_REG_CH1_INTR) { 546 toclear |= CMPCI_REG_CH1_INTR_ENABLE; 547 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 548 } 549 550 if (toclear) { 551 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear); 552 snd_mtxunlock(sc->lock); 553 554 /* Signal interrupts to channel */ 555 if (intrstat & CMPCI_REG_CH0_INTR) { 556 chn_intr(sc->pch.channel); 557 } 558 559 if (intrstat & CMPCI_REG_CH1_INTR) { 560 chn_intr(sc->rch.channel); 561 } 562 563 snd_mtxlock(sc->lock); 564 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear); 565 566 } 567 } 568 if(sc->mpu_intr) { 569 (sc->mpu_intr)(sc->mpu); 570 } 571 snd_mtxunlock(sc->lock); 572 return; 573 } 574 575 static struct pcmchan_caps * 576 cmichan_getcaps(kobj_t obj, void *data) 577 { 578 return &cmi_caps; 579 } 580 581 static kobj_method_t cmichan_methods[] = { 582 KOBJMETHOD(channel_init, cmichan_init), 583 KOBJMETHOD(channel_setformat, cmichan_setformat), 584 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 585 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 586 KOBJMETHOD(channel_trigger, cmichan_trigger), 587 KOBJMETHOD(channel_getptr, cmichan_getptr), 588 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 589 { 0, 0 } 590 }; 591 CHANNEL_DECLARE(cmichan); 592 593 /* ------------------------------------------------------------------------- */ 594 /* Mixer - sb16 with kinks */ 595 596 static void 597 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 598 { 599 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 600 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 601 } 602 603 static u_int8_t 604 cmimix_rd(struct sc_info *sc, u_int8_t port) 605 { 606 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 607 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 608 } 609 610 struct sb16props { 611 u_int8_t rreg; /* right reg chan register */ 612 u_int8_t stereo:1; /* (no explanation needed, honest) */ 613 u_int8_t rec:1; /* recording source */ 614 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 615 u_int8_t oselect; /* output select mask */ 616 u_int8_t iselect; /* right input select mask */ 617 } static const cmt[SOUND_MIXER_NRDEVICES] = { 618 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 619 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 620 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 621 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 622 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 623 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 624 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 625 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 626 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 627 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 628 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 629 /* These controls are not implemented in CMI8738, but maybe at a 630 future date. They are not documented in C-Media documentation, 631 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 632 */ 633 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 634 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 635 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 636 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 637 /* The mic pre-amp is implemented with non-SB16 compatible 638 registers. */ 639 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 640 }; 641 642 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 643 644 static int 645 cmimix_init(struct snd_mixer *m) 646 { 647 struct sc_info *sc = mix_getdevinfo(m); 648 u_int32_t i,v; 649 650 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 651 if (cmt[i].bits) v |= 1 << i; 652 } 653 mix_setdevs(m, v); 654 655 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 656 if (cmt[i].rec) v |= 1 << i; 657 } 658 mix_setrecdevs(m, v); 659 660 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 661 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 662 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 663 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 664 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 665 return 0; 666 } 667 668 static int 669 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 670 { 671 struct sc_info *sc = mix_getdevinfo(m); 672 u_int32_t r, l, max; 673 u_int8_t v; 674 675 max = (1 << cmt[dev].bits) - 1; 676 677 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 678 /* For time being this can only be one thing (mic in 679 * mic/aux reg) */ 680 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 681 l = left * max / 100; 682 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 683 v |= ((l << 1) | (~l >> 3)) & 0x0f; 684 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 685 return 0; 686 } 687 688 l = (left * max / 100) << (8 - cmt[dev].bits); 689 if (cmt[dev].stereo) { 690 r = (right * max / 100) << (8 - cmt[dev].bits); 691 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 692 cmimix_wr(sc, cmt[dev].rreg, r); 693 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 694 "value 0x%02x:0x%02x\n", 695 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 696 } else { 697 r = l; 698 cmimix_wr(sc, cmt[dev].rreg, l); 699 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 700 "value 0x%02x:0x%02x\n", 701 dev, cmt[dev].rreg, l, l)); 702 } 703 704 /* Zero gain does not mute channel from output, but this does... */ 705 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 706 if (l == 0 && r == 0) { 707 v &= ~cmt[dev].oselect; 708 } else { 709 v |= cmt[dev].oselect; 710 } 711 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 712 713 return 0; 714 } 715 716 static int 717 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 718 { 719 struct sc_info *sc = mix_getdevinfo(m); 720 u_int32_t i, ml, sl; 721 722 ml = sl = 0; 723 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 724 if ((1<<i) & src) { 725 if (cmt[i].stereo) { 726 sl |= cmt[i].iselect; 727 } else { 728 ml |= cmt[i].iselect; 729 } 730 } 731 } 732 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 733 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 734 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 735 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 736 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 737 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 738 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 739 740 return src; 741 } 742 743 /* Optional SPDIF support. */ 744 745 static int 746 cmi_initsys(struct sc_info* sc) 747 { 748 #ifdef SND_DYNSYSCTL 749 /* XXX: an user should be able to set this with a control tool, 750 if not done before 7.0-RELEASE, this needs to be converted 751 to a device specific sysctl "dev.pcm.X.yyy" via 752 device_get_sysctl_*() as discussed on multimedia@ in msg-id 753 <861wujij2q.fsf@xps.des.no> */ 754 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 755 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 756 OID_AUTO, "spdif_enabled", CTLFLAG_RW, 757 &sc->spdif_enabled, 0, 758 "enable SPDIF output at 44.1 kHz and above"); 759 #endif /* SND_DYNSYSCTL */ 760 return 0; 761 } 762 763 /* ------------------------------------------------------------------------- */ 764 static kobj_method_t cmi_mixer_methods[] = { 765 KOBJMETHOD(mixer_init, cmimix_init), 766 KOBJMETHOD(mixer_set, cmimix_set), 767 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 768 { 0, 0 } 769 }; 770 MIXER_DECLARE(cmi_mixer); 771 772 /* 773 * mpu401 functions 774 */ 775 776 static unsigned char 777 cmi_mread(void *arg, struct sc_info *sc, int reg) 778 { 779 unsigned int d; 780 781 d = bus_space_read_1(0,0, 0x330 + reg); 782 /* printf("cmi_mread: reg %x %x\n",reg, d); 783 */ 784 return d; 785 } 786 787 static void 788 cmi_mwrite(void *arg, struct sc_info *sc, int reg, unsigned char b) 789 { 790 791 bus_space_write_1(0,0,0x330 + reg , b); 792 } 793 794 static int 795 cmi_muninit(void *arg, struct sc_info *sc) 796 { 797 798 snd_mtxlock(sc->lock); 799 sc->mpu_intr = 0; 800 sc->mpu = 0; 801 snd_mtxunlock(sc->lock); 802 803 return 0; 804 } 805 806 static kobj_method_t cmi_mpu_methods[] = { 807 KOBJMETHOD(mpufoi_read, cmi_mread), 808 KOBJMETHOD(mpufoi_write, cmi_mwrite), 809 KOBJMETHOD(mpufoi_uninit, cmi_muninit), 810 { 0, 0 } 811 }; 812 813 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0); 814 815 static void 816 cmi_midiattach(struct sc_info *sc) { 817 /* 818 const struct { 819 int port,bits; 820 } *p, ports[] = { 821 {0x330,0}, 822 {0x320,1}, 823 {0x310,2}, 824 {0x300,3}, 825 {0,0} } ; 826 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does 827 anyone know how to bus_space tag? 828 */ 829 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 830 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL, 831 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT); 832 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL, 833 0 << CMPCI_REG_VMPUSEL_SHIFT ); 834 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 835 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr); 836 } 837 838 839 840 /* ------------------------------------------------------------------------- */ 841 /* Power and reset */ 842 843 static void 844 cmi_power(struct sc_info *sc, int state) 845 { 846 switch (state) { 847 case 0: /* full power */ 848 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 849 break; 850 default: 851 /* power off */ 852 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 853 break; 854 } 855 } 856 857 static int 858 cmi_init(struct sc_info *sc) 859 { 860 /* Effect reset */ 861 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 862 DELAY(100); 863 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 864 865 /* Disable interrupts and channels */ 866 cmi_clr4(sc, CMPCI_REG_FUNC_0, 867 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 868 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 869 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 870 871 /* Configure DMA channels, ch0 = play, ch1 = capture */ 872 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 873 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 874 875 /* Attempt to enable 4 Channel output */ 876 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 877 878 /* Disable SPDIF1 - not compatible with config */ 879 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 880 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 881 882 return 0; 883 } 884 885 static void 886 cmi_uninit(struct sc_info *sc) 887 { 888 /* Disable interrupts and channels */ 889 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 890 CMPCI_REG_CH0_INTR_ENABLE | 891 CMPCI_REG_CH1_INTR_ENABLE | 892 CMPCI_REG_TDMA_INTR_ENABLE); 893 cmi_clr4(sc, CMPCI_REG_FUNC_0, 894 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 895 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 896 897 if( sc->mpu ) 898 sc->mpu_intr = 0; 899 } 900 901 /* ------------------------------------------------------------------------- */ 902 /* Bus and device registration */ 903 static int 904 cmi_probe(device_t dev) 905 { 906 switch(pci_get_devid(dev)) { 907 case CMI8338A_PCI_ID: 908 device_set_desc(dev, "CMedia CMI8338A"); 909 return BUS_PROBE_DEFAULT; 910 case CMI8338B_PCI_ID: 911 device_set_desc(dev, "CMedia CMI8338B"); 912 return BUS_PROBE_DEFAULT; 913 case CMI8738_PCI_ID: 914 device_set_desc(dev, "CMedia CMI8738"); 915 return BUS_PROBE_DEFAULT; 916 case CMI8738B_PCI_ID: 917 device_set_desc(dev, "CMedia CMI8738B"); 918 return BUS_PROBE_DEFAULT; 919 default: 920 return ENXIO; 921 } 922 } 923 924 static int 925 cmi_attach(device_t dev) 926 { 927 struct sc_info *sc; 928 u_int32_t data; 929 char status[SND_STATUSLEN]; 930 931 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 932 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc"); 933 data = pci_read_config(dev, PCIR_COMMAND, 2); 934 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 935 pci_write_config(dev, PCIR_COMMAND, data, 2); 936 data = pci_read_config(dev, PCIR_COMMAND, 2); 937 938 sc->dev = dev; 939 sc->regid = PCIR_BAR(0); 940 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid, 941 RF_ACTIVE); 942 if (!sc->reg) { 943 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 944 goto bad; 945 } 946 sc->st = rman_get_bustag(sc->reg); 947 sc->sh = rman_get_bushandle(sc->reg); 948 949 if (0) 950 cmi_midiattach(sc); 951 952 sc->irqid = 0; 953 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 954 RF_ACTIVE | RF_SHAREABLE); 955 if (!sc->irq || 956 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 957 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 958 goto bad; 959 } 960 961 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 962 963 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 964 /*boundary*/0, 965 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 966 /*highaddr*/BUS_SPACE_MAXADDR, 967 /*filter*/NULL, /*filterarg*/NULL, 968 /*maxsize*/sc->bufsz, /*nsegments*/1, 969 /*maxsegz*/0x3ffff, /*flags*/0, 970 /*lockfunc*/NULL, 971 /*lockfunc*/NULL, 972 &sc->parent_dmat) != 0) { 973 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 974 goto bad; 975 } 976 977 cmi_power(sc, 0); 978 if (cmi_init(sc)) 979 goto bad; 980 981 if (mixer_init(dev, &cmi_mixer_class, sc)) 982 goto bad; 983 984 if (pcm_register(dev, sc, 1, 1)) 985 goto bad; 986 987 cmi_initsys(sc); 988 989 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 990 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 991 992 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 993 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi)); 994 pcm_setstatus(dev, status); 995 996 DEB(printf("cmi_attach: succeeded\n")); 997 return 0; 998 999 bad: 1000 if (sc->parent_dmat) 1001 bus_dma_tag_destroy(sc->parent_dmat); 1002 if (sc->ih) 1003 bus_teardown_intr(dev, sc->irq, sc->ih); 1004 if (sc->irq) 1005 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1006 if (sc->reg) 1007 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1008 if (sc->lock) 1009 snd_mtxfree(sc->lock); 1010 if (sc) 1011 free(sc, M_DEVBUF); 1012 1013 return ENXIO; 1014 } 1015 1016 static int 1017 cmi_detach(device_t dev) 1018 { 1019 struct sc_info *sc; 1020 int r; 1021 1022 r = pcm_unregister(dev); 1023 if (r) return r; 1024 1025 sc = pcm_getdevinfo(dev); 1026 cmi_uninit(sc); 1027 cmi_power(sc, 3); 1028 1029 bus_dma_tag_destroy(sc->parent_dmat); 1030 bus_teardown_intr(dev, sc->irq, sc->ih); 1031 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1032 if(sc->mpu) 1033 mpu401_uninit(sc->mpu); 1034 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1035 if (sc->mpu_reg) 1036 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg); 1037 1038 snd_mtxfree(sc->lock); 1039 free(sc, M_DEVBUF); 1040 1041 return 0; 1042 } 1043 1044 static int 1045 cmi_suspend(device_t dev) 1046 { 1047 struct sc_info *sc = pcm_getdevinfo(dev); 1048 1049 snd_mtxlock(sc->lock); 1050 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 1051 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 1052 cmi_power(sc, 3); 1053 snd_mtxunlock(sc->lock); 1054 return 0; 1055 } 1056 1057 static int 1058 cmi_resume(device_t dev) 1059 { 1060 struct sc_info *sc = pcm_getdevinfo(dev); 1061 1062 snd_mtxlock(sc->lock); 1063 cmi_power(sc, 0); 1064 if (cmi_init(sc) != 0) { 1065 device_printf(dev, "unable to reinitialize the card\n"); 1066 snd_mtxunlock(sc->lock); 1067 return ENXIO; 1068 } 1069 1070 if (mixer_reinit(dev) == -1) { 1071 device_printf(dev, "unable to reinitialize the mixer\n"); 1072 snd_mtxunlock(sc->lock); 1073 return ENXIO; 1074 } 1075 1076 if (sc->pch.dma_was_active) { 1077 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 1078 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 1079 cmi_ch0_start(sc, &sc->pch); 1080 } 1081 1082 if (sc->rch.dma_was_active) { 1083 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 1084 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 1085 cmi_ch1_start(sc, &sc->rch); 1086 } 1087 snd_mtxunlock(sc->lock); 1088 return 0; 1089 } 1090 1091 static device_method_t cmi_methods[] = { 1092 DEVMETHOD(device_probe, cmi_probe), 1093 DEVMETHOD(device_attach, cmi_attach), 1094 DEVMETHOD(device_detach, cmi_detach), 1095 DEVMETHOD(device_resume, cmi_resume), 1096 DEVMETHOD(device_suspend, cmi_suspend), 1097 { 0, 0 } 1098 }; 1099 1100 static driver_t cmi_driver = { 1101 "pcm", 1102 cmi_methods, 1103 PCM_SOFTC_SIZE 1104 }; 1105 1106 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0); 1107 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1108 MODULE_DEPEND(snd_cmi, midi, 1,1,1); 1109 MODULE_VERSION(snd_cmi, 1); 1110