1 /*- 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This driver exists largely as a result of other people's efforts. 29 * Much of register handling is based on NetBSD CMI8x38 audio driver 30 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 31 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 32 * registers and the 8738 mixer devices. His Linux driver was also a 33 * useful reference point. 34 * 35 * TODO: MIDI 36 * 37 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 38 * 39 * This card/code does not always manage to sample at 44100 - actual 40 * rate drifts slightly between recordings (usually 0-3%). No 41 * differences visible in register dumps between times that work and 42 * those that don't. 43 */ 44 45 #include <dev/sound/pcm/sound.h> 46 #include <dev/sound/pci/cmireg.h> 47 #include <dev/sound/isa/sb.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #include <sys/sysctl.h> 53 #include <dev/sound/midi/mpu401.h> 54 55 #include "mixer_if.h" 56 #include "mpufoi_if.h" 57 58 SND_DECLARE_FILE("$FreeBSD$"); 59 60 /* Supported chip ID's */ 61 #define CMI8338A_PCI_ID 0x010013f6 62 #define CMI8338B_PCI_ID 0x010113f6 63 #define CMI8738_PCI_ID 0x011113f6 64 #define CMI8738B_PCI_ID 0x011213f6 65 #define CMI120_USB_ID 0x01030d8c 66 67 /* Buffer size max is 64k for permitted DMA boundaries */ 68 #define CMI_DEFAULT_BUFSZ 16384 69 70 /* Interrupts per length of buffer */ 71 #define CMI_INTR_PER_BUFFER 2 72 73 /* Clarify meaning of named defines in cmireg.h */ 74 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 75 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 76 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 77 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 78 79 /* Our indication of custom mixer control */ 80 #define CMPCI_NON_SB16_CONTROL 0xff 81 82 /* Debugging macro's */ 83 #undef DEB 84 #ifndef DEB 85 #define DEB(x) /* x */ 86 #endif /* DEB */ 87 88 #ifndef DEBMIX 89 #define DEBMIX(x) /* x */ 90 #endif /* DEBMIX */ 91 92 /* ------------------------------------------------------------------------- */ 93 /* Structures */ 94 95 struct sc_info; 96 97 struct sc_chinfo { 98 struct sc_info *parent; 99 struct pcm_channel *channel; 100 struct snd_dbuf *buffer; 101 u_int32_t fmt, spd, phys_buf, bps; 102 u_int32_t dma_active:1, dma_was_active:1; 103 int dir; 104 }; 105 106 struct sc_info { 107 device_t dev; 108 109 bus_space_tag_t st; 110 bus_space_handle_t sh; 111 bus_dma_tag_t parent_dmat; 112 struct resource *reg, *irq; 113 int regid, irqid; 114 void *ih; 115 struct mtx *lock; 116 117 int spdif_enabled; 118 unsigned int bufsz; 119 struct sc_chinfo pch, rch; 120 121 struct mpu401 *mpu; 122 mpu401_intr_t *mpu_intr; 123 struct resource *mpu_reg; 124 int mpu_regid; 125 bus_space_tag_t mpu_bt; 126 bus_space_handle_t mpu_bh; 127 }; 128 129 /* Channel caps */ 130 131 static u_int32_t cmi_fmt[] = { 132 AFMT_U8, 133 AFMT_STEREO | AFMT_U8, 134 AFMT_S16_LE, 135 AFMT_STEREO | AFMT_S16_LE, 136 0 137 }; 138 139 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 140 141 /* ------------------------------------------------------------------------- */ 142 /* Register Utilities */ 143 144 static u_int32_t 145 cmi_rd(struct sc_info *sc, int regno, int size) 146 { 147 switch (size) { 148 case 1: 149 return bus_space_read_1(sc->st, sc->sh, regno); 150 case 2: 151 return bus_space_read_2(sc->st, sc->sh, regno); 152 case 4: 153 return bus_space_read_4(sc->st, sc->sh, regno); 154 default: 155 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 156 return 0xFFFFFFFF; 157 } 158 } 159 160 static void 161 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size) 162 { 163 switch (size) { 164 case 1: 165 bus_space_write_1(sc->st, sc->sh, regno, data); 166 break; 167 case 2: 168 bus_space_write_2(sc->st, sc->sh, regno, data); 169 break; 170 case 4: 171 bus_space_write_4(sc->st, sc->sh, regno, data); 172 break; 173 } 174 } 175 176 static void 177 cmi_partial_wr4(struct sc_info *sc, 178 int reg, int shift, u_int32_t mask, u_int32_t val) 179 { 180 u_int32_t r; 181 182 r = cmi_rd(sc, reg, 4); 183 r &= ~(mask << shift); 184 r |= val << shift; 185 cmi_wr(sc, reg, r, 4); 186 } 187 188 static void 189 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask) 190 { 191 u_int32_t r; 192 193 r = cmi_rd(sc, reg, 4); 194 r &= ~mask; 195 cmi_wr(sc, reg, r, 4); 196 } 197 198 static void 199 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask) 200 { 201 u_int32_t r; 202 203 r = cmi_rd(sc, reg, 4); 204 r |= mask; 205 cmi_wr(sc, reg, r, 4); 206 } 207 208 /* ------------------------------------------------------------------------- */ 209 /* Rate Mapping */ 210 211 static int cmi_rates[] = {5512, 8000, 11025, 16000, 212 22050, 32000, 44100, 48000}; 213 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 214 215 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 216 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 217 218 static u_int32_t 219 cmpci_rate_to_regvalue(int rate) 220 { 221 int i, r; 222 223 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 224 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 225 break; 226 } 227 } 228 229 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 230 231 r = ((i >> 1) | (i << 2)) & 0x07; 232 return r; 233 } 234 235 static int 236 cmpci_regvalue_to_rate(u_int32_t r) 237 { 238 int i; 239 240 i = ((r << 1) | (r >> 2)) & 0x07; 241 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 242 return cmi_rates[i]; 243 } 244 245 /* ------------------------------------------------------------------------- */ 246 /* ADC/DAC control - there are 2 dma channels on 8738, either can be 247 * playback or capture. We use ch0 for playback and ch1 for capture. */ 248 249 static void 250 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base) 251 { 252 u_int32_t s, i, sz; 253 254 ch->phys_buf = sndbuf_getbufaddr(ch->buffer); 255 256 cmi_wr(sc, base, ch->phys_buf, 4); 257 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 258 259 s = sz / ch->bps - 1; 260 cmi_wr(sc, base + 4, s, 2); 261 262 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 263 cmi_wr(sc, base + 6, i, 2); 264 } 265 266 267 static void 268 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch) 269 { 270 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 271 272 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 273 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 274 CMPCI_REG_CH0_INTR_ENABLE); 275 276 ch->dma_active = 1; 277 } 278 279 static u_int32_t 280 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch) 281 { 282 u_int32_t r = ch->dma_active; 283 284 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 285 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 286 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 287 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 288 ch->dma_active = 0; 289 return r; 290 } 291 292 static void 293 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch) 294 { 295 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 296 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 297 /* Enable Interrupts */ 298 cmi_set4(sc, CMPCI_REG_INTR_CTRL, 299 CMPCI_REG_CH1_INTR_ENABLE); 300 DEB(printf("cmi_ch1_start: dma prog\n")); 301 ch->dma_active = 1; 302 } 303 304 static u_int32_t 305 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch) 306 { 307 u_int32_t r = ch->dma_active; 308 309 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 310 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 311 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 312 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 313 ch->dma_active = 0; 314 return r; 315 } 316 317 static void 318 cmi_spdif_speed(struct sc_info *sc, int speed) { 319 u_int32_t fcr1, lcr, mcr; 320 321 if (speed >= 44100) { 322 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 323 lcr = CMPCI_REG_XSPDIF_ENABLE; 324 mcr = (speed == 48000) ? 325 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 326 } else { 327 fcr1 = mcr = lcr = 0; 328 } 329 330 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0, 331 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 332 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0, 333 CMPCI_REG_SPDIF0_ENABLE, fcr1); 334 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0, 335 CMPCI_REG_XSPDIF_ENABLE, lcr); 336 } 337 338 /* ------------------------------------------------------------------------- */ 339 /* Channel Interface implementation */ 340 341 static void * 342 cmichan_init(kobj_t obj, void *devinfo, 343 struct snd_dbuf *b, struct pcm_channel *c, int dir) 344 { 345 struct sc_info *sc = devinfo; 346 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 347 348 ch->parent = sc; 349 ch->channel = c; 350 ch->bps = 1; 351 ch->fmt = AFMT_U8; 352 ch->spd = DSP_DEFAULT_SPEED; 353 ch->buffer = b; 354 ch->dma_active = 0; 355 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 356 DEB(printf("cmichan_init failed\n")); 357 return NULL; 358 } 359 360 ch->dir = dir; 361 snd_mtxlock(sc->lock); 362 if (ch->dir == PCMDIR_PLAY) { 363 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE); 364 } else { 365 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE); 366 } 367 snd_mtxunlock(sc->lock); 368 369 return ch; 370 } 371 372 static int 373 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 374 { 375 struct sc_chinfo *ch = data; 376 struct sc_info *sc = ch->parent; 377 u_int32_t f; 378 379 if (format & AFMT_S16_LE) { 380 f = CMPCI_REG_FORMAT_16BIT; 381 ch->bps = 2; 382 } else { 383 f = CMPCI_REG_FORMAT_8BIT; 384 ch->bps = 1; 385 } 386 387 if (format & AFMT_STEREO) { 388 f |= CMPCI_REG_FORMAT_STEREO; 389 ch->bps *= 2; 390 } else { 391 f |= CMPCI_REG_FORMAT_MONO; 392 } 393 394 snd_mtxlock(sc->lock); 395 if (ch->dir == PCMDIR_PLAY) { 396 cmi_partial_wr4(ch->parent, 397 CMPCI_REG_CHANNEL_FORMAT, 398 CMPCI_REG_CH0_FORMAT_SHIFT, 399 CMPCI_REG_CH0_FORMAT_MASK, 400 f); 401 } else { 402 cmi_partial_wr4(ch->parent, 403 CMPCI_REG_CHANNEL_FORMAT, 404 CMPCI_REG_CH1_FORMAT_SHIFT, 405 CMPCI_REG_CH1_FORMAT_MASK, 406 f); 407 } 408 snd_mtxunlock(sc->lock); 409 ch->fmt = format; 410 411 return 0; 412 } 413 414 static int 415 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 416 { 417 struct sc_chinfo *ch = data; 418 struct sc_info *sc = ch->parent; 419 u_int32_t r, rsp; 420 421 r = cmpci_rate_to_regvalue(speed); 422 snd_mtxlock(sc->lock); 423 if (ch->dir == PCMDIR_PLAY) { 424 if (speed < 44100) { 425 /* disable if req before rate change */ 426 cmi_spdif_speed(ch->parent, speed); 427 } 428 cmi_partial_wr4(ch->parent, 429 CMPCI_REG_FUNC_1, 430 CMPCI_REG_DAC_FS_SHIFT, 431 CMPCI_REG_DAC_FS_MASK, 432 r); 433 if (speed >= 44100 && ch->parent->spdif_enabled) { 434 /* enable if req after rate change */ 435 cmi_spdif_speed(ch->parent, speed); 436 } 437 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 438 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 439 rsp &= CMPCI_REG_DAC_FS_MASK; 440 } else { 441 cmi_partial_wr4(ch->parent, 442 CMPCI_REG_FUNC_1, 443 CMPCI_REG_ADC_FS_SHIFT, 444 CMPCI_REG_ADC_FS_MASK, 445 r); 446 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 447 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 448 rsp &= CMPCI_REG_ADC_FS_MASK; 449 } 450 snd_mtxunlock(sc->lock); 451 ch->spd = cmpci_regvalue_to_rate(r); 452 453 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 454 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 455 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 456 457 return ch->spd; 458 } 459 460 static int 461 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 462 { 463 struct sc_chinfo *ch = data; 464 struct sc_info *sc = ch->parent; 465 466 /* user has requested interrupts every blocksize bytes */ 467 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) { 468 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER; 469 } 470 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 471 472 return blocksize; 473 } 474 475 static int 476 cmichan_trigger(kobj_t obj, void *data, int go) 477 { 478 struct sc_chinfo *ch = data; 479 struct sc_info *sc = ch->parent; 480 481 if (!PCMTRIG_COMMON(go)) 482 return 0; 483 484 snd_mtxlock(sc->lock); 485 if (ch->dir == PCMDIR_PLAY) { 486 switch(go) { 487 case PCMTRIG_START: 488 cmi_ch0_start(sc, ch); 489 break; 490 case PCMTRIG_STOP: 491 case PCMTRIG_ABORT: 492 cmi_ch0_stop(sc, ch); 493 break; 494 } 495 } else { 496 switch(go) { 497 case PCMTRIG_START: 498 cmi_ch1_start(sc, ch); 499 break; 500 case PCMTRIG_STOP: 501 case PCMTRIG_ABORT: 502 cmi_ch1_stop(sc, ch); 503 break; 504 } 505 } 506 snd_mtxunlock(sc->lock); 507 return 0; 508 } 509 510 static int 511 cmichan_getptr(kobj_t obj, void *data) 512 { 513 struct sc_chinfo *ch = data; 514 struct sc_info *sc = ch->parent; 515 u_int32_t physptr, bufptr, sz; 516 517 snd_mtxlock(sc->lock); 518 if (ch->dir == PCMDIR_PLAY) { 519 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4); 520 } else { 521 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4); 522 } 523 snd_mtxunlock(sc->lock); 524 525 sz = sndbuf_getsize(ch->buffer); 526 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 527 528 return bufptr; 529 } 530 531 static void 532 cmi_intr(void *data) 533 { 534 struct sc_info *sc = data; 535 u_int32_t intrstat; 536 u_int32_t toclear; 537 538 snd_mtxlock(sc->lock); 539 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4); 540 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) { 541 542 toclear = 0; 543 if (intrstat & CMPCI_REG_CH0_INTR) { 544 toclear |= CMPCI_REG_CH0_INTR_ENABLE; 545 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 546 } 547 548 if (intrstat & CMPCI_REG_CH1_INTR) { 549 toclear |= CMPCI_REG_CH1_INTR_ENABLE; 550 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 551 } 552 553 if (toclear) { 554 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear); 555 snd_mtxunlock(sc->lock); 556 557 /* Signal interrupts to channel */ 558 if (intrstat & CMPCI_REG_CH0_INTR) { 559 chn_intr(sc->pch.channel); 560 } 561 562 if (intrstat & CMPCI_REG_CH1_INTR) { 563 chn_intr(sc->rch.channel); 564 } 565 566 snd_mtxlock(sc->lock); 567 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear); 568 569 } 570 } 571 if(sc->mpu_intr) { 572 (sc->mpu_intr)(sc->mpu); 573 } 574 snd_mtxunlock(sc->lock); 575 return; 576 } 577 578 static struct pcmchan_caps * 579 cmichan_getcaps(kobj_t obj, void *data) 580 { 581 return &cmi_caps; 582 } 583 584 static kobj_method_t cmichan_methods[] = { 585 KOBJMETHOD(channel_init, cmichan_init), 586 KOBJMETHOD(channel_setformat, cmichan_setformat), 587 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 588 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 589 KOBJMETHOD(channel_trigger, cmichan_trigger), 590 KOBJMETHOD(channel_getptr, cmichan_getptr), 591 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 592 { 0, 0 } 593 }; 594 CHANNEL_DECLARE(cmichan); 595 596 /* ------------------------------------------------------------------------- */ 597 /* Mixer - sb16 with kinks */ 598 599 static void 600 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val) 601 { 602 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 603 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1); 604 } 605 606 static u_int8_t 607 cmimix_rd(struct sc_info *sc, u_int8_t port) 608 { 609 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1); 610 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1); 611 } 612 613 struct sb16props { 614 u_int8_t rreg; /* right reg chan register */ 615 u_int8_t stereo:1; /* (no explanation needed, honest) */ 616 u_int8_t rec:1; /* recording source */ 617 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 618 u_int8_t oselect; /* output select mask */ 619 u_int8_t iselect; /* right input select mask */ 620 } static const cmt[SOUND_MIXER_NRDEVICES] = { 621 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 622 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 623 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 624 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 625 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 626 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 627 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 628 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 629 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 630 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 631 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 632 /* These controls are not implemented in CMI8738, but maybe at a 633 future date. They are not documented in C-Media documentation, 634 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 635 */ 636 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 637 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 638 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 639 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 640 /* The mic pre-amp is implemented with non-SB16 compatible 641 registers. */ 642 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 643 }; 644 645 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 646 647 static int 648 cmimix_init(struct snd_mixer *m) 649 { 650 struct sc_info *sc = mix_getdevinfo(m); 651 u_int32_t i,v; 652 653 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 654 if (cmt[i].bits) v |= 1 << i; 655 } 656 mix_setdevs(m, v); 657 658 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) { 659 if (cmt[i].rec) v |= 1 << i; 660 } 661 mix_setrecdevs(m, v); 662 663 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0); 664 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 665 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 666 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, 667 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 668 return 0; 669 } 670 671 static int 672 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 673 { 674 struct sc_info *sc = mix_getdevinfo(m); 675 u_int32_t r, l, max; 676 u_int8_t v; 677 678 max = (1 << cmt[dev].bits) - 1; 679 680 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 681 /* For time being this can only be one thing (mic in 682 * mic/aux reg) */ 683 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0; 684 l = left * max / 100; 685 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */ 686 v |= ((l << 1) | (~l >> 3)) & 0x0f; 687 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1); 688 return 0; 689 } 690 691 l = (left * max / 100) << (8 - cmt[dev].bits); 692 if (cmt[dev].stereo) { 693 r = (right * max / 100) << (8 - cmt[dev].bits); 694 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 695 cmimix_wr(sc, cmt[dev].rreg, r); 696 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 697 "value 0x%02x:0x%02x\n", 698 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 699 } else { 700 r = l; 701 cmimix_wr(sc, cmt[dev].rreg, l); 702 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 703 "value 0x%02x:0x%02x\n", 704 dev, cmt[dev].rreg, l, l)); 705 } 706 707 /* Zero gain does not mute channel from output, but this does... */ 708 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX); 709 if (l == 0 && r == 0) { 710 v &= ~cmt[dev].oselect; 711 } else { 712 v |= cmt[dev].oselect; 713 } 714 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v); 715 716 return 0; 717 } 718 719 static int 720 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src) 721 { 722 struct sc_info *sc = mix_getdevinfo(m); 723 u_int32_t i, ml, sl; 724 725 ml = sl = 0; 726 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 727 if ((1<<i) & src) { 728 if (cmt[i].stereo) { 729 sl |= cmt[i].iselect; 730 } else { 731 ml |= cmt[i].iselect; 732 } 733 } 734 } 735 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 736 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 737 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 738 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 739 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 740 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 741 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 742 743 return src; 744 } 745 746 /* Optional SPDIF support. */ 747 748 static int 749 cmi_initsys(struct sc_info* sc) 750 { 751 #ifdef SND_DYNSYSCTL 752 /* XXX: an user should be able to set this with a control tool, 753 if not done before 7.0-RELEASE, this needs to be converted 754 to a device specific sysctl "dev.pcm.X.yyy" via 755 device_get_sysctl_*() as discussed on multimedia@ in msg-id 756 <861wujij2q.fsf@xps.des.no> */ 757 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 758 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 759 OID_AUTO, "spdif_enabled", CTLFLAG_RW, 760 &sc->spdif_enabled, 0, 761 "enable SPDIF output at 44.1 kHz and above"); 762 #endif /* SND_DYNSYSCTL */ 763 return 0; 764 } 765 766 /* ------------------------------------------------------------------------- */ 767 static kobj_method_t cmi_mixer_methods[] = { 768 KOBJMETHOD(mixer_init, cmimix_init), 769 KOBJMETHOD(mixer_set, cmimix_set), 770 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 771 { 0, 0 } 772 }; 773 MIXER_DECLARE(cmi_mixer); 774 775 /* 776 * mpu401 functions 777 */ 778 779 static unsigned char 780 cmi_mread(void *arg, struct sc_info *sc, int reg) 781 { 782 unsigned int d; 783 784 d = bus_space_read_1(0,0, 0x330 + reg); 785 /* printf("cmi_mread: reg %x %x\n",reg, d); 786 */ 787 return d; 788 } 789 790 static void 791 cmi_mwrite(void *arg, struct sc_info *sc, int reg, unsigned char b) 792 { 793 794 bus_space_write_1(0,0,0x330 + reg , b); 795 } 796 797 static int 798 cmi_muninit(void *arg, struct sc_info *sc) 799 { 800 801 snd_mtxlock(sc->lock); 802 sc->mpu_intr = 0; 803 sc->mpu = 0; 804 snd_mtxunlock(sc->lock); 805 806 return 0; 807 } 808 809 static kobj_method_t cmi_mpu_methods[] = { 810 KOBJMETHOD(mpufoi_read, cmi_mread), 811 KOBJMETHOD(mpufoi_write, cmi_mwrite), 812 KOBJMETHOD(mpufoi_uninit, cmi_muninit), 813 { 0, 0 } 814 }; 815 816 static DEFINE_CLASS(cmi_mpu, cmi_mpu_methods, 0); 817 818 static void 819 cmi_midiattach(struct sc_info *sc) { 820 /* 821 const struct { 822 int port,bits; 823 } *p, ports[] = { 824 {0x330,0}, 825 {0x320,1}, 826 {0x310,2}, 827 {0x300,3}, 828 {0,0} } ; 829 Notes, CMPCI_REG_VMPUSEL sets the io port for the mpu. Does 830 anyone know how to bus_space tag? 831 */ 832 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 833 cmi_clr4(sc, CMPCI_REG_LEGACY_CTRL, 834 CMPCI_REG_VMPUSEL_MASK << CMPCI_REG_VMPUSEL_SHIFT); 835 cmi_set4(sc, CMPCI_REG_LEGACY_CTRL, 836 0 << CMPCI_REG_VMPUSEL_SHIFT ); 837 cmi_set4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 838 sc->mpu = mpu401_init(&cmi_mpu_class, sc, cmi_intr, &sc->mpu_intr); 839 } 840 841 842 843 /* ------------------------------------------------------------------------- */ 844 /* Power and reset */ 845 846 static void 847 cmi_power(struct sc_info *sc, int state) 848 { 849 switch (state) { 850 case 0: /* full power */ 851 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 852 break; 853 default: 854 /* power off */ 855 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 856 break; 857 } 858 } 859 860 static int 861 cmi_init(struct sc_info *sc) 862 { 863 /* Effect reset */ 864 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 865 DELAY(100); 866 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET); 867 868 /* Disable interrupts and channels */ 869 cmi_clr4(sc, CMPCI_REG_FUNC_0, 870 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 871 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 872 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE); 873 874 /* Configure DMA channels, ch0 = play, ch1 = capture */ 875 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 876 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 877 878 /* Attempt to enable 4 Channel output */ 879 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D); 880 881 /* Disable SPDIF1 - not compatible with config */ 882 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE); 883 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 884 885 return 0; 886 } 887 888 static void 889 cmi_uninit(struct sc_info *sc) 890 { 891 /* Disable interrupts and channels */ 892 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, 893 CMPCI_REG_CH0_INTR_ENABLE | 894 CMPCI_REG_CH1_INTR_ENABLE | 895 CMPCI_REG_TDMA_INTR_ENABLE); 896 cmi_clr4(sc, CMPCI_REG_FUNC_0, 897 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 898 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE); 899 900 if( sc->mpu ) 901 sc->mpu_intr = 0; 902 } 903 904 /* ------------------------------------------------------------------------- */ 905 /* Bus and device registration */ 906 static int 907 cmi_probe(device_t dev) 908 { 909 switch(pci_get_devid(dev)) { 910 case CMI8338A_PCI_ID: 911 device_set_desc(dev, "CMedia CMI8338A"); 912 return BUS_PROBE_DEFAULT; 913 case CMI8338B_PCI_ID: 914 device_set_desc(dev, "CMedia CMI8338B"); 915 return BUS_PROBE_DEFAULT; 916 case CMI8738_PCI_ID: 917 device_set_desc(dev, "CMedia CMI8738"); 918 return BUS_PROBE_DEFAULT; 919 case CMI8738B_PCI_ID: 920 device_set_desc(dev, "CMedia CMI8738B"); 921 return BUS_PROBE_DEFAULT; 922 case CMI120_USB_ID: 923 device_set_desc(dev, "CMedia CMI120"); 924 return BUS_PROBE_DEFAULT; 925 default: 926 return ENXIO; 927 } 928 } 929 930 static int 931 cmi_attach(device_t dev) 932 { 933 struct sc_info *sc; 934 u_int32_t data; 935 char status[SND_STATUSLEN]; 936 937 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 938 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc"); 939 data = pci_read_config(dev, PCIR_COMMAND, 2); 940 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 941 pci_write_config(dev, PCIR_COMMAND, data, 2); 942 data = pci_read_config(dev, PCIR_COMMAND, 2); 943 944 sc->dev = dev; 945 sc->regid = PCIR_BAR(0); 946 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid, 947 RF_ACTIVE); 948 if (!sc->reg) { 949 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 950 goto bad; 951 } 952 sc->st = rman_get_bustag(sc->reg); 953 sc->sh = rman_get_bushandle(sc->reg); 954 955 if (0) 956 cmi_midiattach(sc); 957 958 sc->irqid = 0; 959 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 960 RF_ACTIVE | RF_SHAREABLE); 961 if (!sc->irq || 962 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) { 963 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 964 goto bad; 965 } 966 967 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536); 968 969 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 970 /*boundary*/0, 971 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 972 /*highaddr*/BUS_SPACE_MAXADDR, 973 /*filter*/NULL, /*filterarg*/NULL, 974 /*maxsize*/sc->bufsz, /*nsegments*/1, 975 /*maxsegz*/0x3ffff, /*flags*/0, 976 /*lockfunc*/NULL, 977 /*lockfunc*/NULL, 978 &sc->parent_dmat) != 0) { 979 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 980 goto bad; 981 } 982 983 cmi_power(sc, 0); 984 if (cmi_init(sc)) 985 goto bad; 986 987 if (mixer_init(dev, &cmi_mixer_class, sc)) 988 goto bad; 989 990 if (pcm_register(dev, sc, 1, 1)) 991 goto bad; 992 993 cmi_initsys(sc); 994 995 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc); 996 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc); 997 998 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s", 999 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi)); 1000 pcm_setstatus(dev, status); 1001 1002 DEB(printf("cmi_attach: succeeded\n")); 1003 return 0; 1004 1005 bad: 1006 if (sc->parent_dmat) 1007 bus_dma_tag_destroy(sc->parent_dmat); 1008 if (sc->ih) 1009 bus_teardown_intr(dev, sc->irq, sc->ih); 1010 if (sc->irq) 1011 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1012 if (sc->reg) 1013 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1014 if (sc->lock) 1015 snd_mtxfree(sc->lock); 1016 if (sc) 1017 free(sc, M_DEVBUF); 1018 1019 return ENXIO; 1020 } 1021 1022 static int 1023 cmi_detach(device_t dev) 1024 { 1025 struct sc_info *sc; 1026 int r; 1027 1028 r = pcm_unregister(dev); 1029 if (r) return r; 1030 1031 sc = pcm_getdevinfo(dev); 1032 cmi_uninit(sc); 1033 cmi_power(sc, 3); 1034 1035 bus_dma_tag_destroy(sc->parent_dmat); 1036 bus_teardown_intr(dev, sc->irq, sc->ih); 1037 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1038 if(sc->mpu) 1039 mpu401_uninit(sc->mpu); 1040 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg); 1041 if (sc->mpu_reg) 1042 bus_release_resource(dev, SYS_RES_IOPORT, sc->mpu_regid, sc->mpu_reg); 1043 1044 snd_mtxfree(sc->lock); 1045 free(sc, M_DEVBUF); 1046 1047 return 0; 1048 } 1049 1050 static int 1051 cmi_suspend(device_t dev) 1052 { 1053 struct sc_info *sc = pcm_getdevinfo(dev); 1054 1055 snd_mtxlock(sc->lock); 1056 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch); 1057 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch); 1058 cmi_power(sc, 3); 1059 snd_mtxunlock(sc->lock); 1060 return 0; 1061 } 1062 1063 static int 1064 cmi_resume(device_t dev) 1065 { 1066 struct sc_info *sc = pcm_getdevinfo(dev); 1067 1068 snd_mtxlock(sc->lock); 1069 cmi_power(sc, 0); 1070 if (cmi_init(sc) != 0) { 1071 device_printf(dev, "unable to reinitialize the card\n"); 1072 snd_mtxunlock(sc->lock); 1073 return ENXIO; 1074 } 1075 1076 if (mixer_reinit(dev) == -1) { 1077 device_printf(dev, "unable to reinitialize the mixer\n"); 1078 snd_mtxunlock(sc->lock); 1079 return ENXIO; 1080 } 1081 1082 if (sc->pch.dma_was_active) { 1083 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd); 1084 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt); 1085 cmi_ch0_start(sc, &sc->pch); 1086 } 1087 1088 if (sc->rch.dma_was_active) { 1089 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd); 1090 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt); 1091 cmi_ch1_start(sc, &sc->rch); 1092 } 1093 snd_mtxunlock(sc->lock); 1094 return 0; 1095 } 1096 1097 static device_method_t cmi_methods[] = { 1098 DEVMETHOD(device_probe, cmi_probe), 1099 DEVMETHOD(device_attach, cmi_attach), 1100 DEVMETHOD(device_detach, cmi_detach), 1101 DEVMETHOD(device_resume, cmi_resume), 1102 DEVMETHOD(device_suspend, cmi_suspend), 1103 { 0, 0 } 1104 }; 1105 1106 static driver_t cmi_driver = { 1107 "pcm", 1108 cmi_methods, 1109 PCM_SOFTC_SIZE 1110 }; 1111 1112 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0); 1113 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1114 MODULE_DEPEND(snd_cmi, midi, 1,1,1); 1115 MODULE_VERSION(snd_cmi, 1); 1116