1 /* 2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * This driver exists largely as a result of other people's efforts. 27 * Much of register handling is based on NetBSD CMI8x38 audio driver 28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien 29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related 30 * registers and the 8738 mixer devices. His Linux was driver a also 31 * useful reference point. 32 * 33 * TODO: MIDI / suspend / resume 34 * 35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>. 36 * 37 * $FreeBSD$ 38 */ 39 40 #include <dev/sound/pcm/sound.h> 41 #include <dev/sound/pci/cmireg.h> 42 #include <dev/sound/isa/sb.h> 43 44 #include <pci/pcireg.h> 45 #include <pci/pcivar.h> 46 47 #include "mixer_if.h" 48 49 /* Supported chip ID's */ 50 #define CMI8338A_PCI_ID 0x010013f6 51 #define CMI8338B_PCI_ID 0x010113f6 52 #define CMI8738_PCI_ID 0x011113f6 53 #define CMI8738B_PCI_ID 0x011213f6 54 55 /* Buffer size max is 64k for permitted DMA boundaries */ 56 #define CMI_BUFFER_SIZE 16384 57 58 /* Interrupts per length of buffer */ 59 #define CMI_INTR_PER_BUFFER 2 60 61 /* Clarify meaning of named defines in cmireg.h */ 62 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES 63 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES 64 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES 65 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES 66 67 /* Our indication of custom mixer control */ 68 #define CMPCI_NON_SB16_CONTROL 0xff 69 70 /* Debugging macro's */ 71 #ifndef DEB 72 #define DEB(x) /* x */ 73 #endif /* DEB */ 74 75 #ifndef DEBMIX 76 #define DEBMIX(x) /* x */ 77 #endif /* DEBMIX */ 78 79 /* ------------------------------------------------------------------------- */ 80 /* Structures */ 81 82 struct cmi_info; 83 84 struct cmi_chinfo { 85 struct cmi_info *parent; 86 pcm_channel *channel; 87 snd_dbuf *buffer; 88 int dir; 89 int bps; /* bytes per sample */ 90 u_int32_t fmt, spd, phys_buf; 91 u_int32_t dma_configured; 92 }; 93 94 struct cmi_info { 95 device_t dev; 96 u_int32_t type, rev; 97 98 bus_space_tag_t st; 99 bus_space_handle_t sh; 100 bus_dma_tag_t parent_dmat; 101 struct resource *reg, *irq; 102 int regid, irqid; 103 void *ih; 104 105 struct cmi_chinfo pch, rch; 106 }; 107 108 /* Channel caps */ 109 110 static u_int32_t cmi_fmt[] = { 111 AFMT_U8, 112 AFMT_STEREO | AFMT_U8, 113 AFMT_S16_LE, 114 AFMT_STEREO | AFMT_S16_LE, 115 0 116 }; 117 118 static pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0}; 119 120 /* ------------------------------------------------------------------------- */ 121 /* Register Utilities */ 122 123 static u_int32_t 124 cmi_rd(struct cmi_info *cmi, int regno, int size) 125 { 126 switch (size) { 127 case 1: 128 return bus_space_read_1(cmi->st, cmi->sh, regno); 129 case 2: 130 return bus_space_read_2(cmi->st, cmi->sh, regno); 131 case 4: 132 return bus_space_read_4(cmi->st, cmi->sh, regno); 133 default: 134 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size)); 135 return 0xFFFFFFFF; 136 } 137 } 138 139 static void 140 cmi_wr(struct cmi_info *cmi, int regno, u_int32_t data, int size) 141 { 142 switch (size) { 143 case 1: 144 bus_space_write_1(cmi->st, cmi->sh, regno, data); 145 break; 146 case 2: 147 bus_space_write_2(cmi->st, cmi->sh, regno, data); 148 break; 149 case 4: 150 bus_space_write_4(cmi->st, cmi->sh, regno, data); 151 break; 152 } 153 DELAY(10); 154 } 155 156 static void 157 cmi_partial_wr4(struct cmi_info *cmi, 158 int reg, int shift, u_int32_t mask, u_int32_t val) 159 { 160 u_int32_t r; 161 162 r = cmi_rd(cmi, reg, 4); 163 r &= ~(mask << shift); 164 r |= val << shift; 165 cmi_wr(cmi, reg, r, 4); 166 } 167 168 static void 169 cmi_clr4(struct cmi_info *cmi, int reg, u_int32_t mask) 170 { 171 u_int32_t r; 172 173 r = cmi_rd(cmi, reg, 4); 174 r &= ~mask; 175 cmi_wr(cmi, reg, r, 4); 176 } 177 178 static void 179 cmi_set4(struct cmi_info *cmi, int reg, u_int32_t mask) 180 { 181 u_int32_t r; 182 183 r = cmi_rd(cmi, reg, 4); 184 r |= mask; 185 cmi_wr(cmi, reg, r, 4); 186 } 187 188 /* ------------------------------------------------------------------------- */ 189 /* Rate Mapping */ 190 191 static int cmi_rates[] = {5512, 8000, 11025, 16000, 192 22050, 32000, 44100, 48000}; 193 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0])) 194 195 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1 196 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */ 197 198 static u_int32_t 199 cmpci_rate_to_regvalue(int rate) 200 { 201 int i, r; 202 203 for(i = 0; i < NUM_CMI_RATES - 1; i++) { 204 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) { 205 break; 206 } 207 } 208 209 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i])); 210 211 r = ((i >> 1) | (i << 2)) & 0x07; 212 return r; 213 } 214 215 static int 216 cmpci_regvalue_to_rate(u_int32_t r) 217 { 218 int i; 219 220 i = ((r << 1) | (r >> 2)) & 0x07; 221 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i)); 222 return cmi_rates[i]; 223 } 224 225 /* ------------------------------------------------------------------------- */ 226 /* ADC/DAC control */ 227 228 static void 229 cmi_dac_start(struct cmi_info *cmi, struct cmi_chinfo *ch) 230 { 231 if (ch->dma_configured == 0) { 232 u_int32_t s, i, sz; 233 ch->phys_buf = vtophys(sndbuf_getbuf(ch->buffer)); 234 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 235 s = (sz + 1) / ch->bps - 1; 236 i = (sz + 1) / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 237 cmi_wr(cmi, CMPCI_REG_DMA0_BASE, ch->phys_buf, 4); 238 cmi_wr(cmi, CMPCI_REG_DMA0_MAX_SAMPLES, s, 2); 239 cmi_wr(cmi, CMPCI_REG_DMA0_INTR_SAMPLES, i, 2); 240 ch->dma_configured = 1; 241 DEB(printf("cmi_dac_start: dma prog\n")); 242 } 243 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 244 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_PAUSE); 245 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 246 cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 247 } 248 249 static void 250 cmi_dac_stop(struct cmi_info *cmi) 251 { 252 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 253 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 254 } 255 256 static void 257 cmi_dac_reset(struct cmi_info *cmi, struct cmi_chinfo *ch) 258 { 259 cmi_dac_stop(cmi); 260 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 261 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 262 ch->dma_configured = 0; 263 DEB(printf("cmi_dac_reset\n")); 264 } 265 266 static void 267 cmi_adc_start(struct cmi_info *cmi, struct cmi_chinfo *ch) 268 { 269 if (ch->dma_configured == 0) { 270 u_int32_t s, i, sz; 271 ch->phys_buf = vtophys(sndbuf_getbuf(ch->buffer)); 272 sz = (u_int32_t)sndbuf_getsize(ch->buffer); 273 s = (sz + 1) / ch->bps - 1; 274 i = (sz + 1) / (ch->bps * CMI_INTR_PER_BUFFER) - 1; 275 276 cmi_wr(cmi, CMPCI_REG_DMA1_BASE, ch->phys_buf, 4); 277 cmi_wr(cmi, CMPCI_REG_DMA1_MAX_SAMPLES, s, 2); 278 cmi_wr(cmi, CMPCI_REG_DMA1_INTR_SAMPLES, i, 2); 279 ch->dma_configured = 1; 280 DEB(printf("cmi_adc_start: dma prog\n")); 281 } 282 283 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 284 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_PAUSE); 285 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 286 cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 287 } 288 289 static void 290 cmi_adc_stop(struct cmi_info *cmi) 291 { 292 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 293 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 294 } 295 296 static void 297 cmi_adc_reset(struct cmi_info *cmi, struct cmi_chinfo *ch) 298 { 299 cmi_adc_stop(cmi); 300 cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 301 cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 302 ch->dma_configured = 0; 303 DEB(printf("cmi_adc_reset\n")); 304 } 305 306 static void 307 cmi_spdif_speed(struct cmi_info *cmi, int speed) { 308 u_int32_t fcr1, lcr, mcr; 309 310 if (speed >= 44100) { 311 fcr1 = CMPCI_REG_SPDIF0_ENABLE; 312 lcr = CMPCI_REG_XSPDIF_ENABLE; 313 mcr = (speed == 48000) ? 314 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0; 315 } else { 316 fcr1 = mcr = lcr = 0; 317 } 318 319 cmi_partial_wr4(cmi, CMPCI_REG_MISC, 0, 320 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); 321 cmi_partial_wr4(cmi, CMPCI_REG_LEGACY_CTRL, 0, 322 CMPCI_REG_XSPDIF_ENABLE, lcr); 323 cmi_partial_wr4(cmi, CMPCI_REG_FUNC_1, 0, 324 CMPCI_REG_SPDIF0_ENABLE, fcr1); 325 } 326 327 /* ------------------------------------------------------------------------- */ 328 /* Channel Interface implementation */ 329 330 static void * 331 cmichan_init(kobj_t obj, void *devinfo, snd_dbuf *b, pcm_channel *c, int dir) 332 { 333 struct cmi_info *cmi = devinfo; 334 struct cmi_chinfo *ch = (dir == PCMDIR_PLAY) ? &cmi->pch : &cmi->rch; 335 336 ch->parent = cmi; 337 ch->channel = c; 338 ch->bps = 1; 339 ch->fmt = AFMT_U8; 340 ch->spd = DSP_DEFAULT_SPEED; 341 ch->dma_configured = 0; 342 ch->buffer = b; 343 if (sndbuf_alloc(ch->buffer, cmi->parent_dmat, CMI_BUFFER_SIZE) != 0) { 344 DEB(printf("cmichan_init failed\n")); 345 return NULL; 346 } 347 348 ch->dir = dir; 349 if (dir == PCMDIR_PLAY) { 350 cmi_clr4(ch->parent, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); 351 } else { 352 cmi_set4(ch->parent, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); 353 } 354 355 return ch; 356 } 357 358 static int 359 cmichan_setformat(kobj_t obj, void *data, u_int32_t format) 360 { 361 struct cmi_chinfo *ch = data; 362 u_int32_t f; 363 364 if (format & AFMT_S16_LE) { 365 f = CMPCI_REG_FORMAT_16BIT; 366 ch->bps = 2; 367 } else { 368 f = CMPCI_REG_FORMAT_8BIT; 369 ch->bps = 1; 370 } 371 372 if (format & AFMT_STEREO) { 373 f |= CMPCI_REG_FORMAT_STEREO; 374 ch->bps *= 2; 375 } else { 376 f |= CMPCI_REG_FORMAT_MONO; 377 } 378 379 if (ch->dir == PCMDIR_PLAY) { 380 cmi_partial_wr4(ch->parent, 381 CMPCI_REG_CHANNEL_FORMAT, 382 CMPCI_REG_CH0_FORMAT_SHIFT, 383 CMPCI_REG_CH0_FORMAT_MASK, 384 f); 385 } else { 386 cmi_partial_wr4(ch->parent, 387 CMPCI_REG_CHANNEL_FORMAT, 388 CMPCI_REG_CH1_FORMAT_SHIFT, 389 CMPCI_REG_CH1_FORMAT_MASK, 390 f); 391 } 392 ch->fmt = format; 393 ch->dma_configured = 0; 394 395 return 0; 396 } 397 398 static int 399 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed) 400 { 401 struct cmi_chinfo *ch = data; 402 u_int32_t r, rsp; 403 404 r = cmpci_rate_to_regvalue(speed); 405 if (ch->dir == PCMDIR_PLAY) { 406 if (speed < 44100) /* disable if req before rate change */ 407 cmi_spdif_speed(ch->parent, speed); 408 cmi_partial_wr4(ch->parent, 409 CMPCI_REG_FUNC_1, 410 CMPCI_REG_DAC_FS_SHIFT, 411 CMPCI_REG_DAC_FS_MASK, 412 r); 413 if (speed >= 44100) /* enable if req after rate change */ 414 cmi_spdif_speed(ch->parent, speed); 415 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 416 rsp >>= CMPCI_REG_DAC_FS_SHIFT; 417 rsp &= CMPCI_REG_DAC_FS_MASK; 418 } else { 419 cmi_partial_wr4(ch->parent, 420 CMPCI_REG_FUNC_1, 421 CMPCI_REG_ADC_FS_SHIFT, 422 CMPCI_REG_ADC_FS_MASK, 423 r); 424 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4); 425 rsp >>= CMPCI_REG_ADC_FS_SHIFT; 426 rsp &= CMPCI_REG_ADC_FS_MASK; 427 } 428 ch->spd = cmpci_regvalue_to_rate(r); 429 430 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n", 431 (ch->dir == PCMDIR_PLAY) ? "play" : "rec", 432 speed, ch->spd, cmpci_regvalue_to_rate(rsp))); 433 434 return ch->spd; 435 } 436 437 static int 438 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 439 { 440 struct cmi_chinfo *ch = data; 441 442 /* user has requested interrupts every blocksize bytes */ 443 if (blocksize > CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER) { 444 blocksize = CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER; 445 } 446 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize); 447 448 ch->dma_configured = 0; 449 return sndbuf_getsize(ch->buffer); 450 } 451 452 static int 453 cmichan_trigger(kobj_t obj, void *data, int go) 454 { 455 struct cmi_chinfo *ch = data; 456 struct cmi_info *cmi = ch->parent; 457 458 if (ch->dir == PCMDIR_PLAY) { 459 switch(go) { 460 case PCMTRIG_START: 461 cmi_dac_start(cmi, ch); 462 break; 463 case PCMTRIG_ABORT: 464 cmi_dac_reset(cmi, ch); 465 break; 466 } 467 } else { 468 switch(go) { 469 case PCMTRIG_START: 470 cmi_adc_start(cmi, ch); 471 break; 472 case PCMTRIG_ABORT: 473 cmi_adc_reset(cmi, ch); 474 break; 475 } 476 } 477 return 0; 478 } 479 480 static int 481 cmichan_getptr(kobj_t obj, void *data) 482 { 483 struct cmi_chinfo *ch = data; 484 struct cmi_info *cmi = ch->parent; 485 u_int32_t physptr, bufptr, sz; 486 487 if (ch->dir == PCMDIR_PLAY) { 488 physptr = cmi_rd(cmi, CMPCI_REG_DMA0_BASE, 4); 489 } else { 490 physptr = cmi_rd(cmi, CMPCI_REG_DMA1_BASE, 4); 491 } 492 493 sz = sndbuf_getsize(ch->buffer); 494 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz; 495 496 return bufptr; 497 } 498 499 static void 500 cmi_intr(void *data) 501 { 502 struct cmi_info *cmi = data; 503 u_int32_t intrstat; 504 505 intrstat = cmi_rd(cmi, CMPCI_REG_INTR_STATUS, 4); 506 if ((intrstat & CMPCI_REG_ANY_INTR) == 0) { 507 return; 508 } 509 510 /* Disable interrupts */ 511 if (intrstat & CMPCI_REG_CH0_INTR) { 512 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 513 } 514 515 if (intrstat & CMPCI_REG_CH1_INTR) { 516 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 517 } 518 519 DEB(printf("cmi_intr - play %d rec %d\n", 520 intrstat & CMPCI_REG_CH0_INTR, 521 (intrstat & CMPCI_REG_CH1_INTR)>>1)); 522 523 /* Signal interrupts to channel */ 524 if (intrstat & CMPCI_REG_CH0_INTR) { 525 chn_intr(cmi->pch.channel); 526 } 527 528 if (intrstat & CMPCI_REG_CH1_INTR) { 529 chn_intr(cmi->rch.channel); 530 } 531 532 /* Enable interrupts */ 533 if (intrstat & CMPCI_REG_CH0_INTR) { 534 cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 535 } 536 537 if (intrstat & CMPCI_REG_CH1_INTR) { 538 cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 539 } 540 541 return; 542 } 543 544 static pcmchan_caps * 545 cmichan_getcaps(kobj_t obj, void *data) 546 { 547 return &cmi_caps; 548 } 549 550 static kobj_method_t cmichan_methods[] = { 551 KOBJMETHOD(channel_init, cmichan_init), 552 KOBJMETHOD(channel_setformat, cmichan_setformat), 553 KOBJMETHOD(channel_setspeed, cmichan_setspeed), 554 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize), 555 KOBJMETHOD(channel_trigger, cmichan_trigger), 556 KOBJMETHOD(channel_getptr, cmichan_getptr), 557 KOBJMETHOD(channel_getcaps, cmichan_getcaps), 558 { 0, 0 } 559 }; 560 CHANNEL_DECLARE(cmichan); 561 562 /* ------------------------------------------------------------------------- */ 563 /* Mixer - sb16 with kinks */ 564 565 static void 566 cmimix_wr(struct cmi_info *cmi, u_int8_t port, u_int8_t val) 567 { 568 cmi_wr(cmi, CMPCI_REG_SBADDR, port, 1); 569 cmi_wr(cmi, CMPCI_REG_SBDATA, val, 1); 570 } 571 572 static u_int8_t 573 cmimix_rd(struct cmi_info *cmi, u_int8_t port) 574 { 575 cmi_wr(cmi, CMPCI_REG_SBADDR, port, 1); 576 return (u_int8_t)cmi_rd(cmi, CMPCI_REG_SBDATA, 1); 577 } 578 579 struct sb16props { 580 u_int8_t rreg; /* right reg chan register */ 581 u_int8_t stereo:1; /* (no explanation needed, honest) */ 582 u_int8_t rec:1; /* recording source */ 583 u_int8_t bits:3; /* num bits to represent maximum gain rep */ 584 u_int8_t oselect; /* output select mask */ 585 u_int8_t iselect; /* right input select mask */ 586 } static const cmt[SOUND_MIXER_NRDEVICES] = { 587 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5, 588 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R}, 589 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5, 590 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R}, 591 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5, 592 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R}, 593 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5, 594 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC}, 595 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0}, 596 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0}, 597 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0}, 598 /* These controls are not implemented in CMI8738, but maybe at a 599 future date. They are not documented in C-Media documentation, 600 though appear in other drivers for future h/w (ALSA, Linux, NetBSD). 601 */ 602 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0}, 603 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0}, 604 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0}, 605 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0}, 606 /* The mic pre-amp is implemented with non-SB16 compatible registers. */ 607 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0}, 608 }; 609 610 #define MIXER_GAIN_REG_RTOL(r) (r - 1) 611 612 static int 613 cmimix_init(snd_mixer *m) 614 { 615 struct cmi_info *cmi = mix_getdevinfo(m); 616 u_int32_t i,v; 617 618 v = 0; 619 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 620 if (cmt[i].bits) v |= 1 << i; 621 } 622 mix_setdevs(m, v); 623 v = 0; 624 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 625 if (cmt[i].rec) v |= 1 << i; 626 } 627 mix_setrecdevs(m, v); 628 629 cmimix_wr(cmi, CMPCI_SB16_MIXER_RESET, 0); 630 cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_L, 0); 631 cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_R, 0); 632 cmimix_wr(cmi, CMPCI_SB16_MIXER_OUTMIX, 633 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 634 return 0; 635 } 636 637 static int 638 cmimix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right) 639 { 640 struct cmi_info *cmi = mix_getdevinfo(m); 641 u_int32_t r, l, max; 642 u_int8_t v; 643 644 max = (1 << cmt[dev].bits) - 1; 645 646 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) { 647 /* For time being this can only be one thing (mic in mic/aux reg) */ 648 u_int8_t v; 649 v = cmi_rd(cmi, CMPCI_REG_AUX_MIC, 1) & 0xf0; 650 l = left * max / 100; 651 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value*/ 652 v |= ((l << 1) | (~l >> 3)) & 0x0f; 653 cmi_wr(cmi, CMPCI_REG_AUX_MIC, v, 1); 654 return 0; 655 } 656 657 l = (left * max / 100) << (8 - cmt[dev].bits); 658 if (cmt[dev].stereo) { 659 r = (right * max / 100) << (8 - cmt[dev].bits); 660 cmimix_wr(cmi, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l); 661 cmimix_wr(cmi, cmt[dev].rreg, r); 662 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\ 663 "value 0x%02x:0x%02x\n", 664 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r)); 665 } else { 666 r = l; 667 cmimix_wr(cmi, cmt[dev].rreg, l); 668 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \ 669 "value 0x%02x:0x%02x\n", 670 dev, cmt[dev].rreg, l, l)); 671 } 672 673 /* Zero gain does not mute channel from output, but this does... */ 674 v = cmimix_rd(cmi, CMPCI_SB16_MIXER_OUTMIX); 675 if (l == 0 && r == 0) { 676 v &= ~cmt[dev].oselect; 677 } else { 678 v |= cmt[dev].oselect; 679 } 680 cmimix_wr(cmi, CMPCI_SB16_MIXER_OUTMIX, v); 681 682 return 0; 683 } 684 685 static int 686 cmimix_setrecsrc(snd_mixer *m, u_int32_t src) 687 { 688 struct cmi_info *cmi = mix_getdevinfo(m); 689 u_int32_t i, ml, sl; 690 691 ml = sl = 0; 692 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 693 if ((1<<i) & src) { 694 if (cmt[i].stereo) { 695 sl |= cmt[i].iselect; 696 } else { 697 ml |= cmt[i].iselect; 698 } 699 } 700 } 701 cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml); 702 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 703 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml)); 704 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml); 705 cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml); 706 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n", 707 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml)); 708 709 return src; 710 } 711 712 static kobj_method_t cmi_mixer_methods[] = { 713 KOBJMETHOD(mixer_init, cmimix_init), 714 KOBJMETHOD(mixer_set, cmimix_set), 715 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc), 716 { 0, 0 } 717 }; 718 MIXER_DECLARE(cmi_mixer); 719 720 /* ------------------------------------------------------------------------- */ 721 /* Power and reset */ 722 723 static void 724 cmi_power(struct cmi_info *cmi, int state) 725 { 726 switch (state) { 727 case 0: /* full power */ 728 cmi_clr4(cmi, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 729 break; 730 default: 731 /* power off */ 732 cmi_set4(cmi, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN); 733 break; 734 } 735 } 736 737 /* ------------------------------------------------------------------------- */ 738 /* Bus and device registration */ 739 static int 740 cmi_probe(device_t dev) 741 { 742 switch(pci_get_devid(dev)) { 743 case CMI8338A_PCI_ID: 744 device_set_desc(dev, "CMedia CMI8338A"); 745 return 0; 746 case CMI8338B_PCI_ID: 747 device_set_desc(dev, "CMedia CMI8338B"); 748 return 0; 749 case CMI8738_PCI_ID: 750 device_set_desc(dev, "CMedia CMI8738"); 751 return 0; 752 case CMI8738B_PCI_ID: 753 device_set_desc(dev, "CMedia CMI8738B"); 754 return 0; 755 default: 756 return ENXIO; 757 } 758 } 759 760 static int 761 cmi_attach(device_t dev) 762 { 763 snddev_info *d; 764 struct cmi_info *cmi; 765 u_int32_t data; 766 char status[SND_STATUSLEN]; 767 768 d = device_get_softc(dev); 769 770 if ((cmi = malloc(sizeof(struct cmi_info), M_DEVBUF, M_NOWAIT)) == NULL) { 771 device_printf(dev, "cannot allocate softc\n"); 772 return ENXIO; 773 } 774 775 bzero(cmi, sizeof(*cmi)); 776 777 data = pci_read_config(dev, PCIR_COMMAND, 2); 778 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN); 779 pci_write_config(dev, PCIR_COMMAND, data, 2); 780 data = pci_read_config(dev, PCIR_COMMAND, 2); 781 782 cmi->regid = PCIR_MAPS; 783 cmi->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &cmi->regid, 784 0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE); 785 if (!cmi->reg) { 786 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n"); 787 goto bad; 788 } 789 cmi->st = rman_get_bustag(cmi->reg); 790 cmi->sh = rman_get_bushandle(cmi->reg); 791 792 cmi->irqid = 0; 793 cmi->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &cmi->irqid, 794 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 795 if (!cmi->irq || 796 bus_setup_intr(dev, cmi->irq, INTR_TYPE_TTY, cmi_intr, cmi, &cmi->ih)){ 797 device_printf(dev, "cmi_attach: Unable to map interrupt\n"); 798 goto bad; 799 } 800 801 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 802 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 803 /*highaddr*/BUS_SPACE_MAXADDR, 804 /*filter*/NULL, /*filterarg*/NULL, 805 /*maxsize*/CMI_BUFFER_SIZE, /*nsegments*/1, 806 /*maxsegz*/0x3ffff, /*flags*/0, 807 &cmi->parent_dmat) != 0) { 808 device_printf(dev, "cmi_attach: Unable to create dma tag\n"); 809 goto bad; 810 } 811 812 cmi_power(cmi, 0); 813 /* Disable interrupts and channels */ 814 cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, 815 CMPCI_REG_CH0_INTR_ENABLE | 816 CMPCI_REG_CH1_INTR_ENABLE | 817 CMPCI_REG_TDMA_INTR_ENABLE); 818 cmi_clr4(cmi, CMPCI_REG_FUNC_0, 819 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE); 820 821 if (mixer_init(dev, &cmi_mixer_class, cmi)) 822 goto bad; 823 824 if (pcm_register(dev, cmi, 1, 1)) 825 goto bad; 826 827 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, cmi); 828 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, cmi); 829 830 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld", 831 rman_get_start(cmi->reg), rman_get_start(cmi->irq)); 832 pcm_setstatus(dev, status); 833 834 DEB(printf("cmi_attach: succeeded\n")); 835 return 0; 836 837 bad: 838 if (cmi->parent_dmat) bus_dma_tag_destroy(cmi->parent_dmat); 839 if (cmi->ih) bus_teardown_intr(dev, cmi->irq, cmi->ih); 840 if (cmi->irq) bus_release_resource(dev, SYS_RES_IRQ, cmi->irqid, cmi->irq); 841 if (cmi->reg) bus_release_resource(dev, SYS_RES_IOPORT, 842 cmi->regid, cmi->reg); 843 if (cmi) free(cmi, M_DEVBUF); 844 845 return ENXIO; 846 } 847 848 static int 849 cmi_detach(device_t dev) 850 { 851 struct cmi_info *cmi; 852 int r; 853 854 r = pcm_unregister(dev); 855 if (r) return r; 856 857 cmi = pcm_getdevinfo(dev); 858 cmi_power(cmi, 3); 859 bus_dma_tag_destroy(cmi->parent_dmat); 860 bus_teardown_intr(dev, cmi->irq, cmi->ih); 861 bus_release_resource(dev, SYS_RES_IRQ, cmi->irqid, cmi->irq); 862 bus_release_resource(dev, SYS_RES_IOPORT, cmi->regid, cmi->reg); 863 free(cmi, M_DEVBUF); 864 865 return 0; 866 } 867 868 static device_method_t cmi_methods[] = { 869 DEVMETHOD(device_probe, cmi_probe), 870 DEVMETHOD(device_attach, cmi_attach), 871 DEVMETHOD(device_detach, cmi_detach), 872 DEVMETHOD(device_resume, bus_generic_resume), 873 DEVMETHOD(device_suspend, bus_generic_suspend), 874 { 0, 0 } 875 }; 876 877 static driver_t cmi_driver = { 878 "pcm", 879 cmi_methods, 880 sizeof(snddev_info) 881 }; 882 883 static devclass_t pcm_devclass; 884 DRIVER_MODULE(snd_cmipci, pci, cmi_driver, pcm_devclass, 0, 0); 885 MODULE_DEPEND(snd_cmipci, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 886 MODULE_VERSION(snd_cmipci, 1); 887