1 /*- 2 * Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * FreeBSD pcm driver for ATI IXP 150/200/250/300 AC97 controllers 29 * 30 * Features 31 * * 16bit playback / recording 32 * * 32bit native playback - yay! 33 * * 32bit native recording (seems broken on few hardwares) 34 * 35 * Issues / TODO: 36 * * SPDIF 37 * * Support for more than 2 channels. 38 * * VRA ? VRM ? DRA ? 39 * * 32bit native recording seems broken on few hardwares, most 40 * probably because of incomplete VRA/DRA cleanup. 41 * 42 * 43 * Thanks goes to: 44 * 45 * Shaharil @ SCAN Associates whom relentlessly providing me the 46 * mind blowing Acer Ferrari 4002 WLMi with this ATI IXP hardware. 47 * 48 * Reinoud Zandijk <reinoud@NetBSD.org> (auixp), which this driver is 49 * largely based upon although large part of it has been reworked. His 50 * driver is the primary reference and pretty much well documented. 51 * 52 * Takashi Iwai (ALSA snd-atiixp), for register definitions and some 53 * random ninja hackery. 54 */ 55 56 #include <dev/sound/pcm/sound.h> 57 #include <dev/sound/pcm/ac97.h> 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 #include <sys/sysctl.h> 62 #include <sys/endian.h> 63 64 #include <dev/sound/pci/atiixp.h> 65 66 SND_DECLARE_FILE("$FreeBSD$"); 67 68 struct atiixp_dma_op { 69 volatile uint32_t addr; 70 volatile uint16_t status; 71 volatile uint16_t size; 72 volatile uint32_t next; 73 }; 74 75 struct atiixp_info; 76 77 struct atiixp_chinfo { 78 struct snd_dbuf *buffer; 79 struct pcm_channel *channel; 80 struct atiixp_info *parent; 81 struct atiixp_dma_op *sgd_table; 82 bus_addr_t sgd_addr; 83 uint32_t enable_bit, flush_bit, linkptr_bit, dma_dt_cur_bit; 84 uint32_t dma_segs; 85 uint32_t fmt; 86 int caps_32bit, dir, active; 87 }; 88 89 struct atiixp_info { 90 device_t dev; 91 92 bus_space_tag_t st; 93 bus_space_handle_t sh; 94 bus_dma_tag_t parent_dmat; 95 bus_dma_tag_t sgd_dmat; 96 bus_dmamap_t sgd_dmamap; 97 bus_addr_t sgd_addr; 98 99 struct resource *reg, *irq; 100 int regtype, regid, irqid; 101 void *ih; 102 struct ac97_info *codec; 103 104 struct atiixp_chinfo pch; 105 struct atiixp_chinfo rch; 106 struct atiixp_dma_op *sgd_table; 107 struct intr_config_hook delayed_attach; 108 109 uint32_t bufsz; 110 uint32_t codec_not_ready_bits, codec_idx, codec_found; 111 uint32_t dma_segs; 112 int registered_channels; 113 114 struct mtx *lock; 115 }; 116 117 #define atiixp_rd(_sc, _reg) \ 118 bus_space_read_4((_sc)->st, (_sc)->sh, _reg) 119 #define atiixp_wr(_sc, _reg, _val) \ 120 bus_space_write_4((_sc)->st, (_sc)->sh, _reg, _val) 121 122 #define atiixp_lock(_sc) snd_mtxlock((_sc)->lock) 123 #define atiixp_unlock(_sc) snd_mtxunlock((_sc)->lock) 124 #define atiixp_assert(_sc) snd_mtxassert((_sc)->lock) 125 126 static uint32_t atiixp_fmt_32bit[] = { 127 AFMT_STEREO | AFMT_S16_LE, 128 AFMT_STEREO | AFMT_S32_LE, 129 0 130 }; 131 132 static uint32_t atiixp_fmt[] = { 133 AFMT_STEREO | AFMT_S16_LE, 134 0 135 }; 136 137 static struct pcmchan_caps atiixp_caps_32bit = { 138 ATI_IXP_BASE_RATE, 139 ATI_IXP_BASE_RATE, 140 atiixp_fmt_32bit, 0 141 }; 142 143 static struct pcmchan_caps atiixp_caps = { 144 ATI_IXP_BASE_RATE, 145 ATI_IXP_BASE_RATE, 146 atiixp_fmt, 0 147 }; 148 149 static const struct { 150 uint16_t vendor; 151 uint16_t devid; 152 char *desc; 153 } atiixp_hw[] = { 154 { ATI_VENDOR_ID, ATI_IXP_200_ID, "ATI IXP 200" }, 155 { ATI_VENDOR_ID, ATI_IXP_300_ID, "ATI IXP 300" }, 156 { ATI_VENDOR_ID, ATI_IXP_400_ID, "ATI IXP 400" }, 157 }; 158 159 static void atiixp_enable_interrupts(struct atiixp_info *); 160 static void atiixp_disable_interrupts(struct atiixp_info *); 161 static void atiixp_reset_aclink(struct atiixp_info *); 162 static void atiixp_flush_dma(struct atiixp_info *, struct atiixp_chinfo *); 163 static void atiixp_enable_dma(struct atiixp_info *, struct atiixp_chinfo *); 164 static void atiixp_disable_dma(struct atiixp_info *, struct atiixp_chinfo *); 165 166 static int atiixp_waitready_codec(struct atiixp_info *); 167 static int atiixp_rdcd(kobj_t, void *, int); 168 static int atiixp_wrcd(kobj_t, void *, int, uint32_t); 169 170 static void *atiixp_chan_init(kobj_t, void *, struct snd_dbuf *, 171 struct pcm_channel *, int); 172 static int atiixp_chan_setformat(kobj_t, void *, uint32_t); 173 static int atiixp_chan_setspeed(kobj_t, void *, uint32_t); 174 static int atiixp_chan_setblocksize(kobj_t, void *, uint32_t); 175 static void atiixp_buildsgdt(struct atiixp_chinfo *); 176 static int atiixp_chan_trigger(kobj_t, void *, int); 177 static int atiixp_chan_getptr(kobj_t, void *); 178 static struct pcmchan_caps *atiixp_chan_getcaps(kobj_t, void *); 179 180 static void atiixp_intr(void *); 181 static void atiixp_dma_cb(void *, bus_dma_segment_t *, int, int); 182 static void atiixp_chip_pre_init(struct atiixp_info *); 183 static void atiixp_chip_post_init(void *); 184 static void atiixp_release_resource(struct atiixp_info *); 185 static int atiixp_pci_probe(device_t); 186 static int atiixp_pci_attach(device_t); 187 static int atiixp_pci_detach(device_t); 188 static int atiixp_pci_suspend(device_t); 189 static int atiixp_pci_resume(device_t); 190 191 /* 192 * ATI IXP helper functions 193 */ 194 static void 195 atiixp_enable_interrupts(struct atiixp_info *sc) 196 { 197 uint32_t value; 198 199 /* clear all pending */ 200 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 201 202 /* enable all relevant interrupt sources we can handle */ 203 value = atiixp_rd(sc, ATI_REG_IER); 204 205 value |= ATI_REG_IER_IO_STATUS_EN; 206 207 /* 208 * Disable / ignore internal xrun/spdf interrupt flags 209 * since it doesn't interest us (for now). 210 */ 211 #if 0 212 value |= ATI_REG_IER_IN_XRUN_EN; 213 value |= ATI_REG_IER_OUT_XRUN_EN; 214 215 value |= ATI_REG_IER_SPDF_XRUN_EN; 216 value |= ATI_REG_IER_SPDF_STATUS_EN; 217 #endif 218 219 atiixp_wr(sc, ATI_REG_IER, value); 220 } 221 222 static void 223 atiixp_disable_interrupts(struct atiixp_info *sc) 224 { 225 /* disable all interrupt sources */ 226 atiixp_wr(sc, ATI_REG_IER, 0); 227 228 /* clear all pending */ 229 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 230 } 231 232 static void 233 atiixp_reset_aclink(struct atiixp_info *sc) 234 { 235 uint32_t value, timeout; 236 237 /* if power is down, power it up */ 238 value = atiixp_rd(sc, ATI_REG_CMD); 239 if (value & ATI_REG_CMD_POWERDOWN) { 240 /* explicitly enable power */ 241 value &= ~ATI_REG_CMD_POWERDOWN; 242 atiixp_wr(sc, ATI_REG_CMD, value); 243 244 /* have to wait at least 10 usec for it to initialise */ 245 DELAY(20); 246 }; 247 248 /* perform a soft reset */ 249 value = atiixp_rd(sc, ATI_REG_CMD); 250 value |= ATI_REG_CMD_AC_SOFT_RESET; 251 atiixp_wr(sc, ATI_REG_CMD, value); 252 253 /* need to read the CMD reg and wait aprox. 10 usec to init */ 254 value = atiixp_rd(sc, ATI_REG_CMD); 255 DELAY(20); 256 257 /* clear soft reset flag again */ 258 value = atiixp_rd(sc, ATI_REG_CMD); 259 value &= ~ATI_REG_CMD_AC_SOFT_RESET; 260 atiixp_wr(sc, ATI_REG_CMD, value); 261 262 /* check if the ac-link is working; reset device otherwise */ 263 timeout = 10; 264 value = atiixp_rd(sc, ATI_REG_CMD); 265 while (!(value & ATI_REG_CMD_ACLINK_ACTIVE) 266 && --timeout) { 267 #if 0 268 device_printf(sc->dev, "not up; resetting aclink hardware\n"); 269 #endif 270 271 /* dip aclink reset but keep the acsync */ 272 value &= ~ATI_REG_CMD_AC_RESET; 273 value |= ATI_REG_CMD_AC_SYNC; 274 atiixp_wr(sc, ATI_REG_CMD, value); 275 276 /* need to read CMD again and wait again (clocking in issue?) */ 277 value = atiixp_rd(sc, ATI_REG_CMD); 278 DELAY(20); 279 280 /* assert aclink reset again */ 281 value = atiixp_rd(sc, ATI_REG_CMD); 282 value |= ATI_REG_CMD_AC_RESET; 283 atiixp_wr(sc, ATI_REG_CMD, value); 284 285 /* check if its active now */ 286 value = atiixp_rd(sc, ATI_REG_CMD); 287 }; 288 289 if (timeout == 0) 290 device_printf(sc->dev, "giving up aclink reset\n"); 291 #if 0 292 if (timeout != 10) 293 device_printf(sc->dev, "aclink hardware reset successful\n"); 294 #endif 295 296 /* assert reset and sync for safety */ 297 value = atiixp_rd(sc, ATI_REG_CMD); 298 value |= ATI_REG_CMD_AC_SYNC | ATI_REG_CMD_AC_RESET; 299 atiixp_wr(sc, ATI_REG_CMD, value); 300 } 301 302 static void 303 atiixp_flush_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 304 { 305 atiixp_wr(sc, ATI_REG_FIFO_FLUSH, ch->flush_bit); 306 } 307 308 static void 309 atiixp_enable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 310 { 311 uint32_t value; 312 313 value = atiixp_rd(sc, ATI_REG_CMD); 314 if (!(value & ch->enable_bit)) { 315 value |= ch->enable_bit; 316 atiixp_wr(sc, ATI_REG_CMD, value); 317 } 318 } 319 320 static void 321 atiixp_disable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 322 { 323 uint32_t value; 324 325 value = atiixp_rd(sc, ATI_REG_CMD); 326 if (value & ch->enable_bit) { 327 value &= ~ch->enable_bit; 328 atiixp_wr(sc, ATI_REG_CMD, value); 329 } 330 } 331 332 /* 333 * AC97 interface 334 */ 335 static int 336 atiixp_waitready_codec(struct atiixp_info *sc) 337 { 338 int timeout = 500; 339 340 do { 341 if ((atiixp_rd(sc, ATI_REG_PHYS_OUT_ADDR) & 342 ATI_REG_PHYS_OUT_ADDR_EN) == 0) 343 return 0; 344 DELAY(1); 345 } while (timeout--); 346 347 return -1; 348 } 349 350 static int 351 atiixp_rdcd(kobj_t obj, void *devinfo, int reg) 352 { 353 struct atiixp_info *sc = devinfo; 354 uint32_t data; 355 int timeout; 356 357 if (atiixp_waitready_codec(sc)) 358 return -1; 359 360 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 361 ATI_REG_PHYS_OUT_ADDR_EN | 362 ATI_REG_PHYS_OUT_RW | sc->codec_idx; 363 364 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 365 366 if (atiixp_waitready_codec(sc)) 367 return -1; 368 369 timeout = 500; 370 do { 371 data = atiixp_rd(sc, ATI_REG_PHYS_IN_ADDR); 372 if (data & ATI_REG_PHYS_IN_READ_FLAG) 373 return data >> ATI_REG_PHYS_IN_DATA_SHIFT; 374 DELAY(1); 375 } while (timeout--); 376 377 if (reg < 0x7c) 378 device_printf(sc->dev, "codec read timeout! (reg 0x%x)\n", reg); 379 380 return -1; 381 } 382 383 static int 384 atiixp_wrcd(kobj_t obj, void *devinfo, int reg, uint32_t data) 385 { 386 struct atiixp_info *sc = devinfo; 387 388 if (atiixp_waitready_codec(sc)) 389 return -1; 390 391 data = (data << ATI_REG_PHYS_OUT_DATA_SHIFT) | 392 (((uint32_t)reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 393 ATI_REG_PHYS_OUT_ADDR_EN | sc->codec_idx; 394 395 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 396 397 return 0; 398 } 399 400 static kobj_method_t atiixp_ac97_methods[] = { 401 KOBJMETHOD(ac97_read, atiixp_rdcd), 402 KOBJMETHOD(ac97_write, atiixp_wrcd), 403 { 0, 0 } 404 }; 405 AC97_DECLARE(atiixp_ac97); 406 407 /* 408 * Playback / Record channel interface 409 */ 410 static void * 411 atiixp_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 412 struct pcm_channel *c, int dir) 413 { 414 struct atiixp_info *sc = devinfo; 415 struct atiixp_chinfo *ch; 416 int num; 417 418 atiixp_lock(sc); 419 420 if (dir == PCMDIR_PLAY) { 421 ch = &sc->pch; 422 ch->linkptr_bit = ATI_REG_OUT_DMA_LINKPTR; 423 ch->enable_bit = ATI_REG_CMD_OUT_DMA_EN | ATI_REG_CMD_SEND_EN; 424 ch->flush_bit = ATI_REG_FIFO_OUT_FLUSH; 425 ch->dma_dt_cur_bit = ATI_REG_OUT_DMA_DT_CUR; 426 /* Native 32bit playback working properly */ 427 ch->caps_32bit = 1; 428 } else { 429 ch = &sc->rch; 430 ch->linkptr_bit = ATI_REG_IN_DMA_LINKPTR; 431 ch->enable_bit = ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_RECEIVE_EN; 432 ch->flush_bit = ATI_REG_FIFO_IN_FLUSH; 433 ch->dma_dt_cur_bit = ATI_REG_IN_DMA_DT_CUR; 434 /* XXX Native 32bit recording appear to be broken */ 435 ch->caps_32bit = 1; 436 } 437 438 ch->buffer = b; 439 ch->parent = sc; 440 ch->channel = c; 441 ch->dir = dir; 442 ch->dma_segs = sc->dma_segs; 443 444 atiixp_unlock(sc); 445 446 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1) 447 return NULL; 448 449 atiixp_lock(sc); 450 num = sc->registered_channels++; 451 ch->sgd_table = &sc->sgd_table[num * ch->dma_segs]; 452 ch->sgd_addr = sc->sgd_addr + 453 (num * ch->dma_segs * sizeof(struct atiixp_dma_op)); 454 atiixp_disable_dma(sc, ch); 455 atiixp_unlock(sc); 456 457 return ch; 458 } 459 460 static int 461 atiixp_chan_setformat(kobj_t obj, void *data, uint32_t format) 462 { 463 struct atiixp_chinfo *ch = data; 464 struct atiixp_info *sc = ch->parent; 465 uint32_t value; 466 467 atiixp_lock(sc); 468 if (ch->dir == PCMDIR_REC) { 469 value = atiixp_rd(sc, ATI_REG_CMD); 470 value &= ~ATI_REG_CMD_INTERLEAVE_IN; 471 if ((format & AFMT_32BIT) == 0) 472 value |= ATI_REG_CMD_INTERLEAVE_IN; 473 atiixp_wr(sc, ATI_REG_CMD, value); 474 } else { 475 value = atiixp_rd(sc, ATI_REG_OUT_DMA_SLOT); 476 value &= ~ATI_REG_OUT_DMA_SLOT_MASK; 477 /* We do not have support for more than 2 channels, _yet_. */ 478 value |= ATI_REG_OUT_DMA_SLOT_BIT(3) | 479 ATI_REG_OUT_DMA_SLOT_BIT(4); 480 value |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 481 atiixp_wr(sc, ATI_REG_OUT_DMA_SLOT, value); 482 value = atiixp_rd(sc, ATI_REG_CMD); 483 value &= ~ATI_REG_CMD_INTERLEAVE_OUT; 484 if ((format & AFMT_32BIT) == 0) 485 value |= ATI_REG_CMD_INTERLEAVE_OUT; 486 atiixp_wr(sc, ATI_REG_CMD, value); 487 value = atiixp_rd(sc, ATI_REG_6CH_REORDER); 488 value &= ~ATI_REG_6CH_REORDER_EN; 489 atiixp_wr(sc, ATI_REG_6CH_REORDER, value); 490 } 491 ch->fmt = format; 492 atiixp_unlock(sc); 493 494 return 0; 495 } 496 497 static int 498 atiixp_chan_setspeed(kobj_t obj, void *data, uint32_t spd) 499 { 500 /* XXX We're supposed to do VRA/DRA processing right here */ 501 return ATI_IXP_BASE_RATE; 502 } 503 504 static int 505 atiixp_chan_setblocksize(kobj_t obj, void *data, uint32_t blksz) 506 { 507 struct atiixp_chinfo *ch = data; 508 struct atiixp_info *sc = ch->parent; 509 510 if (blksz > (sc->bufsz / ch->dma_segs)) 511 blksz = sc->bufsz / ch->dma_segs; 512 513 sndbuf_resize(ch->buffer, ch->dma_segs, blksz); 514 515 return sndbuf_getblksz(ch->buffer); 516 } 517 518 static void 519 atiixp_buildsgdt(struct atiixp_chinfo *ch) 520 { 521 uint32_t addr, blksz; 522 int i; 523 524 addr = sndbuf_getbufaddr(ch->buffer); 525 blksz = sndbuf_getblksz(ch->buffer); 526 527 for (i = 0; i < ch->dma_segs; i++) { 528 ch->sgd_table[i].addr = htole32(addr + (i * blksz)); 529 ch->sgd_table[i].status = htole16(0); 530 ch->sgd_table[i].size = htole16(blksz >> 2); 531 ch->sgd_table[i].next = htole32((uint32_t)ch->sgd_addr + 532 (((i + 1) % ch->dma_segs) * 533 sizeof(struct atiixp_dma_op))); 534 } 535 } 536 537 static int 538 atiixp_chan_trigger(kobj_t obj, void *data, int go) 539 { 540 struct atiixp_chinfo *ch = data; 541 struct atiixp_info *sc = ch->parent; 542 uint32_t value; 543 544 atiixp_lock(sc); 545 546 switch (go) { 547 case PCMTRIG_START: 548 atiixp_flush_dma(sc, ch); 549 atiixp_buildsgdt(ch); 550 atiixp_wr(sc, ch->linkptr_bit, 0); 551 atiixp_enable_dma(sc, ch); 552 atiixp_wr(sc, ch->linkptr_bit, 553 (uint32_t)ch->sgd_addr | ATI_REG_LINKPTR_EN); 554 break; 555 case PCMTRIG_STOP: 556 case PCMTRIG_ABORT: 557 atiixp_disable_dma(sc, ch); 558 atiixp_flush_dma(sc, ch); 559 break; 560 default: 561 atiixp_unlock(sc); 562 return 0; 563 break; 564 } 565 566 /* Update bus busy status */ 567 value = atiixp_rd(sc, ATI_REG_IER); 568 if (atiixp_rd(sc, ATI_REG_CMD) & ( 569 ATI_REG_CMD_SEND_EN | ATI_REG_CMD_RECEIVE_EN | 570 ATI_REG_CMD_SPDF_OUT_EN)) 571 value |= ATI_REG_IER_SET_BUS_BUSY; 572 else 573 value &= ~ATI_REG_IER_SET_BUS_BUSY; 574 atiixp_wr(sc, ATI_REG_IER, value); 575 576 atiixp_unlock(sc); 577 578 return 0; 579 } 580 581 static int 582 atiixp_chan_getptr(kobj_t obj, void *data) 583 { 584 struct atiixp_chinfo *ch = data; 585 struct atiixp_info *sc = ch->parent; 586 uint32_t addr, align, retry, sz; 587 volatile uint32_t ptr; 588 589 addr = sndbuf_getbufaddr(ch->buffer); 590 align = (ch->fmt & AFMT_32BIT) ? 7 : 3; 591 retry = 100; 592 sz = sndbuf_getblksz(ch->buffer) * ch->dma_segs; 593 594 atiixp_lock(sc); 595 do { 596 ptr = atiixp_rd(sc, ch->dma_dt_cur_bit); 597 if (ptr < addr) 598 continue; 599 ptr -= addr; 600 if (ptr < sz && !(ptr & align)) 601 break; 602 } while (--retry); 603 atiixp_unlock(sc); 604 605 #if 0 606 if (retry != 100) { 607 device_printf(sc->dev, 608 "%saligned hwptr: dir=PCMDIR_%s ptr=%u fmt=0x%08x retry=%d\n", 609 (ptr & align) ? "un" : "", 610 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", ptr, 611 ch->fmt, 100 - retry); 612 } 613 #endif 614 615 return (retry > 0) ? ptr : 0; 616 } 617 618 static struct pcmchan_caps * 619 atiixp_chan_getcaps(kobj_t obj, void *data) 620 { 621 struct atiixp_chinfo *ch = data; 622 623 if (ch->caps_32bit) 624 return &atiixp_caps_32bit; 625 return &atiixp_caps; 626 } 627 628 static kobj_method_t atiixp_chan_methods[] = { 629 KOBJMETHOD(channel_init, atiixp_chan_init), 630 KOBJMETHOD(channel_setformat, atiixp_chan_setformat), 631 KOBJMETHOD(channel_setspeed, atiixp_chan_setspeed), 632 KOBJMETHOD(channel_setblocksize, atiixp_chan_setblocksize), 633 KOBJMETHOD(channel_trigger, atiixp_chan_trigger), 634 KOBJMETHOD(channel_getptr, atiixp_chan_getptr), 635 KOBJMETHOD(channel_getcaps, atiixp_chan_getcaps), 636 { 0, 0 } 637 }; 638 CHANNEL_DECLARE(atiixp_chan); 639 640 /* 641 * PCI driver interface 642 */ 643 static void 644 atiixp_intr(void *p) 645 { 646 struct atiixp_info *sc = p; 647 uint32_t status, enable, detected_codecs; 648 649 atiixp_lock(sc); 650 status = atiixp_rd(sc, ATI_REG_ISR); 651 652 if (status == 0) { 653 atiixp_unlock(sc); 654 return; 655 } 656 657 if ((status & ATI_REG_ISR_IN_STATUS) && sc->rch.channel) { 658 atiixp_unlock(sc); 659 chn_intr(sc->rch.channel); 660 atiixp_lock(sc); 661 } 662 if ((status & ATI_REG_ISR_OUT_STATUS) && sc->pch.channel) { 663 atiixp_unlock(sc); 664 chn_intr(sc->pch.channel); 665 atiixp_lock(sc); 666 } 667 668 #if 0 669 if (status & ATI_REG_ISR_IN_XRUN) { 670 device_printf(sc->dev, 671 "Recieve IN XRUN interrupt\n"); 672 } 673 if (status & ATI_REG_ISR_OUT_XRUN) { 674 device_printf(sc->dev, 675 "Recieve OUT XRUN interrupt\n"); 676 } 677 #endif 678 679 if (status & CODEC_CHECK_BITS) { 680 /* mark missing codecs as not ready */ 681 detected_codecs = status & CODEC_CHECK_BITS; 682 sc->codec_not_ready_bits |= detected_codecs; 683 684 /* disable detected interupt sources */ 685 enable = atiixp_rd(sc, ATI_REG_IER); 686 enable &= ~detected_codecs; 687 atiixp_wr(sc, ATI_REG_IER, enable); 688 } 689 690 /* acknowledge */ 691 atiixp_wr(sc, ATI_REG_ISR, status); 692 atiixp_unlock(sc); 693 } 694 695 static void 696 atiixp_dma_cb(void *p, bus_dma_segment_t *bds, int a, int b) 697 { 698 struct atiixp_info *sc = (struct atiixp_info *)p; 699 sc->sgd_addr = bds->ds_addr; 700 } 701 702 static void 703 atiixp_chip_pre_init(struct atiixp_info *sc) 704 { 705 uint32_t value; 706 707 atiixp_lock(sc); 708 709 /* disable interrupts */ 710 atiixp_disable_interrupts(sc); 711 712 /* clear all DMA enables (preserving rest of settings) */ 713 value = atiixp_rd(sc, ATI_REG_CMD); 714 value &= ~(ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_OUT_DMA_EN | 715 ATI_REG_CMD_SPDF_OUT_EN ); 716 atiixp_wr(sc, ATI_REG_CMD, value); 717 718 /* reset aclink */ 719 atiixp_reset_aclink(sc); 720 721 sc->codec_not_ready_bits = 0; 722 723 /* enable all codecs to interrupt as well as the new frame interrupt */ 724 atiixp_wr(sc, ATI_REG_IER, CODEC_CHECK_BITS); 725 726 atiixp_unlock(sc); 727 } 728 729 static void 730 atiixp_chip_post_init(void *arg) 731 { 732 struct atiixp_info *sc = (struct atiixp_info *)arg; 733 uint32_t subdev; 734 int i, timeout, found; 735 char status[SND_STATUSLEN]; 736 737 atiixp_lock(sc); 738 739 if (sc->delayed_attach.ich_func) { 740 config_intrhook_disestablish(&sc->delayed_attach); 741 sc->delayed_attach.ich_func = NULL; 742 } 743 744 /* wait for the interrupts to happen */ 745 timeout = 100; 746 while (--timeout) { 747 msleep(sc, sc->lock, PWAIT, "ixpslp", 1); 748 if (sc->codec_not_ready_bits) 749 break; 750 } 751 752 atiixp_disable_interrupts(sc); 753 754 if (timeout == 0) { 755 device_printf(sc->dev, 756 "WARNING: timeout during codec detection; " 757 "codecs might be present but haven't interrupted\n"); 758 atiixp_unlock(sc); 759 goto postinitbad; 760 } 761 762 found = 0; 763 764 /* 765 * ATI IXP can have upto 3 codecs, but single codec should be 766 * suffice for now. 767 */ 768 if (!(sc->codec_not_ready_bits & 769 ATI_REG_ISR_CODEC0_NOT_READY)) { 770 /* codec 0 present */ 771 sc->codec_found++; 772 sc->codec_idx = 0; 773 found++; 774 } 775 776 if (!(sc->codec_not_ready_bits & 777 ATI_REG_ISR_CODEC1_NOT_READY)) { 778 /* codec 1 present */ 779 sc->codec_found++; 780 } 781 782 if (!(sc->codec_not_ready_bits & 783 ATI_REG_ISR_CODEC2_NOT_READY)) { 784 /* codec 2 present */ 785 sc->codec_found++; 786 } 787 788 atiixp_unlock(sc); 789 790 if (found == 0) 791 goto postinitbad; 792 793 /* create/init mixer */ 794 sc->codec = AC97_CREATE(sc->dev, sc, atiixp_ac97); 795 if (sc->codec == NULL) 796 goto postinitbad; 797 798 subdev = (pci_get_subdevice(sc->dev) << 16) | pci_get_subvendor(sc->dev); 799 switch (subdev) { 800 case 0x2043161f: /* Maxselect x710s - http://maxselect.ru/ */ 801 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 802 break; 803 default: 804 break; 805 } 806 807 mixer_init(sc->dev, ac97_getmixerclass(), sc->codec); 808 809 if (pcm_register(sc->dev, sc, ATI_IXP_NPCHAN, ATI_IXP_NRCHAN)) 810 goto postinitbad; 811 812 for (i = 0; i < ATI_IXP_NPCHAN; i++) 813 pcm_addchan(sc->dev, PCMDIR_PLAY, &atiixp_chan_class, sc); 814 for (i = 0; i < ATI_IXP_NRCHAN; i++) 815 pcm_addchan(sc->dev, PCMDIR_REC, &atiixp_chan_class, sc); 816 817 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s", 818 rman_get_start(sc->reg), rman_get_start(sc->irq), 819 PCM_KLDSTRING(snd_atiixp)); 820 821 pcm_setstatus(sc->dev, status); 822 823 atiixp_lock(sc); 824 atiixp_enable_interrupts(sc); 825 atiixp_unlock(sc); 826 827 return; 828 829 postinitbad: 830 atiixp_release_resource(sc); 831 } 832 833 static void 834 atiixp_release_resource(struct atiixp_info *sc) 835 { 836 if (sc == NULL) 837 return; 838 if (sc->codec) { 839 ac97_destroy(sc->codec); 840 sc->codec = NULL; 841 } 842 if (sc->ih) { 843 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 844 sc->ih = 0; 845 } 846 if (sc->reg) { 847 bus_release_resource(sc->dev, sc->regtype, sc->regid, sc->reg); 848 sc->reg = 0; 849 } 850 if (sc->irq) { 851 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irqid, sc->irq); 852 sc->irq = 0; 853 } 854 if (sc->parent_dmat) { 855 bus_dma_tag_destroy(sc->parent_dmat); 856 sc->parent_dmat = 0; 857 } 858 if (sc->sgd_dmamap) { 859 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 860 sc->sgd_dmamap = 0; 861 } 862 if (sc->sgd_dmat) { 863 bus_dma_tag_destroy(sc->sgd_dmat); 864 sc->sgd_dmat = 0; 865 } 866 if (sc->lock) { 867 snd_mtxfree(sc->lock); 868 sc->lock = NULL; 869 } 870 } 871 872 static int 873 atiixp_pci_probe(device_t dev) 874 { 875 int i; 876 uint16_t devid, vendor; 877 878 vendor = pci_get_vendor(dev); 879 devid = pci_get_device(dev); 880 for (i = 0; i < sizeof(atiixp_hw)/sizeof(atiixp_hw[0]); i++) { 881 if (vendor == atiixp_hw[i].vendor && 882 devid == atiixp_hw[i].devid) { 883 device_set_desc(dev, atiixp_hw[i].desc); 884 return BUS_PROBE_DEFAULT; 885 } 886 } 887 888 return ENXIO; 889 } 890 891 static int 892 atiixp_pci_attach(device_t dev) 893 { 894 struct atiixp_info *sc; 895 int i; 896 897 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 898 device_printf(dev, "cannot allocate softc\n"); 899 return ENXIO; 900 } 901 902 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 903 sc->dev = dev; 904 /* 905 * Default DMA segments per playback / recording channel 906 */ 907 sc->dma_segs = ATI_IXP_DMA_CHSEGS; 908 909 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 910 pci_enable_busmaster(dev); 911 912 sc->regid = PCIR_BAR(0); 913 sc->regtype = SYS_RES_MEMORY; 914 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 915 RF_ACTIVE); 916 917 if (!sc->reg) { 918 device_printf(dev, "unable to allocate register space\n"); 919 goto bad; 920 } 921 922 sc->st = rman_get_bustag(sc->reg); 923 sc->sh = rman_get_bushandle(sc->reg); 924 925 sc->bufsz = pcm_getbuffersize(dev, 4096, ATI_IXP_DEFAULT_BUFSZ, 65536); 926 927 sc->irqid = 0; 928 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 929 RF_ACTIVE | RF_SHAREABLE); 930 if (!sc->irq || 931 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, 932 atiixp_intr, sc, &sc->ih)) { 933 device_printf(dev, "unable to map interrupt\n"); 934 goto bad; 935 } 936 937 /* 938 * Let the user choose the best DMA segments. 939 */ 940 if (resource_int_value(device_get_name(dev), 941 device_get_unit(dev), "dma_segs", 942 &i) == 0) { 943 if (i < ATI_IXP_DMA_CHSEGS_MIN) 944 i = ATI_IXP_DMA_CHSEGS_MIN; 945 if (i > ATI_IXP_DMA_CHSEGS_MAX) 946 i = ATI_IXP_DMA_CHSEGS_MAX; 947 sc->dma_segs = i; 948 } 949 950 /* 951 * round the value to the nearest ^2 952 */ 953 i = 0; 954 while (sc->dma_segs >> i) 955 i++; 956 sc->dma_segs = 1 << (i - 1); 957 if (sc->dma_segs < ATI_IXP_DMA_CHSEGS_MIN) 958 sc->dma_segs = ATI_IXP_DMA_CHSEGS_MIN; 959 else if (sc->dma_segs > ATI_IXP_DMA_CHSEGS_MAX) 960 sc->dma_segs = ATI_IXP_DMA_CHSEGS_MAX; 961 962 /* 963 * DMA tag for scatter-gather buffers and link pointers 964 */ 965 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/sc->bufsz, /*boundary*/0, 966 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 967 /*highaddr*/BUS_SPACE_MAXADDR, 968 /*filter*/NULL, /*filterarg*/NULL, 969 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 970 /*flags*/0, /*lockfunc*/NULL, 971 /*lockarg*/NULL, &sc->parent_dmat) != 0) { 972 device_printf(dev, "unable to create dma tag\n"); 973 goto bad; 974 } 975 976 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 977 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 978 /*highaddr*/BUS_SPACE_MAXADDR, 979 /*filter*/NULL, /*filterarg*/NULL, 980 /*maxsize*/sc->dma_segs * ATI_IXP_NCHANS * 981 sizeof(struct atiixp_dma_op), 982 /*nsegments*/1, /*maxsegz*/0x3ffff, 983 /*flags*/0, /*lockfunc*/NULL, 984 /*lockarg*/NULL, &sc->sgd_dmat) != 0) { 985 device_printf(dev, "unable to create dma tag\n"); 986 goto bad; 987 } 988 989 if (bus_dmamem_alloc(sc->sgd_dmat, (void **)&sc->sgd_table, 990 BUS_DMA_NOWAIT, &sc->sgd_dmamap) == -1) 991 goto bad; 992 993 if (bus_dmamap_load(sc->sgd_dmat, sc->sgd_dmamap, sc->sgd_table, 994 sc->dma_segs * ATI_IXP_NCHANS * 995 sizeof(struct atiixp_dma_op), 996 atiixp_dma_cb, sc, 0)) 997 goto bad; 998 999 1000 atiixp_chip_pre_init(sc); 1001 1002 sc->delayed_attach.ich_func = atiixp_chip_post_init; 1003 sc->delayed_attach.ich_arg = sc; 1004 if (cold == 0 || 1005 config_intrhook_establish(&sc->delayed_attach) != 0) { 1006 sc->delayed_attach.ich_func = NULL; 1007 atiixp_chip_post_init(sc); 1008 } 1009 1010 return 0; 1011 1012 bad: 1013 atiixp_release_resource(sc); 1014 return ENXIO; 1015 } 1016 1017 static int 1018 atiixp_pci_detach(device_t dev) 1019 { 1020 int r; 1021 struct atiixp_info *sc; 1022 1023 sc = pcm_getdevinfo(dev); 1024 if (sc != NULL) { 1025 if (sc->codec != NULL) { 1026 r = pcm_unregister(dev); 1027 if (r) 1028 return r; 1029 } 1030 sc->codec = NULL; 1031 atiixp_disable_interrupts(sc); 1032 atiixp_release_resource(sc); 1033 free(sc, M_DEVBUF); 1034 } 1035 return 0; 1036 } 1037 1038 static int 1039 atiixp_pci_suspend(device_t dev) 1040 { 1041 struct atiixp_info *sc = pcm_getdevinfo(dev); 1042 uint32_t value; 1043 1044 /* quickly disable interrupts and save channels active state */ 1045 atiixp_lock(sc); 1046 atiixp_disable_interrupts(sc); 1047 value = atiixp_rd(sc, ATI_REG_CMD); 1048 sc->pch.active = (value & ATI_REG_CMD_SEND_EN) ? 1 : 0; 1049 sc->rch.active = (value & ATI_REG_CMD_RECEIVE_EN) ? 1 : 0; 1050 atiixp_unlock(sc); 1051 1052 /* stop everything */ 1053 if (sc->pch.channel && sc->pch.active) 1054 atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_STOP); 1055 if (sc->rch.channel && sc->rch.active) 1056 atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_STOP); 1057 1058 /* power down aclink and pci bus */ 1059 atiixp_lock(sc); 1060 value = atiixp_rd(sc, ATI_REG_CMD); 1061 value |= ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET; 1062 atiixp_wr(sc, ATI_REG_CMD, ATI_REG_CMD_POWERDOWN); 1063 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1064 atiixp_unlock(sc); 1065 1066 return 0; 1067 } 1068 1069 static int 1070 atiixp_pci_resume(device_t dev) 1071 { 1072 struct atiixp_info *sc = pcm_getdevinfo(dev); 1073 1074 atiixp_lock(sc); 1075 /* power up pci bus */ 1076 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1077 pci_enable_io(dev, SYS_RES_MEMORY); 1078 pci_enable_busmaster(dev); 1079 /* reset / power up aclink */ 1080 atiixp_reset_aclink(sc); 1081 atiixp_unlock(sc); 1082 1083 if (mixer_reinit(dev) == -1) { 1084 device_printf(dev, "unable to reinitialize the mixer\n"); 1085 return ENXIO; 1086 } 1087 1088 /* 1089 * Resume channel activities. Reset channel format regardless 1090 * of its previous state. 1091 */ 1092 if (sc->pch.channel) { 1093 if (sc->pch.fmt) 1094 atiixp_chan_setformat(NULL, &sc->pch, sc->pch.fmt); 1095 if (sc->pch.active) 1096 atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_START); 1097 } 1098 if (sc->rch.channel) { 1099 if (sc->rch.fmt) 1100 atiixp_chan_setformat(NULL, &sc->rch, sc->rch.fmt); 1101 if (sc->rch.active) 1102 atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_START); 1103 } 1104 1105 /* enable interrupts */ 1106 atiixp_lock(sc); 1107 atiixp_enable_interrupts(sc); 1108 atiixp_unlock(sc); 1109 1110 return 0; 1111 } 1112 1113 static device_method_t atiixp_methods[] = { 1114 DEVMETHOD(device_probe, atiixp_pci_probe), 1115 DEVMETHOD(device_attach, atiixp_pci_attach), 1116 DEVMETHOD(device_detach, atiixp_pci_detach), 1117 DEVMETHOD(device_suspend, atiixp_pci_suspend), 1118 DEVMETHOD(device_resume, atiixp_pci_resume), 1119 { 0, 0 } 1120 }; 1121 1122 static driver_t atiixp_driver = { 1123 "pcm", 1124 atiixp_methods, 1125 PCM_SOFTC_SIZE, 1126 }; 1127 1128 DRIVER_MODULE(snd_atiixp, pci, atiixp_driver, pcm_devclass, 0, 0); 1129 MODULE_DEPEND(snd_atiixp, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1130 MODULE_VERSION(snd_atiixp, 1); 1131