1 /*- 2 * Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * FreeBSD pcm driver for ATI IXP 150/200/250/300 AC97 controllers 29 * 30 * Features 31 * * 16bit playback / recording 32 * * 32bit native playback - yay! 33 * 34 * Issues / TODO: 35 * * SPDIF 36 * * Support for more than 2 channels. 37 * * VRA ? VRM ? DRA ? 38 * * 32bit native recording (seems broken, disabled) 39 * 40 * 41 * Thanks goes to: 42 * 43 * Shaharil @ SCAN Associates whom relentlessly providing me the 44 * mind blowing Acer Ferrari 4002 WLMi with this ATI IXP hardware. 45 * 46 * Reinoud Zandijk <reinoud@NetBSD.org> (auixp), which this driver is 47 * largely based upon although large part of it has been reworked. His 48 * driver is the primary reference and pretty much well documented. 49 * 50 * Takashi Iwai (ALSA snd-atiixp), for register definitions and some 51 * random ninja hackery. 52 */ 53 54 #include <dev/sound/pcm/sound.h> 55 #include <dev/sound/pcm/ac97.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 #include <sys/sysctl.h> 60 #include <sys/endian.h> 61 62 #include <dev/sound/pci/atiixp.h> 63 64 SND_DECLARE_FILE("$FreeBSD$"); 65 66 67 struct atiixp_dma_op { 68 uint32_t addr; 69 uint16_t status; 70 uint16_t size; 71 uint32_t next; 72 }; 73 74 struct atiixp_info; 75 76 struct atiixp_chinfo { 77 struct snd_dbuf *buffer; 78 struct pcm_channel *channel; 79 struct atiixp_info *parent; 80 struct atiixp_dma_op *sgd_table; 81 bus_addr_t sgd_addr; 82 uint32_t enable_bit, flush_bit, linkptr_bit, dma_dt_cur_bit; 83 uint32_t dma_segs; 84 uint32_t fmt; 85 int caps_32bit, dir, active; 86 }; 87 88 struct atiixp_info { 89 device_t dev; 90 91 bus_space_tag_t st; 92 bus_space_handle_t sh; 93 bus_dma_tag_t parent_dmat; 94 bus_dma_tag_t sgd_dmat; 95 bus_dmamap_t sgd_dmamap; 96 bus_addr_t sgd_addr; 97 98 struct resource *reg, *irq; 99 int regtype, regid, irqid; 100 void *ih; 101 struct ac97_info *codec; 102 103 struct atiixp_chinfo pch; 104 struct atiixp_chinfo rch; 105 struct atiixp_dma_op *sgd_table; 106 struct intr_config_hook delayed_attach; 107 108 uint32_t bufsz; 109 uint32_t codec_not_ready_bits, codec_idx, codec_found; 110 uint32_t dma_segs; 111 int registered_channels; 112 113 struct mtx *lock; 114 }; 115 116 #define atiixp_rd(_sc, _reg) \ 117 bus_space_read_4((_sc)->st, (_sc)->sh, _reg) 118 #define atiixp_wr(_sc, _reg, _val) \ 119 bus_space_write_4((_sc)->st, (_sc)->sh, _reg, _val) 120 121 #define atiixp_lock(_sc) snd_mtxlock((_sc)->lock) 122 #define atiixp_unlock(_sc) snd_mtxunlock((_sc)->lock) 123 #define atiixp_assert(_sc) snd_mtxassert((_sc)->lock) 124 125 static uint32_t atiixp_fmt_32bit[] = { 126 AFMT_STEREO | AFMT_S16_LE, 127 #ifdef AFMT_S32_LE 128 AFMT_STEREO | AFMT_S32_LE, 129 #endif 130 0 131 }; 132 133 static uint32_t atiixp_fmt[] = { 134 AFMT_STEREO | AFMT_S16_LE, 135 0 136 }; 137 138 static struct pcmchan_caps atiixp_caps_32bit = { 139 ATI_IXP_BASE_RATE, 140 ATI_IXP_BASE_RATE, 141 atiixp_fmt_32bit, 0 142 }; 143 144 static struct pcmchan_caps atiixp_caps = { 145 ATI_IXP_BASE_RATE, 146 ATI_IXP_BASE_RATE, 147 atiixp_fmt, 0 148 }; 149 150 static const struct { 151 uint16_t vendor; 152 uint16_t devid; 153 char *desc; 154 } atiixp_hw[] = { 155 { ATI_VENDOR_ID, ATI_IXP_200_ID, "ATI IXP 200" }, 156 { ATI_VENDOR_ID, ATI_IXP_300_ID, "ATI IXP 300" }, 157 { ATI_VENDOR_ID, ATI_IXP_400_ID, "ATI IXP 400" }, 158 }; 159 160 static void atiixp_enable_interrupts(struct atiixp_info *); 161 static void atiixp_disable_interrupts(struct atiixp_info *); 162 static void atiixp_reset_aclink(struct atiixp_info *); 163 static void atiixp_flush_dma(struct atiixp_info *, struct atiixp_chinfo *); 164 static void atiixp_enable_dma(struct atiixp_info *, struct atiixp_chinfo *); 165 static void atiixp_disable_dma(struct atiixp_info *, struct atiixp_chinfo *); 166 167 static int atiixp_waitready_codec(struct atiixp_info *); 168 static int atiixp_rdcd(kobj_t, void *, int); 169 static int atiixp_wrcd(kobj_t, void *, int, uint32_t); 170 171 static void *atiixp_chan_init(kobj_t, void *, struct snd_dbuf *, 172 struct pcm_channel *, int); 173 static int atiixp_chan_setformat(kobj_t, void *, uint32_t); 174 static int atiixp_chan_setspeed(kobj_t, void *, uint32_t); 175 static int atiixp_chan_setblocksize(kobj_t, void *, uint32_t); 176 static void atiixp_buildsgdt(struct atiixp_chinfo *); 177 static int atiixp_chan_trigger(kobj_t, void *, int); 178 static int atiixp_chan_getptr(kobj_t, void *); 179 static struct pcmchan_caps *atiixp_chan_getcaps(kobj_t, void *); 180 181 static void atiixp_intr(void *); 182 static void atiixp_dma_cb(void *, bus_dma_segment_t *, int, int); 183 static void atiixp_chip_pre_init(struct atiixp_info *); 184 static void atiixp_chip_post_init(void *); 185 static int atiixp_pci_probe(device_t); 186 static int atiixp_pci_attach(device_t); 187 static int atiixp_pci_detach(device_t); 188 static int atiixp_pci_suspend(device_t); 189 static int atiixp_pci_resume(device_t); 190 191 /* 192 * ATI IXP helper functions 193 */ 194 static void 195 atiixp_enable_interrupts(struct atiixp_info *sc) 196 { 197 uint32_t value; 198 199 /* clear all pending */ 200 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 201 202 /* enable all relevant interrupt sources we can handle */ 203 value = atiixp_rd(sc, ATI_REG_IER); 204 205 value |= ATI_REG_IER_IO_STATUS_EN; 206 207 /* 208 * Disable / ignore internal xrun/spdf interrupt flags 209 * since it doesn't interest us (for now). 210 */ 211 #if 0 212 value |= ATI_REG_IER_IN_XRUN_EN; 213 value |= ATI_REG_IER_OUT_XRUN_EN; 214 215 value |= ATI_REG_IER_SPDF_XRUN_EN; 216 value |= ATI_REG_IER_SPDF_STATUS_EN; 217 #endif 218 219 atiixp_wr(sc, ATI_REG_IER, value); 220 } 221 222 static void 223 atiixp_disable_interrupts(struct atiixp_info *sc) 224 { 225 /* disable all interrupt sources */ 226 atiixp_wr(sc, ATI_REG_IER, 0); 227 228 /* clear all pending */ 229 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 230 } 231 232 static void 233 atiixp_reset_aclink(struct atiixp_info *sc) 234 { 235 uint32_t value, timeout; 236 237 /* if power is down, power it up */ 238 value = atiixp_rd(sc, ATI_REG_CMD); 239 if (value & ATI_REG_CMD_POWERDOWN) { 240 /* explicitly enable power */ 241 value &= ~ATI_REG_CMD_POWERDOWN; 242 atiixp_wr(sc, ATI_REG_CMD, value); 243 244 /* have to wait at least 10 usec for it to initialise */ 245 DELAY(20); 246 }; 247 248 /* perform a soft reset */ 249 value = atiixp_rd(sc, ATI_REG_CMD); 250 value |= ATI_REG_CMD_AC_SOFT_RESET; 251 atiixp_wr(sc, ATI_REG_CMD, value); 252 253 /* need to read the CMD reg and wait aprox. 10 usec to init */ 254 value = atiixp_rd(sc, ATI_REG_CMD); 255 DELAY(20); 256 257 /* clear soft reset flag again */ 258 value = atiixp_rd(sc, ATI_REG_CMD); 259 value &= ~ATI_REG_CMD_AC_SOFT_RESET; 260 atiixp_wr(sc, ATI_REG_CMD, value); 261 262 /* check if the ac-link is working; reset device otherwise */ 263 timeout = 10; 264 value = atiixp_rd(sc, ATI_REG_CMD); 265 while (!(value & ATI_REG_CMD_ACLINK_ACTIVE) 266 && --timeout) { 267 #if 0 268 device_printf(sc->dev, "not up; resetting aclink hardware\n"); 269 #endif 270 271 /* dip aclink reset but keep the acsync */ 272 value &= ~ATI_REG_CMD_AC_RESET; 273 value |= ATI_REG_CMD_AC_SYNC; 274 atiixp_wr(sc, ATI_REG_CMD, value); 275 276 /* need to read CMD again and wait again (clocking in issue?) */ 277 value = atiixp_rd(sc, ATI_REG_CMD); 278 DELAY(20); 279 280 /* assert aclink reset again */ 281 value = atiixp_rd(sc, ATI_REG_CMD); 282 value |= ATI_REG_CMD_AC_RESET; 283 atiixp_wr(sc, ATI_REG_CMD, value); 284 285 /* check if its active now */ 286 value = atiixp_rd(sc, ATI_REG_CMD); 287 }; 288 289 if (timeout == 0) 290 device_printf(sc->dev, "giving up aclink reset\n"); 291 #if 0 292 if (timeout != 10) 293 device_printf(sc->dev, "aclink hardware reset successful\n"); 294 #endif 295 296 /* assert reset and sync for safety */ 297 value = atiixp_rd(sc, ATI_REG_CMD); 298 value |= ATI_REG_CMD_AC_SYNC | ATI_REG_CMD_AC_RESET; 299 atiixp_wr(sc, ATI_REG_CMD, value); 300 } 301 302 static void 303 atiixp_flush_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 304 { 305 atiixp_wr(sc, ATI_REG_FIFO_FLUSH, ch->flush_bit); 306 } 307 308 static void 309 atiixp_enable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 310 { 311 uint32_t value; 312 313 value = atiixp_rd(sc, ATI_REG_CMD); 314 if (!(value & ch->enable_bit)) { 315 value |= ch->enable_bit; 316 atiixp_wr(sc, ATI_REG_CMD, value); 317 } 318 } 319 320 static void 321 atiixp_disable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 322 { 323 uint32_t value; 324 325 value = atiixp_rd(sc, ATI_REG_CMD); 326 if (value & ch->enable_bit) { 327 value &= ~ch->enable_bit; 328 atiixp_wr(sc, ATI_REG_CMD, value); 329 } 330 } 331 332 /* 333 * AC97 interface 334 */ 335 static int 336 atiixp_waitready_codec(struct atiixp_info *sc) 337 { 338 int timeout = 500; 339 340 do { 341 if ((atiixp_rd(sc, ATI_REG_PHYS_OUT_ADDR) & 342 ATI_REG_PHYS_OUT_ADDR_EN) == 0) 343 return 0; 344 DELAY(1); 345 } while (timeout--); 346 347 return -1; 348 } 349 350 static int 351 atiixp_rdcd(kobj_t obj, void *devinfo, int reg) 352 { 353 struct atiixp_info *sc = devinfo; 354 uint32_t data; 355 int timeout; 356 357 if (atiixp_waitready_codec(sc)) 358 return -1; 359 360 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 361 ATI_REG_PHYS_OUT_ADDR_EN | 362 ATI_REG_PHYS_OUT_RW | sc->codec_idx; 363 364 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 365 366 if (atiixp_waitready_codec(sc)) 367 return -1; 368 369 timeout = 500; 370 do { 371 data = atiixp_rd(sc, ATI_REG_PHYS_IN_ADDR); 372 if (data & ATI_REG_PHYS_IN_READ_FLAG) 373 return data >> ATI_REG_PHYS_IN_DATA_SHIFT; 374 DELAY(1); 375 } while (timeout--); 376 377 if (reg < 0x7c) 378 device_printf(sc->dev, "codec read timeout! (reg 0x%x)\n", reg); 379 380 return -1; 381 } 382 383 static int 384 atiixp_wrcd(kobj_t obj, void *devinfo, int reg, uint32_t data) 385 { 386 struct atiixp_info *sc = devinfo; 387 388 if (atiixp_waitready_codec(sc)) 389 return -1; 390 391 data = (data << ATI_REG_PHYS_OUT_DATA_SHIFT) | 392 (((uint32_t)reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 393 ATI_REG_PHYS_OUT_ADDR_EN | sc->codec_idx; 394 395 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 396 397 return 0; 398 } 399 400 static kobj_method_t atiixp_ac97_methods[] = { 401 KOBJMETHOD(ac97_read, atiixp_rdcd), 402 KOBJMETHOD(ac97_write, atiixp_wrcd), 403 { 0, 0 } 404 }; 405 AC97_DECLARE(atiixp_ac97); 406 407 /* 408 * Playback / Record channel interface 409 */ 410 static void * 411 atiixp_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 412 struct pcm_channel *c, int dir) 413 { 414 struct atiixp_info *sc = devinfo; 415 struct atiixp_chinfo *ch; 416 int num; 417 418 atiixp_lock(sc); 419 420 if (dir == PCMDIR_PLAY) { 421 ch = &sc->pch; 422 ch->linkptr_bit = ATI_REG_OUT_DMA_LINKPTR; 423 ch->enable_bit = ATI_REG_CMD_OUT_DMA_EN | ATI_REG_CMD_SEND_EN; 424 ch->flush_bit = ATI_REG_FIFO_OUT_FLUSH; 425 ch->dma_dt_cur_bit = ATI_REG_OUT_DMA_DT_CUR; 426 /* Native 32bit playback working properly */ 427 ch->caps_32bit = 1; 428 } else { 429 ch = &sc->rch; 430 ch->linkptr_bit = ATI_REG_IN_DMA_LINKPTR; 431 ch->enable_bit = ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_RECEIVE_EN; 432 ch->flush_bit = ATI_REG_FIFO_IN_FLUSH; 433 ch->dma_dt_cur_bit = ATI_REG_IN_DMA_DT_CUR; 434 /* XXX Native 32bit recording appear to be broken */ 435 ch->caps_32bit = 0; 436 } 437 438 ch->buffer = b; 439 ch->parent = sc; 440 ch->channel = c; 441 ch->dir = dir; 442 ch->dma_segs = sc->dma_segs; 443 444 atiixp_unlock(sc); 445 446 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1) 447 return NULL; 448 449 atiixp_lock(sc); 450 num = sc->registered_channels++; 451 ch->sgd_table = &sc->sgd_table[num * ch->dma_segs]; 452 ch->sgd_addr = sc->sgd_addr + 453 (num * ch->dma_segs * sizeof(struct atiixp_dma_op)); 454 atiixp_disable_dma(sc, ch); 455 atiixp_unlock(sc); 456 457 return ch; 458 } 459 460 static int 461 atiixp_chan_setformat(kobj_t obj, void *data, uint32_t format) 462 { 463 struct atiixp_chinfo *ch = data; 464 struct atiixp_info *sc = ch->parent; 465 uint32_t value; 466 467 atiixp_lock(sc); 468 if (ch->dir == PCMDIR_REC) { 469 value = atiixp_rd(sc, ATI_REG_CMD); 470 value &= ~ATI_REG_CMD_INTERLEAVE_IN; 471 if (ch->caps_32bit == 0 || 472 (format & (AFMT_8BIT|AFMT_16BIT)) != 0) 473 value |= ATI_REG_CMD_INTERLEAVE_IN; 474 atiixp_wr(sc, ATI_REG_CMD, value); 475 } else { 476 value = atiixp_rd(sc, ATI_REG_OUT_DMA_SLOT); 477 value &= ~ATI_REG_OUT_DMA_SLOT_MASK; 478 /* We do not have support for more than 2 channels, _yet_. */ 479 value |= ATI_REG_OUT_DMA_SLOT_BIT(3) | 480 ATI_REG_OUT_DMA_SLOT_BIT(4); 481 value |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 482 atiixp_wr(sc, ATI_REG_OUT_DMA_SLOT, value); 483 value = atiixp_rd(sc, ATI_REG_CMD); 484 value &= ~ATI_REG_CMD_INTERLEAVE_OUT; 485 if (ch->caps_32bit == 0 || 486 (format & (AFMT_8BIT|AFMT_16BIT)) != 0) 487 value |= ATI_REG_CMD_INTERLEAVE_OUT; 488 atiixp_wr(sc, ATI_REG_CMD, value); 489 value = atiixp_rd(sc, ATI_REG_6CH_REORDER); 490 value &= ~ATI_REG_6CH_REORDER_EN; 491 atiixp_wr(sc, ATI_REG_6CH_REORDER, value); 492 } 493 ch->fmt = format; 494 atiixp_unlock(sc); 495 496 return 0; 497 } 498 499 static int 500 atiixp_chan_setspeed(kobj_t obj, void *data, uint32_t spd) 501 { 502 /* XXX We're supposed to do VRA/DRA processing right here */ 503 return ATI_IXP_BASE_RATE; 504 } 505 506 static int 507 atiixp_chan_setblocksize(kobj_t obj, void *data, uint32_t blksz) 508 { 509 struct atiixp_chinfo *ch = data; 510 struct atiixp_info *sc = ch->parent; 511 512 if (blksz > (sc->bufsz / ch->dma_segs)) 513 blksz = sc->bufsz / ch->dma_segs; 514 515 sndbuf_resize(ch->buffer, ch->dma_segs, blksz); 516 517 return sndbuf_getblksz(ch->buffer); 518 } 519 520 static void 521 atiixp_buildsgdt(struct atiixp_chinfo *ch) 522 { 523 uint32_t addr, blksz; 524 int i; 525 526 addr = sndbuf_getbufaddr(ch->buffer); 527 blksz = sndbuf_getblksz(ch->buffer); 528 529 for (i = 0; i < ch->dma_segs; i++) { 530 ch->sgd_table[i].addr = htole32(addr + (i * blksz)); 531 ch->sgd_table[i].status = htole16(0); 532 ch->sgd_table[i].size = htole16(blksz >> 2); 533 ch->sgd_table[i].next = htole32((uint32_t)ch->sgd_addr + 534 (((i + 1) % ch->dma_segs) * 535 sizeof(struct atiixp_dma_op))); 536 } 537 } 538 539 static int 540 atiixp_chan_trigger(kobj_t obj, void *data, int go) 541 { 542 struct atiixp_chinfo *ch = data; 543 struct atiixp_info *sc = ch->parent; 544 uint32_t value; 545 546 atiixp_lock(sc); 547 548 switch (go) { 549 case PCMTRIG_START: 550 atiixp_flush_dma(sc, ch); 551 atiixp_buildsgdt(ch); 552 atiixp_wr(sc, ch->linkptr_bit, 0); 553 atiixp_enable_dma(sc, ch); 554 atiixp_wr(sc, ch->linkptr_bit, 555 (uint32_t)ch->sgd_addr | ATI_REG_LINKPTR_EN); 556 break; 557 case PCMTRIG_STOP: 558 case PCMTRIG_ABORT: 559 atiixp_disable_dma(sc, ch); 560 atiixp_flush_dma(sc, ch); 561 break; 562 default: 563 atiixp_unlock(sc); 564 return 0; 565 break; 566 } 567 568 /* Update bus busy status */ 569 value = atiixp_rd(sc, ATI_REG_IER); 570 if (atiixp_rd(sc, ATI_REG_CMD) & ( 571 ATI_REG_CMD_SEND_EN | ATI_REG_CMD_RECEIVE_EN | 572 ATI_REG_CMD_SPDF_OUT_EN)) 573 value |= ATI_REG_IER_SET_BUS_BUSY; 574 else 575 value &= ~ATI_REG_IER_SET_BUS_BUSY; 576 atiixp_wr(sc, ATI_REG_IER, value); 577 578 atiixp_unlock(sc); 579 580 return 0; 581 } 582 583 static int 584 atiixp_chan_getptr(kobj_t obj, void *data) 585 { 586 struct atiixp_chinfo *ch = data; 587 struct atiixp_info *sc = ch->parent; 588 uint32_t ptr; 589 590 atiixp_lock(sc); 591 ptr = atiixp_rd(sc, ch->dma_dt_cur_bit); 592 atiixp_unlock(sc); 593 594 return ptr; 595 } 596 597 static struct pcmchan_caps * 598 atiixp_chan_getcaps(kobj_t obj, void *data) 599 { 600 struct atiixp_chinfo *ch = data; 601 602 if (ch->caps_32bit) 603 return &atiixp_caps_32bit; 604 return &atiixp_caps; 605 } 606 607 static kobj_method_t atiixp_chan_methods[] = { 608 KOBJMETHOD(channel_init, atiixp_chan_init), 609 KOBJMETHOD(channel_setformat, atiixp_chan_setformat), 610 KOBJMETHOD(channel_setspeed, atiixp_chan_setspeed), 611 KOBJMETHOD(channel_setblocksize, atiixp_chan_setblocksize), 612 KOBJMETHOD(channel_trigger, atiixp_chan_trigger), 613 KOBJMETHOD(channel_getptr, atiixp_chan_getptr), 614 KOBJMETHOD(channel_getcaps, atiixp_chan_getcaps), 615 { 0, 0 } 616 }; 617 CHANNEL_DECLARE(atiixp_chan); 618 619 /* 620 * PCI driver interface 621 */ 622 static void 623 atiixp_intr(void *p) 624 { 625 struct atiixp_info *sc = p; 626 uint32_t status, enable, detected_codecs; 627 628 atiixp_lock(sc); 629 status = atiixp_rd(sc, ATI_REG_ISR); 630 631 if (status == 0) { 632 atiixp_unlock(sc); 633 return; 634 } 635 636 if ((status & ATI_REG_ISR_IN_STATUS) && sc->rch.channel) { 637 atiixp_unlock(sc); 638 chn_intr(sc->rch.channel); 639 atiixp_lock(sc); 640 } 641 if ((status & ATI_REG_ISR_OUT_STATUS) && sc->pch.channel) { 642 atiixp_unlock(sc); 643 chn_intr(sc->pch.channel); 644 atiixp_lock(sc); 645 } 646 647 #if 0 648 if (status & ATI_REG_ISR_IN_XRUN) { 649 device_printf(sc->dev, 650 "Recieve IN XRUN interrupt\n"); 651 } 652 if (status & ATI_REG_ISR_OUT_XRUN) { 653 device_printf(sc->dev, 654 "Recieve OUT XRUN interrupt\n"); 655 } 656 #endif 657 658 if (status & CODEC_CHECK_BITS) { 659 /* mark missing codecs as not ready */ 660 detected_codecs = status & CODEC_CHECK_BITS; 661 sc->codec_not_ready_bits |= detected_codecs; 662 663 /* disable detected interupt sources */ 664 enable = atiixp_rd(sc, ATI_REG_IER); 665 enable &= ~detected_codecs; 666 atiixp_wr(sc, ATI_REG_IER, enable); 667 } 668 669 /* acknowledge */ 670 atiixp_wr(sc, ATI_REG_ISR, status); 671 atiixp_unlock(sc); 672 } 673 674 static void 675 atiixp_dma_cb(void *p, bus_dma_segment_t *bds, int a, int b) 676 { 677 struct atiixp_info *sc = (struct atiixp_info *)p; 678 sc->sgd_addr = bds->ds_addr; 679 } 680 681 static void 682 atiixp_chip_pre_init(struct atiixp_info *sc) 683 { 684 uint32_t value; 685 686 atiixp_lock(sc); 687 688 /* disable interrupts */ 689 atiixp_disable_interrupts(sc); 690 691 /* clear all DMA enables (preserving rest of settings) */ 692 value = atiixp_rd(sc, ATI_REG_CMD); 693 value &= ~(ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_OUT_DMA_EN | 694 ATI_REG_CMD_SPDF_OUT_EN ); 695 atiixp_wr(sc, ATI_REG_CMD, value); 696 697 /* reset aclink */ 698 atiixp_reset_aclink(sc); 699 700 sc->codec_not_ready_bits = 0; 701 702 /* enable all codecs to interrupt as well as the new frame interrupt */ 703 atiixp_wr(sc, ATI_REG_IER, CODEC_CHECK_BITS); 704 705 atiixp_unlock(sc); 706 } 707 708 static void 709 atiixp_chip_post_init(void *arg) 710 { 711 struct atiixp_info *sc = (struct atiixp_info *)arg; 712 int i, timeout, found; 713 char status[SND_STATUSLEN]; 714 715 atiixp_lock(sc); 716 717 if (sc->delayed_attach.ich_func) { 718 config_intrhook_disestablish(&sc->delayed_attach); 719 sc->delayed_attach.ich_func = NULL; 720 } 721 722 /* wait for the interrupts to happen */ 723 timeout = 100; /* 100.000 usec -> 0.1 sec */ 724 725 while (--timeout) { 726 atiixp_unlock(sc); 727 DELAY(1000); 728 atiixp_lock(sc); 729 if (sc->codec_not_ready_bits) 730 break; 731 } 732 733 atiixp_disable_interrupts(sc); 734 735 if (timeout == 0) { 736 device_printf(sc->dev, 737 "WARNING: timeout during codec detection; " 738 "codecs might be present but haven't interrupted\n"); 739 atiixp_unlock(sc); 740 return; 741 } 742 743 found = 0; 744 745 /* 746 * ATI IXP can have upto 3 codecs, but single codec should be 747 * suffice for now. 748 */ 749 if (!(sc->codec_not_ready_bits & 750 ATI_REG_ISR_CODEC0_NOT_READY)) { 751 /* codec 0 present */ 752 sc->codec_found++; 753 sc->codec_idx = 0; 754 found++; 755 } 756 757 if (!(sc->codec_not_ready_bits & 758 ATI_REG_ISR_CODEC1_NOT_READY)) { 759 /* codec 1 present */ 760 sc->codec_found++; 761 } 762 763 if (!(sc->codec_not_ready_bits & 764 ATI_REG_ISR_CODEC2_NOT_READY)) { 765 /* codec 2 present */ 766 sc->codec_found++; 767 } 768 769 atiixp_unlock(sc); 770 771 if (found == 0) 772 return; 773 774 /* create/init mixer */ 775 sc->codec = AC97_CREATE(sc->dev, sc, atiixp_ac97); 776 if (sc->codec == NULL) 777 goto postinitbad; 778 779 mixer_init(sc->dev, ac97_getmixerclass(), sc->codec); 780 781 if (pcm_register(sc->dev, sc, ATI_IXP_NPCHAN, ATI_IXP_NRCHAN)) 782 goto postinitbad; 783 784 for (i = 0; i < ATI_IXP_NPCHAN; i++) 785 pcm_addchan(sc->dev, PCMDIR_PLAY, &atiixp_chan_class, sc); 786 for (i = 0; i < ATI_IXP_NRCHAN; i++) 787 pcm_addchan(sc->dev, PCMDIR_REC, &atiixp_chan_class, sc); 788 789 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s", 790 rman_get_start(sc->reg), rman_get_start(sc->irq), 791 PCM_KLDSTRING(snd_atiixp)); 792 793 pcm_setstatus(sc->dev, status); 794 795 atiixp_lock(sc); 796 atiixp_enable_interrupts(sc); 797 atiixp_unlock(sc); 798 799 return; 800 801 postinitbad: 802 if (sc->codec) 803 ac97_destroy(sc->codec); 804 if (sc->ih) 805 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 806 if (sc->reg) 807 bus_release_resource(sc->dev, sc->regtype, sc->regid, sc->reg); 808 if (sc->irq) 809 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irqid, sc->irq); 810 if (sc->parent_dmat) 811 bus_dma_tag_destroy(sc->parent_dmat); 812 if (sc->sgd_dmamap) 813 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 814 if (sc->sgd_dmat) 815 bus_dma_tag_destroy(sc->sgd_dmat); 816 if (sc->lock) 817 snd_mtxfree(sc->lock); 818 free(sc, M_DEVBUF); 819 } 820 821 static int 822 atiixp_pci_probe(device_t dev) 823 { 824 int i; 825 uint16_t devid, vendor; 826 827 vendor = pci_get_vendor(dev); 828 devid = pci_get_device(dev); 829 for (i = 0; i < sizeof(atiixp_hw)/sizeof(atiixp_hw[0]); i++) { 830 if (vendor == atiixp_hw[i].vendor && 831 devid == atiixp_hw[i].devid) { 832 device_set_desc(dev, atiixp_hw[i].desc); 833 return BUS_PROBE_DEFAULT; 834 } 835 } 836 837 return ENXIO; 838 } 839 840 static int 841 atiixp_pci_attach(device_t dev) 842 { 843 struct atiixp_info *sc; 844 int i; 845 846 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 847 device_printf(dev, "cannot allocate softc\n"); 848 return ENXIO; 849 } 850 851 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 852 sc->dev = dev; 853 /* 854 * Default DMA segments per playback / recording channel 855 */ 856 sc->dma_segs = ATI_IXP_DMA_CHSEGS; 857 858 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 859 pci_enable_busmaster(dev); 860 861 sc->regid = PCIR_BAR(0); 862 sc->regtype = SYS_RES_MEMORY; 863 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 864 RF_ACTIVE); 865 866 if (!sc->reg) { 867 device_printf(dev, "unable to allocate register space\n"); 868 goto bad; 869 } 870 871 sc->st = rman_get_bustag(sc->reg); 872 sc->sh = rman_get_bushandle(sc->reg); 873 874 sc->bufsz = pcm_getbuffersize(dev, 4096, ATI_IXP_DEFAULT_BUFSZ, 65536); 875 876 sc->irqid = 0; 877 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 878 RF_ACTIVE | RF_SHAREABLE); 879 if (!sc->irq || 880 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, 881 atiixp_intr, sc, &sc->ih)) { 882 device_printf(dev, "unable to map interrupt\n"); 883 goto bad; 884 } 885 886 /* 887 * Let the user choose the best DMA segments. 888 */ 889 if (resource_int_value(device_get_name(dev), 890 device_get_unit(dev), "dma_segs", 891 &i) == 0) { 892 if (i < ATI_IXP_DMA_CHSEGS_MIN) 893 i = ATI_IXP_DMA_CHSEGS_MIN; 894 if (i > ATI_IXP_DMA_CHSEGS_MAX) 895 i = ATI_IXP_DMA_CHSEGS_MAX; 896 /* round the value */ 897 sc->dma_segs = i & ~1; 898 } 899 900 /* 901 * DMA tag for scatter-gather buffers and link pointers 902 */ 903 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 904 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 905 /*highaddr*/BUS_SPACE_MAXADDR, 906 /*filter*/NULL, /*filterarg*/NULL, 907 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 908 /*flags*/0, /*lockfunc*/NULL, 909 /*lockarg*/NULL, &sc->parent_dmat) != 0) { 910 device_printf(dev, "unable to create dma tag\n"); 911 goto bad; 912 } 913 914 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 915 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 916 /*highaddr*/BUS_SPACE_MAXADDR, 917 /*filter*/NULL, /*filterarg*/NULL, 918 /*maxsize*/sc->dma_segs * ATI_IXP_NCHANS * 919 sizeof(struct atiixp_dma_op), 920 /*nsegments*/1, /*maxsegz*/0x3ffff, 921 /*flags*/0, /*lockfunc*/NULL, 922 /*lockarg*/NULL, &sc->sgd_dmat) != 0) { 923 device_printf(dev, "unable to create dma tag\n"); 924 goto bad; 925 } 926 927 if (bus_dmamem_alloc(sc->sgd_dmat, (void **)&sc->sgd_table, 928 BUS_DMA_NOWAIT, &sc->sgd_dmamap) == -1) 929 goto bad; 930 931 if (bus_dmamap_load(sc->sgd_dmat, sc->sgd_dmamap, sc->sgd_table, 932 sc->dma_segs * ATI_IXP_NCHANS * 933 sizeof(struct atiixp_dma_op), 934 atiixp_dma_cb, sc, 0)) 935 goto bad; 936 937 938 atiixp_chip_pre_init(sc); 939 940 sc->delayed_attach.ich_func = atiixp_chip_post_init; 941 sc->delayed_attach.ich_arg = sc; 942 if (cold == 0 || 943 config_intrhook_establish(&sc->delayed_attach) != 0) { 944 sc->delayed_attach.ich_func = NULL; 945 atiixp_chip_post_init(sc); 946 } 947 948 return 0; 949 950 bad: 951 if (sc->codec) 952 ac97_destroy(sc->codec); 953 if (sc->ih) 954 bus_teardown_intr(dev, sc->irq, sc->ih); 955 if (sc->reg) 956 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 957 if (sc->irq) 958 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 959 if (sc->parent_dmat) 960 bus_dma_tag_destroy(sc->parent_dmat); 961 if (sc->sgd_dmamap) 962 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 963 if (sc->sgd_dmat) 964 bus_dma_tag_destroy(sc->sgd_dmat); 965 if (sc->lock) 966 snd_mtxfree(sc->lock); 967 free(sc, M_DEVBUF); 968 969 return ENXIO; 970 } 971 972 static int 973 atiixp_pci_detach(device_t dev) 974 { 975 int r; 976 struct atiixp_info *sc; 977 978 r = pcm_unregister(dev); 979 if (r) 980 return r; 981 982 sc = pcm_getdevinfo(dev); 983 984 atiixp_disable_interrupts(sc); 985 986 bus_teardown_intr(dev, sc->irq, sc->ih); 987 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 988 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 989 bus_dma_tag_destroy(sc->parent_dmat); 990 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 991 bus_dma_tag_destroy(sc->sgd_dmat); 992 snd_mtxfree(sc->lock); 993 free(sc, M_DEVBUF); 994 995 return 0; 996 } 997 998 static int 999 atiixp_pci_suspend(device_t dev) 1000 { 1001 struct atiixp_info *sc = pcm_getdevinfo(dev); 1002 uint32_t value; 1003 1004 /* quickly disable interrupts and save channels active state */ 1005 atiixp_lock(sc); 1006 atiixp_disable_interrupts(sc); 1007 value = atiixp_rd(sc, ATI_REG_CMD); 1008 sc->pch.active = (value & ATI_REG_CMD_SEND_EN) ? 1 : 0; 1009 sc->rch.active = (value & ATI_REG_CMD_RECEIVE_EN) ? 1 : 0; 1010 atiixp_unlock(sc); 1011 1012 /* stop everything */ 1013 if (sc->pch.channel && sc->pch.active) 1014 atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_STOP); 1015 if (sc->rch.channel && sc->rch.active) 1016 atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_STOP); 1017 1018 /* power down aclink and pci bus */ 1019 atiixp_lock(sc); 1020 value = atiixp_rd(sc, ATI_REG_CMD); 1021 value |= ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET; 1022 atiixp_wr(sc, ATI_REG_CMD, ATI_REG_CMD_POWERDOWN); 1023 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1024 atiixp_unlock(sc); 1025 1026 return 0; 1027 } 1028 1029 static int 1030 atiixp_pci_resume(device_t dev) 1031 { 1032 struct atiixp_info *sc = pcm_getdevinfo(dev); 1033 1034 atiixp_lock(sc); 1035 /* power up pci bus */ 1036 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1037 pci_enable_io(dev, SYS_RES_MEMORY); 1038 pci_enable_busmaster(dev); 1039 /* reset / power up aclink */ 1040 atiixp_reset_aclink(sc); 1041 atiixp_unlock(sc); 1042 1043 if (mixer_reinit(dev) == -1) { 1044 device_printf(dev, "unable to reinitialize the mixer\n"); 1045 return ENXIO; 1046 } 1047 1048 /* 1049 * Resume channel activities. Reset channel format regardless 1050 * of its previous state. 1051 */ 1052 if (sc->pch.channel) { 1053 if (sc->pch.fmt) 1054 atiixp_chan_setformat(NULL, &sc->pch, sc->pch.fmt); 1055 if (sc->pch.active) 1056 atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_START); 1057 } 1058 if (sc->rch.channel) { 1059 if (sc->rch.fmt) 1060 atiixp_chan_setformat(NULL, &sc->rch, sc->rch.fmt); 1061 if (sc->rch.active) 1062 atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_START); 1063 } 1064 1065 /* enable interrupts */ 1066 atiixp_lock(sc); 1067 atiixp_enable_interrupts(sc); 1068 atiixp_unlock(sc); 1069 1070 return 0; 1071 } 1072 1073 static device_method_t atiixp_methods[] = { 1074 DEVMETHOD(device_probe, atiixp_pci_probe), 1075 DEVMETHOD(device_attach, atiixp_pci_attach), 1076 DEVMETHOD(device_detach, atiixp_pci_detach), 1077 DEVMETHOD(device_suspend, atiixp_pci_suspend), 1078 DEVMETHOD(device_resume, atiixp_pci_resume), 1079 { 0, 0 } 1080 }; 1081 1082 static driver_t atiixp_driver = { 1083 "pcm", 1084 atiixp_methods, 1085 PCM_SOFTC_SIZE, 1086 }; 1087 1088 DRIVER_MODULE(snd_atiixp, pci, atiixp_driver, pcm_devclass, 0, 0); 1089 MODULE_DEPEND(snd_atiixp, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1090 MODULE_VERSION(snd_atiixp, 1); 1091