1 /*- 2 * Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * FreeBSD pcm driver for ATI IXP 150/200/250/300 AC97 controllers 29 * 30 * Features 31 * * 16bit playback / recording 32 * * 32bit native playback - yay! 33 * * 32bit native recording (seems broken on few hardwares) 34 * 35 * Issues / TODO: 36 * * SPDIF 37 * * Support for more than 2 channels. 38 * * VRA ? VRM ? DRA ? 39 * * 32bit native recording seems broken on few hardwares, most 40 * probably because of incomplete VRA/DRA cleanup. 41 * 42 * 43 * Thanks goes to: 44 * 45 * Shaharil @ SCAN Associates whom relentlessly providing me the 46 * mind blowing Acer Ferrari 4002 WLMi with this ATI IXP hardware. 47 * 48 * Reinoud Zandijk <reinoud@NetBSD.org> (auixp), which this driver is 49 * largely based upon although large part of it has been reworked. His 50 * driver is the primary reference and pretty much well documented. 51 * 52 * Takashi Iwai (ALSA snd-atiixp), for register definitions and some 53 * random ninja hackery. 54 */ 55 56 #include <dev/sound/pcm/sound.h> 57 #include <dev/sound/pcm/ac97.h> 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 #include <sys/sysctl.h> 62 #include <sys/endian.h> 63 64 #include <dev/sound/pci/atiixp.h> 65 66 SND_DECLARE_FILE("$FreeBSD$"); 67 68 69 struct atiixp_dma_op { 70 volatile uint32_t addr; 71 volatile uint16_t status; 72 volatile uint16_t size; 73 volatile uint32_t next; 74 }; 75 76 struct atiixp_info; 77 78 struct atiixp_chinfo { 79 struct snd_dbuf *buffer; 80 struct pcm_channel *channel; 81 struct atiixp_info *parent; 82 struct atiixp_dma_op *sgd_table; 83 bus_addr_t sgd_addr; 84 uint32_t enable_bit, flush_bit, linkptr_bit, dma_dt_cur_bit; 85 uint32_t dma_segs; 86 uint32_t fmt; 87 int caps_32bit, dir, active; 88 }; 89 90 struct atiixp_info { 91 device_t dev; 92 93 bus_space_tag_t st; 94 bus_space_handle_t sh; 95 bus_dma_tag_t parent_dmat; 96 bus_dma_tag_t sgd_dmat; 97 bus_dmamap_t sgd_dmamap; 98 bus_addr_t sgd_addr; 99 100 struct resource *reg, *irq; 101 int regtype, regid, irqid; 102 void *ih; 103 struct ac97_info *codec; 104 105 struct atiixp_chinfo pch; 106 struct atiixp_chinfo rch; 107 struct atiixp_dma_op *sgd_table; 108 struct intr_config_hook delayed_attach; 109 110 uint32_t bufsz; 111 uint32_t codec_not_ready_bits, codec_idx, codec_found; 112 uint32_t dma_segs; 113 int registered_channels; 114 115 struct mtx *lock; 116 }; 117 118 #define atiixp_rd(_sc, _reg) \ 119 bus_space_read_4((_sc)->st, (_sc)->sh, _reg) 120 #define atiixp_wr(_sc, _reg, _val) \ 121 bus_space_write_4((_sc)->st, (_sc)->sh, _reg, _val) 122 123 #define atiixp_lock(_sc) snd_mtxlock((_sc)->lock) 124 #define atiixp_unlock(_sc) snd_mtxunlock((_sc)->lock) 125 #define atiixp_assert(_sc) snd_mtxassert((_sc)->lock) 126 127 static uint32_t atiixp_fmt_32bit[] = { 128 AFMT_STEREO | AFMT_S16_LE, 129 #ifdef AFMT_S32_LE 130 AFMT_STEREO | AFMT_S32_LE, 131 #endif 132 0 133 }; 134 135 static uint32_t atiixp_fmt[] = { 136 AFMT_STEREO | AFMT_S16_LE, 137 0 138 }; 139 140 static struct pcmchan_caps atiixp_caps_32bit = { 141 ATI_IXP_BASE_RATE, 142 ATI_IXP_BASE_RATE, 143 atiixp_fmt_32bit, 0 144 }; 145 146 static struct pcmchan_caps atiixp_caps = { 147 ATI_IXP_BASE_RATE, 148 ATI_IXP_BASE_RATE, 149 atiixp_fmt, 0 150 }; 151 152 static const struct { 153 uint16_t vendor; 154 uint16_t devid; 155 char *desc; 156 } atiixp_hw[] = { 157 { ATI_VENDOR_ID, ATI_IXP_200_ID, "ATI IXP 200" }, 158 { ATI_VENDOR_ID, ATI_IXP_300_ID, "ATI IXP 300" }, 159 { ATI_VENDOR_ID, ATI_IXP_400_ID, "ATI IXP 400" }, 160 }; 161 162 static void atiixp_enable_interrupts(struct atiixp_info *); 163 static void atiixp_disable_interrupts(struct atiixp_info *); 164 static void atiixp_reset_aclink(struct atiixp_info *); 165 static void atiixp_flush_dma(struct atiixp_info *, struct atiixp_chinfo *); 166 static void atiixp_enable_dma(struct atiixp_info *, struct atiixp_chinfo *); 167 static void atiixp_disable_dma(struct atiixp_info *, struct atiixp_chinfo *); 168 169 static int atiixp_waitready_codec(struct atiixp_info *); 170 static int atiixp_rdcd(kobj_t, void *, int); 171 static int atiixp_wrcd(kobj_t, void *, int, uint32_t); 172 173 static void *atiixp_chan_init(kobj_t, void *, struct snd_dbuf *, 174 struct pcm_channel *, int); 175 static int atiixp_chan_setformat(kobj_t, void *, uint32_t); 176 static int atiixp_chan_setspeed(kobj_t, void *, uint32_t); 177 static int atiixp_chan_setblocksize(kobj_t, void *, uint32_t); 178 static void atiixp_buildsgdt(struct atiixp_chinfo *); 179 static int atiixp_chan_trigger(kobj_t, void *, int); 180 static int atiixp_chan_getptr(kobj_t, void *); 181 static struct pcmchan_caps *atiixp_chan_getcaps(kobj_t, void *); 182 183 static void atiixp_intr(void *); 184 static void atiixp_dma_cb(void *, bus_dma_segment_t *, int, int); 185 static void atiixp_chip_pre_init(struct atiixp_info *); 186 static void atiixp_chip_post_init(void *); 187 static int atiixp_pci_probe(device_t); 188 static int atiixp_pci_attach(device_t); 189 static int atiixp_pci_detach(device_t); 190 static int atiixp_pci_suspend(device_t); 191 static int atiixp_pci_resume(device_t); 192 193 /* 194 * ATI IXP helper functions 195 */ 196 static void 197 atiixp_enable_interrupts(struct atiixp_info *sc) 198 { 199 uint32_t value; 200 201 /* clear all pending */ 202 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 203 204 /* enable all relevant interrupt sources we can handle */ 205 value = atiixp_rd(sc, ATI_REG_IER); 206 207 value |= ATI_REG_IER_IO_STATUS_EN; 208 209 /* 210 * Disable / ignore internal xrun/spdf interrupt flags 211 * since it doesn't interest us (for now). 212 */ 213 #if 0 214 value |= ATI_REG_IER_IN_XRUN_EN; 215 value |= ATI_REG_IER_OUT_XRUN_EN; 216 217 value |= ATI_REG_IER_SPDF_XRUN_EN; 218 value |= ATI_REG_IER_SPDF_STATUS_EN; 219 #endif 220 221 atiixp_wr(sc, ATI_REG_IER, value); 222 } 223 224 static void 225 atiixp_disable_interrupts(struct atiixp_info *sc) 226 { 227 /* disable all interrupt sources */ 228 atiixp_wr(sc, ATI_REG_IER, 0); 229 230 /* clear all pending */ 231 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 232 } 233 234 static void 235 atiixp_reset_aclink(struct atiixp_info *sc) 236 { 237 uint32_t value, timeout; 238 239 /* if power is down, power it up */ 240 value = atiixp_rd(sc, ATI_REG_CMD); 241 if (value & ATI_REG_CMD_POWERDOWN) { 242 /* explicitly enable power */ 243 value &= ~ATI_REG_CMD_POWERDOWN; 244 atiixp_wr(sc, ATI_REG_CMD, value); 245 246 /* have to wait at least 10 usec for it to initialise */ 247 DELAY(20); 248 }; 249 250 /* perform a soft reset */ 251 value = atiixp_rd(sc, ATI_REG_CMD); 252 value |= ATI_REG_CMD_AC_SOFT_RESET; 253 atiixp_wr(sc, ATI_REG_CMD, value); 254 255 /* need to read the CMD reg and wait aprox. 10 usec to init */ 256 value = atiixp_rd(sc, ATI_REG_CMD); 257 DELAY(20); 258 259 /* clear soft reset flag again */ 260 value = atiixp_rd(sc, ATI_REG_CMD); 261 value &= ~ATI_REG_CMD_AC_SOFT_RESET; 262 atiixp_wr(sc, ATI_REG_CMD, value); 263 264 /* check if the ac-link is working; reset device otherwise */ 265 timeout = 10; 266 value = atiixp_rd(sc, ATI_REG_CMD); 267 while (!(value & ATI_REG_CMD_ACLINK_ACTIVE) 268 && --timeout) { 269 #if 0 270 device_printf(sc->dev, "not up; resetting aclink hardware\n"); 271 #endif 272 273 /* dip aclink reset but keep the acsync */ 274 value &= ~ATI_REG_CMD_AC_RESET; 275 value |= ATI_REG_CMD_AC_SYNC; 276 atiixp_wr(sc, ATI_REG_CMD, value); 277 278 /* need to read CMD again and wait again (clocking in issue?) */ 279 value = atiixp_rd(sc, ATI_REG_CMD); 280 DELAY(20); 281 282 /* assert aclink reset again */ 283 value = atiixp_rd(sc, ATI_REG_CMD); 284 value |= ATI_REG_CMD_AC_RESET; 285 atiixp_wr(sc, ATI_REG_CMD, value); 286 287 /* check if its active now */ 288 value = atiixp_rd(sc, ATI_REG_CMD); 289 }; 290 291 if (timeout == 0) 292 device_printf(sc->dev, "giving up aclink reset\n"); 293 #if 0 294 if (timeout != 10) 295 device_printf(sc->dev, "aclink hardware reset successful\n"); 296 #endif 297 298 /* assert reset and sync for safety */ 299 value = atiixp_rd(sc, ATI_REG_CMD); 300 value |= ATI_REG_CMD_AC_SYNC | ATI_REG_CMD_AC_RESET; 301 atiixp_wr(sc, ATI_REG_CMD, value); 302 } 303 304 static void 305 atiixp_flush_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 306 { 307 atiixp_wr(sc, ATI_REG_FIFO_FLUSH, ch->flush_bit); 308 } 309 310 static void 311 atiixp_enable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 312 { 313 uint32_t value; 314 315 value = atiixp_rd(sc, ATI_REG_CMD); 316 if (!(value & ch->enable_bit)) { 317 value |= ch->enable_bit; 318 atiixp_wr(sc, ATI_REG_CMD, value); 319 } 320 } 321 322 static void 323 atiixp_disable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 324 { 325 uint32_t value; 326 327 value = atiixp_rd(sc, ATI_REG_CMD); 328 if (value & ch->enable_bit) { 329 value &= ~ch->enable_bit; 330 atiixp_wr(sc, ATI_REG_CMD, value); 331 } 332 } 333 334 /* 335 * AC97 interface 336 */ 337 static int 338 atiixp_waitready_codec(struct atiixp_info *sc) 339 { 340 int timeout = 500; 341 342 do { 343 if ((atiixp_rd(sc, ATI_REG_PHYS_OUT_ADDR) & 344 ATI_REG_PHYS_OUT_ADDR_EN) == 0) 345 return 0; 346 DELAY(1); 347 } while (timeout--); 348 349 return -1; 350 } 351 352 static int 353 atiixp_rdcd(kobj_t obj, void *devinfo, int reg) 354 { 355 struct atiixp_info *sc = devinfo; 356 uint32_t data; 357 int timeout; 358 359 if (atiixp_waitready_codec(sc)) 360 return -1; 361 362 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 363 ATI_REG_PHYS_OUT_ADDR_EN | 364 ATI_REG_PHYS_OUT_RW | sc->codec_idx; 365 366 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 367 368 if (atiixp_waitready_codec(sc)) 369 return -1; 370 371 timeout = 500; 372 do { 373 data = atiixp_rd(sc, ATI_REG_PHYS_IN_ADDR); 374 if (data & ATI_REG_PHYS_IN_READ_FLAG) 375 return data >> ATI_REG_PHYS_IN_DATA_SHIFT; 376 DELAY(1); 377 } while (timeout--); 378 379 if (reg < 0x7c) 380 device_printf(sc->dev, "codec read timeout! (reg 0x%x)\n", reg); 381 382 return -1; 383 } 384 385 static int 386 atiixp_wrcd(kobj_t obj, void *devinfo, int reg, uint32_t data) 387 { 388 struct atiixp_info *sc = devinfo; 389 390 if (atiixp_waitready_codec(sc)) 391 return -1; 392 393 data = (data << ATI_REG_PHYS_OUT_DATA_SHIFT) | 394 (((uint32_t)reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 395 ATI_REG_PHYS_OUT_ADDR_EN | sc->codec_idx; 396 397 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 398 399 return 0; 400 } 401 402 static kobj_method_t atiixp_ac97_methods[] = { 403 KOBJMETHOD(ac97_read, atiixp_rdcd), 404 KOBJMETHOD(ac97_write, atiixp_wrcd), 405 { 0, 0 } 406 }; 407 AC97_DECLARE(atiixp_ac97); 408 409 /* 410 * Playback / Record channel interface 411 */ 412 static void * 413 atiixp_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 414 struct pcm_channel *c, int dir) 415 { 416 struct atiixp_info *sc = devinfo; 417 struct atiixp_chinfo *ch; 418 int num; 419 420 atiixp_lock(sc); 421 422 if (dir == PCMDIR_PLAY) { 423 ch = &sc->pch; 424 ch->linkptr_bit = ATI_REG_OUT_DMA_LINKPTR; 425 ch->enable_bit = ATI_REG_CMD_OUT_DMA_EN | ATI_REG_CMD_SEND_EN; 426 ch->flush_bit = ATI_REG_FIFO_OUT_FLUSH; 427 ch->dma_dt_cur_bit = ATI_REG_OUT_DMA_DT_CUR; 428 /* Native 32bit playback working properly */ 429 ch->caps_32bit = 1; 430 } else { 431 ch = &sc->rch; 432 ch->linkptr_bit = ATI_REG_IN_DMA_LINKPTR; 433 ch->enable_bit = ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_RECEIVE_EN; 434 ch->flush_bit = ATI_REG_FIFO_IN_FLUSH; 435 ch->dma_dt_cur_bit = ATI_REG_IN_DMA_DT_CUR; 436 /* XXX Native 32bit recording appear to be broken */ 437 ch->caps_32bit = 1; 438 } 439 440 ch->buffer = b; 441 ch->parent = sc; 442 ch->channel = c; 443 ch->dir = dir; 444 ch->dma_segs = sc->dma_segs; 445 446 atiixp_unlock(sc); 447 448 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1) 449 return NULL; 450 451 atiixp_lock(sc); 452 num = sc->registered_channels++; 453 ch->sgd_table = &sc->sgd_table[num * ch->dma_segs]; 454 ch->sgd_addr = sc->sgd_addr + 455 (num * ch->dma_segs * sizeof(struct atiixp_dma_op)); 456 atiixp_disable_dma(sc, ch); 457 atiixp_unlock(sc); 458 459 return ch; 460 } 461 462 static int 463 atiixp_chan_setformat(kobj_t obj, void *data, uint32_t format) 464 { 465 struct atiixp_chinfo *ch = data; 466 struct atiixp_info *sc = ch->parent; 467 uint32_t value; 468 469 atiixp_lock(sc); 470 if (ch->dir == PCMDIR_REC) { 471 value = atiixp_rd(sc, ATI_REG_CMD); 472 value &= ~ATI_REG_CMD_INTERLEAVE_IN; 473 if ((format & AFMT_32BIT) == 0) 474 value |= ATI_REG_CMD_INTERLEAVE_IN; 475 atiixp_wr(sc, ATI_REG_CMD, value); 476 } else { 477 value = atiixp_rd(sc, ATI_REG_OUT_DMA_SLOT); 478 value &= ~ATI_REG_OUT_DMA_SLOT_MASK; 479 /* We do not have support for more than 2 channels, _yet_. */ 480 value |= ATI_REG_OUT_DMA_SLOT_BIT(3) | 481 ATI_REG_OUT_DMA_SLOT_BIT(4); 482 value |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 483 atiixp_wr(sc, ATI_REG_OUT_DMA_SLOT, value); 484 value = atiixp_rd(sc, ATI_REG_CMD); 485 value &= ~ATI_REG_CMD_INTERLEAVE_OUT; 486 if ((format & AFMT_32BIT) == 0) 487 value |= ATI_REG_CMD_INTERLEAVE_OUT; 488 atiixp_wr(sc, ATI_REG_CMD, value); 489 value = atiixp_rd(sc, ATI_REG_6CH_REORDER); 490 value &= ~ATI_REG_6CH_REORDER_EN; 491 atiixp_wr(sc, ATI_REG_6CH_REORDER, value); 492 } 493 ch->fmt = format; 494 atiixp_unlock(sc); 495 496 return 0; 497 } 498 499 static int 500 atiixp_chan_setspeed(kobj_t obj, void *data, uint32_t spd) 501 { 502 /* XXX We're supposed to do VRA/DRA processing right here */ 503 return ATI_IXP_BASE_RATE; 504 } 505 506 static int 507 atiixp_chan_setblocksize(kobj_t obj, void *data, uint32_t blksz) 508 { 509 struct atiixp_chinfo *ch = data; 510 struct atiixp_info *sc = ch->parent; 511 512 if (blksz > (sc->bufsz / ch->dma_segs)) 513 blksz = sc->bufsz / ch->dma_segs; 514 515 sndbuf_resize(ch->buffer, ch->dma_segs, blksz); 516 517 return sndbuf_getblksz(ch->buffer); 518 } 519 520 static void 521 atiixp_buildsgdt(struct atiixp_chinfo *ch) 522 { 523 uint32_t addr, blksz; 524 int i; 525 526 addr = sndbuf_getbufaddr(ch->buffer); 527 blksz = sndbuf_getblksz(ch->buffer); 528 529 for (i = 0; i < ch->dma_segs; i++) { 530 ch->sgd_table[i].addr = htole32(addr + (i * blksz)); 531 ch->sgd_table[i].status = htole16(0); 532 ch->sgd_table[i].size = htole16(blksz >> 2); 533 ch->sgd_table[i].next = htole32((uint32_t)ch->sgd_addr + 534 (((i + 1) % ch->dma_segs) * 535 sizeof(struct atiixp_dma_op))); 536 } 537 } 538 539 static int 540 atiixp_chan_trigger(kobj_t obj, void *data, int go) 541 { 542 struct atiixp_chinfo *ch = data; 543 struct atiixp_info *sc = ch->parent; 544 uint32_t value; 545 546 atiixp_lock(sc); 547 548 switch (go) { 549 case PCMTRIG_START: 550 atiixp_flush_dma(sc, ch); 551 atiixp_buildsgdt(ch); 552 atiixp_wr(sc, ch->linkptr_bit, 0); 553 atiixp_enable_dma(sc, ch); 554 atiixp_wr(sc, ch->linkptr_bit, 555 (uint32_t)ch->sgd_addr | ATI_REG_LINKPTR_EN); 556 break; 557 case PCMTRIG_STOP: 558 case PCMTRIG_ABORT: 559 atiixp_disable_dma(sc, ch); 560 atiixp_flush_dma(sc, ch); 561 break; 562 default: 563 atiixp_unlock(sc); 564 return 0; 565 break; 566 } 567 568 /* Update bus busy status */ 569 value = atiixp_rd(sc, ATI_REG_IER); 570 if (atiixp_rd(sc, ATI_REG_CMD) & ( 571 ATI_REG_CMD_SEND_EN | ATI_REG_CMD_RECEIVE_EN | 572 ATI_REG_CMD_SPDF_OUT_EN)) 573 value |= ATI_REG_IER_SET_BUS_BUSY; 574 else 575 value &= ~ATI_REG_IER_SET_BUS_BUSY; 576 atiixp_wr(sc, ATI_REG_IER, value); 577 578 atiixp_unlock(sc); 579 580 return 0; 581 } 582 583 static int 584 atiixp_chan_getptr(kobj_t obj, void *data) 585 { 586 struct atiixp_chinfo *ch = data; 587 struct atiixp_info *sc = ch->parent; 588 uint32_t addr, align, retry, sz; 589 volatile uint32_t ptr; 590 591 addr = sndbuf_getbufaddr(ch->buffer); 592 align = (ch->fmt & AFMT_32BIT) ? 7 : 3; 593 retry = 100; 594 sz = sndbuf_getblksz(ch->buffer) * ch->dma_segs; 595 596 atiixp_lock(sc); 597 do { 598 ptr = atiixp_rd(sc, ch->dma_dt_cur_bit); 599 if (ptr < addr) 600 continue; 601 ptr -= addr; 602 if (ptr < sz && !(ptr & align)) 603 break; 604 } while (--retry); 605 atiixp_unlock(sc); 606 607 #if 0 608 if (retry != 100) { 609 device_printf(sc->dev, 610 "%saligned hwptr: dir=PCMDIR_%s ptr=%u fmt=0x%08x retry=%d\n", 611 (ptr & align) ? "un" : "", 612 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", ptr, 613 ch->fmt, 100 - retry); 614 } 615 #endif 616 617 return (retry > 0) ? ptr : 0; 618 } 619 620 static struct pcmchan_caps * 621 atiixp_chan_getcaps(kobj_t obj, void *data) 622 { 623 struct atiixp_chinfo *ch = data; 624 625 if (ch->caps_32bit) 626 return &atiixp_caps_32bit; 627 return &atiixp_caps; 628 } 629 630 static kobj_method_t atiixp_chan_methods[] = { 631 KOBJMETHOD(channel_init, atiixp_chan_init), 632 KOBJMETHOD(channel_setformat, atiixp_chan_setformat), 633 KOBJMETHOD(channel_setspeed, atiixp_chan_setspeed), 634 KOBJMETHOD(channel_setblocksize, atiixp_chan_setblocksize), 635 KOBJMETHOD(channel_trigger, atiixp_chan_trigger), 636 KOBJMETHOD(channel_getptr, atiixp_chan_getptr), 637 KOBJMETHOD(channel_getcaps, atiixp_chan_getcaps), 638 { 0, 0 } 639 }; 640 CHANNEL_DECLARE(atiixp_chan); 641 642 /* 643 * PCI driver interface 644 */ 645 static void 646 atiixp_intr(void *p) 647 { 648 struct atiixp_info *sc = p; 649 uint32_t status, enable, detected_codecs; 650 651 atiixp_lock(sc); 652 status = atiixp_rd(sc, ATI_REG_ISR); 653 654 if (status == 0) { 655 atiixp_unlock(sc); 656 return; 657 } 658 659 if ((status & ATI_REG_ISR_IN_STATUS) && sc->rch.channel) { 660 atiixp_unlock(sc); 661 chn_intr(sc->rch.channel); 662 atiixp_lock(sc); 663 } 664 if ((status & ATI_REG_ISR_OUT_STATUS) && sc->pch.channel) { 665 atiixp_unlock(sc); 666 chn_intr(sc->pch.channel); 667 atiixp_lock(sc); 668 } 669 670 #if 0 671 if (status & ATI_REG_ISR_IN_XRUN) { 672 device_printf(sc->dev, 673 "Recieve IN XRUN interrupt\n"); 674 } 675 if (status & ATI_REG_ISR_OUT_XRUN) { 676 device_printf(sc->dev, 677 "Recieve OUT XRUN interrupt\n"); 678 } 679 #endif 680 681 if (status & CODEC_CHECK_BITS) { 682 /* mark missing codecs as not ready */ 683 detected_codecs = status & CODEC_CHECK_BITS; 684 sc->codec_not_ready_bits |= detected_codecs; 685 686 /* disable detected interupt sources */ 687 enable = atiixp_rd(sc, ATI_REG_IER); 688 enable &= ~detected_codecs; 689 atiixp_wr(sc, ATI_REG_IER, enable); 690 } 691 692 /* acknowledge */ 693 atiixp_wr(sc, ATI_REG_ISR, status); 694 atiixp_unlock(sc); 695 } 696 697 static void 698 atiixp_dma_cb(void *p, bus_dma_segment_t *bds, int a, int b) 699 { 700 struct atiixp_info *sc = (struct atiixp_info *)p; 701 sc->sgd_addr = bds->ds_addr; 702 } 703 704 static void 705 atiixp_chip_pre_init(struct atiixp_info *sc) 706 { 707 uint32_t value; 708 709 atiixp_lock(sc); 710 711 /* disable interrupts */ 712 atiixp_disable_interrupts(sc); 713 714 /* clear all DMA enables (preserving rest of settings) */ 715 value = atiixp_rd(sc, ATI_REG_CMD); 716 value &= ~(ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_OUT_DMA_EN | 717 ATI_REG_CMD_SPDF_OUT_EN ); 718 atiixp_wr(sc, ATI_REG_CMD, value); 719 720 /* reset aclink */ 721 atiixp_reset_aclink(sc); 722 723 sc->codec_not_ready_bits = 0; 724 725 /* enable all codecs to interrupt as well as the new frame interrupt */ 726 atiixp_wr(sc, ATI_REG_IER, CODEC_CHECK_BITS); 727 728 atiixp_unlock(sc); 729 } 730 731 static void 732 atiixp_chip_post_init(void *arg) 733 { 734 struct atiixp_info *sc = (struct atiixp_info *)arg; 735 uint32_t subdev; 736 int i, timeout, found; 737 char status[SND_STATUSLEN]; 738 739 atiixp_lock(sc); 740 741 if (sc->delayed_attach.ich_func) { 742 config_intrhook_disestablish(&sc->delayed_attach); 743 sc->delayed_attach.ich_func = NULL; 744 } 745 746 /* wait for the interrupts to happen */ 747 timeout = 100; /* 100.000 usec -> 0.1 sec */ 748 749 while (--timeout) { 750 atiixp_unlock(sc); 751 DELAY(1000); 752 atiixp_lock(sc); 753 if (sc->codec_not_ready_bits) 754 break; 755 } 756 757 atiixp_disable_interrupts(sc); 758 759 if (timeout == 0) { 760 device_printf(sc->dev, 761 "WARNING: timeout during codec detection; " 762 "codecs might be present but haven't interrupted\n"); 763 atiixp_unlock(sc); 764 return; 765 } 766 767 found = 0; 768 769 /* 770 * ATI IXP can have upto 3 codecs, but single codec should be 771 * suffice for now. 772 */ 773 if (!(sc->codec_not_ready_bits & 774 ATI_REG_ISR_CODEC0_NOT_READY)) { 775 /* codec 0 present */ 776 sc->codec_found++; 777 sc->codec_idx = 0; 778 found++; 779 } 780 781 if (!(sc->codec_not_ready_bits & 782 ATI_REG_ISR_CODEC1_NOT_READY)) { 783 /* codec 1 present */ 784 sc->codec_found++; 785 } 786 787 if (!(sc->codec_not_ready_bits & 788 ATI_REG_ISR_CODEC2_NOT_READY)) { 789 /* codec 2 present */ 790 sc->codec_found++; 791 } 792 793 atiixp_unlock(sc); 794 795 if (found == 0) 796 return; 797 798 /* create/init mixer */ 799 sc->codec = AC97_CREATE(sc->dev, sc, atiixp_ac97); 800 if (sc->codec == NULL) 801 goto postinitbad; 802 803 subdev = (pci_get_subdevice(sc->dev) << 16) | pci_get_subvendor(sc->dev); 804 switch (subdev) { 805 case 0x2043161f: /* Maxselect x710s - http://maxselect.ru/ */ 806 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 807 break; 808 default: 809 break; 810 } 811 812 mixer_init(sc->dev, ac97_getmixerclass(), sc->codec); 813 814 if (pcm_register(sc->dev, sc, ATI_IXP_NPCHAN, ATI_IXP_NRCHAN)) 815 goto postinitbad; 816 817 for (i = 0; i < ATI_IXP_NPCHAN; i++) 818 pcm_addchan(sc->dev, PCMDIR_PLAY, &atiixp_chan_class, sc); 819 for (i = 0; i < ATI_IXP_NRCHAN; i++) 820 pcm_addchan(sc->dev, PCMDIR_REC, &atiixp_chan_class, sc); 821 822 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s", 823 rman_get_start(sc->reg), rman_get_start(sc->irq), 824 PCM_KLDSTRING(snd_atiixp)); 825 826 pcm_setstatus(sc->dev, status); 827 828 atiixp_lock(sc); 829 atiixp_enable_interrupts(sc); 830 atiixp_unlock(sc); 831 832 return; 833 834 postinitbad: 835 if (sc->codec) 836 ac97_destroy(sc->codec); 837 if (sc->ih) 838 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 839 if (sc->reg) 840 bus_release_resource(sc->dev, sc->regtype, sc->regid, sc->reg); 841 if (sc->irq) 842 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irqid, sc->irq); 843 if (sc->parent_dmat) 844 bus_dma_tag_destroy(sc->parent_dmat); 845 if (sc->sgd_dmamap) 846 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 847 if (sc->sgd_dmat) 848 bus_dma_tag_destroy(sc->sgd_dmat); 849 if (sc->lock) 850 snd_mtxfree(sc->lock); 851 free(sc, M_DEVBUF); 852 } 853 854 static int 855 atiixp_pci_probe(device_t dev) 856 { 857 int i; 858 uint16_t devid, vendor; 859 860 vendor = pci_get_vendor(dev); 861 devid = pci_get_device(dev); 862 for (i = 0; i < sizeof(atiixp_hw)/sizeof(atiixp_hw[0]); i++) { 863 if (vendor == atiixp_hw[i].vendor && 864 devid == atiixp_hw[i].devid) { 865 device_set_desc(dev, atiixp_hw[i].desc); 866 return BUS_PROBE_DEFAULT; 867 } 868 } 869 870 return ENXIO; 871 } 872 873 static int 874 atiixp_pci_attach(device_t dev) 875 { 876 struct atiixp_info *sc; 877 int i; 878 879 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 880 device_printf(dev, "cannot allocate softc\n"); 881 return ENXIO; 882 } 883 884 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 885 sc->dev = dev; 886 /* 887 * Default DMA segments per playback / recording channel 888 */ 889 sc->dma_segs = ATI_IXP_DMA_CHSEGS; 890 891 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 892 pci_enable_busmaster(dev); 893 894 sc->regid = PCIR_BAR(0); 895 sc->regtype = SYS_RES_MEMORY; 896 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 897 RF_ACTIVE); 898 899 if (!sc->reg) { 900 device_printf(dev, "unable to allocate register space\n"); 901 goto bad; 902 } 903 904 sc->st = rman_get_bustag(sc->reg); 905 sc->sh = rman_get_bushandle(sc->reg); 906 907 sc->bufsz = pcm_getbuffersize(dev, 4096, ATI_IXP_DEFAULT_BUFSZ, 65536); 908 909 sc->irqid = 0; 910 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 911 RF_ACTIVE | RF_SHAREABLE); 912 if (!sc->irq || 913 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, 914 atiixp_intr, sc, &sc->ih)) { 915 device_printf(dev, "unable to map interrupt\n"); 916 goto bad; 917 } 918 919 /* 920 * Let the user choose the best DMA segments. 921 */ 922 if (resource_int_value(device_get_name(dev), 923 device_get_unit(dev), "dma_segs", 924 &i) == 0) { 925 if (i < ATI_IXP_DMA_CHSEGS_MIN) 926 i = ATI_IXP_DMA_CHSEGS_MIN; 927 if (i > ATI_IXP_DMA_CHSEGS_MAX) 928 i = ATI_IXP_DMA_CHSEGS_MAX; 929 sc->dma_segs = i; 930 } 931 932 /* 933 * round the value to the nearest ^2 934 */ 935 i = 0; 936 while (sc->dma_segs >> i) 937 i++; 938 sc->dma_segs = 1 << (i - 1); 939 if (sc->dma_segs < ATI_IXP_DMA_CHSEGS_MIN) 940 sc->dma_segs = ATI_IXP_DMA_CHSEGS_MIN; 941 else if (sc->dma_segs > ATI_IXP_DMA_CHSEGS_MAX) 942 sc->dma_segs = ATI_IXP_DMA_CHSEGS_MAX; 943 944 /* 945 * DMA tag for scatter-gather buffers and link pointers 946 */ 947 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/sc->bufsz, /*boundary*/0, 948 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 949 /*highaddr*/BUS_SPACE_MAXADDR, 950 /*filter*/NULL, /*filterarg*/NULL, 951 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 952 /*flags*/0, /*lockfunc*/NULL, 953 /*lockarg*/NULL, &sc->parent_dmat) != 0) { 954 device_printf(dev, "unable to create dma tag\n"); 955 goto bad; 956 } 957 958 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 959 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 960 /*highaddr*/BUS_SPACE_MAXADDR, 961 /*filter*/NULL, /*filterarg*/NULL, 962 /*maxsize*/sc->dma_segs * ATI_IXP_NCHANS * 963 sizeof(struct atiixp_dma_op), 964 /*nsegments*/1, /*maxsegz*/0x3ffff, 965 /*flags*/0, /*lockfunc*/NULL, 966 /*lockarg*/NULL, &sc->sgd_dmat) != 0) { 967 device_printf(dev, "unable to create dma tag\n"); 968 goto bad; 969 } 970 971 if (bus_dmamem_alloc(sc->sgd_dmat, (void **)&sc->sgd_table, 972 BUS_DMA_NOWAIT, &sc->sgd_dmamap) == -1) 973 goto bad; 974 975 if (bus_dmamap_load(sc->sgd_dmat, sc->sgd_dmamap, sc->sgd_table, 976 sc->dma_segs * ATI_IXP_NCHANS * 977 sizeof(struct atiixp_dma_op), 978 atiixp_dma_cb, sc, 0)) 979 goto bad; 980 981 982 atiixp_chip_pre_init(sc); 983 984 sc->delayed_attach.ich_func = atiixp_chip_post_init; 985 sc->delayed_attach.ich_arg = sc; 986 if (cold == 0 || 987 config_intrhook_establish(&sc->delayed_attach) != 0) { 988 sc->delayed_attach.ich_func = NULL; 989 atiixp_chip_post_init(sc); 990 } 991 992 return 0; 993 994 bad: 995 if (sc->codec) 996 ac97_destroy(sc->codec); 997 if (sc->ih) 998 bus_teardown_intr(dev, sc->irq, sc->ih); 999 if (sc->reg) 1000 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1001 if (sc->irq) 1002 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1003 if (sc->parent_dmat) 1004 bus_dma_tag_destroy(sc->parent_dmat); 1005 if (sc->sgd_dmamap) 1006 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 1007 if (sc->sgd_dmat) 1008 bus_dma_tag_destroy(sc->sgd_dmat); 1009 if (sc->lock) 1010 snd_mtxfree(sc->lock); 1011 free(sc, M_DEVBUF); 1012 1013 return ENXIO; 1014 } 1015 1016 static int 1017 atiixp_pci_detach(device_t dev) 1018 { 1019 int r; 1020 struct atiixp_info *sc; 1021 1022 r = pcm_unregister(dev); 1023 if (r) 1024 return r; 1025 1026 sc = pcm_getdevinfo(dev); 1027 1028 atiixp_disable_interrupts(sc); 1029 1030 bus_teardown_intr(dev, sc->irq, sc->ih); 1031 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 1032 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1033 bus_dma_tag_destroy(sc->parent_dmat); 1034 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 1035 bus_dma_tag_destroy(sc->sgd_dmat); 1036 snd_mtxfree(sc->lock); 1037 free(sc, M_DEVBUF); 1038 1039 return 0; 1040 } 1041 1042 static int 1043 atiixp_pci_suspend(device_t dev) 1044 { 1045 struct atiixp_info *sc = pcm_getdevinfo(dev); 1046 uint32_t value; 1047 1048 /* quickly disable interrupts and save channels active state */ 1049 atiixp_lock(sc); 1050 atiixp_disable_interrupts(sc); 1051 value = atiixp_rd(sc, ATI_REG_CMD); 1052 sc->pch.active = (value & ATI_REG_CMD_SEND_EN) ? 1 : 0; 1053 sc->rch.active = (value & ATI_REG_CMD_RECEIVE_EN) ? 1 : 0; 1054 atiixp_unlock(sc); 1055 1056 /* stop everything */ 1057 if (sc->pch.channel && sc->pch.active) 1058 atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_STOP); 1059 if (sc->rch.channel && sc->rch.active) 1060 atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_STOP); 1061 1062 /* power down aclink and pci bus */ 1063 atiixp_lock(sc); 1064 value = atiixp_rd(sc, ATI_REG_CMD); 1065 value |= ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET; 1066 atiixp_wr(sc, ATI_REG_CMD, ATI_REG_CMD_POWERDOWN); 1067 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1068 atiixp_unlock(sc); 1069 1070 return 0; 1071 } 1072 1073 static int 1074 atiixp_pci_resume(device_t dev) 1075 { 1076 struct atiixp_info *sc = pcm_getdevinfo(dev); 1077 1078 atiixp_lock(sc); 1079 /* power up pci bus */ 1080 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1081 pci_enable_io(dev, SYS_RES_MEMORY); 1082 pci_enable_busmaster(dev); 1083 /* reset / power up aclink */ 1084 atiixp_reset_aclink(sc); 1085 atiixp_unlock(sc); 1086 1087 if (mixer_reinit(dev) == -1) { 1088 device_printf(dev, "unable to reinitialize the mixer\n"); 1089 return ENXIO; 1090 } 1091 1092 /* 1093 * Resume channel activities. Reset channel format regardless 1094 * of its previous state. 1095 */ 1096 if (sc->pch.channel) { 1097 if (sc->pch.fmt) 1098 atiixp_chan_setformat(NULL, &sc->pch, sc->pch.fmt); 1099 if (sc->pch.active) 1100 atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_START); 1101 } 1102 if (sc->rch.channel) { 1103 if (sc->rch.fmt) 1104 atiixp_chan_setformat(NULL, &sc->rch, sc->rch.fmt); 1105 if (sc->rch.active) 1106 atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_START); 1107 } 1108 1109 /* enable interrupts */ 1110 atiixp_lock(sc); 1111 atiixp_enable_interrupts(sc); 1112 atiixp_unlock(sc); 1113 1114 return 0; 1115 } 1116 1117 static device_method_t atiixp_methods[] = { 1118 DEVMETHOD(device_probe, atiixp_pci_probe), 1119 DEVMETHOD(device_attach, atiixp_pci_attach), 1120 DEVMETHOD(device_detach, atiixp_pci_detach), 1121 DEVMETHOD(device_suspend, atiixp_pci_suspend), 1122 DEVMETHOD(device_resume, atiixp_pci_resume), 1123 { 0, 0 } 1124 }; 1125 1126 static driver_t atiixp_driver = { 1127 "pcm", 1128 atiixp_methods, 1129 PCM_SOFTC_SIZE, 1130 }; 1131 1132 DRIVER_MODULE(snd_atiixp, pci, atiixp_driver, pcm_devclass, 0, 0); 1133 MODULE_DEPEND(snd_atiixp, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1134 MODULE_VERSION(snd_atiixp, 1); 1135