1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * FreeBSD pcm driver for ATI IXP 150/200/250/300 AC97 controllers 31 * 32 * Features 33 * * 16bit playback / recording 34 * * 32bit native playback - yay! 35 * * 32bit native recording (seems broken on few hardwares) 36 * 37 * Issues / TODO: 38 * * SPDIF 39 * * Support for more than 2 channels. 40 * * VRA ? VRM ? DRA ? 41 * * 32bit native recording seems broken on few hardwares, most 42 * probably because of incomplete VRA/DRA cleanup. 43 * 44 * 45 * Thanks goes to: 46 * 47 * Shaharil @ SCAN Associates whom relentlessly providing me the 48 * mind blowing Acer Ferrari 4002 WLMi with this ATI IXP hardware. 49 * 50 * Reinoud Zandijk <reinoud@NetBSD.org> (auixp), which this driver is 51 * largely based upon although large part of it has been reworked. His 52 * driver is the primary reference and pretty much well documented. 53 * 54 * Takashi Iwai (ALSA snd-atiixp), for register definitions and some 55 * random ninja hackery. 56 */ 57 58 #ifdef HAVE_KERNEL_OPTION_HEADERS 59 #include "opt_snd.h" 60 #endif 61 62 #include <dev/sound/pcm/sound.h> 63 #include <dev/sound/pcm/ac97.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 #include <sys/sysctl.h> 68 #include <sys/endian.h> 69 70 #include <dev/sound/pci/atiixp.h> 71 72 #define ATI_IXP_DMA_RETRY_MAX 100 73 74 #define ATI_IXP_BUFSZ_MIN 4096 75 #define ATI_IXP_BUFSZ_MAX 65536 76 #define ATI_IXP_BUFSZ_DEFAULT 16384 77 78 #define ATI_IXP_BLK_MIN 32 79 #define ATI_IXP_BLK_ALIGN (~(ATI_IXP_BLK_MIN - 1)) 80 81 #define ATI_IXP_CHN_RUNNING 0x00000001 82 #define ATI_IXP_CHN_SUSPEND 0x00000002 83 84 struct atiixp_dma_op { 85 volatile uint32_t addr; 86 volatile uint16_t status; 87 volatile uint16_t size; 88 volatile uint32_t next; 89 }; 90 91 struct atiixp_info; 92 93 struct atiixp_chinfo { 94 struct snd_dbuf *buffer; 95 struct pcm_channel *channel; 96 struct atiixp_info *parent; 97 struct atiixp_dma_op *sgd_table; 98 bus_addr_t sgd_addr; 99 uint32_t enable_bit, flush_bit, linkptr_bit, dt_cur_bit; 100 uint32_t blksz, blkcnt; 101 uint32_t ptr, prevptr; 102 uint32_t fmt; 103 uint32_t flags; 104 int caps_32bit, dir; 105 }; 106 107 struct atiixp_info { 108 device_t dev; 109 110 bus_space_tag_t st; 111 bus_space_handle_t sh; 112 bus_dma_tag_t parent_dmat; 113 bus_dma_tag_t sgd_dmat; 114 bus_dmamap_t sgd_dmamap; 115 bus_addr_t sgd_addr; 116 117 struct resource *reg, *irq; 118 int regtype, regid, irqid; 119 void *ih; 120 struct ac97_info *codec; 121 122 struct atiixp_chinfo pch; 123 struct atiixp_chinfo rch; 124 struct atiixp_dma_op *sgd_table; 125 struct intr_config_hook delayed_attach; 126 127 uint32_t bufsz; 128 uint32_t codec_not_ready_bits, codec_idx, codec_found; 129 uint32_t blkcnt; 130 int registered_channels; 131 132 struct mtx *lock; 133 struct callout poll_timer; 134 int poll_ticks, polling; 135 }; 136 137 #define atiixp_rd(_sc, _reg) \ 138 bus_space_read_4((_sc)->st, (_sc)->sh, _reg) 139 #define atiixp_wr(_sc, _reg, _val) \ 140 bus_space_write_4((_sc)->st, (_sc)->sh, _reg, _val) 141 142 #define atiixp_lock(_sc) snd_mtxlock((_sc)->lock) 143 #define atiixp_unlock(_sc) snd_mtxunlock((_sc)->lock) 144 #define atiixp_assert(_sc) snd_mtxassert((_sc)->lock) 145 146 static uint32_t atiixp_fmt_32bit[] = { 147 SND_FORMAT(AFMT_S16_LE, 2, 0), 148 SND_FORMAT(AFMT_S32_LE, 2, 0), 149 0 150 }; 151 152 static uint32_t atiixp_fmt[] = { 153 SND_FORMAT(AFMT_S16_LE, 2, 0), 154 0 155 }; 156 157 static struct pcmchan_caps atiixp_caps_32bit = { 158 ATI_IXP_BASE_RATE, 159 ATI_IXP_BASE_RATE, 160 atiixp_fmt_32bit, 0 161 }; 162 163 static struct pcmchan_caps atiixp_caps = { 164 ATI_IXP_BASE_RATE, 165 ATI_IXP_BASE_RATE, 166 atiixp_fmt, 0 167 }; 168 169 static const struct { 170 uint16_t vendor; 171 uint16_t devid; 172 char *desc; 173 } atiixp_hw[] = { 174 { ATI_VENDOR_ID, ATI_IXP_200_ID, "ATI IXP 200" }, 175 { ATI_VENDOR_ID, ATI_IXP_300_ID, "ATI IXP 300" }, 176 { ATI_VENDOR_ID, ATI_IXP_400_ID, "ATI IXP 400" }, 177 { ATI_VENDOR_ID, ATI_IXP_SB600_ID, "ATI IXP SB600" }, 178 }; 179 180 static void atiixp_enable_interrupts(struct atiixp_info *); 181 static void atiixp_disable_interrupts(struct atiixp_info *); 182 static void atiixp_reset_aclink(struct atiixp_info *); 183 static void atiixp_flush_dma(struct atiixp_chinfo *); 184 static void atiixp_enable_dma(struct atiixp_chinfo *); 185 static void atiixp_disable_dma(struct atiixp_chinfo *); 186 187 static int atiixp_waitready_codec(struct atiixp_info *); 188 static int atiixp_rdcd(kobj_t, void *, int); 189 static int atiixp_wrcd(kobj_t, void *, int, uint32_t); 190 191 static void *atiixp_chan_init(kobj_t, void *, struct snd_dbuf *, 192 struct pcm_channel *, int); 193 static int atiixp_chan_setformat(kobj_t, void *, uint32_t); 194 static uint32_t atiixp_chan_setspeed(kobj_t, void *, uint32_t); 195 static int atiixp_chan_setfragments(kobj_t, void *, uint32_t, uint32_t); 196 static uint32_t atiixp_chan_setblocksize(kobj_t, void *, uint32_t); 197 static void atiixp_buildsgdt(struct atiixp_chinfo *); 198 static int atiixp_chan_trigger(kobj_t, void *, int); 199 static __inline uint32_t atiixp_dmapos(struct atiixp_chinfo *); 200 static uint32_t atiixp_chan_getptr(kobj_t, void *); 201 static struct pcmchan_caps *atiixp_chan_getcaps(kobj_t, void *); 202 203 static void atiixp_intr(void *); 204 static void atiixp_dma_cb(void *, bus_dma_segment_t *, int, int); 205 static void atiixp_chip_pre_init(struct atiixp_info *); 206 static void atiixp_chip_post_init(void *); 207 static void atiixp_release_resource(struct atiixp_info *); 208 static int atiixp_pci_probe(device_t); 209 static int atiixp_pci_attach(device_t); 210 static int atiixp_pci_detach(device_t); 211 static int atiixp_pci_suspend(device_t); 212 static int atiixp_pci_resume(device_t); 213 214 /* 215 * ATI IXP helper functions 216 */ 217 static void 218 atiixp_enable_interrupts(struct atiixp_info *sc) 219 { 220 uint32_t value; 221 222 /* clear all pending */ 223 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 224 225 /* enable all relevant interrupt sources we can handle */ 226 value = atiixp_rd(sc, ATI_REG_IER); 227 228 value |= ATI_REG_IER_IO_STATUS_EN; 229 230 /* 231 * Disable / ignore internal xrun/spdf interrupt flags 232 * since it doesn't interest us (for now). 233 */ 234 #if 1 235 value &= ~(ATI_REG_IER_IN_XRUN_EN | ATI_REG_IER_OUT_XRUN_EN | 236 ATI_REG_IER_SPDF_XRUN_EN | ATI_REG_IER_SPDF_STATUS_EN); 237 #else 238 value |= ATI_REG_IER_IN_XRUN_EN; 239 value |= ATI_REG_IER_OUT_XRUN_EN; 240 241 value |= ATI_REG_IER_SPDF_XRUN_EN; 242 value |= ATI_REG_IER_SPDF_STATUS_EN; 243 #endif 244 245 atiixp_wr(sc, ATI_REG_IER, value); 246 } 247 248 static void 249 atiixp_disable_interrupts(struct atiixp_info *sc) 250 { 251 /* disable all interrupt sources */ 252 atiixp_wr(sc, ATI_REG_IER, 0); 253 254 /* clear all pending */ 255 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 256 } 257 258 static void 259 atiixp_reset_aclink(struct atiixp_info *sc) 260 { 261 uint32_t value, timeout; 262 263 /* if power is down, power it up */ 264 value = atiixp_rd(sc, ATI_REG_CMD); 265 if (value & ATI_REG_CMD_POWERDOWN) { 266 /* explicitly enable power */ 267 value &= ~ATI_REG_CMD_POWERDOWN; 268 atiixp_wr(sc, ATI_REG_CMD, value); 269 270 /* have to wait at least 10 usec for it to initialise */ 271 DELAY(20); 272 } 273 274 /* perform a soft reset */ 275 value = atiixp_rd(sc, ATI_REG_CMD); 276 value |= ATI_REG_CMD_AC_SOFT_RESET; 277 atiixp_wr(sc, ATI_REG_CMD, value); 278 279 /* need to read the CMD reg and wait aprox. 10 usec to init */ 280 value = atiixp_rd(sc, ATI_REG_CMD); 281 DELAY(20); 282 283 /* clear soft reset flag again */ 284 value = atiixp_rd(sc, ATI_REG_CMD); 285 value &= ~ATI_REG_CMD_AC_SOFT_RESET; 286 atiixp_wr(sc, ATI_REG_CMD, value); 287 288 /* check if the ac-link is working; reset device otherwise */ 289 timeout = 10; 290 value = atiixp_rd(sc, ATI_REG_CMD); 291 while (!(value & ATI_REG_CMD_ACLINK_ACTIVE) && --timeout) { 292 #if 0 293 device_printf(sc->dev, "not up; resetting aclink hardware\n"); 294 #endif 295 296 /* dip aclink reset but keep the acsync */ 297 value &= ~ATI_REG_CMD_AC_RESET; 298 value |= ATI_REG_CMD_AC_SYNC; 299 atiixp_wr(sc, ATI_REG_CMD, value); 300 301 /* need to read CMD again and wait again (clocking in issue?) */ 302 value = atiixp_rd(sc, ATI_REG_CMD); 303 DELAY(20); 304 305 /* assert aclink reset again */ 306 value = atiixp_rd(sc, ATI_REG_CMD); 307 value |= ATI_REG_CMD_AC_RESET; 308 atiixp_wr(sc, ATI_REG_CMD, value); 309 310 /* check if its active now */ 311 value = atiixp_rd(sc, ATI_REG_CMD); 312 } 313 314 if (timeout == 0) 315 device_printf(sc->dev, "giving up aclink reset\n"); 316 #if 0 317 if (timeout != 10) 318 device_printf(sc->dev, "aclink hardware reset successful\n"); 319 #endif 320 321 /* assert reset and sync for safety */ 322 value = atiixp_rd(sc, ATI_REG_CMD); 323 value |= ATI_REG_CMD_AC_SYNC | ATI_REG_CMD_AC_RESET; 324 atiixp_wr(sc, ATI_REG_CMD, value); 325 } 326 327 static void 328 atiixp_flush_dma(struct atiixp_chinfo *ch) 329 { 330 atiixp_wr(ch->parent, ATI_REG_FIFO_FLUSH, ch->flush_bit); 331 } 332 333 static void 334 atiixp_enable_dma(struct atiixp_chinfo *ch) 335 { 336 uint32_t value; 337 338 value = atiixp_rd(ch->parent, ATI_REG_CMD); 339 if (!(value & ch->enable_bit)) { 340 value |= ch->enable_bit; 341 atiixp_wr(ch->parent, ATI_REG_CMD, value); 342 } 343 } 344 345 static void 346 atiixp_disable_dma(struct atiixp_chinfo *ch) 347 { 348 uint32_t value; 349 350 value = atiixp_rd(ch->parent, ATI_REG_CMD); 351 if (value & ch->enable_bit) { 352 value &= ~ch->enable_bit; 353 atiixp_wr(ch->parent, ATI_REG_CMD, value); 354 } 355 } 356 357 /* 358 * AC97 interface 359 */ 360 static int 361 atiixp_waitready_codec(struct atiixp_info *sc) 362 { 363 int timeout = 500; 364 365 do { 366 if ((atiixp_rd(sc, ATI_REG_PHYS_OUT_ADDR) & 367 ATI_REG_PHYS_OUT_ADDR_EN) == 0) 368 return (0); 369 DELAY(1); 370 } while (--timeout); 371 372 return (-1); 373 } 374 375 static int 376 atiixp_rdcd(kobj_t obj, void *devinfo, int reg) 377 { 378 struct atiixp_info *sc = devinfo; 379 uint32_t data; 380 int timeout; 381 382 if (atiixp_waitready_codec(sc)) 383 return (-1); 384 385 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 386 ATI_REG_PHYS_OUT_ADDR_EN | ATI_REG_PHYS_OUT_RW | sc->codec_idx; 387 388 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 389 390 if (atiixp_waitready_codec(sc)) 391 return (-1); 392 393 timeout = 500; 394 do { 395 data = atiixp_rd(sc, ATI_REG_PHYS_IN_ADDR); 396 if (data & ATI_REG_PHYS_IN_READ_FLAG) 397 return (data >> ATI_REG_PHYS_IN_DATA_SHIFT); 398 DELAY(1); 399 } while (--timeout); 400 401 if (reg < 0x7c) 402 device_printf(sc->dev, "codec read timeout! (reg 0x%x)\n", reg); 403 404 return (-1); 405 } 406 407 static int 408 atiixp_wrcd(kobj_t obj, void *devinfo, int reg, uint32_t data) 409 { 410 struct atiixp_info *sc = devinfo; 411 412 if (atiixp_waitready_codec(sc)) 413 return (-1); 414 415 data = (data << ATI_REG_PHYS_OUT_DATA_SHIFT) | 416 (((uint32_t)reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 417 ATI_REG_PHYS_OUT_ADDR_EN | sc->codec_idx; 418 419 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 420 421 return (0); 422 } 423 424 static kobj_method_t atiixp_ac97_methods[] = { 425 KOBJMETHOD(ac97_read, atiixp_rdcd), 426 KOBJMETHOD(ac97_write, atiixp_wrcd), 427 KOBJMETHOD_END 428 }; 429 AC97_DECLARE(atiixp_ac97); 430 431 /* 432 * Playback / Record channel interface 433 */ 434 static void * 435 atiixp_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 436 struct pcm_channel *c, int dir) 437 { 438 struct atiixp_info *sc = devinfo; 439 struct atiixp_chinfo *ch; 440 int num; 441 442 atiixp_lock(sc); 443 444 if (dir == PCMDIR_PLAY) { 445 ch = &sc->pch; 446 ch->linkptr_bit = ATI_REG_OUT_DMA_LINKPTR; 447 ch->enable_bit = ATI_REG_CMD_OUT_DMA_EN | ATI_REG_CMD_SEND_EN; 448 ch->flush_bit = ATI_REG_FIFO_OUT_FLUSH; 449 ch->dt_cur_bit = ATI_REG_OUT_DMA_DT_CUR; 450 /* Native 32bit playback working properly */ 451 ch->caps_32bit = 1; 452 } else { 453 ch = &sc->rch; 454 ch->linkptr_bit = ATI_REG_IN_DMA_LINKPTR; 455 ch->enable_bit = ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_RECEIVE_EN; 456 ch->flush_bit = ATI_REG_FIFO_IN_FLUSH; 457 ch->dt_cur_bit = ATI_REG_IN_DMA_DT_CUR; 458 /* XXX Native 32bit recording appear to be broken */ 459 ch->caps_32bit = 1; 460 } 461 462 ch->buffer = b; 463 ch->parent = sc; 464 ch->channel = c; 465 ch->dir = dir; 466 ch->blkcnt = sc->blkcnt; 467 ch->blksz = sc->bufsz / ch->blkcnt; 468 469 atiixp_unlock(sc); 470 471 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) == -1) 472 return (NULL); 473 474 atiixp_lock(sc); 475 num = sc->registered_channels++; 476 ch->sgd_table = &sc->sgd_table[num * ATI_IXP_DMA_CHSEGS_MAX]; 477 ch->sgd_addr = sc->sgd_addr + (num * ATI_IXP_DMA_CHSEGS_MAX * 478 sizeof(struct atiixp_dma_op)); 479 atiixp_disable_dma(ch); 480 atiixp_unlock(sc); 481 482 return (ch); 483 } 484 485 static int 486 atiixp_chan_setformat(kobj_t obj, void *data, uint32_t format) 487 { 488 struct atiixp_chinfo *ch = data; 489 struct atiixp_info *sc = ch->parent; 490 uint32_t value; 491 492 atiixp_lock(sc); 493 if (ch->dir == PCMDIR_REC) { 494 value = atiixp_rd(sc, ATI_REG_CMD); 495 value &= ~ATI_REG_CMD_INTERLEAVE_IN; 496 if ((format & AFMT_32BIT) == 0) 497 value |= ATI_REG_CMD_INTERLEAVE_IN; 498 atiixp_wr(sc, ATI_REG_CMD, value); 499 } else { 500 value = atiixp_rd(sc, ATI_REG_OUT_DMA_SLOT); 501 value &= ~ATI_REG_OUT_DMA_SLOT_MASK; 502 /* We do not have support for more than 2 channels, _yet_. */ 503 value |= ATI_REG_OUT_DMA_SLOT_BIT(3) | 504 ATI_REG_OUT_DMA_SLOT_BIT(4); 505 value |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 506 atiixp_wr(sc, ATI_REG_OUT_DMA_SLOT, value); 507 value = atiixp_rd(sc, ATI_REG_CMD); 508 value &= ~ATI_REG_CMD_INTERLEAVE_OUT; 509 if ((format & AFMT_32BIT) == 0) 510 value |= ATI_REG_CMD_INTERLEAVE_OUT; 511 atiixp_wr(sc, ATI_REG_CMD, value); 512 value = atiixp_rd(sc, ATI_REG_6CH_REORDER); 513 value &= ~ATI_REG_6CH_REORDER_EN; 514 atiixp_wr(sc, ATI_REG_6CH_REORDER, value); 515 } 516 ch->fmt = format; 517 atiixp_unlock(sc); 518 519 return (0); 520 } 521 522 static uint32_t 523 atiixp_chan_setspeed(kobj_t obj, void *data, uint32_t spd) 524 { 525 /* XXX We're supposed to do VRA/DRA processing right here */ 526 return (ATI_IXP_BASE_RATE); 527 } 528 529 static int 530 atiixp_chan_setfragments(kobj_t obj, void *data, 531 uint32_t blksz, uint32_t blkcnt) 532 { 533 struct atiixp_chinfo *ch = data; 534 struct atiixp_info *sc = ch->parent; 535 536 blksz &= ATI_IXP_BLK_ALIGN; 537 538 if (blksz > (sndbuf_getmaxsize(ch->buffer) / ATI_IXP_DMA_CHSEGS_MIN)) 539 blksz = sndbuf_getmaxsize(ch->buffer) / ATI_IXP_DMA_CHSEGS_MIN; 540 if (blksz < ATI_IXP_BLK_MIN) 541 blksz = ATI_IXP_BLK_MIN; 542 if (blkcnt > ATI_IXP_DMA_CHSEGS_MAX) 543 blkcnt = ATI_IXP_DMA_CHSEGS_MAX; 544 if (blkcnt < ATI_IXP_DMA_CHSEGS_MIN) 545 blkcnt = ATI_IXP_DMA_CHSEGS_MIN; 546 547 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->buffer)) { 548 if ((blkcnt >> 1) >= ATI_IXP_DMA_CHSEGS_MIN) 549 blkcnt >>= 1; 550 else if ((blksz >> 1) >= ATI_IXP_BLK_MIN) 551 blksz >>= 1; 552 else 553 break; 554 } 555 556 if ((sndbuf_getblksz(ch->buffer) != blksz || 557 sndbuf_getblkcnt(ch->buffer) != blkcnt) && 558 sndbuf_resize(ch->buffer, blkcnt, blksz) != 0) 559 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 560 __func__, blksz, blkcnt); 561 562 ch->blksz = sndbuf_getblksz(ch->buffer); 563 ch->blkcnt = sndbuf_getblkcnt(ch->buffer); 564 565 return (0); 566 } 567 568 static uint32_t 569 atiixp_chan_setblocksize(kobj_t obj, void *data, uint32_t blksz) 570 { 571 struct atiixp_chinfo *ch = data; 572 struct atiixp_info *sc = ch->parent; 573 574 atiixp_chan_setfragments(obj, data, blksz, sc->blkcnt); 575 576 return (ch->blksz); 577 } 578 579 static void 580 atiixp_buildsgdt(struct atiixp_chinfo *ch) 581 { 582 struct atiixp_info *sc = ch->parent; 583 uint32_t addr, blksz, blkcnt; 584 int i; 585 586 addr = sndbuf_getbufaddr(ch->buffer); 587 588 if (sc->polling != 0) { 589 blksz = ch->blksz * ch->blkcnt; 590 blkcnt = 1; 591 } else { 592 blksz = ch->blksz; 593 blkcnt = ch->blkcnt; 594 } 595 596 for (i = 0; i < blkcnt; i++) { 597 ch->sgd_table[i].addr = htole32(addr + (i * blksz)); 598 ch->sgd_table[i].status = htole16(0); 599 ch->sgd_table[i].size = htole16(blksz >> 2); 600 ch->sgd_table[i].next = htole32((uint32_t)ch->sgd_addr + 601 (((i + 1) % blkcnt) * sizeof(struct atiixp_dma_op))); 602 } 603 } 604 605 static __inline uint32_t 606 atiixp_dmapos(struct atiixp_chinfo *ch) 607 { 608 struct atiixp_info *sc = ch->parent; 609 uint32_t reg, addr, sz, retry; 610 volatile uint32_t ptr; 611 612 reg = ch->dt_cur_bit; 613 addr = sndbuf_getbufaddr(ch->buffer); 614 sz = ch->blkcnt * ch->blksz; 615 retry = ATI_IXP_DMA_RETRY_MAX; 616 617 do { 618 ptr = atiixp_rd(sc, reg); 619 if (ptr < addr) 620 continue; 621 ptr -= addr; 622 if (ptr < sz) { 623 #if 0 624 #ifdef ATI_IXP_DEBUG 625 if ((ptr & ~(ch->blksz - 1)) != ch->ptr) { 626 uint32_t delta; 627 628 delta = (sz + ptr - ch->prevptr) % sz; 629 #ifndef ATI_IXP_DEBUG_VERBOSE 630 if (delta < ch->blksz) 631 #endif 632 device_printf(sc->dev, 633 "PCMDIR_%s: incoherent DMA " 634 "prevptr=%u ptr=%u " 635 "ptr=%u blkcnt=%u " 636 "[delta=%u != blksz=%u] " 637 "(%s)\n", 638 (ch->dir == PCMDIR_PLAY) ? 639 "PLAY" : "REC", 640 ch->prevptr, ptr, 641 ch->ptr, ch->blkcnt, 642 delta, ch->blksz, 643 (delta < ch->blksz) ? 644 "OVERLAPPED!" : "Ok"); 645 ch->ptr = ptr & ~(ch->blksz - 1); 646 } 647 ch->prevptr = ptr; 648 #endif 649 #endif 650 return (ptr); 651 } 652 } while (--retry); 653 654 device_printf(sc->dev, "PCMDIR_%s: invalid DMA pointer ptr=%u\n", 655 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", ptr); 656 657 return (0); 658 } 659 660 static __inline int 661 atiixp_poll_channel(struct atiixp_chinfo *ch) 662 { 663 uint32_t sz, delta; 664 volatile uint32_t ptr; 665 666 if (!(ch->flags & ATI_IXP_CHN_RUNNING)) 667 return (0); 668 669 sz = ch->blksz * ch->blkcnt; 670 ptr = atiixp_dmapos(ch); 671 ch->ptr = ptr; 672 ptr %= sz; 673 ptr &= ~(ch->blksz - 1); 674 delta = (sz + ptr - ch->prevptr) % sz; 675 676 if (delta < ch->blksz) 677 return (0); 678 679 ch->prevptr = ptr; 680 681 return (1); 682 } 683 684 #define atiixp_chan_active(sc) (((sc)->pch.flags | (sc)->rch.flags) & \ 685 ATI_IXP_CHN_RUNNING) 686 687 static void 688 atiixp_poll_callback(void *arg) 689 { 690 struct atiixp_info *sc = arg; 691 uint32_t trigger = 0; 692 693 if (sc == NULL) 694 return; 695 696 atiixp_lock(sc); 697 if (sc->polling == 0 || atiixp_chan_active(sc) == 0) { 698 atiixp_unlock(sc); 699 return; 700 } 701 702 trigger |= (atiixp_poll_channel(&sc->pch) != 0) ? 1 : 0; 703 trigger |= (atiixp_poll_channel(&sc->rch) != 0) ? 2 : 0; 704 705 /* XXX */ 706 callout_reset(&sc->poll_timer, 1/*sc->poll_ticks*/, 707 atiixp_poll_callback, sc); 708 709 atiixp_unlock(sc); 710 711 if (trigger & 1) 712 chn_intr(sc->pch.channel); 713 if (trigger & 2) 714 chn_intr(sc->rch.channel); 715 } 716 717 static int 718 atiixp_chan_trigger(kobj_t obj, void *data, int go) 719 { 720 struct atiixp_chinfo *ch = data; 721 struct atiixp_info *sc = ch->parent; 722 uint32_t value; 723 int pollticks; 724 725 if (!PCMTRIG_COMMON(go)) 726 return (0); 727 728 atiixp_lock(sc); 729 730 switch (go) { 731 case PCMTRIG_START: 732 atiixp_flush_dma(ch); 733 atiixp_buildsgdt(ch); 734 atiixp_wr(sc, ch->linkptr_bit, 0); 735 atiixp_enable_dma(ch); 736 atiixp_wr(sc, ch->linkptr_bit, 737 (uint32_t)ch->sgd_addr | ATI_REG_LINKPTR_EN); 738 if (sc->polling != 0) { 739 ch->ptr = 0; 740 ch->prevptr = 0; 741 pollticks = ((uint64_t)hz * ch->blksz) / 742 ((uint64_t)sndbuf_getalign(ch->buffer) * 743 sndbuf_getspd(ch->buffer)); 744 pollticks >>= 2; 745 if (pollticks > hz) 746 pollticks = hz; 747 if (pollticks < 1) 748 pollticks = 1; 749 if (atiixp_chan_active(sc) == 0 || 750 pollticks < sc->poll_ticks) { 751 if (bootverbose) { 752 if (atiixp_chan_active(sc) == 0) 753 device_printf(sc->dev, 754 "%s: pollticks=%d\n", 755 __func__, pollticks); 756 else 757 device_printf(sc->dev, 758 "%s: pollticks %d -> %d\n", 759 __func__, sc->poll_ticks, 760 pollticks); 761 } 762 sc->poll_ticks = pollticks; 763 callout_reset(&sc->poll_timer, 1, 764 atiixp_poll_callback, sc); 765 } 766 } 767 ch->flags |= ATI_IXP_CHN_RUNNING; 768 break; 769 case PCMTRIG_STOP: 770 case PCMTRIG_ABORT: 771 atiixp_disable_dma(ch); 772 atiixp_flush_dma(ch); 773 ch->flags &= ~ATI_IXP_CHN_RUNNING; 774 if (sc->polling != 0) { 775 if (atiixp_chan_active(sc) == 0) { 776 callout_stop(&sc->poll_timer); 777 sc->poll_ticks = 1; 778 } else { 779 if (sc->pch.flags & ATI_IXP_CHN_RUNNING) 780 ch = &sc->pch; 781 else 782 ch = &sc->rch; 783 pollticks = ((uint64_t)hz * ch->blksz) / 784 ((uint64_t)sndbuf_getalign(ch->buffer) * 785 sndbuf_getspd(ch->buffer)); 786 pollticks >>= 2; 787 if (pollticks > hz) 788 pollticks = hz; 789 if (pollticks < 1) 790 pollticks = 1; 791 if (pollticks > sc->poll_ticks) { 792 if (bootverbose) 793 device_printf(sc->dev, 794 "%s: pollticks %d -> %d\n", 795 __func__, sc->poll_ticks, 796 pollticks); 797 sc->poll_ticks = pollticks; 798 callout_reset(&sc->poll_timer, 799 1, atiixp_poll_callback, 800 sc); 801 } 802 } 803 } 804 break; 805 default: 806 atiixp_unlock(sc); 807 return (0); 808 break; 809 } 810 811 /* Update bus busy status */ 812 value = atiixp_rd(sc, ATI_REG_IER); 813 if (atiixp_rd(sc, ATI_REG_CMD) & (ATI_REG_CMD_SEND_EN | 814 ATI_REG_CMD_RECEIVE_EN | ATI_REG_CMD_SPDF_OUT_EN)) 815 value |= ATI_REG_IER_SET_BUS_BUSY; 816 else 817 value &= ~ATI_REG_IER_SET_BUS_BUSY; 818 atiixp_wr(sc, ATI_REG_IER, value); 819 820 atiixp_unlock(sc); 821 822 return (0); 823 } 824 825 static uint32_t 826 atiixp_chan_getptr(kobj_t obj, void *data) 827 { 828 struct atiixp_chinfo *ch = data; 829 struct atiixp_info *sc = ch->parent; 830 uint32_t ptr; 831 832 atiixp_lock(sc); 833 if (sc->polling != 0) 834 ptr = ch->ptr; 835 else 836 ptr = atiixp_dmapos(ch); 837 atiixp_unlock(sc); 838 839 return (ptr); 840 } 841 842 static struct pcmchan_caps * 843 atiixp_chan_getcaps(kobj_t obj, void *data) 844 { 845 struct atiixp_chinfo *ch = data; 846 847 if (ch->caps_32bit) 848 return (&atiixp_caps_32bit); 849 return (&atiixp_caps); 850 } 851 852 static kobj_method_t atiixp_chan_methods[] = { 853 KOBJMETHOD(channel_init, atiixp_chan_init), 854 KOBJMETHOD(channel_setformat, atiixp_chan_setformat), 855 KOBJMETHOD(channel_setspeed, atiixp_chan_setspeed), 856 KOBJMETHOD(channel_setblocksize, atiixp_chan_setblocksize), 857 KOBJMETHOD(channel_setfragments, atiixp_chan_setfragments), 858 KOBJMETHOD(channel_trigger, atiixp_chan_trigger), 859 KOBJMETHOD(channel_getptr, atiixp_chan_getptr), 860 KOBJMETHOD(channel_getcaps, atiixp_chan_getcaps), 861 KOBJMETHOD_END 862 }; 863 CHANNEL_DECLARE(atiixp_chan); 864 865 /* 866 * PCI driver interface 867 */ 868 static void 869 atiixp_intr(void *p) 870 { 871 struct atiixp_info *sc = p; 872 uint32_t status, enable, detected_codecs; 873 uint32_t trigger = 0; 874 875 atiixp_lock(sc); 876 if (sc->polling != 0) { 877 atiixp_unlock(sc); 878 return; 879 } 880 status = atiixp_rd(sc, ATI_REG_ISR); 881 882 if (status == 0) { 883 atiixp_unlock(sc); 884 return; 885 } 886 887 if ((status & ATI_REG_ISR_OUT_STATUS) && 888 (sc->pch.flags & ATI_IXP_CHN_RUNNING)) 889 trigger |= 1; 890 if ((status & ATI_REG_ISR_IN_STATUS) && 891 (sc->rch.flags & ATI_IXP_CHN_RUNNING)) 892 trigger |= 2; 893 894 #if 0 895 if (status & ATI_REG_ISR_IN_XRUN) { 896 device_printf(sc->dev, 897 "Recieve IN XRUN interrupt\n"); 898 } 899 if (status & ATI_REG_ISR_OUT_XRUN) { 900 device_printf(sc->dev, 901 "Recieve OUT XRUN interrupt\n"); 902 } 903 #endif 904 905 if (status & CODEC_CHECK_BITS) { 906 /* mark missing codecs as not ready */ 907 detected_codecs = status & CODEC_CHECK_BITS; 908 sc->codec_not_ready_bits |= detected_codecs; 909 910 /* disable detected interrupt sources */ 911 enable = atiixp_rd(sc, ATI_REG_IER); 912 enable &= ~detected_codecs; 913 atiixp_wr(sc, ATI_REG_IER, enable); 914 wakeup(sc); 915 } 916 917 /* acknowledge */ 918 atiixp_wr(sc, ATI_REG_ISR, status); 919 atiixp_unlock(sc); 920 921 if (trigger & 1) 922 chn_intr(sc->pch.channel); 923 if (trigger & 2) 924 chn_intr(sc->rch.channel); 925 } 926 927 static void 928 atiixp_dma_cb(void *p, bus_dma_segment_t *bds, int a, int b) 929 { 930 struct atiixp_info *sc = (struct atiixp_info *)p; 931 sc->sgd_addr = bds->ds_addr; 932 } 933 934 static void 935 atiixp_chip_pre_init(struct atiixp_info *sc) 936 { 937 uint32_t value; 938 939 atiixp_lock(sc); 940 941 /* disable interrupts */ 942 atiixp_disable_interrupts(sc); 943 944 /* clear all DMA enables (preserving rest of settings) */ 945 value = atiixp_rd(sc, ATI_REG_CMD); 946 value &= ~(ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_OUT_DMA_EN | 947 ATI_REG_CMD_SPDF_OUT_EN ); 948 atiixp_wr(sc, ATI_REG_CMD, value); 949 950 /* reset aclink */ 951 atiixp_reset_aclink(sc); 952 953 sc->codec_not_ready_bits = 0; 954 955 /* enable all codecs to interrupt as well as the new frame interrupt */ 956 atiixp_wr(sc, ATI_REG_IER, CODEC_CHECK_BITS); 957 958 atiixp_unlock(sc); 959 } 960 961 static int 962 sysctl_atiixp_polling(SYSCTL_HANDLER_ARGS) 963 { 964 struct atiixp_info *sc; 965 device_t dev; 966 int err, val; 967 968 dev = oidp->oid_arg1; 969 sc = pcm_getdevinfo(dev); 970 if (sc == NULL) 971 return (EINVAL); 972 atiixp_lock(sc); 973 val = sc->polling; 974 atiixp_unlock(sc); 975 err = sysctl_handle_int(oidp, &val, 0, req); 976 977 if (err || req->newptr == NULL) 978 return (err); 979 if (val < 0 || val > 1) 980 return (EINVAL); 981 982 atiixp_lock(sc); 983 if (val != sc->polling) { 984 if (atiixp_chan_active(sc) != 0) 985 err = EBUSY; 986 else if (val == 0) { 987 atiixp_enable_interrupts(sc); 988 sc->polling = 0; 989 DELAY(1000); 990 } else { 991 atiixp_disable_interrupts(sc); 992 sc->polling = 1; 993 DELAY(1000); 994 } 995 } 996 atiixp_unlock(sc); 997 998 return (err); 999 } 1000 1001 static void 1002 atiixp_chip_post_init(void *arg) 1003 { 1004 struct atiixp_info *sc = (struct atiixp_info *)arg; 1005 uint32_t subdev; 1006 int i, timeout, found, polling; 1007 char status[SND_STATUSLEN]; 1008 1009 atiixp_lock(sc); 1010 1011 if (sc->delayed_attach.ich_func) { 1012 config_intrhook_disestablish(&sc->delayed_attach); 1013 sc->delayed_attach.ich_func = NULL; 1014 } 1015 1016 polling = sc->polling; 1017 sc->polling = 0; 1018 1019 timeout = 10; 1020 if (sc->codec_not_ready_bits == 0) { 1021 /* wait for the interrupts to happen */ 1022 do { 1023 msleep(sc, sc->lock, PWAIT, "ixpslp", max(hz / 10, 1)); 1024 if (sc->codec_not_ready_bits != 0) 1025 break; 1026 } while (--timeout); 1027 } 1028 1029 sc->polling = polling; 1030 atiixp_disable_interrupts(sc); 1031 1032 if (sc->codec_not_ready_bits == 0 && timeout == 0) { 1033 device_printf(sc->dev, 1034 "WARNING: timeout during codec detection; " 1035 "codecs might be present but haven't interrupted\n"); 1036 atiixp_unlock(sc); 1037 goto postinitbad; 1038 } 1039 1040 found = 0; 1041 1042 /* 1043 * ATI IXP can have upto 3 codecs, but single codec should be 1044 * suffice for now. 1045 */ 1046 if (!(sc->codec_not_ready_bits & ATI_REG_ISR_CODEC0_NOT_READY)) { 1047 /* codec 0 present */ 1048 sc->codec_found++; 1049 sc->codec_idx = 0; 1050 found++; 1051 } 1052 1053 if (!(sc->codec_not_ready_bits & ATI_REG_ISR_CODEC1_NOT_READY)) { 1054 /* codec 1 present */ 1055 sc->codec_found++; 1056 } 1057 1058 if (!(sc->codec_not_ready_bits & ATI_REG_ISR_CODEC2_NOT_READY)) { 1059 /* codec 2 present */ 1060 sc->codec_found++; 1061 } 1062 1063 atiixp_unlock(sc); 1064 1065 if (found == 0) 1066 goto postinitbad; 1067 1068 /* create/init mixer */ 1069 sc->codec = AC97_CREATE(sc->dev, sc, atiixp_ac97); 1070 if (sc->codec == NULL) 1071 goto postinitbad; 1072 1073 subdev = (pci_get_subdevice(sc->dev) << 16) | 1074 pci_get_subvendor(sc->dev); 1075 switch (subdev) { 1076 case 0x11831043: /* ASUS A6R */ 1077 case 0x2043161f: /* Maxselect x710s - http://maxselect.ru/ */ 1078 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | 1079 AC97_F_EAPD_INV); 1080 break; 1081 default: 1082 break; 1083 } 1084 1085 mixer_init(sc->dev, ac97_getmixerclass(), sc->codec); 1086 1087 if (pcm_register(sc->dev, sc, ATI_IXP_NPCHAN, ATI_IXP_NRCHAN)) 1088 goto postinitbad; 1089 1090 for (i = 0; i < ATI_IXP_NPCHAN; i++) 1091 pcm_addchan(sc->dev, PCMDIR_PLAY, &atiixp_chan_class, sc); 1092 for (i = 0; i < ATI_IXP_NRCHAN; i++) 1093 pcm_addchan(sc->dev, PCMDIR_REC, &atiixp_chan_class, sc); 1094 1095 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1096 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1097 "polling", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc->dev, 1098 sizeof(sc->dev), sysctl_atiixp_polling, "I", "Enable polling mode"); 1099 1100 snprintf(status, SND_STATUSLEN, "at memory 0x%jx irq %jd %s", 1101 rman_get_start(sc->reg), rman_get_start(sc->irq), 1102 PCM_KLDSTRING(snd_atiixp)); 1103 1104 pcm_setstatus(sc->dev, status); 1105 1106 atiixp_lock(sc); 1107 if (sc->polling == 0) 1108 atiixp_enable_interrupts(sc); 1109 atiixp_unlock(sc); 1110 1111 return; 1112 1113 postinitbad: 1114 atiixp_release_resource(sc); 1115 } 1116 1117 static void 1118 atiixp_release_resource(struct atiixp_info *sc) 1119 { 1120 if (sc == NULL) 1121 return; 1122 if (sc->registered_channels != 0) { 1123 atiixp_lock(sc); 1124 sc->polling = 0; 1125 callout_stop(&sc->poll_timer); 1126 atiixp_unlock(sc); 1127 callout_drain(&sc->poll_timer); 1128 } 1129 if (sc->codec) { 1130 ac97_destroy(sc->codec); 1131 sc->codec = NULL; 1132 } 1133 if (sc->ih) { 1134 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 1135 sc->ih = NULL; 1136 } 1137 if (sc->reg) { 1138 bus_release_resource(sc->dev, sc->regtype, sc->regid, sc->reg); 1139 sc->reg = NULL; 1140 } 1141 if (sc->irq) { 1142 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1143 sc->irq = NULL; 1144 } 1145 if (sc->parent_dmat) { 1146 bus_dma_tag_destroy(sc->parent_dmat); 1147 sc->parent_dmat = NULL; 1148 } 1149 if (sc->sgd_addr) { 1150 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 1151 sc->sgd_addr = 0; 1152 } 1153 if (sc->sgd_table) { 1154 bus_dmamem_free(sc->sgd_dmat, sc->sgd_table, sc->sgd_dmamap); 1155 sc->sgd_table = NULL; 1156 } 1157 if (sc->sgd_dmat) { 1158 bus_dma_tag_destroy(sc->sgd_dmat); 1159 sc->sgd_dmat = NULL; 1160 } 1161 if (sc->lock) { 1162 snd_mtxfree(sc->lock); 1163 sc->lock = NULL; 1164 } 1165 free(sc, M_DEVBUF); 1166 } 1167 1168 static int 1169 atiixp_pci_probe(device_t dev) 1170 { 1171 int i; 1172 uint16_t devid, vendor; 1173 1174 vendor = pci_get_vendor(dev); 1175 devid = pci_get_device(dev); 1176 for (i = 0; i < sizeof(atiixp_hw) / sizeof(atiixp_hw[0]); i++) { 1177 if (vendor == atiixp_hw[i].vendor && 1178 devid == atiixp_hw[i].devid) { 1179 device_set_desc(dev, atiixp_hw[i].desc); 1180 return (BUS_PROBE_DEFAULT); 1181 } 1182 } 1183 1184 return (ENXIO); 1185 } 1186 1187 static int 1188 atiixp_pci_attach(device_t dev) 1189 { 1190 struct atiixp_info *sc; 1191 int i; 1192 1193 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 1194 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_atiixp softc"); 1195 sc->dev = dev; 1196 1197 callout_init(&sc->poll_timer, 1); 1198 sc->poll_ticks = 1; 1199 1200 if (resource_int_value(device_get_name(sc->dev), 1201 device_get_unit(sc->dev), "polling", &i) == 0 && i != 0) 1202 sc->polling = 1; 1203 else 1204 sc->polling = 0; 1205 1206 pci_enable_busmaster(dev); 1207 1208 sc->regid = PCIR_BAR(0); 1209 sc->regtype = SYS_RES_MEMORY; 1210 sc->reg = bus_alloc_resource_any(dev, sc->regtype, 1211 &sc->regid, RF_ACTIVE); 1212 1213 if (!sc->reg) { 1214 device_printf(dev, "unable to allocate register space\n"); 1215 goto bad; 1216 } 1217 1218 sc->st = rman_get_bustag(sc->reg); 1219 sc->sh = rman_get_bushandle(sc->reg); 1220 1221 sc->bufsz = pcm_getbuffersize(dev, ATI_IXP_BUFSZ_MIN, 1222 ATI_IXP_BUFSZ_DEFAULT, ATI_IXP_BUFSZ_MAX); 1223 1224 sc->irqid = 0; 1225 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 1226 RF_ACTIVE | RF_SHAREABLE); 1227 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, 1228 atiixp_intr, sc, &sc->ih)) { 1229 device_printf(dev, "unable to map interrupt\n"); 1230 goto bad; 1231 } 1232 1233 /* 1234 * Let the user choose the best DMA segments. 1235 */ 1236 if (resource_int_value(device_get_name(dev), 1237 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 1238 i &= ATI_IXP_BLK_ALIGN; 1239 if (i < ATI_IXP_BLK_MIN) 1240 i = ATI_IXP_BLK_MIN; 1241 sc->blkcnt = sc->bufsz / i; 1242 i = 0; 1243 while (sc->blkcnt >> i) 1244 i++; 1245 sc->blkcnt = 1 << (i - 1); 1246 if (sc->blkcnt < ATI_IXP_DMA_CHSEGS_MIN) 1247 sc->blkcnt = ATI_IXP_DMA_CHSEGS_MIN; 1248 else if (sc->blkcnt > ATI_IXP_DMA_CHSEGS_MAX) 1249 sc->blkcnt = ATI_IXP_DMA_CHSEGS_MAX; 1250 1251 } else 1252 sc->blkcnt = ATI_IXP_DMA_CHSEGS; 1253 1254 /* 1255 * DMA tag for scatter-gather buffers and link pointers 1256 */ 1257 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 1258 /*boundary*/0, 1259 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 1260 /*highaddr*/BUS_SPACE_MAXADDR, 1261 /*filter*/NULL, /*filterarg*/NULL, 1262 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 1263 /*flags*/0, /*lockfunc*/NULL, 1264 /*lockarg*/NULL, &sc->parent_dmat) != 0) { 1265 device_printf(dev, "unable to create dma tag\n"); 1266 goto bad; 1267 } 1268 1269 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 1270 /*boundary*/0, 1271 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 1272 /*highaddr*/BUS_SPACE_MAXADDR, 1273 /*filter*/NULL, /*filterarg*/NULL, 1274 /*maxsize*/ATI_IXP_DMA_CHSEGS_MAX * ATI_IXP_NCHANS * 1275 sizeof(struct atiixp_dma_op), 1276 /*nsegments*/1, /*maxsegz*/0x3ffff, 1277 /*flags*/0, /*lockfunc*/NULL, 1278 /*lockarg*/NULL, &sc->sgd_dmat) != 0) { 1279 device_printf(dev, "unable to create dma tag\n"); 1280 goto bad; 1281 } 1282 1283 if (bus_dmamem_alloc(sc->sgd_dmat, (void **)&sc->sgd_table, 1284 BUS_DMA_NOWAIT, &sc->sgd_dmamap) == -1) 1285 goto bad; 1286 1287 if (bus_dmamap_load(sc->sgd_dmat, sc->sgd_dmamap, sc->sgd_table, 1288 ATI_IXP_DMA_CHSEGS_MAX * ATI_IXP_NCHANS * 1289 sizeof(struct atiixp_dma_op), atiixp_dma_cb, sc, 0)) 1290 goto bad; 1291 1292 atiixp_chip_pre_init(sc); 1293 1294 sc->delayed_attach.ich_func = atiixp_chip_post_init; 1295 sc->delayed_attach.ich_arg = sc; 1296 if (cold == 0 || 1297 config_intrhook_establish(&sc->delayed_attach) != 0) { 1298 sc->delayed_attach.ich_func = NULL; 1299 atiixp_chip_post_init(sc); 1300 } 1301 1302 return (0); 1303 1304 bad: 1305 atiixp_release_resource(sc); 1306 return (ENXIO); 1307 } 1308 1309 static int 1310 atiixp_pci_detach(device_t dev) 1311 { 1312 int r; 1313 struct atiixp_info *sc; 1314 1315 sc = pcm_getdevinfo(dev); 1316 if (sc != NULL) { 1317 if (sc->codec != NULL) { 1318 r = pcm_unregister(dev); 1319 if (r) 1320 return (r); 1321 } 1322 sc->codec = NULL; 1323 if (sc->st != 0 && sc->sh != 0) 1324 atiixp_disable_interrupts(sc); 1325 atiixp_release_resource(sc); 1326 } 1327 return (0); 1328 } 1329 1330 static int 1331 atiixp_pci_suspend(device_t dev) 1332 { 1333 struct atiixp_info *sc = pcm_getdevinfo(dev); 1334 1335 /* quickly disable interrupts and save channels active state */ 1336 atiixp_lock(sc); 1337 atiixp_disable_interrupts(sc); 1338 atiixp_unlock(sc); 1339 1340 /* stop everything */ 1341 if (sc->pch.flags & ATI_IXP_CHN_RUNNING) { 1342 atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_STOP); 1343 sc->pch.flags |= ATI_IXP_CHN_SUSPEND; 1344 } 1345 if (sc->rch.flags & ATI_IXP_CHN_RUNNING) { 1346 atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_STOP); 1347 sc->rch.flags |= ATI_IXP_CHN_SUSPEND; 1348 } 1349 1350 /* power down aclink and pci bus */ 1351 atiixp_lock(sc); 1352 atiixp_wr(sc, ATI_REG_CMD, ATI_REG_CMD_POWERDOWN); 1353 atiixp_unlock(sc); 1354 1355 return (0); 1356 } 1357 1358 static int 1359 atiixp_pci_resume(device_t dev) 1360 { 1361 struct atiixp_info *sc = pcm_getdevinfo(dev); 1362 1363 atiixp_lock(sc); 1364 /* reset / power up aclink */ 1365 atiixp_reset_aclink(sc); 1366 atiixp_unlock(sc); 1367 1368 if (mixer_reinit(dev) == -1) { 1369 device_printf(dev, "unable to reinitialize the mixer\n"); 1370 return (ENXIO); 1371 } 1372 1373 /* 1374 * Resume channel activities. Reset channel format regardless 1375 * of its previous state. 1376 */ 1377 if (sc->pch.channel != NULL) { 1378 if (sc->pch.fmt != 0) 1379 atiixp_chan_setformat(NULL, &sc->pch, sc->pch.fmt); 1380 if (sc->pch.flags & ATI_IXP_CHN_SUSPEND) { 1381 sc->pch.flags &= ~ATI_IXP_CHN_SUSPEND; 1382 atiixp_chan_trigger(NULL, &sc->pch, PCMTRIG_START); 1383 } 1384 } 1385 if (sc->rch.channel != NULL) { 1386 if (sc->rch.fmt != 0) 1387 atiixp_chan_setformat(NULL, &sc->rch, sc->rch.fmt); 1388 if (sc->rch.flags & ATI_IXP_CHN_SUSPEND) { 1389 sc->rch.flags &= ~ATI_IXP_CHN_SUSPEND; 1390 atiixp_chan_trigger(NULL, &sc->rch, PCMTRIG_START); 1391 } 1392 } 1393 1394 /* enable interrupts */ 1395 atiixp_lock(sc); 1396 if (sc->polling == 0) 1397 atiixp_enable_interrupts(sc); 1398 atiixp_unlock(sc); 1399 1400 return (0); 1401 } 1402 1403 static device_method_t atiixp_methods[] = { 1404 DEVMETHOD(device_probe, atiixp_pci_probe), 1405 DEVMETHOD(device_attach, atiixp_pci_attach), 1406 DEVMETHOD(device_detach, atiixp_pci_detach), 1407 DEVMETHOD(device_suspend, atiixp_pci_suspend), 1408 DEVMETHOD(device_resume, atiixp_pci_resume), 1409 { 0, 0 } 1410 }; 1411 1412 static driver_t atiixp_driver = { 1413 "pcm", 1414 atiixp_methods, 1415 PCM_SOFTC_SIZE, 1416 }; 1417 1418 DRIVER_MODULE(snd_atiixp, pci, atiixp_driver, 0, 0); 1419 MODULE_DEPEND(snd_atiixp, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1420 MODULE_VERSION(snd_atiixp, 1); 1421