1 /*- 2 * Copyright (c) 2005 Ariff Abdullah <ariff@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * FreeBSD pcm driver for ATI IXP 150/200/250/300 AC97 controllers 29 * 30 * Features 31 * * 16bit playback / recording 32 * * 32bit native playback - yay! 33 * 34 * Issues / TODO: 35 * * SPDIF 36 * * Support for more than 2 channels. 37 * * VRA ? VRM ? DRA ? 38 * * Suspend / Resume. 39 * * 32bit native recording (seems broken, disabled) 40 * 41 * 42 * Thanks goes to: 43 * 44 * Shaharil @ SCAN Associates whom relentlessly providing me the 45 * mind blowing Acer Ferrari 4002 WLMi with this ATI IXP hardware. 46 * 47 * Reinoud Zandijk <reinoud@NetBSD.org> (auixp), which this driver is 48 * largely based upon although large part of it has been reworked. His 49 * driver is the primary reference and pretty much well documented. 50 * 51 * Takashi Iwai (ALSA snd-atiixp), for register definitions and some 52 * random ninja hackery. 53 */ 54 55 #include <dev/sound/pcm/sound.h> 56 #include <dev/sound/pcm/ac97.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <sys/sysctl.h> 61 #include <sys/endian.h> 62 63 #include <dev/sound/pci/atiixp.h> 64 65 SND_DECLARE_FILE("$FreeBSD$"); 66 67 68 struct atiixp_dma_op { 69 uint32_t addr; 70 uint16_t status; 71 uint16_t size; 72 uint32_t next; 73 }; 74 75 struct atiixp_info; 76 77 struct atiixp_chinfo { 78 struct snd_dbuf *buffer; 79 struct pcm_channel *channel; 80 struct atiixp_info *parent; 81 struct atiixp_dma_op *sgd_table; 82 bus_addr_t sgd_addr; 83 uint32_t enable_bit, flush_bit, linkptr_bit, dma_dt_cur_bit; 84 uint32_t dma_segs; 85 int caps_32bit, dir; 86 }; 87 88 struct atiixp_info { 89 device_t dev; 90 91 bus_space_tag_t st; 92 bus_space_handle_t sh; 93 bus_dma_tag_t parent_dmat; 94 bus_dma_tag_t sgd_dmat; 95 bus_dmamap_t sgd_dmamap; 96 bus_addr_t sgd_addr; 97 98 struct resource *reg, *irq; 99 int regtype, regid, irqid; 100 void *ih; 101 struct ac97_info *codec; 102 103 struct atiixp_chinfo pch; 104 struct atiixp_chinfo rch; 105 struct atiixp_dma_op *sgd_table; 106 struct intr_config_hook delayed_attach; 107 108 uint32_t bufsz; 109 uint32_t codec_not_ready_bits, codec_idx, codec_found; 110 uint32_t dma_segs; 111 int registered_channels; 112 113 struct mtx *lock; 114 }; 115 116 #define atiixp_rd(_sc, _reg) \ 117 bus_space_read_4((_sc)->st, (_sc)->sh, _reg) 118 #define atiixp_wr(_sc, _reg, _val) \ 119 bus_space_write_4((_sc)->st, (_sc)->sh, _reg, _val) 120 121 #define atiixp_lock(_sc) snd_mtxlock((_sc)->lock) 122 #define atiixp_unlock(_sc) snd_mtxunlock((_sc)->lock) 123 #define atiixp_assert(_sc) snd_mtxassert((_sc)->lock) 124 125 static uint32_t atiixp_fmt_32bit[] = { 126 AFMT_STEREO | AFMT_S16_LE, 127 #ifdef AFMT_S32_LE 128 AFMT_STEREO | AFMT_S32_LE, 129 #endif 130 0 131 }; 132 133 static uint32_t atiixp_fmt[] = { 134 AFMT_STEREO | AFMT_S16_LE, 135 0 136 }; 137 138 static struct pcmchan_caps atiixp_caps_32bit = { 139 ATI_IXP_BASE_RATE, 140 ATI_IXP_BASE_RATE, 141 atiixp_fmt_32bit, 0 142 }; 143 144 static struct pcmchan_caps atiixp_caps = { 145 ATI_IXP_BASE_RATE, 146 ATI_IXP_BASE_RATE, 147 atiixp_fmt, 0 148 }; 149 150 static const struct { 151 uint16_t vendor; 152 uint16_t devid; 153 char *desc; 154 } atiixp_hw[] = { 155 { ATI_VENDOR_ID, ATI_IXP_200_ID, "ATI IXP 200" }, 156 { ATI_VENDOR_ID, ATI_IXP_300_ID, "ATI IXP 300" }, 157 { ATI_VENDOR_ID, ATI_IXP_400_ID, "ATI IXP 400" }, 158 }; 159 160 static void atiixp_enable_interrupts(struct atiixp_info *); 161 static void atiixp_disable_interrupts(struct atiixp_info *); 162 static void atiixp_reset_aclink(struct atiixp_info *); 163 static void atiixp_flush_dma(struct atiixp_info *, struct atiixp_chinfo *); 164 static void atiixp_enable_dma(struct atiixp_info *, struct atiixp_chinfo *); 165 static void atiixp_disable_dma(struct atiixp_info *, struct atiixp_chinfo *); 166 167 static int atiixp_waitready_codec(struct atiixp_info *); 168 static int atiixp_rdcd(kobj_t, void *, int); 169 static int atiixp_wrcd(kobj_t, void *, int, uint32_t); 170 171 static void *atiixp_chan_init(kobj_t, void *, struct snd_dbuf *, 172 struct pcm_channel *, int); 173 static int atiixp_chan_setformat(kobj_t, void *, uint32_t); 174 static int atiixp_chan_setspeed(kobj_t, void *, uint32_t); 175 static int atiixp_chan_setblocksize(kobj_t, void *, uint32_t); 176 static void atiixp_buildsgdt(struct atiixp_chinfo *); 177 static int atiixp_chan_trigger(kobj_t, void *, int); 178 static int atiixp_chan_getptr(kobj_t, void *); 179 static struct pcmchan_caps *atiixp_chan_getcaps(kobj_t, void *); 180 181 static void atiixp_intr(void *); 182 static void atiixp_dma_cb(void *, bus_dma_segment_t *, int, int); 183 static void atiixp_chip_pre_init(struct atiixp_info *); 184 static void atiixp_chip_post_init(void *); 185 static int atiixp_pci_probe(device_t); 186 static int atiixp_pci_attach(device_t); 187 static int atiixp_pci_detach(device_t); 188 189 /* 190 * ATI IXP helper functions 191 */ 192 static void 193 atiixp_enable_interrupts(struct atiixp_info *sc) 194 { 195 uint32_t value; 196 197 /* clear all pending */ 198 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 199 200 /* enable all relevant interrupt sources we can handle */ 201 value = atiixp_rd(sc, ATI_REG_IER); 202 203 value |= ATI_REG_IER_IO_STATUS_EN; 204 205 /* 206 * Disable / ignore internal xrun/spdf interrupt flags 207 * since it doesn't interest us (for now). 208 */ 209 #if 0 210 value |= ATI_REG_IER_IN_XRUN_EN; 211 value |= ATI_REG_IER_OUT_XRUN_EN; 212 213 value |= ATI_REG_IER_SPDF_XRUN_EN; 214 value |= ATI_REG_IER_SPDF_STATUS_EN; 215 #endif 216 217 atiixp_wr(sc, ATI_REG_IER, value); 218 } 219 220 static void 221 atiixp_disable_interrupts(struct atiixp_info *sc) 222 { 223 /* disable all interrupt sources */ 224 atiixp_wr(sc, ATI_REG_IER, 0); 225 226 /* clear all pending */ 227 atiixp_wr(sc, ATI_REG_ISR, 0xffffffff); 228 } 229 230 static void 231 atiixp_reset_aclink(struct atiixp_info *sc) 232 { 233 uint32_t value, timeout; 234 235 /* if power is down, power it up */ 236 value = atiixp_rd(sc, ATI_REG_CMD); 237 if (value & ATI_REG_CMD_POWERDOWN) { 238 /* explicitly enable power */ 239 value &= ~ATI_REG_CMD_POWERDOWN; 240 atiixp_wr(sc, ATI_REG_CMD, value); 241 242 /* have to wait at least 10 usec for it to initialise */ 243 DELAY(20); 244 }; 245 246 /* perform a soft reset */ 247 value = atiixp_rd(sc, ATI_REG_CMD); 248 value |= ATI_REG_CMD_AC_SOFT_RESET; 249 atiixp_wr(sc, ATI_REG_CMD, value); 250 251 /* need to read the CMD reg and wait aprox. 10 usec to init */ 252 value = atiixp_rd(sc, ATI_REG_CMD); 253 DELAY(20); 254 255 /* clear soft reset flag again */ 256 value = atiixp_rd(sc, ATI_REG_CMD); 257 value &= ~ATI_REG_CMD_AC_SOFT_RESET; 258 atiixp_wr(sc, ATI_REG_CMD, value); 259 260 /* check if the ac-link is working; reset device otherwise */ 261 timeout = 10; 262 value = atiixp_rd(sc, ATI_REG_CMD); 263 while (!(value & ATI_REG_CMD_ACLINK_ACTIVE) 264 && --timeout) { 265 device_printf(sc->dev, "not up; resetting aclink hardware\n"); 266 267 /* dip aclink reset but keep the acsync */ 268 value &= ~ATI_REG_CMD_AC_RESET; 269 value |= ATI_REG_CMD_AC_SYNC; 270 atiixp_wr(sc, ATI_REG_CMD, value); 271 272 /* need to read CMD again and wait again (clocking in issue?) */ 273 value = atiixp_rd(sc, ATI_REG_CMD); 274 DELAY(20); 275 276 /* assert aclink reset again */ 277 value = atiixp_rd(sc, ATI_REG_CMD); 278 value |= ATI_REG_CMD_AC_RESET; 279 atiixp_wr(sc, ATI_REG_CMD, value); 280 281 /* check if its active now */ 282 value = atiixp_rd(sc, ATI_REG_CMD); 283 }; 284 285 if (timeout == 0) 286 device_printf(sc->dev, "giving up aclink reset\n"); 287 if (timeout != 10) 288 device_printf(sc->dev, "aclink hardware reset successful\n"); 289 290 /* assert reset and sync for safety */ 291 value = atiixp_rd(sc, ATI_REG_CMD); 292 value |= ATI_REG_CMD_AC_SYNC | ATI_REG_CMD_AC_RESET; 293 atiixp_wr(sc, ATI_REG_CMD, value); 294 } 295 296 static void 297 atiixp_flush_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 298 { 299 atiixp_wr(sc, ATI_REG_FIFO_FLUSH, ch->flush_bit); 300 } 301 302 static void 303 atiixp_enable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 304 { 305 uint32_t value; 306 307 value = atiixp_rd(sc, ATI_REG_CMD); 308 if (!(value & ch->enable_bit)) { 309 value |= ch->enable_bit; 310 atiixp_wr(sc, ATI_REG_CMD, value); 311 } 312 } 313 314 static void 315 atiixp_disable_dma(struct atiixp_info *sc, struct atiixp_chinfo *ch) 316 { 317 uint32_t value; 318 319 value = atiixp_rd(sc, ATI_REG_CMD); 320 if (value & ch->enable_bit) { 321 value &= ~ch->enable_bit; 322 atiixp_wr(sc, ATI_REG_CMD, value); 323 } 324 } 325 326 /* 327 * AC97 interface 328 */ 329 static int 330 atiixp_waitready_codec(struct atiixp_info *sc) 331 { 332 int timeout = 500; 333 334 do { 335 if ((atiixp_rd(sc, ATI_REG_PHYS_OUT_ADDR) & 336 ATI_REG_PHYS_OUT_ADDR_EN) == 0) 337 return 0; 338 DELAY(1); 339 } while (timeout--); 340 341 return -1; 342 } 343 344 static int 345 atiixp_rdcd(kobj_t obj, void *devinfo, int reg) 346 { 347 struct atiixp_info *sc = devinfo; 348 uint32_t data; 349 int timeout; 350 351 if (atiixp_waitready_codec(sc)) 352 return -1; 353 354 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 355 ATI_REG_PHYS_OUT_ADDR_EN | 356 ATI_REG_PHYS_OUT_RW | sc->codec_idx; 357 358 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 359 360 if (atiixp_waitready_codec(sc)) 361 return -1; 362 363 timeout = 500; 364 do { 365 data = atiixp_rd(sc, ATI_REG_PHYS_IN_ADDR); 366 if (data & ATI_REG_PHYS_IN_READ_FLAG) 367 return data >> ATI_REG_PHYS_IN_DATA_SHIFT; 368 DELAY(1); 369 } while (timeout--); 370 371 if (reg < 0x7c) 372 device_printf(sc->dev, "codec read timeout! (reg 0x%x)\n", reg); 373 374 return -1; 375 } 376 377 static int 378 atiixp_wrcd(kobj_t obj, void *devinfo, int reg, uint32_t data) 379 { 380 struct atiixp_info *sc = devinfo; 381 382 if (atiixp_waitready_codec(sc)) 383 return -1; 384 385 data = (data << ATI_REG_PHYS_OUT_DATA_SHIFT) | 386 (((uint32_t)reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 387 ATI_REG_PHYS_OUT_ADDR_EN | sc->codec_idx; 388 389 atiixp_wr(sc, ATI_REG_PHYS_OUT_ADDR, data); 390 391 return 0; 392 } 393 394 static kobj_method_t atiixp_ac97_methods[] = { 395 KOBJMETHOD(ac97_read, atiixp_rdcd), 396 KOBJMETHOD(ac97_write, atiixp_wrcd), 397 { 0, 0 } 398 }; 399 AC97_DECLARE(atiixp_ac97); 400 401 /* 402 * Playback / Record channel interface 403 */ 404 static void * 405 atiixp_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 406 struct pcm_channel *c, int dir) 407 { 408 struct atiixp_info *sc = devinfo; 409 struct atiixp_chinfo *ch; 410 int num; 411 412 atiixp_lock(sc); 413 414 if (dir == PCMDIR_PLAY) { 415 ch = &sc->pch; 416 ch->linkptr_bit = ATI_REG_OUT_DMA_LINKPTR; 417 ch->enable_bit = ATI_REG_CMD_OUT_DMA_EN | ATI_REG_CMD_SEND_EN; 418 ch->flush_bit = ATI_REG_FIFO_OUT_FLUSH; 419 ch->dma_dt_cur_bit = ATI_REG_OUT_DMA_DT_CUR; 420 /* Native 32bit playback working properly */ 421 ch->caps_32bit = 1; 422 } else { 423 ch = &sc->rch; 424 ch->linkptr_bit = ATI_REG_IN_DMA_LINKPTR; 425 ch->enable_bit = ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_RECEIVE_EN; 426 ch->flush_bit = ATI_REG_FIFO_IN_FLUSH; 427 ch->dma_dt_cur_bit = ATI_REG_IN_DMA_DT_CUR; 428 /* XXX Native 32bit recording appear to be broken */ 429 ch->caps_32bit = 0; 430 } 431 432 ch->buffer = b; 433 ch->parent = sc; 434 ch->channel = c; 435 ch->dir = dir; 436 ch->dma_segs = sc->dma_segs; 437 438 atiixp_unlock(sc); 439 440 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1) 441 return NULL; 442 443 atiixp_lock(sc); 444 num = sc->registered_channels++; 445 ch->sgd_table = &sc->sgd_table[num * ch->dma_segs]; 446 ch->sgd_addr = sc->sgd_addr + 447 (num * ch->dma_segs * sizeof(struct atiixp_dma_op)); 448 atiixp_disable_dma(sc, ch); 449 atiixp_unlock(sc); 450 451 return ch; 452 } 453 454 static int 455 atiixp_chan_setformat(kobj_t obj, void *data, uint32_t format) 456 { 457 struct atiixp_chinfo *ch = data; 458 struct atiixp_info *sc = ch->parent; 459 uint32_t value; 460 461 atiixp_lock(sc); 462 if (ch->dir == PCMDIR_REC) { 463 value = atiixp_rd(sc, ATI_REG_CMD); 464 value &= ~ATI_REG_CMD_INTERLEAVE_IN; 465 if (ch->caps_32bit == 0 || 466 (format & (AFMT_8BIT|AFMT_16BIT)) != 0) 467 value |= ATI_REG_CMD_INTERLEAVE_IN; 468 atiixp_wr(sc, ATI_REG_CMD, value); 469 } else { 470 value = atiixp_rd(sc, ATI_REG_OUT_DMA_SLOT); 471 value &= ~ATI_REG_OUT_DMA_SLOT_MASK; 472 /* We do not have support for more than 2 channels, _yet_. */ 473 value |= ATI_REG_OUT_DMA_SLOT_BIT(3) | 474 ATI_REG_OUT_DMA_SLOT_BIT(4); 475 value |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 476 atiixp_wr(sc, ATI_REG_OUT_DMA_SLOT, value); 477 value = atiixp_rd(sc, ATI_REG_CMD); 478 value &= ~ATI_REG_CMD_INTERLEAVE_OUT; 479 if (ch->caps_32bit == 0 || 480 (format & (AFMT_8BIT|AFMT_16BIT)) != 0) 481 value |= ATI_REG_CMD_INTERLEAVE_OUT; 482 atiixp_wr(sc, ATI_REG_CMD, value); 483 value = atiixp_rd(sc, ATI_REG_6CH_REORDER); 484 value &= ~ATI_REG_6CH_REORDER_EN; 485 atiixp_wr(sc, ATI_REG_6CH_REORDER, value); 486 } 487 atiixp_unlock(sc); 488 489 return 0; 490 } 491 492 static int 493 atiixp_chan_setspeed(kobj_t obj, void *data, uint32_t spd) 494 { 495 /* XXX We're supposed to do VRA/DRA processing right here */ 496 return ATI_IXP_BASE_RATE; 497 } 498 499 static int 500 atiixp_chan_setblocksize(kobj_t obj, void *data, uint32_t blksz) 501 { 502 struct atiixp_chinfo *ch = data; 503 struct atiixp_info *sc = ch->parent; 504 505 if (blksz > (sc->bufsz / ch->dma_segs)) 506 blksz = sc->bufsz / ch->dma_segs; 507 508 sndbuf_resize(ch->buffer, ch->dma_segs, blksz); 509 510 return sndbuf_getblksz(ch->buffer); 511 } 512 513 static void 514 atiixp_buildsgdt(struct atiixp_chinfo *ch) 515 { 516 uint32_t addr, blksz; 517 int i; 518 519 addr = sndbuf_getbufaddr(ch->buffer); 520 blksz = sndbuf_getblksz(ch->buffer); 521 522 for (i = 0; i < ch->dma_segs; i++) { 523 ch->sgd_table[i].addr = htole32(addr + (i * blksz)); 524 ch->sgd_table[i].status = htole16(0); 525 ch->sgd_table[i].size = htole16(blksz >> 2); 526 ch->sgd_table[i].next = htole32((uint32_t)ch->sgd_addr + 527 (((i + 1) % ch->dma_segs) * 528 sizeof(struct atiixp_dma_op))); 529 } 530 } 531 532 static int 533 atiixp_chan_trigger(kobj_t obj, void *data, int go) 534 { 535 struct atiixp_chinfo *ch = data; 536 struct atiixp_info *sc = ch->parent; 537 uint32_t value; 538 539 atiixp_lock(sc); 540 541 switch (go) { 542 case PCMTRIG_START: 543 atiixp_flush_dma(sc, ch); 544 atiixp_buildsgdt(ch); 545 atiixp_wr(sc, ch->linkptr_bit, 0); 546 atiixp_enable_dma(sc, ch); 547 atiixp_wr(sc, ch->linkptr_bit, 548 (uint32_t)ch->sgd_addr | ATI_REG_LINKPTR_EN); 549 break; 550 case PCMTRIG_STOP: 551 case PCMTRIG_ABORT: 552 atiixp_disable_dma(sc, ch); 553 atiixp_flush_dma(sc, ch); 554 break; 555 default: 556 atiixp_unlock(sc); 557 return 0; 558 break; 559 } 560 561 /* Update bus busy status */ 562 value = atiixp_rd(sc, ATI_REG_IER); 563 if (atiixp_rd(sc, ATI_REG_CMD) & ( 564 ATI_REG_CMD_SEND_EN | ATI_REG_CMD_RECEIVE_EN | 565 ATI_REG_CMD_SPDF_OUT_EN)) 566 value |= ATI_REG_IER_SET_BUS_BUSY; 567 else 568 value &= ~ATI_REG_IER_SET_BUS_BUSY; 569 atiixp_wr(sc, ATI_REG_IER, value); 570 571 atiixp_unlock(sc); 572 573 return 0; 574 } 575 576 static int 577 atiixp_chan_getptr(kobj_t obj, void *data) 578 { 579 struct atiixp_chinfo *ch = data; 580 struct atiixp_info *sc = ch->parent; 581 uint32_t ptr; 582 583 atiixp_lock(sc); 584 ptr = atiixp_rd(sc, ch->dma_dt_cur_bit); 585 atiixp_unlock(sc); 586 587 return ptr; 588 } 589 590 static struct pcmchan_caps * 591 atiixp_chan_getcaps(kobj_t obj, void *data) 592 { 593 struct atiixp_chinfo *ch = data; 594 595 if (ch->caps_32bit) 596 return &atiixp_caps_32bit; 597 return &atiixp_caps; 598 } 599 600 static kobj_method_t atiixp_chan_methods[] = { 601 KOBJMETHOD(channel_init, atiixp_chan_init), 602 KOBJMETHOD(channel_setformat, atiixp_chan_setformat), 603 KOBJMETHOD(channel_setspeed, atiixp_chan_setspeed), 604 KOBJMETHOD(channel_setblocksize, atiixp_chan_setblocksize), 605 KOBJMETHOD(channel_trigger, atiixp_chan_trigger), 606 KOBJMETHOD(channel_getptr, atiixp_chan_getptr), 607 KOBJMETHOD(channel_getcaps, atiixp_chan_getcaps), 608 { 0, 0 } 609 }; 610 CHANNEL_DECLARE(atiixp_chan); 611 612 /* 613 * PCI driver interface 614 */ 615 static void 616 atiixp_intr(void *p) 617 { 618 struct atiixp_info *sc = p; 619 uint32_t status, enable, detected_codecs; 620 621 atiixp_lock(sc); 622 status = atiixp_rd(sc, ATI_REG_ISR); 623 624 if (status == 0) { 625 atiixp_unlock(sc); 626 return; 627 } 628 629 if (status & ATI_REG_ISR_IN_STATUS) { 630 atiixp_unlock(sc); 631 chn_intr(sc->rch.channel); 632 atiixp_lock(sc); 633 } 634 if (status & ATI_REG_ISR_OUT_STATUS) { 635 atiixp_unlock(sc); 636 chn_intr(sc->pch.channel); 637 atiixp_lock(sc); 638 } 639 640 #if 0 641 if (status & ATI_REG_ISR_IN_XRUN) { 642 device_printf(sc->dev, 643 "Recieve IN XRUN interrupt\n"); 644 } 645 if (status & ATI_REG_ISR_OUT_XRUN) { 646 device_printf(sc->dev, 647 "Recieve OUT XRUN interrupt\n"); 648 } 649 #endif 650 651 if (status & CODEC_CHECK_BITS) { 652 /* mark missing codecs as not ready */ 653 detected_codecs = status & CODEC_CHECK_BITS; 654 sc->codec_not_ready_bits |= detected_codecs; 655 656 /* disable detected interupt sources */ 657 enable = atiixp_rd(sc, ATI_REG_IER); 658 enable &= ~detected_codecs; 659 atiixp_wr(sc, ATI_REG_IER, enable); 660 } 661 662 /* acknowledge */ 663 atiixp_wr(sc, ATI_REG_ISR, status); 664 atiixp_unlock(sc); 665 } 666 667 static void 668 atiixp_dma_cb(void *p, bus_dma_segment_t *bds, int a, int b) 669 { 670 struct atiixp_info *sc = (struct atiixp_info *)p; 671 sc->sgd_addr = bds->ds_addr; 672 } 673 674 static void 675 atiixp_chip_pre_init(struct atiixp_info *sc) 676 { 677 uint32_t value; 678 679 atiixp_lock(sc); 680 681 /* disable interrupts */ 682 atiixp_disable_interrupts(sc); 683 684 /* clear all DMA enables (preserving rest of settings) */ 685 value = atiixp_rd(sc, ATI_REG_CMD); 686 value &= ~(ATI_REG_CMD_IN_DMA_EN | ATI_REG_CMD_OUT_DMA_EN | 687 ATI_REG_CMD_SPDF_OUT_EN ); 688 atiixp_wr(sc, ATI_REG_CMD, value); 689 690 /* reset aclink */ 691 atiixp_reset_aclink(sc); 692 693 sc->codec_not_ready_bits = 0; 694 695 /* enable all codecs to interrupt as well as the new frame interrupt */ 696 atiixp_wr(sc, ATI_REG_IER, CODEC_CHECK_BITS); 697 698 atiixp_unlock(sc); 699 } 700 701 static void 702 atiixp_chip_post_init(void *arg) 703 { 704 struct atiixp_info *sc = (struct atiixp_info *)arg; 705 int i, timeout, found; 706 char status[SND_STATUSLEN]; 707 708 atiixp_lock(sc); 709 710 if (sc->delayed_attach.ich_func) { 711 config_intrhook_disestablish(&sc->delayed_attach); 712 sc->delayed_attach.ich_func = NULL; 713 } 714 715 /* wait for the interrupts to happen */ 716 timeout = 100; /* 100.000 usec -> 0.1 sec */ 717 718 while (--timeout) { 719 atiixp_unlock(sc); 720 DELAY(1000); 721 atiixp_lock(sc); 722 if (sc->codec_not_ready_bits) 723 break; 724 } 725 726 atiixp_disable_interrupts(sc); 727 728 if (timeout == 0) { 729 device_printf(sc->dev, 730 "WARNING: timeout during codec detection; " 731 "codecs might be present but haven't interrupted\n"); 732 atiixp_unlock(sc); 733 return; 734 } 735 736 found = 0; 737 738 /* 739 * ATI IXP can have upto 3 codecs, but single codec should be 740 * suffice for now. 741 */ 742 if (!(sc->codec_not_ready_bits & 743 ATI_REG_ISR_CODEC0_NOT_READY)) { 744 /* codec 0 present */ 745 sc->codec_found++; 746 sc->codec_idx = 0; 747 found++; 748 } 749 750 if (!(sc->codec_not_ready_bits & 751 ATI_REG_ISR_CODEC1_NOT_READY)) { 752 /* codec 1 present */ 753 sc->codec_found++; 754 } 755 756 if (!(sc->codec_not_ready_bits & 757 ATI_REG_ISR_CODEC2_NOT_READY)) { 758 /* codec 2 present */ 759 sc->codec_found++; 760 } 761 762 atiixp_unlock(sc); 763 764 if (found == 0) 765 return; 766 767 /* create/init mixer */ 768 sc->codec = AC97_CREATE(sc->dev, sc, atiixp_ac97); 769 if (sc->codec == NULL) 770 goto postinitbad; 771 772 mixer_init(sc->dev, ac97_getmixerclass(), sc->codec); 773 774 if (pcm_register(sc->dev, sc, ATI_IXP_NPCHAN, ATI_IXP_NRCHAN)) 775 goto postinitbad; 776 777 for (i = 0; i < ATI_IXP_NPCHAN; i++) 778 pcm_addchan(sc->dev, PCMDIR_PLAY, &atiixp_chan_class, sc); 779 for (i = 0; i < ATI_IXP_NRCHAN; i++) 780 pcm_addchan(sc->dev, PCMDIR_REC, &atiixp_chan_class, sc); 781 782 snprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s", 783 rman_get_start(sc->reg), rman_get_start(sc->irq), 784 PCM_KLDSTRING(snd_atiixp)); 785 786 pcm_setstatus(sc->dev, status); 787 788 atiixp_lock(sc); 789 atiixp_enable_interrupts(sc); 790 atiixp_unlock(sc); 791 792 return; 793 794 postinitbad: 795 if (sc->codec) 796 ac97_destroy(sc->codec); 797 if (sc->ih) 798 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 799 if (sc->reg) 800 bus_release_resource(sc->dev, sc->regtype, sc->regid, sc->reg); 801 if (sc->irq) 802 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irqid, sc->irq); 803 if (sc->parent_dmat) 804 bus_dma_tag_destroy(sc->parent_dmat); 805 if (sc->sgd_dmamap) 806 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 807 if (sc->sgd_dmat) 808 bus_dma_tag_destroy(sc->sgd_dmat); 809 if (sc->lock) 810 snd_mtxfree(sc->lock); 811 free(sc, M_DEVBUF); 812 } 813 814 static int 815 atiixp_pci_probe(device_t dev) 816 { 817 int i; 818 uint16_t devid, vendor; 819 820 vendor = pci_get_vendor(dev); 821 devid = pci_get_device(dev); 822 for (i = 0; i < sizeof(atiixp_hw)/sizeof(atiixp_hw[0]); i++) { 823 if (vendor == atiixp_hw[i].vendor && 824 devid == atiixp_hw[i].devid) { 825 device_set_desc(dev, atiixp_hw[i].desc); 826 return BUS_PROBE_DEFAULT; 827 } 828 } 829 830 return ENXIO; 831 } 832 833 static int 834 atiixp_pci_attach(device_t dev) 835 { 836 struct atiixp_info *sc; 837 int i; 838 839 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 840 device_printf(dev, "cannot allocate softc\n"); 841 return ENXIO; 842 } 843 844 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 845 sc->dev = dev; 846 /* 847 * Default DMA segments per playback / recording channel 848 */ 849 sc->dma_segs = ATI_IXP_DMA_CHSEGS; 850 851 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 852 pci_enable_busmaster(dev); 853 854 sc->regid = PCIR_BAR(0); 855 sc->regtype = SYS_RES_MEMORY; 856 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 857 RF_ACTIVE); 858 859 if (!sc->reg) { 860 device_printf(dev, "unable to allocate register space\n"); 861 goto bad; 862 } 863 864 sc->st = rman_get_bustag(sc->reg); 865 sc->sh = rman_get_bushandle(sc->reg); 866 867 sc->bufsz = pcm_getbuffersize(dev, 4096, ATI_IXP_DEFAULT_BUFSZ, 65536); 868 869 sc->irqid = 0; 870 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 871 RF_ACTIVE | RF_SHAREABLE); 872 if (!sc->irq || 873 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, 874 atiixp_intr, sc, &sc->ih)) { 875 device_printf(dev, "unable to map interrupt\n"); 876 goto bad; 877 } 878 879 /* 880 * Let the user choose the best DMA segments. 881 */ 882 if (resource_int_value(device_get_name(dev), 883 device_get_unit(dev), "dma_segs", 884 &i) == 0) { 885 if (i < ATI_IXP_DMA_CHSEGS_MIN) 886 i = ATI_IXP_DMA_CHSEGS_MIN; 887 if (i > ATI_IXP_DMA_CHSEGS_MAX) 888 i = ATI_IXP_DMA_CHSEGS_MAX; 889 /* round the value */ 890 sc->dma_segs = i & ~1; 891 } 892 893 /* 894 * DMA tag for scatter-gather buffers and link pointers 895 */ 896 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 897 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 898 /*highaddr*/BUS_SPACE_MAXADDR, 899 /*filter*/NULL, /*filterarg*/NULL, 900 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff, 901 /*flags*/0, /*lockfunc*/NULL, 902 /*lockarg*/NULL, &sc->parent_dmat) != 0) { 903 device_printf(dev, "unable to create dma tag\n"); 904 goto bad; 905 } 906 907 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 908 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 909 /*highaddr*/BUS_SPACE_MAXADDR, 910 /*filter*/NULL, /*filterarg*/NULL, 911 /*maxsize*/sc->dma_segs * ATI_IXP_NCHANS * 912 sizeof(struct atiixp_dma_op), 913 /*nsegments*/1, /*maxsegz*/0x3ffff, 914 /*flags*/0, /*lockfunc*/NULL, 915 /*lockarg*/NULL, &sc->sgd_dmat) != 0) { 916 device_printf(dev, "unable to create dma tag\n"); 917 goto bad; 918 } 919 920 if (bus_dmamem_alloc(sc->sgd_dmat, (void **)&sc->sgd_table, 921 BUS_DMA_NOWAIT, &sc->sgd_dmamap) == -1) 922 goto bad; 923 924 if (bus_dmamap_load(sc->sgd_dmat, sc->sgd_dmamap, sc->sgd_table, 925 sc->dma_segs * ATI_IXP_NCHANS * 926 sizeof(struct atiixp_dma_op), 927 atiixp_dma_cb, sc, 0)) 928 goto bad; 929 930 931 atiixp_chip_pre_init(sc); 932 933 sc->delayed_attach.ich_func = atiixp_chip_post_init; 934 sc->delayed_attach.ich_arg = sc; 935 if (cold == 0 || 936 config_intrhook_establish(&sc->delayed_attach) != 0) { 937 sc->delayed_attach.ich_func = NULL; 938 atiixp_chip_post_init(sc); 939 } 940 941 return 0; 942 943 bad: 944 if (sc->codec) 945 ac97_destroy(sc->codec); 946 if (sc->ih) 947 bus_teardown_intr(dev, sc->irq, sc->ih); 948 if (sc->reg) 949 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 950 if (sc->irq) 951 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 952 if (sc->parent_dmat) 953 bus_dma_tag_destroy(sc->parent_dmat); 954 if (sc->sgd_dmamap) 955 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 956 if (sc->sgd_dmat) 957 bus_dma_tag_destroy(sc->sgd_dmat); 958 if (sc->lock) 959 snd_mtxfree(sc->lock); 960 free(sc, M_DEVBUF); 961 962 return ENXIO; 963 } 964 965 static int 966 atiixp_pci_detach(device_t dev) 967 { 968 int r; 969 struct atiixp_info *sc; 970 971 r = pcm_unregister(dev); 972 if (r) 973 return r; 974 975 sc = pcm_getdevinfo(dev); 976 977 atiixp_disable_interrupts(sc); 978 979 bus_teardown_intr(dev, sc->irq, sc->ih); 980 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 981 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 982 bus_dma_tag_destroy(sc->parent_dmat); 983 bus_dmamap_unload(sc->sgd_dmat, sc->sgd_dmamap); 984 bus_dma_tag_destroy(sc->sgd_dmat); 985 snd_mtxfree(sc->lock); 986 free(sc, M_DEVBUF); 987 988 return 0; 989 } 990 991 static device_method_t atiixp_methods[] = { 992 DEVMETHOD(device_probe, atiixp_pci_probe), 993 DEVMETHOD(device_attach, atiixp_pci_attach), 994 DEVMETHOD(device_detach, atiixp_pci_detach), 995 { 0, 0 } 996 }; 997 998 static driver_t atiixp_driver = { 999 "pcm", 1000 atiixp_methods, 1001 PCM_SOFTC_SIZE, 1002 }; 1003 1004 DRIVER_MODULE(snd_atiixp, pci, atiixp_driver, pcm_devclass, 0, 0); 1005 MODULE_DEPEND(snd_atiixp, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1006 MODULE_VERSION(snd_atiixp, 1); 1007