1 /*- 2 * Copyright (c) 2006 Benno Rice. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * $FreeBSD$ 25 * 26 */ 27 28 #ifndef _IF_SMCREG_H_ 29 #define _IF_SMCREG_H_ 30 31 /* All Banks, Offset 0xe: Bank Select Register */ 32 #define BSR 0xe 33 #define BSR_BANK_MASK 0x0007 /* Which bank is currently selected */ 34 #define BSR_IDENTIFY 0x3300 /* Static value for identification */ 35 #define BSR_IDENTIFY_MASK 0xff00 36 37 /* Bank 0, Offset 0x0: Transmit Control Register */ 38 #define TCR 0x0 39 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */ 40 #define TCR_LOOP 0x0002 /* Put the PHY into loopback mode */ 41 #define TCR_FORCOL 0x0004 /* Force a collision */ 42 #define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */ 43 #define TCR_NOCRC 0x0100 /* Disable/enable CRC */ 44 #define TCR_MON_CSN 0x0400 /* Monitor carrier signal */ 45 #define TCR_FDUPLX 0x0800 /* Enable/disable full duplex */ 46 #define TCR_STP_SQET 0x1000 /* Stop TX on signal quality error */ 47 #define TCR_EPH_LOOP 0x2000 /* Internal loopback */ 48 #define TCR_SWFDUP 0x8000 /* Switched full duplex */ 49 50 /* Bank 0, Offset 0x2: EPH Status Register */ 51 #define EPHSR 0x2 52 #define EPHSR_TX_SUC 0x0001 /* Last TX was successful */ 53 #define EPHSR_SNGLCOL 0x0002 /* Single collision on last TX */ 54 #define EPHSR_MULCOL 0x0004 /* Multiple collisions on last TX */ 55 #define EPHSR_LTX_MULT 0x0008 /* Last TX was multicast */ 56 #define EPHSR_16COL 0x0010 /* 16 collisions on last TX */ 57 #define EPHSR_SQET 0x0020 /* Signal quality error test */ 58 #define EPHSR_LTX_BRD 0x0040 /* Last TX was broadcast */ 59 #define EPHSR_TX_DEFR 0x0080 /* Transmit deferred */ 60 #define EPHSR_LATCOL 0x0200 /* Late collision on last TX */ 61 #define EPHSR_LOST_CARR 0x0400 /* Lost carrier sense */ 62 #define EPHSR_EXC_DEF 0x0800 /* Excessive deferral */ 63 #define EPHSR_CTR_ROL 0x1000 /* Counter rollover */ 64 #define EPHSR_LINK_OK 0x4000 /* Inverse of nLNK pin */ 65 #define EPHSR_TXUNRN 0x8000 /* Transmit underrun */ 66 67 /* Bank 0, Offset 0x4: Receive Control Register */ 68 #define RCR 0x4 69 #define RCR_RX_ABORT 0x0001 /* RX aborted */ 70 #define RCR_PRMS 0x0002 /* Enable/disable promiscuous mode */ 71 #define RCR_ALMUL 0x0004 /* Accept all multicast frames */ 72 #define RCR_RXEN 0x0100 /* Enable/disable receiver */ 73 #define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */ 74 #define RCR_ABORT_ENB 0x2000 /* Abort RX on collision */ 75 #define RCR_FILT_CAR 0x4000 /* Filter leading 12 bits of carrier */ 76 #define RCR_SOFT_RST 0x8000 /* Software reset */ 77 78 /* Bank 0, Offset 0x6: Counter Register */ 79 #define ECR 0x6 80 #define ECR_SNGLCOL_MASK 0x000f /* Single collisions */ 81 #define ECR_SNGLCOL_SHIFT 0 82 #define ECR_MULCOL_MASK 0x00f0 /* Multiple collisions */ 83 #define ECR_MULCOL_SHIFT 4 84 #define ECR_TX_DEFR_MASK 0x0f00 /* Transmit deferrals */ 85 #define ECR_TX_DEFR_SHIFT 8 86 #define ECR_EXC_DEF_MASK 0xf000 /* Excessive deferrals */ 87 #define ECR_EXC_DEF_SHIFT 12 88 89 /* Bank 0, Offset 0x8: Memory Information Register */ 90 #define MIR 0x8 91 #define MIR_SIZE_MASK 0x00ff /* Memory size (2k pages) */ 92 #define MIR_SIZE_SHIFT 0 93 #define MIR_FREE_MASK 0xff00 /* Memory free (2k pages) */ 94 #define MIR_FREE_SHIFT 8 95 #define MIR_PAGE_SIZE 2048 96 97 /* Bank 0, Offset 0xa: Receive/PHY Control Reigster */ 98 #define RPCR 0xa 99 #define RPCR_ANEG 0x0800 /* Put PHY in autonegotiation mode */ 100 #define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */ 101 #define RPCR_SPEED 0x2000 /* Manual speed selection */ 102 #define RPCR_LSA_MASK 0x00e0 /* Select LED A function */ 103 #define RPCR_LSA_SHIFT 5 104 #define RPCR_LSB_MASK 0x001c /* Select LED B function */ 105 #define RPCR_LSB_SHIFT 2 106 #define RPCR_LED_LINK_ANY 0x0 /* 10baseT or 100baseTX link detected */ 107 #define RPCR_LED_LINK_10 0x2 /* 10baseT link detected */ 108 #define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detected */ 109 #define RPCR_LED_LINK_100 0x5 /* 100baseTX link detected */ 110 #define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */ 111 #define RPCR_LED_ACT_RX 0x6 /* RX activity detected */ 112 #define RPCR_LED_ACT_TX 0x7 /* TX activity detected */ 113 114 /* Bank 1, Offset 0x0: Configuration Register */ 115 #define CR 0x0 116 #define CR_EXT_PHY 0x0200 /* Enable/disable external PHY */ 117 #define CR_GPCNTRL 0x0400 /* Inverse drives nCNTRL pin */ 118 #define CR_NO_WAIT 0x1000 /* Do not request additional waits */ 119 #define CR_EPH_POWER_EN 0x8000 /* Disable/enable low power mode */ 120 121 /* Bank 1, Offset 0x2: Base Address Register */ 122 #define BAR 0x2 123 #define BAR_HIGH_MASK 0xe000 124 #define BAR_LOW_MASK 0x1f00 125 #define BAR_LOW_SHIFT 4 126 #define BAR_ADDRESS(val) \ 127 ((val & BAR_HIGH_MASK) | ((val & BAR_LOW_MASK) >> BAR_LOW_SHIFT)) 128 129 /* Bank 1, Offsets 0x4: Individual Address Registers */ 130 #define IAR0 0x4 131 #define IAR1 0x5 132 #define IAR2 0x6 133 #define IAR3 0x7 134 #define IAR4 0x8 135 #define IAR5 0x9 136 137 /* Bank 1, Offset 0xa: General Purpose Register */ 138 #define GPR 0xa 139 140 /* Bank 1, Offset 0xc: Control Register */ 141 #define CTR 0xa 142 #define CTR_STORE 0x0001 /* Store registers to EEPROM */ 143 #define CTR_RELOAD 0x0002 /* Reload registers from EEPROM */ 144 #define CTR_EEPROM_SELECT 0x0004 /* Select registers to store/reload */ 145 #define CTR_TE_ENABLE 0x0020 /* TX error causes EPH interrupt */ 146 #define CTR_CR_ENABLE 0x0040 /* Ctr rollover causes EPH interrupt */ 147 #define CTR_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */ 148 #define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */ 149 #define CTR_RCV_BAD 0x4000 /* Receive/discard bad CRC packets */ 150 151 /* Bank 2, Offset 0x0: MMU Command Register */ 152 #define MMUCR 0x0 153 #define MMUCR_BUSY 0x0001 /* MMU is busy */ 154 #define MMUCR_CMD_NOOP (0<<5) /* No operation */ 155 #define MMUCR_CMD_TX_ALLOC (1<<5) /* Alloc TX memory (256b chunks) */ 156 #define MMUCR_CMD_MMU_RESET (2<<5) /* Reset MMU */ 157 #define MMUCR_CMD_REMOVE (3<<5) /* Remove frame from RX FIFO */ 158 #define MMUCR_CMD_RELEASE (4<<5) /* Remove and release from RX FIFO */ 159 #define MMUCR_CMD_RELEASE_PKT (5<<5) /* Release packet specified in PNR */ 160 #define MMUCR_CMD_ENQUEUE (6<<5) /* Enqueue packet for TX */ 161 #define MMUCR_CMD_TX_RESET (7<<5) /* Reset TX FIFOs */ 162 163 /* Bank 2, Offset 0x2: Packet Number Register */ 164 #define PNR 0x2 165 #define PNR_MASK 0x3fff 166 167 /* Bank 2, Offset 0x3: Allocation Result Register */ 168 #define ARR 0x3 169 #define ARR_FAILED 0x8000 /* Last allocation request failed */ 170 #define ARR_MASK 0x3000 171 172 /* Bank 2, Offset 0x4: FIFO Ports Register */ 173 #define FIFO_TX 0x4 174 #define FIFO_RX 0x5 175 #define FIFO_EMPTY 0x80 /* FIFO empty */ 176 #define FIFO_PACKET_MASK 0x3f /* Packet number mask */ 177 178 /* Bank 2, Offset 0x6: Pointer Register */ 179 #define PTR 0x6 180 #define PTR_MASK 0x07ff /* Address accessible within TX/RX */ 181 #define PTR_NOT_EMPTY 0x0800 /* Write Data FIFO not empty */ 182 #define PTR_ETEN 0x1000 /* Enable early TX underrun detection */ 183 #define PTR_READ 0x2000 /* Set read/write */ 184 #define PTR_AUTO_INCR 0x4000 /* Auto increment on read/write */ 185 #define PTR_RCV 0x8000 /* Read/write to/from RX/TX */ 186 187 /* Bank 2, Offset 0x8: Data Registers */ 188 #define DATA0 0x8 189 #define DATA1 0xa 190 191 /* Bank 2, Offset 0xc: Interrupt Status Registers */ 192 #define IST 0xc /* read only */ 193 #define ACK 0xc /* write only */ 194 #define MSK 0xd 195 196 #define RCV_INT 0x0001 /* RX */ 197 #define TX_INT 0x0002 /* TX */ 198 #define TX_EMPTY_INT 0x0004 /* TX empty */ 199 #define ALLOC_INT 0x0008 /* Allocation complete */ 200 #define RX_OVRN_INT 0x0010 /* RX overrun */ 201 #define EPH_INT 0x0020 /* EPH interrupt */ 202 #define ERCV_INT 0x0040 /* Early RX */ 203 #define MD_INT 0x0080 /* MII */ 204 205 #define IST_PRINTF "\20\01RCV\02TX\03TX_EMPTY\04ALLOC" \ 206 "\05RX_OVRN\06EPH\07ERCV\10MD" 207 208 /* Bank 3, Offset 0x0: Multicast Table Registers */ 209 #define MT 0x0 210 211 /* Bank 3, Offset 0x8: Management Interface */ 212 #define MGMT 0x8 213 #define MGMT_MDO 0x0001 /* MII management output */ 214 #define MGMT_MDI 0x0002 /* MII management input */ 215 #define MGMT_MCLK 0x0004 /* MII management clock */ 216 #define MGMT_MDOE 0x0008 /* MII management output enable */ 217 #define MGMT_MSK_CRS100 0x4000 /* Disable CRS100 detection during TX */ 218 219 /* Bank 3, Offset 0xa: Revision Register */ 220 #define REV 0xa 221 #define REV_CHIP_MASK 0x00f0 /* Chip ID */ 222 #define REV_CHIP_SHIFT 4 223 #define REV_REV_MASK 0x000f /* Revision ID */ 224 #define REV_REV_SHIFT 0 225 226 #define REV_CHIP_9192 3 227 #define REV_CHIP_9194 4 228 #define REV_CHIP_9195 5 229 #define REV_CHIP_9196 6 230 #define REV_CHIP_91100 7 231 #define REV_CHIP_91100FD 8 232 #define REV_CHIP_91110FD 9 233 234 /* Bank 3, Offset 0xc: Early RCV Register */ 235 #define ERCV 0xc 236 #define ERCV_THRESHOLD_MASK 0x001f /* ERCV int threshold (64b chunks) */ 237 #define ERCV_RCV_DISCARD 0x0080 /* Discard packet being received */ 238 239 /* Control Byte */ 240 #define CTRL_CRC 0x10 /* Frame has CRC */ 241 #define CTRL_ODD 0x20 /* Frame has odd byte count */ 242 243 /* Receive Frame Status */ 244 #define RX_MULTCAST 0x0001 /* Frame was multicast */ 245 #define RX_HASH_MASK 0x007e /* Hash value for multicast */ 246 #define RX_HASH_SHIFT 1 247 #define RX_TOOSHORT 0x0400 /* Frame was too short */ 248 #define RX_TOOLNG 0x0800 /* Frame was too long */ 249 #define RX_ODDFRM 0x1000 /* Frame has odd number of bytes */ 250 #define RX_BADCRC 0x2000 /* Frame failed CRC */ 251 #define RX_BROADCAST 0x4000 /* Frame was broadcast */ 252 #define RX_ALGNERR 0x8000 /* Frame had alignment error */ 253 #define RX_LEN_MASK 0x07ff 254 255 /* Length of status word + byte count + control bytes for packets */ 256 #define PKT_CTRL_DATA_LEN 6 257 258 /* Number of times to spin on TX allocations */ 259 #define TX_ALLOC_WAIT_TIME 1000 260 261 #endif /* IF_SMCREG_H_ */ 262