1d70424edSNicolas Souchu /*- 2d70424edSNicolas Souchu * Copyright (c) 1998 Nicolas Souchu 3d70424edSNicolas Souchu * All rights reserved. 4d70424edSNicolas Souchu * 5d70424edSNicolas Souchu * Redistribution and use in source and binary forms, with or without 6d70424edSNicolas Souchu * modification, are permitted provided that the following conditions 7d70424edSNicolas Souchu * are met: 8d70424edSNicolas Souchu * 1. Redistributions of source code must retain the above copyright 9d70424edSNicolas Souchu * notice, this list of conditions and the following disclaimer. 10d70424edSNicolas Souchu * 2. Redistributions in binary form must reproduce the above copyright 11d70424edSNicolas Souchu * notice, this list of conditions and the following disclaimer in the 12d70424edSNicolas Souchu * documentation and/or other materials provided with the distribution. 13d70424edSNicolas Souchu * 14d70424edSNicolas Souchu * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15d70424edSNicolas Souchu * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16d70424edSNicolas Souchu * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17d70424edSNicolas Souchu * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18d70424edSNicolas Souchu * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19d70424edSNicolas Souchu * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20d70424edSNicolas Souchu * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21d70424edSNicolas Souchu * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22d70424edSNicolas Souchu * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23d70424edSNicolas Souchu * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24d70424edSNicolas Souchu * SUCH DAMAGE. 25d70424edSNicolas Souchu * 263ab1f056SNicolas Souchu * $Id: smbconf.c,v 1.1.1.1 1998/09/03 20:52:54 nsouch Exp $ 27d70424edSNicolas Souchu * 28d70424edSNicolas Souchu */ 29d70424edSNicolas Souchu #include <sys/param.h> 30d70424edSNicolas Souchu #include <sys/systm.h> 31d70424edSNicolas Souchu #include <sys/kernel.h> 32d70424edSNicolas Souchu #include <sys/malloc.h> 33d70424edSNicolas Souchu #include <sys/module.h> 34d70424edSNicolas Souchu #include <sys/bus.h> 35d70424edSNicolas Souchu 36d70424edSNicolas Souchu #include <dev/smbus/smbconf.h> 37d70424edSNicolas Souchu #include <dev/smbus/smbus.h> 38d70424edSNicolas Souchu #include "smbus_if.h" 39d70424edSNicolas Souchu 40d70424edSNicolas Souchu /* 41d70424edSNicolas Souchu * smbus_intr() 42d70424edSNicolas Souchu */ 43d70424edSNicolas Souchu void 44d70424edSNicolas Souchu smbus_intr(device_t bus, u_char devaddr, char low, char high, int error) 45d70424edSNicolas Souchu { 46d70424edSNicolas Souchu struct smbus_softc *sc = (struct smbus_softc *)device_get_softc(bus); 47d70424edSNicolas Souchu 48d70424edSNicolas Souchu /* call owner's intr routine */ 49d70424edSNicolas Souchu if (sc->owner) 50d70424edSNicolas Souchu SMBUS_INTR(sc->owner, devaddr, low, high, error); 51d70424edSNicolas Souchu 52d70424edSNicolas Souchu return; 53d70424edSNicolas Souchu } 54d70424edSNicolas Souchu 55d70424edSNicolas Souchu /* 56d70424edSNicolas Souchu * smbus_alloc_bus() 57d70424edSNicolas Souchu * 58d70424edSNicolas Souchu * Allocate a new bus connected to the given parent device 59d70424edSNicolas Souchu */ 60d70424edSNicolas Souchu device_t 61d70424edSNicolas Souchu smbus_alloc_bus(device_t parent) 62d70424edSNicolas Souchu { 63d70424edSNicolas Souchu device_t child; 64d70424edSNicolas Souchu 65d70424edSNicolas Souchu /* add the bus to the parent */ 66d70424edSNicolas Souchu child = device_add_child(parent, "smbus", -1, NULL); 67d70424edSNicolas Souchu 68d70424edSNicolas Souchu if (child) 69d70424edSNicolas Souchu device_set_desc(child, "System Management Bus"); 70d70424edSNicolas Souchu 71d70424edSNicolas Souchu return (child); 72d70424edSNicolas Souchu } 73d70424edSNicolas Souchu 743ab1f056SNicolas Souchu static int 753ab1f056SNicolas Souchu smbus_poll(struct smbus_softc *sc, int how) 76d70424edSNicolas Souchu { 773ab1f056SNicolas Souchu int error; 78d70424edSNicolas Souchu 79d70424edSNicolas Souchu switch (how) { 80d70424edSNicolas Souchu case (SMB_WAIT | SMB_INTR): 81d70424edSNicolas Souchu error = tsleep(sc, SMBPRI|PCATCH, "smbreq", 0); 82d70424edSNicolas Souchu break; 83d70424edSNicolas Souchu 84d70424edSNicolas Souchu case (SMB_WAIT | SMB_NOINTR): 85d70424edSNicolas Souchu error = tsleep(sc, SMBPRI, "smbreq", 0); 86d70424edSNicolas Souchu break; 87d70424edSNicolas Souchu 88d70424edSNicolas Souchu default: 89d70424edSNicolas Souchu return (EWOULDBLOCK); 90d70424edSNicolas Souchu break; 91d70424edSNicolas Souchu } 92d70424edSNicolas Souchu 933ab1f056SNicolas Souchu return (error); 943ab1f056SNicolas Souchu } 953ab1f056SNicolas Souchu 963ab1f056SNicolas Souchu /* 973ab1f056SNicolas Souchu * smbus_request_bus() 983ab1f056SNicolas Souchu * 993ab1f056SNicolas Souchu * Allocate the device to perform transfers. 1003ab1f056SNicolas Souchu * 1013ab1f056SNicolas Souchu * how : SMB_WAIT or SMB_DONTWAIT 1023ab1f056SNicolas Souchu */ 1033ab1f056SNicolas Souchu int 1043ab1f056SNicolas Souchu smbus_request_bus(device_t bus, device_t dev, int how) 1053ab1f056SNicolas Souchu { 1063ab1f056SNicolas Souchu struct smbus_softc *sc = (struct smbus_softc *)device_get_softc(bus); 1073ab1f056SNicolas Souchu int s, error = 0; 1083ab1f056SNicolas Souchu 1093ab1f056SNicolas Souchu /* first, ask the underlying layers if the request is ok */ 1103ab1f056SNicolas Souchu do { 1113ab1f056SNicolas Souchu error = SMBUS_CALLBACK(device_get_parent(bus), 1123ab1f056SNicolas Souchu SMB_REQUEST_BUS, (caddr_t)&how); 1133ab1f056SNicolas Souchu if (error) 1143ab1f056SNicolas Souchu error = smbus_poll(sc, how); 1153ab1f056SNicolas Souchu } while (error); 1163ab1f056SNicolas Souchu 1173ab1f056SNicolas Souchu while (!error) { 1183ab1f056SNicolas Souchu s = splhigh(); 1193ab1f056SNicolas Souchu if (sc->owner) { 1203ab1f056SNicolas Souchu splx(s); 1213ab1f056SNicolas Souchu 1223ab1f056SNicolas Souchu error = smbus_poll(sc, how); 123d70424edSNicolas Souchu } else { 124d70424edSNicolas Souchu sc->owner = dev; 125d70424edSNicolas Souchu 126d70424edSNicolas Souchu splx(s); 127d70424edSNicolas Souchu return (0); 128d70424edSNicolas Souchu } 129d70424edSNicolas Souchu } 130d70424edSNicolas Souchu 131d70424edSNicolas Souchu return (error); 132d70424edSNicolas Souchu } 133d70424edSNicolas Souchu 134d70424edSNicolas Souchu /* 135d70424edSNicolas Souchu * smbus_release_bus() 136d70424edSNicolas Souchu * 137d70424edSNicolas Souchu * Release the device allocated with smbus_request_dev() 138d70424edSNicolas Souchu */ 139d70424edSNicolas Souchu int 140d70424edSNicolas Souchu smbus_release_bus(device_t bus, device_t dev) 141d70424edSNicolas Souchu { 142d70424edSNicolas Souchu struct smbus_softc *sc = (struct smbus_softc *)device_get_softc(bus); 1433ab1f056SNicolas Souchu int s, error; 1443ab1f056SNicolas Souchu 1453ab1f056SNicolas Souchu /* first, ask the underlying layers if the release is ok */ 1463ab1f056SNicolas Souchu error = SMBUS_CALLBACK(device_get_parent(bus), SMB_RELEASE_BUS, NULL); 1473ab1f056SNicolas Souchu 1483ab1f056SNicolas Souchu if (error) 1493ab1f056SNicolas Souchu return (error); 150d70424edSNicolas Souchu 151d70424edSNicolas Souchu s = splhigh(); 152d70424edSNicolas Souchu if (sc->owner != dev) { 153d70424edSNicolas Souchu splx(s); 154d70424edSNicolas Souchu return (EACCES); 155d70424edSNicolas Souchu } 156d70424edSNicolas Souchu 157d70424edSNicolas Souchu sc->owner = 0; 158d70424edSNicolas Souchu splx(s); 159d70424edSNicolas Souchu 160d70424edSNicolas Souchu /* wakeup waiting processes */ 161d70424edSNicolas Souchu wakeup(sc); 162d70424edSNicolas Souchu 163d70424edSNicolas Souchu return (0); 164d70424edSNicolas Souchu } 165d70424edSNicolas Souchu 166d70424edSNicolas Souchu /* 167d70424edSNicolas Souchu * smbus_get_addr() 168d70424edSNicolas Souchu * 169d70424edSNicolas Souchu * Get the I2C 7 bits address of the device 170d70424edSNicolas Souchu */ 171d70424edSNicolas Souchu u_char 172d70424edSNicolas Souchu smbus_get_addr(device_t dev) 173d70424edSNicolas Souchu { 174d70424edSNicolas Souchu u_long addr; 175d70424edSNicolas Souchu device_t parent = device_get_parent(dev); 176d70424edSNicolas Souchu 177d70424edSNicolas Souchu BUS_READ_IVAR(parent, dev, SMBUS_IVAR_ADDR, &addr); 178d70424edSNicolas Souchu 179d70424edSNicolas Souchu return ((u_char)addr); 180d70424edSNicolas Souchu } 181