xref: /freebsd/sys/dev/smartpqi/smartpqi_main.c (revision 4f52dfbb8d6c4d446500c5b097e3806ec219fbd4)
1 /*-
2  * Copyright (c) 2018 Microsemi Corporation.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 /* $FreeBSD$ */
28 
29 /*
30  * Driver for the Microsemi Smart storage controllers
31  */
32 
33 #include "smartpqi_includes.h"
34 #include "smartpqi_prototypes.h"
35 
36 /*
37  * Supported devices
38  */
39 struct pqi_ident
40 {
41 	u_int16_t		vendor;
42 	u_int16_t		device;
43 	u_int16_t		subvendor;
44 	u_int16_t		subdevice;
45 	int			hwif;
46 	char			*desc;
47 } pqi_identifiers[] = {
48 	/* (MSCC PM8205 8x12G based) */
49 	{0x9005, 0x028f, 0x103c, 0x600, PQI_HWIF_SRCV, "P408i-p SR Gen10"},
50 	{0x9005, 0x028f, 0x103c, 0x601, PQI_HWIF_SRCV, "P408e-p SR Gen10"},
51 	{0x9005, 0x028f, 0x103c, 0x602, PQI_HWIF_SRCV, "P408i-a SR Gen10"},
52 	{0x9005, 0x028f, 0x103c, 0x603, PQI_HWIF_SRCV, "P408i-c SR Gen10"},
53 	{0x9005, 0x028f, 0x1028, 0x1FE0, PQI_HWIF_SRCV, "SmartRAID 3162-8i/eDell"},
54 	{0x9005, 0x028f, 0x9005, 0x608, PQI_HWIF_SRCV, "SmartRAID 3162-8i/e"},
55 	{0x9005, 0x028f, 0x103c, 0x609, PQI_HWIF_SRCV, "P408i-sb SR G10"},
56 
57 	/* (MSCC PM8225 8x12G based) */
58 	{0x9005, 0x028f, 0x103c, 0x650, PQI_HWIF_SRCV, "E208i-p SR Gen10"},
59 	{0x9005, 0x028f, 0x103c, 0x651, PQI_HWIF_SRCV, "E208e-p SR Gen10"},
60 	{0x9005, 0x028f, 0x103c, 0x652, PQI_HWIF_SRCV, "E208i-c SR Gen10"},
61 	{0x9005, 0x028f, 0x103c, 0x654, PQI_HWIF_SRCV, "E208i-a SR Gen10"},
62 	{0x9005, 0x028f, 0x103c, 0x655, PQI_HWIF_SRCV, "P408e-m SR Gen10"},
63 
64 	/* (MSCC PM8221 8x12G based) */
65 	{0x9005, 0x028f, 0x103c, 0x700, PQI_HWIF_SRCV, "P204i-c SR Gen10"},
66 	{0x9005, 0x028f, 0x103c, 0x701, PQI_HWIF_SRCV, "P204i-b SR Gen10"},
67 
68 	/* (MSCC PM8204 8x12G based) */
69 	{0x9005, 0x028f, 0x9005, 0x800, PQI_HWIF_SRCV, "SmartRAID 3154-8i"},
70 	{0x9005, 0x028f, 0x9005, 0x801, PQI_HWIF_SRCV, "SmartRAID 3152-8i"},
71 	{0x9005, 0x028f, 0x9005, 0x802, PQI_HWIF_SRCV, "SmartRAID 3151-4i"},
72 	{0x9005, 0x028f, 0x9005, 0x803, PQI_HWIF_SRCV, "SmartRAID 3101-4i"},
73 	{0x9005, 0x028f, 0x9005, 0x804, PQI_HWIF_SRCV, "SmartRAID 3154-8e"},
74 	{0x9005, 0x028f, 0x9005, 0x805, PQI_HWIF_SRCV, "SmartRAID 3102-8i"},
75 	{0x9005, 0x028f, 0x9005, 0x806, PQI_HWIF_SRCV, "SmartRAID 3100"},
76 	{0x9005, 0x028f, 0x9005, 0x807, PQI_HWIF_SRCV, "SmartRAID 3162-8i"},
77 	{0x9005, 0x028f, 0x152d, 0x8a22, PQI_HWIF_SRCV, "QS-8204-8i"},
78 
79 	/* (MSCC PM8222 8x12G based) */
80 	{0x9005, 0x028f, 0x9005, 0x900, PQI_HWIF_SRCV, "SmartHBA 2100-8i"},
81 	{0x9005, 0x028f, 0x9005, 0x901, PQI_HWIF_SRCV, "SmartHBA 2100-4i"},
82 	{0x9005, 0x028f, 0x9005, 0x902, PQI_HWIF_SRCV, "HBA 1100-8i"},
83 	{0x9005, 0x028f, 0x9005, 0x903, PQI_HWIF_SRCV, "HBA 1100-4i"},
84 	{0x9005, 0x028f, 0x9005, 0x904, PQI_HWIF_SRCV, "SmartHBA 2100-8e"},
85 	{0x9005, 0x028f, 0x9005, 0x905, PQI_HWIF_SRCV, "HBA 1100-8e"},
86 	{0x9005, 0x028f, 0x9005, 0x906, PQI_HWIF_SRCV, "SmartHBA 2100-4i4e"},
87 	{0x9005, 0x028f, 0x9005, 0x907, PQI_HWIF_SRCV, "HBA 1100"},
88 	{0x9005, 0x028f, 0x9005, 0x908, PQI_HWIF_SRCV, "SmartHBA 2100"},
89 	{0x9005, 0x028f, 0x9005, 0x90a, PQI_HWIF_SRCV, "SmartHBA 2100A-8i"},
90 
91 	/* (SRCx MSCC FVB 24x12G based) */
92 	{0x9005, 0x028f, 0x103c, 0x1001, PQI_HWIF_SRCV, "MSCC FVB"},
93 
94 	/* (MSCC PM8241 24x12G based) */
95 
96 	/* (MSCC PM8242 24x12G based) */
97 	{0x9005, 0x028f, 0x152d, 0x8a37, PQI_HWIF_SRCV, "QS-8242-24i"},
98 	{0x9005, 0x028f, 0x9005, 0x1300, PQI_HWIF_SRCV, "HBA 1100-8i8e"},
99 	{0x9005, 0x028f, 0x9005, 0x1301, PQI_HWIF_SRCV, "HBA 1100-24i"},
100 	{0x9005, 0x028f, 0x9005, 0x1302, PQI_HWIF_SRCV, "SmartHBA 2100-8i8e"},
101 	{0x9005, 0x028f, 0x9005, 0x1303, PQI_HWIF_SRCV, "SmartHBA 2100-24i"},
102 
103 	/* (MSCC PM8236 16x12G based) */
104 	{0x9005, 0x028f, 0x152d, 0x8a24, PQI_HWIF_SRCV, "QS-8236-16i"},
105 	{0x9005, 0x028f, 0x9005, 0x1380, PQI_HWIF_SRCV, "SmartRAID 3154-16i"},
106 
107 	/* (MSCC PM8237 24x12G based) */
108 	{0x9005, 0x028f, 0x103c, 0x1100, PQI_HWIF_SRCV, "P816i-a SR Gen10"},
109 	{0x9005, 0x028f, 0x103c, 0x1101, PQI_HWIF_SRCV, "P416ie-m SR G10"},
110 
111 	/* (MSCC PM8238 16x12G based) */
112 	{0x9005, 0x028f, 0x152d, 0x8a23, PQI_HWIF_SRCV, "QS-8238-16i"},
113 	{0x9005, 0x028f, 0x9005, 0x1280, PQI_HWIF_SRCV, "HBA 1100-16i"},
114 	{0x9005, 0x028f, 0x9005, 0x1281, PQI_HWIF_SRCV, "HBA 1100-16e"},
115 
116 	/* (MSCC PM8240 24x12G based) */
117 	{0x9005, 0x028f, 0x152d, 0x8a36, PQI_HWIF_SRCV, "QS-8240-24i"},
118 	{0x9005, 0x028f, 0x9005, 0x1200, PQI_HWIF_SRCV, "SmartRAID 3154-24i"},
119 	{0x9005, 0x028f, 0x9005, 0x1201, PQI_HWIF_SRCV, "SmartRAID 3154-8i16e"},
120 	{0x9005, 0x028f, 0x9005, 0x1202, PQI_HWIF_SRCV, "SmartRAID 3154-8i8e"},
121 
122 	{0, 0, 0, 0, 0, 0}
123 };
124 
125 struct pqi_ident
126 pqi_family_identifiers[] = {
127 	{0x9005, 0x028f, 0, 0, PQI_HWIF_SRCV, "Smart Array Storage Controller"},
128 	{0, 0, 0, 0, 0, 0}
129 };
130 
131 /*
132  * Function to identify the installed adapter.
133  */
134 static struct pqi_ident *
135 pqi_find_ident(device_t dev)
136 {
137 	struct pqi_ident *m;
138 	u_int16_t vendid, devid, sub_vendid, sub_devid;
139 
140 	vendid = pci_get_vendor(dev);
141 	devid = pci_get_device(dev);
142 	sub_vendid = pci_get_subvendor(dev);
143 	sub_devid = pci_get_subdevice(dev);
144 
145 	for (m = pqi_identifiers; m->vendor != 0; m++) {
146 		if ((m->vendor == vendid) && (m->device == devid) &&
147 			(m->subvendor == sub_vendid) &&
148 			(m->subdevice == sub_devid)) {
149 			return (m);
150 		}
151 	}
152 
153 	for (m = pqi_family_identifiers; m->vendor != 0; m++) {
154 		if ((m->vendor == vendid) && (m->device == devid)) {
155 			return (m);
156 		}
157 	}
158 
159 	return (NULL);
160 }
161 
162 /*
163  * Determine whether this is one of our supported adapters.
164  */
165 static int
166 smartpqi_probe(device_t dev)
167 {
168 	struct pqi_ident *id;
169 
170 	if ((id = pqi_find_ident(dev)) != NULL) {
171 		device_set_desc(dev, id->desc);
172 		return(BUS_PROBE_VENDOR);
173 	}
174 
175 	return(ENXIO);
176 }
177 
178 /*
179  * Store Bus/Device/Function in softs
180  */
181 void pqisrc_save_controller_info(struct pqisrc_softstate *softs)
182 {
183 	device_t dev = softs->os_specific.pqi_dev;
184 
185 	softs->bus_id = (uint32_t)pci_get_bus(dev);
186 	softs->device_id = (uint32_t)pci_get_device(dev);
187 	softs->func_id = (uint32_t)pci_get_function(dev);
188 }
189 
190 
191 /*
192  * Allocate resources for our device, set up the bus interface.
193  * Initialize the PQI related functionality, scan devices, register sim to
194  * upper layer, create management interface device node etc.
195  */
196 static int
197 smartpqi_attach(device_t dev)
198 {
199 	struct pqisrc_softstate *softs = NULL;
200 	struct pqi_ident *id = NULL;
201 	int error = 0;
202 	u_int32_t command = 0, i = 0;
203 	int card_index = device_get_unit(dev);
204 	rcb_t *rcbp = NULL;
205 
206 	/*
207 	 * Initialise softc.
208 	 */
209 	softs = device_get_softc(dev);
210 
211 	if (!softs) {
212 		printf("Could not get softc\n");
213 		error = EINVAL;
214 		goto out;
215 	}
216 	memset(softs, 0, sizeof(*softs));
217 	softs->os_specific.pqi_dev = dev;
218 
219 	DBG_FUNC("IN\n");
220 
221 	/* assume failure is 'not configured' */
222 	error = ENXIO;
223 
224 	/*
225 	 * Verify that the adapter is correctly set up in PCI space.
226 	 */
227 	pci_enable_busmaster(softs->os_specific.pqi_dev);
228 	command = pci_read_config(softs->os_specific.pqi_dev, PCIR_COMMAND, 2);
229 	if ((command & PCIM_CMD_MEMEN) == 0) {
230 		DBG_ERR("memory window not available command = %d\n", command);
231 		error = ENXIO;
232 		goto out;
233 	}
234 
235 	/*
236 	 * Detect the hardware interface version, set up the bus interface
237 	 * indirection.
238 	 */
239 	id = pqi_find_ident(dev);
240 	softs->os_specific.pqi_hwif = id->hwif;
241 
242 	switch(softs->os_specific.pqi_hwif) {
243 		case PQI_HWIF_SRCV:
244 			DBG_INFO("set hardware up for PMC SRCv for %p", softs);
245 			break;
246 		default:
247 			softs->os_specific.pqi_hwif = PQI_HWIF_UNKNOWN;
248 			DBG_ERR("unknown hardware type\n");
249 			error = ENXIO;
250 			goto out;
251 	}
252 
253 	pqisrc_save_controller_info(softs);
254 
255 	/*
256 	 * Allocate the PCI register window.
257 	 */
258 	softs->os_specific.pqi_regs_rid0 = PCIR_BAR(0);
259 	if ((softs->os_specific.pqi_regs_res0 =
260 		bus_alloc_resource_any(softs->os_specific.pqi_dev, SYS_RES_MEMORY,
261 		&softs->os_specific.pqi_regs_rid0, RF_ACTIVE)) == NULL) {
262 		DBG_ERR("couldn't allocate register window 0\n");
263 		/* assume failure is 'out of memory' */
264 		error = ENOMEM;
265 		goto out;
266 	}
267 
268 	bus_get_resource_start(softs->os_specific.pqi_dev, SYS_RES_MEMORY,
269 		softs->os_specific.pqi_regs_rid0);
270 
271 	softs->pci_mem_handle.pqi_btag = rman_get_bustag(softs->os_specific.pqi_regs_res0);
272 	softs->pci_mem_handle.pqi_bhandle = rman_get_bushandle(softs->os_specific.pqi_regs_res0);
273 	/* softs->pci_mem_base_vaddr = (uintptr_t)rman_get_virtual(softs->os_specific.pqi_regs_res0); */
274 	softs->pci_mem_base_vaddr = (char *)rman_get_virtual(softs->os_specific.pqi_regs_res0);
275 
276 	/*
277 	 * Allocate the parent bus DMA tag appropriate for our PCI interface.
278 	 *
279 	 * Note that some of these controllers are 64-bit capable.
280 	 */
281 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 	/* parent */
282 				PAGE_SIZE, 0,		/* algnmnt, boundary */
283 				BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
284 				BUS_SPACE_MAXADDR, 	/* highaddr */
285 				NULL, NULL, 		/* filter, filterarg */
286 				BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
287 				BUS_SPACE_UNRESTRICTED,	/* nsegments */
288 				BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
289 				0,			/* flags */
290 				NULL, NULL,		/* No locking needed */
291 				&softs->os_specific.pqi_parent_dmat)) {
292 		DBG_ERR("can't allocate parent DMA tag\n");
293 		/* assume failure is 'out of memory' */
294 		error = ENOMEM;
295 		goto dma_out;
296 	}
297 
298 	softs->os_specific.sim_registered = FALSE;
299 	softs->os_name = "FreeBSD ";
300 
301 	/* Initialize the PQI library */
302 	error = pqisrc_init(softs);
303 	if (error) {
304 		DBG_ERR("Failed to initialize pqi lib error = %d\n", error);
305 		error = PQI_STATUS_FAILURE;
306 		goto out;
307 	}
308 
309         mtx_init(&softs->os_specific.cam_lock, "cam_lock", NULL, MTX_DEF);
310         softs->os_specific.mtx_init = TRUE;
311         mtx_init(&softs->os_specific.map_lock, "map_lock", NULL, MTX_DEF);
312 
313         /*
314          * Create DMA tag for mapping buffers into controller-addressable space.
315          */
316         if (bus_dma_tag_create(softs->os_specific.pqi_parent_dmat,/* parent */
317 				1, 0,			/* algnmnt, boundary */
318 				BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
319 				BUS_SPACE_MAXADDR,	/* highaddr */
320 				NULL, NULL,		/* filter, filterarg */
321 				softs->pqi_cap.max_sg_elem*PAGE_SIZE,/*maxsize*/
322 				softs->pqi_cap.max_sg_elem,	/* nsegments */
323 				BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
324 				BUS_DMA_ALLOCNOW,		/* flags */
325 				busdma_lock_mutex,		/* lockfunc */
326 				&softs->os_specific.map_lock,	/* lockfuncarg*/
327 				&softs->os_specific.pqi_buffer_dmat)) {
328 		DBG_ERR("can't allocate buffer DMA tag for pqi_buffer_dmat\n");
329 		return (ENOMEM);
330         }
331 
332 	rcbp = &softs->rcb[1];
333 	for( i = 1;  i <= softs->pqi_cap.max_outstanding_io; i++, rcbp++ ) {
334 		if ((error = bus_dmamap_create(softs->os_specific.pqi_buffer_dmat, 0, &rcbp->cm_datamap)) != 0) {
335 			DBG_ERR("Cant create datamap for buf @"
336 			"rcbp = %p maxio = %d error = %d\n",
337 			rcbp, softs->pqi_cap.max_outstanding_io, error);
338 			goto dma_out;
339 		}
340 	}
341 
342 	os_start_heartbeat_timer((void *)softs); /* Start the heart-beat timer */
343 	softs->os_specific.wellness_periodic = timeout( os_wellness_periodic,
344 							softs, 120*hz);
345 	/* Register our shutdown handler. */
346 	softs->os_specific.eh = EVENTHANDLER_REGISTER(shutdown_final,
347 				smartpqi_shutdown, softs, SHUTDOWN_PRI_DEFAULT);
348 
349 	error = pqisrc_scan_devices(softs);
350 	if (error) {
351 		DBG_ERR("Failed to scan lib error = %d\n", error);
352 		error = PQI_STATUS_FAILURE;
353 		goto out;
354 	}
355 
356 	error = register_sim(softs, card_index);
357 	if (error) {
358 		DBG_ERR("Failed to register sim index = %d error = %d\n",
359 			card_index, error);
360 		goto out;
361 	}
362 
363 	smartpqi_target_rescan(softs);
364 
365 	TASK_INIT(&softs->os_specific.event_task, 0, pqisrc_event_worker,softs);
366 
367 	error = create_char_dev(softs, card_index);
368 	if (error) {
369 		DBG_ERR("Failed to register character device index=%d r=%d\n",
370 			card_index, error);
371 		goto out;
372 	}
373 	goto out;
374 
375 dma_out:
376 	if (softs->os_specific.pqi_regs_res0 != NULL)
377 		bus_release_resource(softs->os_specific.pqi_dev, SYS_RES_MEMORY,
378 			softs->os_specific.pqi_regs_rid0,
379 			softs->os_specific.pqi_regs_res0);
380 out:
381 	DBG_FUNC("OUT error = %d\n", error);
382 	return(error);
383 }
384 
385 /*
386  * Deallocate resources for our device.
387  */
388 static int
389 smartpqi_detach(device_t dev)
390 {
391 	struct pqisrc_softstate *softs = NULL;
392 	softs = device_get_softc(dev);
393 	DBG_FUNC("IN\n");
394 
395 	EVENTHANDLER_DEREGISTER(shutdown_final, softs->os_specific.eh);
396 
397 	/* kill the periodic event */
398 	untimeout(os_wellness_periodic, softs,
399 			softs->os_specific.wellness_periodic);
400 	/* Kill the heart beat event */
401 	untimeout(os_start_heartbeat_timer, softs,
402 			softs->os_specific.heartbeat_timeout_id);
403 
404 	smartpqi_shutdown(softs);
405 	destroy_char_dev(softs);
406 	pqisrc_uninit(softs);
407 	deregister_sim(softs);
408 	pci_release_msi(dev);
409 
410 	DBG_FUNC("OUT\n");
411 	return 0;
412 }
413 
414 /*
415  * Bring the controller to a quiescent state, ready for system suspend.
416  */
417 static int
418 smartpqi_suspend(device_t dev)
419 {
420 	struct pqisrc_softstate *softs;
421 	softs = device_get_softc(dev);
422 	DBG_FUNC("IN\n");
423 
424 	DBG_INFO("Suspending the device %p\n", softs);
425 	softs->os_specific.pqi_state |= SMART_STATE_SUSPEND;
426 
427 	DBG_FUNC("OUT\n");
428 	return(0);
429 }
430 
431 /*
432  * Bring the controller back to a state ready for operation.
433  */
434 static int
435 smartpqi_resume(device_t dev)
436 {
437 	struct pqisrc_softstate *softs;
438 	softs = device_get_softc(dev);
439 	DBG_FUNC("IN\n");
440 
441 	softs->os_specific.pqi_state &= ~SMART_STATE_SUSPEND;
442 
443 	DBG_FUNC("OUT\n");
444 	return(0);
445 }
446 
447 /*
448  * Do whatever is needed during a system shutdown.
449  */
450 int
451 smartpqi_shutdown(void *arg)
452 {
453 	struct pqisrc_softstate *softs = NULL;
454 	int rval = 0;
455 
456 	DBG_FUNC("IN\n");
457 
458 	softs = (struct pqisrc_softstate *)arg;
459 
460 	rval = pqisrc_flush_cache(softs, PQISRC_SHUTDOWN);
461 	if (rval != PQI_STATUS_SUCCESS) {
462 		DBG_ERR("Unable to flush adapter cache! rval = %d", rval);
463 	}
464 
465 	DBG_FUNC("OUT\n");
466 
467 	return rval;
468 }
469 
470 /*
471  * PCI bus interface.
472  */
473 static device_method_t pqi_methods[] = {
474 	/* Device interface */
475 	DEVMETHOD(device_probe,		smartpqi_probe),
476 	DEVMETHOD(device_attach,	smartpqi_attach),
477 	DEVMETHOD(device_detach,	smartpqi_detach),
478 	DEVMETHOD(device_suspend,	smartpqi_suspend),
479 	DEVMETHOD(device_resume,	smartpqi_resume),
480 	{ 0, 0 }
481 };
482 
483 static devclass_t	pqi_devclass;
484 static driver_t smartpqi_pci_driver = {
485 	"smartpqi",
486 	pqi_methods,
487 	sizeof(struct pqisrc_softstate)
488 };
489 
490 DRIVER_MODULE(smartpqi, pci, smartpqi_pci_driver, pqi_devclass, 0, 0);
491 MODULE_DEPEND(smartpqi, pci, 1, 1, 1);
492