1 /*- 2 * Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 27 #ifndef _PQI_IOCTL_H_ 28 #define _PQI_IOCTL_H_ 29 30 /* IOCTL passthrough macros and structures */ 31 32 #define SENSEINFOBYTES 32 /* note that this value may vary 33 between host implementations */ 34 35 /* transfer direction */ 36 #define PQIIOCTL_NONE 0x00 37 #define PQIIOCTL_WRITE 0x01 38 #define PQIIOCTL_READ 0x02 39 #define PQIIOCTL_BIDIRECTIONAL (PQIIOCTL_READ | PQIIOCTL_WRITE) 40 41 42 /* Type defs used in the following structs */ 43 #define BYTE uint8_t 44 #define WORD uint16_t 45 #define HWORD uint16_t 46 #define DWORD uint32_t 47 48 49 /* Command List Structure */ 50 typedef union _SCSI3Addr_struct { 51 struct { 52 BYTE Dev; 53 BYTE Bus:6; 54 BYTE Mode:2; /* b00 */ 55 } PeripDev; 56 struct { 57 BYTE DevLSB; 58 BYTE DevMSB:6; 59 BYTE Mode:2; /* b01 */ 60 } LogDev; 61 struct { 62 BYTE Dev:5; 63 BYTE Bus:3; 64 BYTE Targ:6; 65 BYTE Mode:2; /* b10 */ 66 } LogUnit; 67 68 }OS_ATTRIBUTE_PACKED SCSI3Addr_struct; 69 70 typedef struct _PhysDevAddr_struct { 71 DWORD TargetId:24; 72 DWORD Bus:6; 73 DWORD Mode:2; 74 SCSI3Addr_struct Target[2]; /* 2 level target device addr */ 75 76 }OS_ATTRIBUTE_PACKED PhysDevAddr_struct; 77 78 typedef struct _LogDevAddr_struct { 79 DWORD VolId:30; 80 DWORD Mode:2; 81 BYTE reserved[4]; 82 83 }OS_ATTRIBUTE_PACKED LogDevAddr_struct; 84 85 typedef union _LUNAddr_struct { 86 BYTE LunAddrBytes[8]; 87 SCSI3Addr_struct SCSI3Lun[4]; 88 PhysDevAddr_struct PhysDev; 89 LogDevAddr_struct LogDev; 90 91 }OS_ATTRIBUTE_PACKED LUNAddr_struct; 92 93 typedef struct _RequestBlock_struct { 94 BYTE CDBLen; 95 struct { 96 BYTE Type:3; 97 BYTE Attribute:3; 98 BYTE Direction:2; 99 } Type; 100 HWORD Timeout; 101 BYTE CDB[16]; 102 103 }OS_ATTRIBUTE_PACKED RequestBlock_struct; 104 105 typedef union _MoreErrInfo_struct{ 106 struct { 107 BYTE Reserved[3]; 108 BYTE Type; 109 DWORD ErrorInfo; 110 } Common_Info; 111 struct{ 112 BYTE Reserved[2]; 113 BYTE offense_size; /* size of offending entry */ 114 BYTE offense_num; /* byte # of offense 0-base */ 115 DWORD offense_value; 116 } Invalid_Cmd; 117 118 }OS_ATTRIBUTE_PACKED MoreErrInfo_struct; 119 120 typedef struct _ErrorInfo_struct { 121 BYTE ScsiStatus; 122 BYTE SenseLen; 123 HWORD CommandStatus; 124 DWORD ResidualCnt; 125 MoreErrInfo_struct MoreErrInfo; 126 BYTE SenseInfo[SENSEINFOBYTES]; 127 128 }OS_ATTRIBUTE_PACKED ErrorInfo_struct; 129 130 131 typedef struct pqi_ioctl_passthruCmd_struct { 132 LUNAddr_struct LUN_info; 133 RequestBlock_struct Request; 134 ErrorInfo_struct error_info; 135 WORD buf_size; /* size in bytes of the buf */ 136 passthru_buf_type_t buf; 137 138 }OS_ATTRIBUTE_PACKED IOCTL_Command_struct; 139 140 141 #endif /* _PQI_IOCTL_H_ */ 142