1 /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Bill Paul. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /*- 38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 39 * 40 * Permission to use, copy, modify, and distribute this software for any 41 * purpose with or without fee is hereby granted, provided that the above 42 * copyright notice and this permission notice appear in all copies. 43 * 44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 51 */ 52 53 /* Values to keep the different chip revisions apart (SK_CHIPVER). */ 54 #define SK_GENESIS 0x0A 55 #define SK_YUKON 0xB0 56 #define SK_YUKON_LITE 0xB1 57 #define SK_YUKON_LP 0xB2 58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0) 59 60 /* Known revisions in SK_CONFIG. */ 61 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */ 62 #define SK_YUKON_LITE_REV_A1 0x3 63 #define SK_YUKON_LITE_REV_A3 0x7 64 65 /* 66 * SysKonnect PCI vendor ID 67 */ 68 #define VENDORID_SK 0x1148 69 70 /* 71 * Marvell PCI vendor ID 72 */ 73 #define VENDORID_MARVELL 0x11AB 74 75 /* 76 * SK-NET gigabit ethernet device IDs 77 */ 78 #define DEVICEID_SK_V1 0x4300 79 #define DEVICEID_SK_V2 0x4320 80 81 /* 82 * Belkin F5D5005 83 */ 84 #define DEVICEID_BELKIN_5005 0x5005 85 86 /* 87 * 3Com PCI vendor ID 88 */ 89 #define VENDORID_3COM 0x10b7 90 91 /* 92 * 3Com gigabit ethernet device ID 93 */ 94 #define DEVICEID_3COM_3C940 0x1700 95 96 /* 97 * Linksys PCI vendor ID 98 */ 99 #define VENDORID_LINKSYS 0x1737 100 101 /* 102 * Linksys gigabit ethernet device ID 103 */ 104 #define DEVICEID_LINKSYS_EG1032 0x1032 105 106 /* 107 * Linksys gigabit ethernet rev 2 sub-device ID 108 */ 109 #define SUBDEVICEID_LINKSYS_EG1032_REV2 0x0015 110 111 /* 112 * D-Link PCI vendor ID 113 */ 114 #define VENDORID_DLINK 0x1186 115 116 /* 117 * D-Link gigabit ethernet device ID 118 */ 119 #define DEVICEID_DLINK_DGE530T_A1 0x4c00 120 #define DEVICEID_DLINK_DGE530T_B1 0x4b01 121 122 /* 123 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 124 * but internally it has a 16K register space. This 16K space is 125 * divided into 128-byte blocks. The first 128 bytes of the I/O 126 * window represent the first block, which is permanently mapped 127 * at the start of the window. The other 127 blocks can be mapped 128 * to the second 128 bytes of the I/O window by setting the desired 129 * block value in the RAP register in block 0. Not all of the 127 130 * blocks are actually used. Most registers are 32 bits wide, but 131 * there are a few 16-bit and 8-bit ones as well. 132 */ 133 134 /* Start of remappable register window. */ 135 #define SK_WIN_BASE 0x0080 136 137 /* Size of a window */ 138 #define SK_WIN_LEN 0x80 139 140 #define SK_WIN_MASK 0x3F80 141 #define SK_REG_MASK 0x7F 142 143 /* Compute the window of a given register (for the RAP register) */ 144 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 145 146 /* Compute the relative offset of a register within the window */ 147 #define SK_REG(reg) ((reg) & SK_REG_MASK) 148 149 #define SK_PORT_A 0 150 #define SK_PORT_B 1 151 152 /* 153 * Compute offset of port-specific register. Since there are two 154 * ports, there are two of some GEnesis modules (e.g. two sets of 155 * DMA queues, two sets of FIFO control registers, etc...). Normally, 156 * the block for port 0 is at offset 0x0 and the block for port 1 is 157 * at offset 0x80 (i.e. the next page over). However for the transmit 158 * BMUs and RAMbuffers, there are two blocks for each port: one for 159 * the sync transmit queue and one for the async queue (which we don't 160 * use). However instead of ordering them like this: 161 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 162 * SysKonnect has instead ordered them like this: 163 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 164 * This means that when referencing the TX BMU and RAMbuffer registers, 165 * we have to double the block offset (0x80 * 2) in order to reach the 166 * second queue. This prevents us from using the same formula 167 * (sk_port * 0x80) to compute the offsets for all of the port-specific 168 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 169 * The simplest thing is to provide an extra argument to these macros: 170 * the 'skip' parameter. The 'skip' value is the number of extra pages 171 * for skip when computing the port0/port1 offsets. For most registers, 172 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 173 */ 174 #define SK_IF_READ_4(sc_if, skip, reg) \ 175 sk_win_read_4(sc_if->sk_softc, reg + \ 176 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 177 #define SK_IF_READ_2(sc_if, skip, reg) \ 178 sk_win_read_2(sc_if->sk_softc, reg + \ 179 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 180 #define SK_IF_READ_1(sc_if, skip, reg) \ 181 sk_win_read_1(sc_if->sk_softc, reg + \ 182 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 183 184 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 185 sk_win_write_4(sc_if->sk_softc, \ 186 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 187 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 188 sk_win_write_2(sc_if->sk_softc, \ 189 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 190 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 191 sk_win_write_1(sc_if->sk_softc, \ 192 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 193 194 /* Block 0 registers, permanently mapped at iobase. */ 195 #define SK_RAP 0x0000 196 #define SK_CSR 0x0004 197 #define SK_LED 0x0006 198 #define SK_ISR 0x0008 /* interrupt source */ 199 #define SK_IMR 0x000C /* interrupt mask */ 200 #define SK_IESR 0x0010 /* interrupt hardware error source */ 201 #define SK_IEMR 0x0014 /* interrupt hardware error mask */ 202 #define SK_ISSR 0x0018 /* special interrupt source */ 203 #define SK_XM_IMR0 0x0020 204 #define SK_XM_ISR0 0x0028 205 #define SK_XM_PHYADDR0 0x0030 206 #define SK_XM_PHYDATA0 0x0034 207 #define SK_XM_IMR1 0x0040 208 #define SK_XM_ISR1 0x0048 209 #define SK_XM_PHYADDR1 0x0050 210 #define SK_XM_PHYDATA1 0x0054 211 #define SK_BMU_RX_CSR0 0x0060 212 #define SK_BMU_RX_CSR1 0x0064 213 #define SK_BMU_TXS_CSR0 0x0068 214 #define SK_BMU_TXA_CSR0 0x006C 215 #define SK_BMU_TXS_CSR1 0x0070 216 #define SK_BMU_TXA_CSR1 0x0074 217 218 /* SK_CSR register */ 219 #define SK_CSR_SW_RESET 0x0001 220 #define SK_CSR_SW_UNRESET 0x0002 221 #define SK_CSR_MASTER_RESET 0x0004 222 #define SK_CSR_MASTER_UNRESET 0x0008 223 #define SK_CSR_MASTER_STOP 0x0010 224 #define SK_CSR_MASTER_DONE 0x0020 225 #define SK_CSR_SW_IRQ_CLEAR 0x0040 226 #define SK_CSR_SW_IRQ_SET 0x0080 227 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 228 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */ 229 230 /* SK_LED register */ 231 #define SK_LED_GREEN_OFF 0x01 232 #define SK_LED_GREEN_ON 0x02 233 234 /* SK_ISR register */ 235 #define SK_ISR_TX2_AS_CHECK 0x00000001 236 #define SK_ISR_TX2_AS_EOF 0x00000002 237 #define SK_ISR_TX2_AS_EOB 0x00000004 238 #define SK_ISR_TX2_S_CHECK 0x00000008 239 #define SK_ISR_TX2_S_EOF 0x00000010 240 #define SK_ISR_TX2_S_EOB 0x00000020 241 #define SK_ISR_TX1_AS_CHECK 0x00000040 242 #define SK_ISR_TX1_AS_EOF 0x00000080 243 #define SK_ISR_TX1_AS_EOB 0x00000100 244 #define SK_ISR_TX1_S_CHECK 0x00000200 245 #define SK_ISR_TX1_S_EOF 0x00000400 246 #define SK_ISR_TX1_S_EOB 0x00000800 247 #define SK_ISR_RX2_CHECK 0x00001000 248 #define SK_ISR_RX2_EOF 0x00002000 249 #define SK_ISR_RX2_EOB 0x00004000 250 #define SK_ISR_RX1_CHECK 0x00008000 251 #define SK_ISR_RX1_EOF 0x00010000 252 #define SK_ISR_RX1_EOB 0x00020000 253 #define SK_ISR_LINK2_OFLOW 0x00040000 254 #define SK_ISR_MAC2 0x00080000 255 #define SK_ISR_LINK1_OFLOW 0x00100000 256 #define SK_ISR_MAC1 0x00200000 257 #define SK_ISR_TIMER 0x00400000 258 #define SK_ISR_EXTERNAL_REG 0x00800000 259 #define SK_ISR_SW 0x01000000 260 #define SK_ISR_I2C_RDY 0x02000000 261 #define SK_ISR_TX2_TIMEO 0x04000000 262 #define SK_ISR_TX1_TIMEO 0x08000000 263 #define SK_ISR_RX2_TIMEO 0x10000000 264 #define SK_ISR_RX1_TIMEO 0x20000000 265 #define SK_ISR_RSVD 0x40000000 266 #define SK_ISR_HWERR 0x80000000 267 268 /* SK_IMR register */ 269 #define SK_IMR_TX2_AS_CHECK 0x00000001 270 #define SK_IMR_TX2_AS_EOF 0x00000002 271 #define SK_IMR_TX2_AS_EOB 0x00000004 272 #define SK_IMR_TX2_S_CHECK 0x00000008 273 #define SK_IMR_TX2_S_EOF 0x00000010 274 #define SK_IMR_TX2_S_EOB 0x00000020 275 #define SK_IMR_TX1_AS_CHECK 0x00000040 276 #define SK_IMR_TX1_AS_EOF 0x00000080 277 #define SK_IMR_TX1_AS_EOB 0x00000100 278 #define SK_IMR_TX1_S_CHECK 0x00000200 279 #define SK_IMR_TX1_S_EOF 0x00000400 280 #define SK_IMR_TX1_S_EOB 0x00000800 281 #define SK_IMR_RX2_CHECK 0x00001000 282 #define SK_IMR_RX2_EOF 0x00002000 283 #define SK_IMR_RX2_EOB 0x00004000 284 #define SK_IMR_RX1_CHECK 0x00008000 285 #define SK_IMR_RX1_EOF 0x00010000 286 #define SK_IMR_RX1_EOB 0x00020000 287 #define SK_IMR_LINK2_OFLOW 0x00040000 288 #define SK_IMR_MAC2 0x00080000 289 #define SK_IMR_LINK1_OFLOW 0x00100000 290 #define SK_IMR_MAC1 0x00200000 291 #define SK_IMR_TIMER 0x00400000 292 #define SK_IMR_EXTERNAL_REG 0x00800000 293 #define SK_IMR_SW 0x01000000 294 #define SK_IMR_I2C_RDY 0x02000000 295 #define SK_IMR_TX2_TIMEO 0x04000000 296 #define SK_IMR_TX1_TIMEO 0x08000000 297 #define SK_IMR_RX2_TIMEO 0x10000000 298 #define SK_IMR_RX1_TIMEO 0x20000000 299 #define SK_IMR_RSVD 0x40000000 300 #define SK_IMR_HWERR 0x80000000 301 302 #define SK_INTRS1 \ 303 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 304 305 #define SK_INTRS2 \ 306 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 307 308 /* SK_IESR register */ 309 #define SK_IESR_PAR_RX2 0x00000001 310 #define SK_IESR_PAR_RX1 0x00000002 311 #define SK_IESR_PAR_MAC2 0x00000004 312 #define SK_IESR_PAR_MAC1 0x00000008 313 #define SK_IESR_PAR_WR_RAM 0x00000010 314 #define SK_IESR_PAR_RD_RAM 0x00000020 315 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 316 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 317 #define SK_IESR_NO_STS_MAC2 0x00000100 318 #define SK_IESR_NO_STS_MAC1 0x00000200 319 #define SK_IESR_IRQ_STS 0x00000400 320 #define SK_IESR_MASTERERR 0x00000800 321 322 /* SK_IEMR register */ 323 #define SK_IEMR_PAR_RX2 0x00000001 324 #define SK_IEMR_PAR_RX1 0x00000002 325 #define SK_IEMR_PAR_MAC2 0x00000004 326 #define SK_IEMR_PAR_MAC1 0x00000008 327 #define SK_IEMR_PAR_WR_RAM 0x00000010 328 #define SK_IEMR_PAR_RD_RAM 0x00000020 329 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 330 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 331 #define SK_IEMR_NO_STS_MAC2 0x00000100 332 #define SK_IEMR_NO_STS_MAC1 0x00000200 333 #define SK_IEMR_IRQ_STS 0x00000400 334 #define SK_IEMR_MASTERERR 0x00000800 335 336 /* Block 2 */ 337 #define SK_MAC0_0 0x0100 338 #define SK_MAC0_1 0x0104 339 #define SK_MAC1_0 0x0108 340 #define SK_MAC1_1 0x010C 341 #define SK_MAC2_0 0x0110 342 #define SK_MAC2_1 0x0114 343 #define SK_CONNTYPE 0x0118 344 #define SK_PMDTYPE 0x0119 345 #define SK_CONFIG 0x011A 346 #define SK_CHIPVER 0x011B 347 #define SK_EPROM0 0x011C 348 #define SK_EPROM1 0x011D /* yukon/genesis */ 349 #define SK_EPROM2 0x011E /* yukon/genesis */ 350 #define SK_EPROM3 0x011F 351 #define SK_EP_ADDR 0x0120 352 #define SK_EP_DATA 0x0124 353 #define SK_EP_LOADCTL 0x0128 354 #define SK_EP_LOADTST 0x0129 355 #define SK_TIMERINIT 0x0130 356 #define SK_TIMER 0x0134 357 #define SK_TIMERCTL 0x0138 358 #define SK_TIMERTST 0x0139 359 #define SK_IMTIMERINIT 0x0140 360 #define SK_IMTIMER 0x0144 361 #define SK_IMTIMERCTL 0x0148 362 #define SK_IMTIMERTST 0x0149 363 #define SK_IMMR 0x014C 364 #define SK_IHWEMR 0x0150 365 #define SK_TESTCTL1 0x0158 366 #define SK_TESTCTL2 0x0159 367 #define SK_GPIO 0x015C 368 #define SK_I2CHWCTL 0x0160 369 #define SK_I2CHWDATA 0x0164 370 #define SK_I2CHWIRQ 0x0168 371 #define SK_I2CSW 0x016C 372 #define SK_BLNKINIT 0x0170 373 #define SK_BLNKCOUNT 0x0174 374 #define SK_BLNKCTL 0x0178 375 #define SK_BLNKSTS 0x0179 376 #define SK_BLNKTST 0x017A 377 378 #define SK_IMCTL_STOP 0x02 379 #define SK_IMCTL_START 0x04 380 381 #define SK_IMTIMER_TICKS_GENESIS 53 382 #define SK_IMTIMER_TICKS_YUKON 78 383 #define SK_IM_USECS(x, t) ((x) * (t)) 384 385 #define SK_IM_MIN 10 386 #define SK_IM_DEFAULT 100 387 #define SK_IM_MAX 10000 388 389 /* 390 * The SK_EPROM0 register contains a byte that describes the 391 * amount of SRAM mounted on the NIC. The value also tells if 392 * the chips are 64K or 128K. This affects the RAMbuffer address 393 * offset that we need to use. 394 */ 395 #define SK_RAMSIZE_512K_64 0x1 396 #define SK_RAMSIZE_1024K_128 0x2 397 #define SK_RAMSIZE_1024K_64 0x3 398 #define SK_RAMSIZE_2048K_128 0x4 399 400 #define SK_RBOFF_0 0x0 401 #define SK_RBOFF_80000 0x80000 402 403 /* 404 * SK_EEPROM1 contains the PHY type, which may be XMAC for 405 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 406 * PHY. 407 */ 408 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 409 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 410 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 411 #define SK_PHYTYPE_NAT 3 /* National DP83891 */ 412 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 413 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 414 415 /* 416 * PHY addresses. 417 */ 418 #define SK_PHYADDR_XMAC 0x0 419 #define SK_PHYADDR_BCOM 0x1 420 #define SK_PHYADDR_LONE 0x3 421 #define SK_PHYADDR_NAT 0x0 422 #define SK_PHYADDR_MARV 0x0 423 424 #define SK_CONFIG_SINGLEMAC 0x01 425 #define SK_CONFIG_DIS_DSL_CLK 0x02 426 427 #define SK_PMD_1000BASELX 0x4C 428 #define SK_PMD_1000BASESX 0x53 429 #define SK_PMD_1000BASECX 0x43 430 #define SK_PMD_1000BASETX 0x54 431 432 /* GPIO bits */ 433 #define SK_GPIO_DAT0 0x00000001 434 #define SK_GPIO_DAT1 0x00000002 435 #define SK_GPIO_DAT2 0x00000004 436 #define SK_GPIO_DAT3 0x00000008 437 #define SK_GPIO_DAT4 0x00000010 438 #define SK_GPIO_DAT5 0x00000020 439 #define SK_GPIO_DAT6 0x00000040 440 #define SK_GPIO_DAT7 0x00000080 441 #define SK_GPIO_DAT8 0x00000100 442 #define SK_GPIO_DAT9 0x00000200 443 #define SK_GPIO_DIR0 0x00010000 444 #define SK_GPIO_DIR1 0x00020000 445 #define SK_GPIO_DIR2 0x00040000 446 #define SK_GPIO_DIR3 0x00080000 447 #define SK_GPIO_DIR4 0x00100000 448 #define SK_GPIO_DIR5 0x00200000 449 #define SK_GPIO_DIR6 0x00400000 450 #define SK_GPIO_DIR7 0x00800000 451 #define SK_GPIO_DIR8 0x01000000 452 #define SK_GPIO_DIR9 0x02000000 453 454 /* Block 3 Ram interface and MAC arbiter registers */ 455 #define SK_RAMADDR 0x0180 456 #define SK_RAMDATA0 0x0184 457 #define SK_RAMDATA1 0x0188 458 #define SK_TO0 0x0190 459 #define SK_TO1 0x0191 460 #define SK_TO2 0x0192 461 #define SK_TO3 0x0193 462 #define SK_TO4 0x0194 463 #define SK_TO5 0x0195 464 #define SK_TO6 0x0196 465 #define SK_TO7 0x0197 466 #define SK_TO8 0x0198 467 #define SK_TO9 0x0199 468 #define SK_TO10 0x019A 469 #define SK_TO11 0x019B 470 #define SK_RITIMEO_TMR 0x019C 471 #define SK_RAMCTL 0x01A0 472 #define SK_RITIMER_TST 0x01A2 473 474 #define SK_RAMCTL_RESET 0x0001 475 #define SK_RAMCTL_UNRESET 0x0002 476 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 477 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 478 479 /* Mac arbiter registers */ 480 #define SK_MINIT_RX1 0x01B0 481 #define SK_MINIT_RX2 0x01B1 482 #define SK_MINIT_TX1 0x01B2 483 #define SK_MINIT_TX2 0x01B3 484 #define SK_MTIMEO_RX1 0x01B4 485 #define SK_MTIMEO_RX2 0x01B5 486 #define SK_MTIMEO_TX1 0x01B6 487 #define SK_MTIEMO_TX2 0x01B7 488 #define SK_MACARB_CTL 0x01B8 489 #define SK_MTIMER_TST 0x01BA 490 #define SK_RCINIT_RX1 0x01C0 491 #define SK_RCINIT_RX2 0x01C1 492 #define SK_RCINIT_TX1 0x01C2 493 #define SK_RCINIT_TX2 0x01C3 494 #define SK_RCTIMEO_RX1 0x01C4 495 #define SK_RCTIMEO_RX2 0x01C5 496 #define SK_RCTIMEO_TX1 0x01C6 497 #define SK_RCTIMEO_TX2 0x01C7 498 #define SK_RECOVERY_CTL 0x01C8 499 #define SK_RCTIMER_TST 0x01CA 500 501 /* Packet arbiter registers */ 502 #define SK_RXPA1_TINIT 0x01D0 503 #define SK_RXPA2_TINIT 0x01D4 504 #define SK_TXPA1_TINIT 0x01D8 505 #define SK_TXPA2_TINIT 0x01DC 506 #define SK_RXPA1_TIMEO 0x01E0 507 #define SK_RXPA2_TIMEO 0x01E4 508 #define SK_TXPA1_TIMEO 0x01E8 509 #define SK_TXPA2_TIMEO 0x01EC 510 #define SK_PKTARB_CTL 0x01F0 511 #define SK_PKTATB_TST 0x01F2 512 513 #define SK_PKTARB_TIMEOUT 0x2000 514 515 #define SK_PKTARBCTL_RESET 0x0001 516 #define SK_PKTARBCTL_UNRESET 0x0002 517 #define SK_PKTARBCTL_RXTO1_OFF 0x0004 518 #define SK_PKTARBCTL_RXTO1_ON 0x0008 519 #define SK_PKTARBCTL_RXTO2_OFF 0x0010 520 #define SK_PKTARBCTL_RXTO2_ON 0x0020 521 #define SK_PKTARBCTL_TXTO1_OFF 0x0040 522 #define SK_PKTARBCTL_TXTO1_ON 0x0080 523 #define SK_PKTARBCTL_TXTO2_OFF 0x0100 524 #define SK_PKTARBCTL_TXTO2_ON 0x0200 525 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 526 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 527 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 528 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 529 530 #define SK_MINIT_XMAC_B2 54 531 #define SK_MINIT_XMAC_C1 63 532 533 #define SK_MACARBCTL_RESET 0x0001 534 #define SK_MACARBCTL_UNRESET 0x0002 535 #define SK_MACARBCTL_FASTOE_OFF 0x0004 536 #define SK_MACARBCRL_FASTOE_ON 0x0008 537 538 #define SK_RCINIT_XMAC_B2 54 539 #define SK_RCINIT_XMAC_C1 0 540 541 #define SK_RECOVERYCTL_RX1_OFF 0x0001 542 #define SK_RECOVERYCTL_RX1_ON 0x0002 543 #define SK_RECOVERYCTL_RX2_OFF 0x0004 544 #define SK_RECOVERYCTL_RX2_ON 0x0008 545 #define SK_RECOVERYCTL_TX1_OFF 0x0010 546 #define SK_RECOVERYCTL_TX1_ON 0x0020 547 #define SK_RECOVERYCTL_TX2_OFF 0x0040 548 #define SK_RECOVERYCTL_TX2_ON 0x0080 549 550 #define SK_RECOVERY_XMAC_B2 \ 551 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 552 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 553 554 #define SK_RECOVERY_XMAC_C1 \ 555 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 556 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 557 558 /* Block 4 -- TX Arbiter MAC 1 */ 559 #define SK_TXAR1_TIMERINIT 0x0200 560 #define SK_TXAR1_TIMERVAL 0x0204 561 #define SK_TXAR1_LIMITINIT 0x0208 562 #define SK_TXAR1_LIMITCNT 0x020C 563 #define SK_TXAR1_COUNTERCTL 0x0210 564 #define SK_TXAR1_COUNTERTST 0x0212 565 #define SK_TXAR1_COUNTERSTS 0x0212 566 567 /* Block 5 -- TX Arbiter MAC 2 */ 568 #define SK_TXAR2_TIMERINIT 0x0280 569 #define SK_TXAR2_TIMERVAL 0x0284 570 #define SK_TXAR2_LIMITINIT 0x0288 571 #define SK_TXAR2_LIMITCNT 0x028C 572 #define SK_TXAR2_COUNTERCTL 0x0290 573 #define SK_TXAR2_COUNTERTST 0x0291 574 #define SK_TXAR2_COUNTERSTS 0x0292 575 576 #define SK_TXARCTL_OFF 0x01 577 #define SK_TXARCTL_ON 0x02 578 #define SK_TXARCTL_RATECTL_OFF 0x04 579 #define SK_TXARCTL_RATECTL_ON 0x08 580 #define SK_TXARCTL_ALLOC_OFF 0x10 581 #define SK_TXARCTL_ALLOC_ON 0x20 582 #define SK_TXARCTL_FSYNC_OFF 0x40 583 #define SK_TXARCTL_FSYNC_ON 0x80 584 585 /* Block 6 -- External registers */ 586 #define SK_EXTREG_BASE 0x300 587 #define SK_EXTREG_END 0x37C 588 589 /* Block 7 -- PCI config registers */ 590 #define SK_PCI_BASE 0x0380 591 #define SK_PCI_END 0x03FC 592 593 /* Compute offset of mirrored PCI register */ 594 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 595 596 /* Block 8 -- RX queue 1 */ 597 #define SK_RXQ1_BUFCNT 0x0400 598 #define SK_RXQ1_BUFCTL 0x0402 599 #define SK_RXQ1_NEXTDESC 0x0404 600 #define SK_RXQ1_RXBUF_LO 0x0408 601 #define SK_RXQ1_RXBUF_HI 0x040C 602 #define SK_RXQ1_RXSTAT 0x0410 603 #define SK_RXQ1_TIMESTAMP 0x0414 604 #define SK_RXQ1_CSUM1 0x0418 605 #define SK_RXQ1_CSUM2 0x041A 606 #define SK_RXQ1_CSUM1_START 0x041C 607 #define SK_RXQ1_CSUM2_START 0x041E 608 #define SK_RXQ1_CURADDR_LO 0x0420 609 #define SK_RXQ1_CURADDR_HI 0x0424 610 #define SK_RXQ1_CURCNT_LO 0x0428 611 #define SK_RXQ1_CURCNT_HI 0x042C 612 #define SK_RXQ1_CURBYTES 0x0430 613 #define SK_RXQ1_BMU_CSR 0x0434 614 #define SK_RXQ1_WATERMARK 0x0438 615 #define SK_RXQ1_FLAG 0x043A 616 #define SK_RXQ1_TEST1 0x043C 617 #define SK_RXQ1_TEST2 0x0440 618 #define SK_RXQ1_TEST3 0x0444 619 620 /* Block 9 -- RX queue 2 */ 621 #define SK_RXQ2_BUFCNT 0x0480 622 #define SK_RXQ2_BUFCTL 0x0482 623 #define SK_RXQ2_NEXTDESC 0x0484 624 #define SK_RXQ2_RXBUF_LO 0x0488 625 #define SK_RXQ2_RXBUF_HI 0x048C 626 #define SK_RXQ2_RXSTAT 0x0490 627 #define SK_RXQ2_TIMESTAMP 0x0494 628 #define SK_RXQ2_CSUM1 0x0498 629 #define SK_RXQ2_CSUM2 0x049A 630 #define SK_RXQ2_CSUM1_START 0x049C 631 #define SK_RXQ2_CSUM2_START 0x049E 632 #define SK_RXQ2_CURADDR_LO 0x04A0 633 #define SK_RXQ2_CURADDR_HI 0x04A4 634 #define SK_RXQ2_CURCNT_LO 0x04A8 635 #define SK_RXQ2_CURCNT_HI 0x04AC 636 #define SK_RXQ2_CURBYTES 0x04B0 637 #define SK_RXQ2_BMU_CSR 0x04B4 638 #define SK_RXQ2_WATERMARK 0x04B8 639 #define SK_RXQ2_FLAG 0x04BA 640 #define SK_RXQ2_TEST1 0x04BC 641 #define SK_RXQ2_TEST2 0x04C0 642 #define SK_RXQ2_TEST3 0x04C4 643 644 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 645 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 646 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 647 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 648 #define SK_RXBMU_RX_START 0x00000010 649 #define SK_RXBMU_RX_STOP 0x00000020 650 #define SK_RXBMU_POLL_OFF 0x00000040 651 #define SK_RXBMU_POLL_ON 0x00000080 652 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 653 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 654 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 655 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 656 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 657 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 658 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 659 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 660 #define SK_RXBMU_PFI_SM_RESET 0x00010000 661 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 662 #define SK_RXBMU_FIFO_RESET 0x00040000 663 #define SK_RXBMU_FIFO_UNRESET 0x00080000 664 #define SK_RXBMU_DESC_RESET 0x00100000 665 #define SK_RXBMU_DESC_UNRESET 0x00200000 666 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 667 668 #define SK_RXBMU_ONLINE \ 669 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 670 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 671 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 672 SK_RXBMU_DESC_UNRESET) 673 674 #define SK_RXBMU_OFFLINE \ 675 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 676 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 677 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 678 SK_RXBMU_DESC_RESET) 679 680 /* Block 12 -- TX sync queue 1 */ 681 #define SK_TXQS1_BUFCNT 0x0600 682 #define SK_TXQS1_BUFCTL 0x0602 683 #define SK_TXQS1_NEXTDESC 0x0604 684 #define SK_TXQS1_RXBUF_LO 0x0608 685 #define SK_TXQS1_RXBUF_HI 0x060C 686 #define SK_TXQS1_RXSTAT 0x0610 687 #define SK_TXQS1_CSUM_STARTVAL 0x0614 688 #define SK_TXQS1_CSUM_STARTPOS 0x0618 689 #define SK_TXQS1_CSUM_WRITEPOS 0x061A 690 #define SK_TXQS1_CURADDR_LO 0x0620 691 #define SK_TXQS1_CURADDR_HI 0x0624 692 #define SK_TXQS1_CURCNT_LO 0x0628 693 #define SK_TXQS1_CURCNT_HI 0x062C 694 #define SK_TXQS1_CURBYTES 0x0630 695 #define SK_TXQS1_BMU_CSR 0x0634 696 #define SK_TXQS1_WATERMARK 0x0638 697 #define SK_TXQS1_FLAG 0x063A 698 #define SK_TXQS1_TEST1 0x063C 699 #define SK_TXQS1_TEST2 0x0640 700 #define SK_TXQS1_TEST3 0x0644 701 702 /* Block 13 -- TX async queue 1 */ 703 #define SK_TXQA1_BUFCNT 0x0680 704 #define SK_TXQA1_BUFCTL 0x0682 705 #define SK_TXQA1_NEXTDESC 0x0684 706 #define SK_TXQA1_RXBUF_LO 0x0688 707 #define SK_TXQA1_RXBUF_HI 0x068C 708 #define SK_TXQA1_RXSTAT 0x0690 709 #define SK_TXQA1_CSUM_STARTVAL 0x0694 710 #define SK_TXQA1_CSUM_STARTPOS 0x0698 711 #define SK_TXQA1_CSUM_WRITEPOS 0x069A 712 #define SK_TXQA1_CURADDR_LO 0x06A0 713 #define SK_TXQA1_CURADDR_HI 0x06A4 714 #define SK_TXQA1_CURCNT_LO 0x06A8 715 #define SK_TXQA1_CURCNT_HI 0x06AC 716 #define SK_TXQA1_CURBYTES 0x06B0 717 #define SK_TXQA1_BMU_CSR 0x06B4 718 #define SK_TXQA1_WATERMARK 0x06B8 719 #define SK_TXQA1_FLAG 0x06BA 720 #define SK_TXQA1_TEST1 0x06BC 721 #define SK_TXQA1_TEST2 0x06C0 722 #define SK_TXQA1_TEST3 0x06C4 723 724 /* Block 14 -- TX sync queue 2 */ 725 #define SK_TXQS2_BUFCNT 0x0700 726 #define SK_TXQS2_BUFCTL 0x0702 727 #define SK_TXQS2_NEXTDESC 0x0704 728 #define SK_TXQS2_RXBUF_LO 0x0708 729 #define SK_TXQS2_RXBUF_HI 0x070C 730 #define SK_TXQS2_RXSTAT 0x0710 731 #define SK_TXQS2_CSUM_STARTVAL 0x0714 732 #define SK_TXQS2_CSUM_STARTPOS 0x0718 733 #define SK_TXQS2_CSUM_WRITEPOS 0x071A 734 #define SK_TXQS2_CURADDR_LO 0x0720 735 #define SK_TXQS2_CURADDR_HI 0x0724 736 #define SK_TXQS2_CURCNT_LO 0x0728 737 #define SK_TXQS2_CURCNT_HI 0x072C 738 #define SK_TXQS2_CURBYTES 0x0730 739 #define SK_TXQS2_BMU_CSR 0x0734 740 #define SK_TXQS2_WATERMARK 0x0738 741 #define SK_TXQS2_FLAG 0x073A 742 #define SK_TXQS2_TEST1 0x073C 743 #define SK_TXQS2_TEST2 0x0740 744 #define SK_TXQS2_TEST3 0x0744 745 746 /* Block 15 -- TX async queue 2 */ 747 #define SK_TXQA2_BUFCNT 0x0780 748 #define SK_TXQA2_BUFCTL 0x0782 749 #define SK_TXQA2_NEXTDESC 0x0784 750 #define SK_TXQA2_RXBUF_LO 0x0788 751 #define SK_TXQA2_RXBUF_HI 0x078C 752 #define SK_TXQA2_RXSTAT 0x0790 753 #define SK_TXQA2_CSUM_STARTVAL 0x0794 754 #define SK_TXQA2_CSUM_STARTPOS 0x0798 755 #define SK_TXQA2_CSUM_WRITEPOS 0x079A 756 #define SK_TXQA2_CURADDR_LO 0x07A0 757 #define SK_TXQA2_CURADDR_HI 0x07A4 758 #define SK_TXQA2_CURCNT_LO 0x07A8 759 #define SK_TXQA2_CURCNT_HI 0x07AC 760 #define SK_TXQA2_CURBYTES 0x07B0 761 #define SK_TXQA2_BMU_CSR 0x07B4 762 #define SK_TXQA2_WATERMARK 0x07B8 763 #define SK_TXQA2_FLAG 0x07BA 764 #define SK_TXQA2_TEST1 0x07BC 765 #define SK_TXQA2_TEST2 0x07C0 766 #define SK_TXQA2_TEST3 0x07C4 767 768 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 769 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 770 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 771 #define SK_TXBMU_TX_START 0x00000010 772 #define SK_TXBMU_TX_STOP 0x00000020 773 #define SK_TXBMU_POLL_OFF 0x00000040 774 #define SK_TXBMU_POLL_ON 0x00000080 775 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 776 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 777 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 778 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 779 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 780 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 781 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 782 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 783 #define SK_TXBMU_PFI_SM_RESET 0x00010000 784 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 785 #define SK_TXBMU_FIFO_RESET 0x00040000 786 #define SK_TXBMU_FIFO_UNRESET 0x00080000 787 #define SK_TXBMU_DESC_RESET 0x00100000 788 #define SK_TXBMU_DESC_UNRESET 0x00200000 789 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 790 791 #define SK_TXBMU_ONLINE \ 792 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 793 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 794 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 795 SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON) 796 797 #define SK_TXBMU_OFFLINE \ 798 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 799 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 800 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 801 SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF) 802 803 /* Block 16 -- Receive RAMbuffer 1 */ 804 #define SK_RXRB1_START 0x0800 805 #define SK_RXRB1_END 0x0804 806 #define SK_RXRB1_WR_PTR 0x0808 807 #define SK_RXRB1_RD_PTR 0x080C 808 #define SK_RXRB1_UTHR_PAUSE 0x0810 809 #define SK_RXRB1_LTHR_PAUSE 0x0814 810 #define SK_RXRB1_UTHR_HIPRIO 0x0818 811 #define SK_RXRB1_UTHR_LOPRIO 0x081C 812 #define SK_RXRB1_PKTCNT 0x0820 813 #define SK_RXRB1_LVL 0x0824 814 #define SK_RXRB1_CTLTST 0x0828 815 816 /* Block 17 -- Receive RAMbuffer 2 */ 817 #define SK_RXRB2_START 0x0880 818 #define SK_RXRB2_END 0x0884 819 #define SK_RXRB2_WR_PTR 0x0888 820 #define SK_RXRB2_RD_PTR 0x088C 821 #define SK_RXRB2_UTHR_PAUSE 0x0890 822 #define SK_RXRB2_LTHR_PAUSE 0x0894 823 #define SK_RXRB2_UTHR_HIPRIO 0x0898 824 #define SK_RXRB2_UTHR_LOPRIO 0x089C 825 #define SK_RXRB2_PKTCNT 0x08A0 826 #define SK_RXRB2_LVL 0x08A4 827 #define SK_RXRB2_CTLTST 0x08A8 828 829 /* Block 20 -- Sync. Transmit RAMbuffer 1 */ 830 #define SK_TXRBS1_START 0x0A00 831 #define SK_TXRBS1_END 0x0A04 832 #define SK_TXRBS1_WR_PTR 0x0A08 833 #define SK_TXRBS1_RD_PTR 0x0A0C 834 #define SK_TXRBS1_PKTCNT 0x0A20 835 #define SK_TXRBS1_LVL 0x0A24 836 #define SK_TXRBS1_CTLTST 0x0A28 837 838 /* Block 21 -- Async. Transmit RAMbuffer 1 */ 839 #define SK_TXRBA1_START 0x0A80 840 #define SK_TXRBA1_END 0x0A84 841 #define SK_TXRBA1_WR_PTR 0x0A88 842 #define SK_TXRBA1_RD_PTR 0x0A8C 843 #define SK_TXRBA1_PKTCNT 0x0AA0 844 #define SK_TXRBA1_LVL 0x0AA4 845 #define SK_TXRBA1_CTLTST 0x0AA8 846 847 /* Block 22 -- Sync. Transmit RAMbuffer 2 */ 848 #define SK_TXRBS2_START 0x0B00 849 #define SK_TXRBS2_END 0x0B04 850 #define SK_TXRBS2_WR_PTR 0x0B08 851 #define SK_TXRBS2_RD_PTR 0x0B0C 852 #define SK_TXRBS2_PKTCNT 0x0B20 853 #define SK_TXRBS2_LVL 0x0B24 854 #define SK_TXRBS2_CTLTST 0x0B28 855 856 /* Block 23 -- Async. Transmit RAMbuffer 2 */ 857 #define SK_TXRBA2_START 0x0B80 858 #define SK_TXRBA2_END 0x0B84 859 #define SK_TXRBA2_WR_PTR 0x0B88 860 #define SK_TXRBA2_RD_PTR 0x0B8C 861 #define SK_TXRBA2_PKTCNT 0x0BA0 862 #define SK_TXRBA2_LVL 0x0BA4 863 #define SK_TXRBA2_CTLTST 0x0BA8 864 865 #define SK_RBCTL_RESET 0x00000001 866 #define SK_RBCTL_UNRESET 0x00000002 867 #define SK_RBCTL_OFF 0x00000004 868 #define SK_RBCTL_ON 0x00000008 869 #define SK_RBCTL_STORENFWD_OFF 0x00000010 870 #define SK_RBCTL_STORENFWD_ON 0x00000020 871 872 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 873 #define SK_RXF1_END 0x0C00 874 #define SK_RXF1_WPTR 0x0C04 875 #define SK_RXF1_RPTR 0x0C0C 876 #define SK_RXF1_PKTCNT 0x0C10 877 #define SK_RXF1_LVL 0x0C14 878 #define SK_RXF1_MACCTL 0x0C18 879 #define SK_RXF1_CTL 0x0C1C 880 #define SK_RXLED1_CNTINIT 0x0C20 881 #define SK_RXLED1_COUNTER 0x0C24 882 #define SK_RXLED1_CTL 0x0C28 883 #define SK_RXLED1_TST 0x0C29 884 #define SK_LINK_SYNC1_CINIT 0x0C30 885 #define SK_LINK_SYNC1_COUNTER 0x0C34 886 #define SK_LINK_SYNC1_CTL 0x0C38 887 #define SK_LINK_SYNC1_TST 0x0C39 888 #define SK_LINKLED1_CTL 0x0C3C 889 890 #define SK_FIFO_END 0x3F 891 892 /* Receive MAC FIFO 1 (Yukon Only) */ 893 #define SK_RXMF1_END 0x0C40 894 #define SK_RXMF1_THRESHOLD 0x0C44 895 #define SK_RXMF1_CTRL_TEST 0x0C48 896 #define SK_RXMF1_FLUSH_MASK 0x0C4C 897 #define SK_RXMF1_FLUSH_THRESHOLD 0x0C50 898 #define SK_RXMF1_WRITE_PTR 0x0C60 899 #define SK_RXMF1_WRITE_LEVEL 0x0C68 900 #define SK_RXMF1_READ_PTR 0x0C70 901 #define SK_RXMF1_READ_LEVEL 0x0C78 902 903 /* Receive MAC FIFO 1 Control/Test */ 904 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 905 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 906 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 907 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 908 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 909 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 910 #define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */ 911 #define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */ 912 #define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */ 913 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 914 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 915 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 916 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 917 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 918 919 #define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */ 920 921 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 922 #define SK_RXF2_END 0x0C80 923 #define SK_RXF2_WPTR 0x0C84 924 #define SK_RXF2_RPTR 0x0C8C 925 #define SK_RXF2_PKTCNT 0x0C90 926 #define SK_RXF2_LVL 0x0C94 927 #define SK_RXF2_MACCTL 0x0C98 928 #define SK_RXF2_CTL 0x0C9C 929 #define SK_RXLED2_CNTINIT 0x0CA0 930 #define SK_RXLED2_COUNTER 0x0CA4 931 #define SK_RXLED2_CTL 0x0CA8 932 #define SK_RXLED2_TST 0x0CA9 933 #define SK_LINK_SYNC2_CINIT 0x0CB0 934 #define SK_LINK_SYNC2_COUNTER 0x0CB4 935 #define SK_LINK_SYNC2_CTL 0x0CB8 936 #define SK_LINK_SYNC2_TST 0x0CB9 937 #define SK_LINKLED2_CTL 0x0CBC 938 939 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 940 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 941 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 942 #define SK_RXMACCTL_RSTAMP_ON 0x00000008 943 #define SK_RXMACCTL_FLUSH_OFF 0x00000010 944 #define SK_RXMACCTL_FLUSH_ON 0x00000020 945 #define SK_RXMACCTL_PAUSE_OFF 0x00000040 946 #define SK_RXMACCTL_PAUSE_ON 0x00000080 947 #define SK_RXMACCTL_AFULL_OFF 0x00000100 948 #define SK_RXMACCTL_AFULL_ON 0x00000200 949 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 950 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 951 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 952 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 953 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 954 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 955 956 #define SK_RXLEDCTL_ENABLE 0x0001 957 #define SK_RXLEDCTL_COUNTER_STOP 0x0002 958 #define SK_RXLEDCTL_COUNTER_START 0x0004 959 960 #define SK_LINKLED_OFF 0x0001 961 #define SK_LINKLED_ON 0x0002 962 #define SK_LINKLED_LINKSYNC_OFF 0x0004 963 #define SK_LINKLED_LINKSYNC_ON 0x0008 964 #define SK_LINKLED_BLINK_OFF 0x0010 965 #define SK_LINKLED_BLINK_ON 0x0020 966 967 /* Block 26 -- TX MAC FIFO 1 regisrers */ 968 #define SK_TXF1_END 0x0D00 969 #define SK_TXF1_WPTR 0x0D04 970 #define SK_TXF1_RPTR 0x0D0C 971 #define SK_TXF1_PKTCNT 0x0D10 972 #define SK_TXF1_LVL 0x0D14 973 #define SK_TXF1_MACCTL 0x0D18 974 #define SK_TXF1_CTL 0x0D1C 975 #define SK_TXLED1_CNTINIT 0x0D20 976 #define SK_TXLED1_COUNTER 0x0D24 977 #define SK_TXLED1_CTL 0x0D28 978 #define SK_TXLED1_TST 0x0D29 979 980 /* Transmit MAC FIFO 1 (Yukon Only) */ 981 #define SK_TXMF1_END 0x0D40 982 #define SK_TXMF1_THRESHOLD 0x0D44 983 #define SK_TXMF1_CTRL_TEST 0x0D48 984 #define SK_TXMF1_WRITE_PTR 0x0D60 985 #define SK_TXMF1_WRITE_SHADOW 0x0D64 986 #define SK_TXMF1_WRITE_LEVEL 0x0D68 987 #define SK_TXMF1_READ_PTR 0x0D70 988 #define SK_TXMF1_RESTART_PTR 0x0D74 989 #define SK_TXMF1_READ_LEVEL 0x0D78 990 991 /* Transmit MAC FIFO Control/Test */ 992 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 993 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 994 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 995 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 996 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 997 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 998 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 999 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 1000 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 1001 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 1002 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 1003 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 1004 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 1005 1006 /* Block 27 -- TX MAC FIFO 2 regisrers */ 1007 #define SK_TXF2_END 0x0D80 1008 #define SK_TXF2_WPTR 0x0D84 1009 #define SK_TXF2_RPTR 0x0D8C 1010 #define SK_TXF2_PKTCNT 0x0D90 1011 #define SK_TXF2_LVL 0x0D94 1012 #define SK_TXF2_MACCTL 0x0D98 1013 #define SK_TXF2_CTL 0x0D9C 1014 #define SK_TXLED2_CNTINIT 0x0DA0 1015 #define SK_TXLED2_COUNTER 0x0DA4 1016 #define SK_TXLED2_CTL 0x0DA8 1017 #define SK_TXLED2_TST 0x0DA9 1018 1019 #define SK_TXMACCTL_XMAC_RESET 0x00000001 1020 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 1021 #define SK_TXMACCTL_LOOP_OFF 0x00000004 1022 #define SK_TXMACCTL_LOOP_ON 0x00000008 1023 #define SK_TXMACCTL_FLUSH_OFF 0x00000010 1024 #define SK_TXMACCTL_FLUSH_ON 0x00000020 1025 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 1026 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 1027 #define SK_TXMACCTL_AFULL_OFF 0x00000100 1028 #define SK_TXMACCTL_AFULL_ON 0x00000200 1029 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 1030 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 1031 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1032 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1033 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1034 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1035 1036 #define SK_TXLEDCTL_ENABLE 0x0001 1037 #define SK_TXLEDCTL_COUNTER_STOP 0x0002 1038 #define SK_TXLEDCTL_COUNTER_START 0x0004 1039 1040 #define SK_FIFO_RESET 0x00000001 1041 #define SK_FIFO_UNRESET 0x00000002 1042 #define SK_FIFO_OFF 0x00000004 1043 #define SK_FIFO_ON 0x00000008 1044 1045 /* Block 28 -- Descriptor Poll Timer */ 1046 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1047 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1048 1049 #define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */ 1050 1051 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1052 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1053 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1054 1055 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1056 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1057 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1058 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1059 1060 /* Block 29 -- reserved */ 1061 1062 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1063 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1064 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1065 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1066 #define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */ 1067 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1068 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1069 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1070 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1071 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1072 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1073 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1074 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1075 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1076 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1077 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1078 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1079 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1080 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1081 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1082 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1083 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1084 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1085 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1086 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1087 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1088 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1089 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1090 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1091 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1092 1093 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1094 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1095 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1096 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1097 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1098 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1099 1100 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1101 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1102 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1103 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1104 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1105 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1106 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1107 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1108 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1109 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1110 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1111 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1112 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1113 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1114 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1115 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1116 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1117 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1118 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1119 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1120 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1121 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1122 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1123 1124 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1125 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1126 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1127 SK_GPHY_HWCFG_M_2 ) 1128 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1129 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1130 1131 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1132 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1133 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1134 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1135 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1136 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1137 1138 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1139 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1140 1141 /* Block 31 -- reserved */ 1142 1143 /* Block 32-33 -- Pattern Ram */ 1144 #define SK_WOL_PRAM 0x1000 1145 1146 /* Block 0x22 - 0x3f -- reserved */ 1147 1148 /* Block 0x40 to 0x4F -- XMAC 1 registers */ 1149 #define SK_XMAC1_BASE 0x2000 1150 1151 /* Block 0x50 to 0x5F -- MARV 1 registers */ 1152 #define SK_MARV1_BASE 0x2800 1153 1154 /* Block 0x60 to 0x6F -- XMAC 2 registers */ 1155 #define SK_XMAC2_BASE 0x3000 1156 1157 /* Block 0x70 to 0x7F -- MARV 2 registers */ 1158 #define SK_MARV2_BASE 0x3800 1159 1160 /* Compute relative offset of an XMAC register in the XMAC window(s). */ 1161 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1162 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1163 1164 #if 0 1165 #define SK_XM_READ_4(sc, reg) \ 1166 ((sk_win_read_2(sc->sk_softc, \ 1167 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1168 ((sk_win_read_2(sc->sk_softc, \ 1169 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1170 1171 #define SK_XM_WRITE_4(sc, reg, val) \ 1172 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1173 ((val) & 0xFFFF)); \ 1174 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1175 ((val) >> 16) & 0xFFFF) 1176 #else 1177 #define SK_XM_READ_4(sc, reg) \ 1178 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1179 1180 #define SK_XM_WRITE_4(sc, reg, val) \ 1181 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1182 #endif 1183 1184 #define SK_XM_READ_2(sc, reg) \ 1185 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1186 1187 #define SK_XM_WRITE_2(sc, reg, val) \ 1188 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1189 1190 #define SK_XM_SETBIT_4(sc, reg, x) \ 1191 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1192 1193 #define SK_XM_CLRBIT_4(sc, reg, x) \ 1194 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1195 1196 #define SK_XM_SETBIT_2(sc, reg, x) \ 1197 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1198 1199 #define SK_XM_CLRBIT_2(sc, reg, x) \ 1200 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1201 1202 /* Compute relative offset of an MARV register in the MARV window(s). */ 1203 #define SK_YU_REG(sc, reg) \ 1204 ((reg) + SK_MARV1_BASE + \ 1205 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1206 1207 #define SK_YU_READ_4(sc, reg) \ 1208 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1209 1210 #define SK_YU_READ_2(sc, reg) \ 1211 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1212 1213 #define SK_YU_WRITE_4(sc, reg, val) \ 1214 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1215 1216 #define SK_YU_WRITE_2(sc, reg, val) \ 1217 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1218 1219 #define SK_YU_SETBIT_4(sc, reg, x) \ 1220 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1221 1222 #define SK_YU_CLRBIT_4(sc, reg, x) \ 1223 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1224 1225 #define SK_YU_SETBIT_2(sc, reg, x) \ 1226 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1227 1228 #define SK_YU_CLRBIT_2(sc, reg, x) \ 1229 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1230 1231 /* 1232 * The default FIFO threshold on the XMAC II is 4 bytes. On 1233 * dual port NICs, this often leads to transmit underruns, so we 1234 * bump the threshold a little. 1235 */ 1236 #define SK_XM_TX_FIFOTHRESH 512 1237 1238 #define SK_PCI_VENDOR_ID 0x0000 1239 #define SK_PCI_DEVICE_ID 0x0002 1240 #define SK_PCI_COMMAND 0x0004 1241 #define SK_PCI_STATUS 0x0006 1242 #define SK_PCI_REVID 0x0008 1243 #define SK_PCI_CLASSCODE 0x0009 1244 #define SK_PCI_CACHELEN 0x000C 1245 #define SK_PCI_LATENCY_TIMER 0x000D 1246 #define SK_PCI_HEADER_TYPE 0x000E 1247 #define SK_PCI_LOMEM 0x0010 1248 #define SK_PCI_LOIO 0x0014 1249 #define SK_PCI_SUBVEN_ID 0x002C 1250 #define SK_PCI_SYBSYS_ID 0x002E 1251 #define SK_PCI_BIOSROM 0x0030 1252 #define SK_PCI_INTLINE 0x003C 1253 #define SK_PCI_INTPIN 0x003D 1254 #define SK_PCI_MINGNT 0x003E 1255 #define SK_PCI_MINLAT 0x003F 1256 1257 /* device specific PCI registers */ 1258 #define SK_PCI_OURREG1 0x0040 1259 #define SK_PCI_OURREG2 0x0044 1260 #define SK_PCI_CAPID 0x0048 /* 8 bits */ 1261 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1262 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1263 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1264 #define SK_PCI_PME_EVENT 0x004F 1265 1266 #define SK_PSTATE_MASK 0x0003 1267 #define SK_PSTATE_D0 0x0000 1268 #define SK_PSTATE_D1 0x0001 1269 #define SK_PSTATE_D2 0x0002 1270 #define SK_PSTATE_D3 0x0003 1271 #define SK_PME_EN 0x0010 1272 #define SK_PME_STATUS 0x8000 1273 1274 #define CSR_WRITE_4(sc, reg, val) \ 1275 bus_write_4((sc)->sk_res[0], (reg), (val)) 1276 #define CSR_WRITE_2(sc, reg, val) \ 1277 bus_write_2((sc)->sk_res[0], (reg), (val)) 1278 #define CSR_WRITE_1(sc, reg, val) \ 1279 bus_write_1((sc)->sk_res[0], (reg), (val)) 1280 1281 #define CSR_READ_4(sc, reg) \ 1282 bus_read_4((sc)->sk_res[0], (reg)) 1283 #define CSR_READ_2(sc, reg) \ 1284 bus_read_2((sc)->sk_res[0], (reg)) 1285 #define CSR_READ_1(sc, reg) \ 1286 bus_read_1((sc)->sk_res[0], (reg)) 1287 1288 struct sk_type { 1289 u_int16_t sk_vid; 1290 u_int16_t sk_did; 1291 const char *sk_name; 1292 }; 1293 1294 #define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 1295 #define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32) 1296 1297 #define SK_RING_ALIGN 64 1298 1299 /* RX queue descriptor data structure */ 1300 struct sk_rx_desc { 1301 u_int32_t sk_ctl; 1302 u_int32_t sk_next; 1303 u_int32_t sk_data_lo; 1304 u_int32_t sk_data_hi; 1305 u_int32_t sk_xmac_rxstat; 1306 u_int32_t sk_timestamp; 1307 u_int32_t sk_csum; 1308 u_int32_t sk_csum_start; 1309 }; 1310 1311 #define SK_OPCODE_DEFAULT 0x00550000 1312 #define SK_OPCODE_CSUM 0x00560000 1313 1314 #define SK_RXCTL_LEN 0x0000FFFF 1315 #define SK_RXCTL_OPCODE 0x00FF0000 1316 #define SK_RXCTL_TSTAMP_VALID 0x01000000 1317 #define SK_RXCTL_STATUS_VALID 0x02000000 1318 #define SK_RXCTL_DEV0 0x04000000 1319 #define SK_RXCTL_EOF_INTR 0x08000000 1320 #define SK_RXCTL_EOB_INTR 0x10000000 1321 #define SK_RXCTL_LASTFRAG 0x20000000 1322 #define SK_RXCTL_FIRSTFRAG 0x40000000 1323 #define SK_RXCTL_OWN 0x80000000 1324 1325 #define SK_RXSTAT \ 1326 (SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG|SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1327 1328 struct sk_tx_desc { 1329 u_int32_t sk_ctl; 1330 u_int32_t sk_next; 1331 u_int32_t sk_data_lo; 1332 u_int32_t sk_data_hi; 1333 u_int32_t sk_xmac_txstat; 1334 u_int32_t sk_csum_startval; 1335 u_int32_t sk_csum_start; 1336 u_int32_t sk_rsvd1; 1337 }; 1338 1339 #define SK_TXCTL_LEN 0x0000FFFF 1340 #define SK_TXCTL_OPCODE 0x00FF0000 1341 #define SK_TXCTL_SW 0x01000000 1342 #define SK_TXCTL_NOCRC 0x02000000 1343 #define SK_TXCTL_STORENFWD 0x04000000 1344 #define SK_TXCTL_EOF_INTR 0x08000000 1345 #define SK_TXCTL_EOB_INTR 0x10000000 1346 #define SK_TXCTL_LASTFRAG 0x20000000 1347 #define SK_TXCTL_FIRSTFRAG 0x40000000 1348 #define SK_TXCTL_OWN 0x80000000 1349 1350 #define SK_TXSTAT \ 1351 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1352 1353 #define SK_RXBYTES(x) ((x) & 0x0000FFFF) 1354 #define SK_TXBYTES SK_RXBYTES 1355 1356 #define SK_TX_RING_CNT 512 1357 #define SK_RX_RING_CNT 256 1358 #define SK_JUMBO_RX_RING_CNT 256 1359 #define SK_MAXTXSEGS 32 1360 1361 #define SK_JUMBO_FRAMELEN 9018 1362 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1363 #define SK_MAX_FRAMELEN \ 1364 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 1365 #define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 1366 1367 struct sk_txdesc { 1368 struct mbuf *tx_m; 1369 bus_dmamap_t tx_dmamap; 1370 STAILQ_ENTRY(sk_txdesc) tx_q; 1371 }; 1372 1373 STAILQ_HEAD(sk_txdq, sk_txdesc); 1374 1375 struct sk_rxdesc { 1376 struct mbuf *rx_m; 1377 bus_dmamap_t rx_dmamap; 1378 }; 1379 1380 struct sk_chain_data { 1381 bus_dma_tag_t sk_parent_tag; 1382 bus_dma_tag_t sk_tx_tag; 1383 struct sk_txdesc sk_txdesc[SK_TX_RING_CNT]; 1384 struct sk_txdq sk_txfreeq; 1385 struct sk_txdq sk_txbusyq; 1386 bus_dma_tag_t sk_rx_tag; 1387 struct sk_rxdesc sk_rxdesc[SK_RX_RING_CNT]; 1388 bus_dma_tag_t sk_tx_ring_tag; 1389 bus_dma_tag_t sk_rx_ring_tag; 1390 bus_dmamap_t sk_tx_ring_map; 1391 bus_dmamap_t sk_rx_ring_map; 1392 bus_dmamap_t sk_rx_sparemap; 1393 bus_dma_tag_t sk_jumbo_rx_tag; 1394 struct sk_rxdesc sk_jumbo_rxdesc[SK_JUMBO_RX_RING_CNT]; 1395 bus_dma_tag_t sk_jumbo_rx_ring_tag; 1396 bus_dmamap_t sk_jumbo_rx_ring_map; 1397 bus_dmamap_t sk_jumbo_rx_sparemap; 1398 int sk_tx_prod; 1399 int sk_tx_cons; 1400 int sk_tx_cnt; 1401 int sk_rx_cons; 1402 int sk_jumbo_rx_cons; 1403 }; 1404 1405 struct sk_ring_data { 1406 struct sk_tx_desc *sk_tx_ring; 1407 bus_addr_t sk_tx_ring_paddr; 1408 struct sk_rx_desc *sk_rx_ring; 1409 bus_addr_t sk_rx_ring_paddr; 1410 struct sk_rx_desc *sk_jumbo_rx_ring; 1411 bus_addr_t sk_jumbo_rx_ring_paddr; 1412 }; 1413 1414 #define SK_TX_RING_ADDR(sc, i) \ 1415 ((sc)->sk_rdata.sk_tx_ring_paddr + sizeof(struct sk_tx_desc) * (i)) 1416 #define SK_RX_RING_ADDR(sc, i) \ 1417 ((sc)->sk_rdata.sk_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i)) 1418 #define SK_JUMBO_RX_RING_ADDR(sc, i) \ 1419 ((sc)->sk_rdata.sk_jumbo_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i)) 1420 1421 #define SK_TX_RING_SZ \ 1422 (sizeof(struct sk_tx_desc) * SK_TX_RING_CNT) 1423 #define SK_RX_RING_SZ \ 1424 (sizeof(struct sk_rx_desc) * SK_RX_RING_CNT) 1425 #define SK_JUMBO_RX_RING_SZ \ 1426 (sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT) 1427 1428 struct sk_bcom_hack { 1429 int reg; 1430 int val; 1431 }; 1432 1433 #define SK_INC(x, y) (x) = (x + 1) % y 1434 1435 /* Forward decl. */ 1436 struct sk_if_softc; 1437 1438 /* Softc for the GEnesis controller. */ 1439 struct sk_softc { 1440 struct resource *sk_res[2]; /* I/O and IRQ resources */ 1441 struct resource_spec *sk_res_spec; 1442 void *sk_intrhand; /* irq handler handle */ 1443 device_t sk_dev; 1444 u_int8_t sk_type; 1445 u_int8_t sk_rev; 1446 u_int8_t spare; 1447 u_int32_t sk_rboff; /* RAMbuffer offset */ 1448 u_int32_t sk_ramsize; /* amount of RAM on NIC */ 1449 u_int32_t sk_pmd; /* physical media type */ 1450 u_int32_t sk_coppertype; 1451 u_int32_t sk_intrmask; 1452 int sk_int_mod; 1453 int sk_int_ticks; 1454 int sk_suspended; 1455 struct sk_if_softc *sk_if[2]; 1456 device_t sk_devs[2]; 1457 struct mtx sk_mii_mtx; 1458 struct mtx sk_mtx; 1459 }; 1460 1461 #define SK_LOCK(_sc) mtx_lock(&(_sc)->sk_mtx) 1462 #define SK_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_mtx) 1463 #define SK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sk_mtx, MA_OWNED) 1464 #define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc) 1465 #define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc) 1466 #define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc) 1467 #define SK_IF_MII_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mii_mtx) 1468 #define SK_IF_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mii_mtx) 1469 1470 /* Softc for each logical interface */ 1471 struct sk_if_softc { 1472 if_t sk_ifp; /* interface info */ 1473 device_t sk_miibus; 1474 device_t sk_if_dev; 1475 u_int8_t sk_port; /* port # on controller */ 1476 u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */ 1477 u_int32_t sk_rx_ramstart; 1478 u_int32_t sk_rx_ramend; 1479 u_int32_t sk_tx_ramstart; 1480 u_int32_t sk_tx_ramend; 1481 int sk_phytype; 1482 int sk_phyaddr; 1483 int sk_link; 1484 struct callout sk_tick_ch; 1485 struct callout sk_watchdog_ch; 1486 int sk_watchdog_timer; 1487 struct sk_chain_data sk_cdata; 1488 struct sk_ring_data sk_rdata; 1489 struct sk_softc *sk_softc; /* parent controller */ 1490 int sk_tx_bmu; /* TX BMU register */ 1491 int sk_if_flags; 1492 int sk_jumbo_disable; 1493 }; 1494 1495 #define SK_TIMEOUT 1000 1496