1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Bill Paul. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 38 * 39 * Permission to use, copy, modify, and distribute this software for any 40 * purpose with or without fee is hereby granted, provided that the above 41 * copyright notice and this permission notice appear in all copies. 42 * 43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 50 */ 51 52 #include <sys/cdefs.h> 53 __FBSDID("$FreeBSD$"); 54 55 /* 56 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 57 * the SK-984x series adapters, both single port and dual port. 58 * References: 59 * The XaQti XMAC II datasheet, 60 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 61 * The SysKonnect GEnesis manual, http://www.syskonnect.com 62 * 63 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 64 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 65 * convenience to others until Vitesse corrects this problem: 66 * 67 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 68 * 69 * Written by Bill Paul <wpaul@ee.columbia.edu> 70 * Department of Electrical Engineering 71 * Columbia University, New York City 72 */ 73 /* 74 * The SysKonnect gigabit ethernet adapters consist of two main 75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 77 * components and a PHY while the GEnesis controller provides a PCI 78 * interface with DMA support. Each card may have between 512K and 79 * 2MB of SRAM on board depending on the configuration. 80 * 81 * The SysKonnect GEnesis controller can have either one or two XMAC 82 * chips connected to it, allowing single or dual port NIC configurations. 83 * SysKonnect has the distinction of being the only vendor on the market 84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 86 * XMAC registers. This driver takes advantage of these features to allow 87 * both XMACs to operate as independent interfaces. 88 */ 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/bus.h> 93 #include <sys/endian.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/module.h> 98 #include <sys/socket.h> 99 #include <sys/sockio.h> 100 #include <sys/queue.h> 101 #include <sys/sysctl.h> 102 103 #include <net/bpf.h> 104 #include <net/ethernet.h> 105 #include <net/if.h> 106 #include <net/if_var.h> 107 #include <net/if_arp.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/if_vlan_var.h> 112 113 #include <netinet/in.h> 114 #include <netinet/in_systm.h> 115 #include <netinet/ip.h> 116 117 #include <machine/bus.h> 118 #include <machine/in_cksum.h> 119 #include <machine/resource.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/brgphyreg.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 129 #if 0 130 #define SK_USEIOSPACE 131 #endif 132 133 #include <dev/sk/if_skreg.h> 134 #include <dev/sk/xmaciireg.h> 135 #include <dev/sk/yukonreg.h> 136 137 MODULE_DEPEND(sk, pci, 1, 1, 1); 138 MODULE_DEPEND(sk, ether, 1, 1, 1); 139 MODULE_DEPEND(sk, miibus, 1, 1, 1); 140 141 /* "device miibus" required. See GENERIC if you get errors here. */ 142 #include "miibus_if.h" 143 144 static const struct sk_type sk_devs[] = { 145 { 146 VENDORID_SK, 147 DEVICEID_SK_V1, 148 "SysKonnect Gigabit Ethernet (V1.0)" 149 }, 150 { 151 VENDORID_SK, 152 DEVICEID_SK_V2, 153 "SysKonnect Gigabit Ethernet (V2.0)" 154 }, 155 { 156 VENDORID_MARVELL, 157 DEVICEID_SK_V2, 158 "Marvell Gigabit Ethernet" 159 }, 160 { 161 VENDORID_MARVELL, 162 DEVICEID_BELKIN_5005, 163 "Belkin F5D5005 Gigabit Ethernet" 164 }, 165 { 166 VENDORID_3COM, 167 DEVICEID_3COM_3C940, 168 "3Com 3C940 Gigabit Ethernet" 169 }, 170 { 171 VENDORID_LINKSYS, 172 DEVICEID_LINKSYS_EG1032, 173 "Linksys EG1032 Gigabit Ethernet" 174 }, 175 { 176 VENDORID_DLINK, 177 DEVICEID_DLINK_DGE530T_A1, 178 "D-Link DGE-530T Gigabit Ethernet" 179 }, 180 { 181 VENDORID_DLINK, 182 DEVICEID_DLINK_DGE530T_B1, 183 "D-Link DGE-530T Gigabit Ethernet" 184 }, 185 { 0, 0, NULL } 186 }; 187 188 static int skc_probe(device_t); 189 static int skc_attach(device_t); 190 static int skc_detach(device_t); 191 static int skc_shutdown(device_t); 192 static int skc_suspend(device_t); 193 static int skc_resume(device_t); 194 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t); 195 static int sk_detach(device_t); 196 static int sk_probe(device_t); 197 static int sk_attach(device_t); 198 static void sk_tick(void *); 199 static void sk_yukon_tick(void *); 200 static void sk_intr(void *); 201 static void sk_intr_xmac(struct sk_if_softc *); 202 static void sk_intr_bcom(struct sk_if_softc *); 203 static void sk_intr_yukon(struct sk_if_softc *); 204 static __inline void sk_rxcksum(if_t, struct mbuf *, u_int32_t); 205 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 206 static void sk_rxeof(struct sk_if_softc *); 207 static void sk_jumbo_rxeof(struct sk_if_softc *); 208 static void sk_txeof(struct sk_if_softc *); 209 static void sk_txcksum(if_t, struct mbuf *, struct sk_tx_desc *); 210 static int sk_encap(struct sk_if_softc *, struct mbuf **); 211 static void sk_start(if_t); 212 static void sk_start_locked(if_t); 213 static int sk_ioctl(if_t, u_long, caddr_t); 214 static void sk_init(void *); 215 static void sk_init_locked(struct sk_if_softc *); 216 static void sk_init_xmac(struct sk_if_softc *); 217 static void sk_init_yukon(struct sk_if_softc *); 218 static void sk_stop(struct sk_if_softc *); 219 static void sk_watchdog(void *); 220 static int sk_ifmedia_upd(if_t); 221 static void sk_ifmedia_sts(if_t, struct ifmediareq *); 222 static void sk_reset(struct sk_softc *); 223 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 224 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 225 static int sk_newbuf(struct sk_if_softc *, int); 226 static int sk_jumbo_newbuf(struct sk_if_softc *, int); 227 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 228 static int sk_dma_alloc(struct sk_if_softc *); 229 static int sk_dma_jumbo_alloc(struct sk_if_softc *); 230 static void sk_dma_free(struct sk_if_softc *); 231 static void sk_dma_jumbo_free(struct sk_if_softc *); 232 static int sk_init_rx_ring(struct sk_if_softc *); 233 static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 234 static void sk_init_tx_ring(struct sk_if_softc *); 235 static u_int32_t sk_win_read_4(struct sk_softc *, int); 236 static u_int16_t sk_win_read_2(struct sk_softc *, int); 237 static u_int8_t sk_win_read_1(struct sk_softc *, int); 238 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 239 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 240 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 241 242 static int sk_miibus_readreg(device_t, int, int); 243 static int sk_miibus_writereg(device_t, int, int, int); 244 static void sk_miibus_statchg(device_t); 245 246 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 247 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 248 int); 249 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 250 251 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 252 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 253 int); 254 static void sk_marv_miibus_statchg(struct sk_if_softc *); 255 256 static uint32_t sk_xmchash(const uint8_t *); 257 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 258 static void sk_rxfilter(struct sk_if_softc *); 259 static void sk_rxfilter_genesis(struct sk_if_softc *); 260 static void sk_rxfilter_yukon(struct sk_if_softc *); 261 262 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 263 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 264 265 /* Tunables. */ 266 static int jumbo_disable = 0; 267 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable); 268 269 /* 270 * It seems that SK-NET GENESIS supports very simple checksum offload 271 * capability for Tx and I believe it can generate 0 checksum value for 272 * UDP packets in Tx as the hardware can't differenciate UDP packets from 273 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 274 * means sender didn't perforam checksum computation. For the safety I 275 * disabled UDP checksum offload capability at the moment. 276 */ 277 #define SK_CSUM_FEATURES (CSUM_TCP) 278 279 /* 280 * Note that we have newbus methods for both the GEnesis controller 281 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 282 * the miibus code is a child of the XMACs. We need to do it this way 283 * so that the miibus drivers can access the PHY registers on the 284 * right PHY. It's not quite what I had in mind, but it's the only 285 * design that achieves the desired effect. 286 */ 287 static device_method_t skc_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, skc_probe), 290 DEVMETHOD(device_attach, skc_attach), 291 DEVMETHOD(device_detach, skc_detach), 292 DEVMETHOD(device_suspend, skc_suspend), 293 DEVMETHOD(device_resume, skc_resume), 294 DEVMETHOD(device_shutdown, skc_shutdown), 295 296 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag), 297 298 DEVMETHOD_END 299 }; 300 301 static driver_t skc_driver = { 302 "skc", 303 skc_methods, 304 sizeof(struct sk_softc) 305 }; 306 307 static device_method_t sk_methods[] = { 308 /* Device interface */ 309 DEVMETHOD(device_probe, sk_probe), 310 DEVMETHOD(device_attach, sk_attach), 311 DEVMETHOD(device_detach, sk_detach), 312 DEVMETHOD(device_shutdown, bus_generic_shutdown), 313 314 /* MII interface */ 315 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 316 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 317 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 318 319 DEVMETHOD_END 320 }; 321 322 static driver_t sk_driver = { 323 "sk", 324 sk_methods, 325 sizeof(struct sk_if_softc) 326 }; 327 328 DRIVER_MODULE(skc, pci, skc_driver, NULL, NULL); 329 DRIVER_MODULE(sk, skc, sk_driver, NULL, NULL); 330 DRIVER_MODULE(miibus, sk, miibus_driver, NULL, NULL); 331 332 static struct resource_spec sk_res_spec_io[] = { 333 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 334 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 335 { -1, 0, 0 } 336 }; 337 338 static struct resource_spec sk_res_spec_mem[] = { 339 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 340 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 341 { -1, 0, 0 } 342 }; 343 344 #define SK_SETBIT(sc, reg, x) \ 345 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 346 347 #define SK_CLRBIT(sc, reg, x) \ 348 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 349 350 #define SK_WIN_SETBIT_4(sc, reg, x) \ 351 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 352 353 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 354 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 355 356 #define SK_WIN_SETBIT_2(sc, reg, x) \ 357 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 358 359 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 360 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 361 362 static u_int32_t 363 sk_win_read_4(sc, reg) 364 struct sk_softc *sc; 365 int reg; 366 { 367 #ifdef SK_USEIOSPACE 368 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 369 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 370 #else 371 return(CSR_READ_4(sc, reg)); 372 #endif 373 } 374 375 static u_int16_t 376 sk_win_read_2(sc, reg) 377 struct sk_softc *sc; 378 int reg; 379 { 380 #ifdef SK_USEIOSPACE 381 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 382 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 383 #else 384 return(CSR_READ_2(sc, reg)); 385 #endif 386 } 387 388 static u_int8_t 389 sk_win_read_1(sc, reg) 390 struct sk_softc *sc; 391 int reg; 392 { 393 #ifdef SK_USEIOSPACE 394 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 395 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 396 #else 397 return(CSR_READ_1(sc, reg)); 398 #endif 399 } 400 401 static void 402 sk_win_write_4(sc, reg, val) 403 struct sk_softc *sc; 404 int reg; 405 u_int32_t val; 406 { 407 #ifdef SK_USEIOSPACE 408 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 409 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 410 #else 411 CSR_WRITE_4(sc, reg, val); 412 #endif 413 return; 414 } 415 416 static void 417 sk_win_write_2(sc, reg, val) 418 struct sk_softc *sc; 419 int reg; 420 u_int32_t val; 421 { 422 #ifdef SK_USEIOSPACE 423 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 424 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 425 #else 426 CSR_WRITE_2(sc, reg, val); 427 #endif 428 return; 429 } 430 431 static void 432 sk_win_write_1(sc, reg, val) 433 struct sk_softc *sc; 434 int reg; 435 u_int32_t val; 436 { 437 #ifdef SK_USEIOSPACE 438 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 439 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 440 #else 441 CSR_WRITE_1(sc, reg, val); 442 #endif 443 return; 444 } 445 446 static int 447 sk_miibus_readreg(dev, phy, reg) 448 device_t dev; 449 int phy, reg; 450 { 451 struct sk_if_softc *sc_if; 452 int v; 453 454 sc_if = device_get_softc(dev); 455 456 SK_IF_MII_LOCK(sc_if); 457 switch(sc_if->sk_softc->sk_type) { 458 case SK_GENESIS: 459 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 460 break; 461 case SK_YUKON: 462 case SK_YUKON_LITE: 463 case SK_YUKON_LP: 464 v = sk_marv_miibus_readreg(sc_if, phy, reg); 465 break; 466 default: 467 v = 0; 468 break; 469 } 470 SK_IF_MII_UNLOCK(sc_if); 471 472 return (v); 473 } 474 475 static int 476 sk_miibus_writereg(dev, phy, reg, val) 477 device_t dev; 478 int phy, reg, val; 479 { 480 struct sk_if_softc *sc_if; 481 int v; 482 483 sc_if = device_get_softc(dev); 484 485 SK_IF_MII_LOCK(sc_if); 486 switch(sc_if->sk_softc->sk_type) { 487 case SK_GENESIS: 488 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 489 break; 490 case SK_YUKON: 491 case SK_YUKON_LITE: 492 case SK_YUKON_LP: 493 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 494 break; 495 default: 496 v = 0; 497 break; 498 } 499 SK_IF_MII_UNLOCK(sc_if); 500 501 return (v); 502 } 503 504 static void 505 sk_miibus_statchg(dev) 506 device_t dev; 507 { 508 struct sk_if_softc *sc_if; 509 510 sc_if = device_get_softc(dev); 511 512 SK_IF_MII_LOCK(sc_if); 513 switch(sc_if->sk_softc->sk_type) { 514 case SK_GENESIS: 515 sk_xmac_miibus_statchg(sc_if); 516 break; 517 case SK_YUKON: 518 case SK_YUKON_LITE: 519 case SK_YUKON_LP: 520 sk_marv_miibus_statchg(sc_if); 521 break; 522 } 523 SK_IF_MII_UNLOCK(sc_if); 524 525 return; 526 } 527 528 static int 529 sk_xmac_miibus_readreg(sc_if, phy, reg) 530 struct sk_if_softc *sc_if; 531 int phy, reg; 532 { 533 int i; 534 535 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 536 SK_XM_READ_2(sc_if, XM_PHY_DATA); 537 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 538 for (i = 0; i < SK_TIMEOUT; i++) { 539 DELAY(1); 540 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 541 XM_MMUCMD_PHYDATARDY) 542 break; 543 } 544 545 if (i == SK_TIMEOUT) { 546 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 547 return(0); 548 } 549 } 550 DELAY(1); 551 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 552 553 return(i); 554 } 555 556 static int 557 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 558 struct sk_if_softc *sc_if; 559 int phy, reg, val; 560 { 561 int i; 562 563 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 564 for (i = 0; i < SK_TIMEOUT; i++) { 565 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 566 break; 567 } 568 569 if (i == SK_TIMEOUT) { 570 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 571 return (ETIMEDOUT); 572 } 573 574 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 575 for (i = 0; i < SK_TIMEOUT; i++) { 576 DELAY(1); 577 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 578 break; 579 } 580 if (i == SK_TIMEOUT) 581 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 582 583 return(0); 584 } 585 586 static void 587 sk_xmac_miibus_statchg(sc_if) 588 struct sk_if_softc *sc_if; 589 { 590 struct mii_data *mii; 591 592 mii = device_get_softc(sc_if->sk_miibus); 593 594 /* 595 * If this is a GMII PHY, manually set the XMAC's 596 * duplex mode accordingly. 597 */ 598 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 599 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 600 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 601 } else { 602 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 603 } 604 } 605 } 606 607 static int 608 sk_marv_miibus_readreg(sc_if, phy, reg) 609 struct sk_if_softc *sc_if; 610 int phy, reg; 611 { 612 u_int16_t val; 613 int i; 614 615 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 616 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) { 617 return(0); 618 } 619 620 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 621 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 622 623 for (i = 0; i < SK_TIMEOUT; i++) { 624 DELAY(1); 625 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 626 if (val & YU_SMICR_READ_VALID) 627 break; 628 } 629 630 if (i == SK_TIMEOUT) { 631 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 632 return(0); 633 } 634 635 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 636 637 return(val); 638 } 639 640 static int 641 sk_marv_miibus_writereg(sc_if, phy, reg, val) 642 struct sk_if_softc *sc_if; 643 int phy, reg, val; 644 { 645 int i; 646 647 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 648 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 649 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 650 651 for (i = 0; i < SK_TIMEOUT; i++) { 652 DELAY(1); 653 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0) 654 break; 655 } 656 if (i == SK_TIMEOUT) 657 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 658 659 return(0); 660 } 661 662 static void 663 sk_marv_miibus_statchg(sc_if) 664 struct sk_if_softc *sc_if; 665 { 666 return; 667 } 668 669 #define HASH_BITS 6 670 671 static u_int32_t 672 sk_xmchash(addr) 673 const uint8_t *addr; 674 { 675 uint32_t crc; 676 677 /* Compute CRC for the address value. */ 678 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 679 680 return (~crc & ((1 << HASH_BITS) - 1)); 681 } 682 683 static void 684 sk_setfilt(sc_if, addr, slot) 685 struct sk_if_softc *sc_if; 686 u_int16_t *addr; 687 int slot; 688 { 689 int base; 690 691 base = XM_RXFILT_ENTRY(slot); 692 693 SK_XM_WRITE_2(sc_if, base, addr[0]); 694 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 695 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 696 697 return; 698 } 699 700 static void 701 sk_rxfilter(sc_if) 702 struct sk_if_softc *sc_if; 703 { 704 struct sk_softc *sc; 705 706 SK_IF_LOCK_ASSERT(sc_if); 707 708 sc = sc_if->sk_softc; 709 if (sc->sk_type == SK_GENESIS) 710 sk_rxfilter_genesis(sc_if); 711 else 712 sk_rxfilter_yukon(sc_if); 713 } 714 715 struct sk_add_maddr_genesis_ctx { 716 struct sk_if_softc *sc_if; 717 uint32_t hashes[2]; 718 uint32_t mode; 719 }; 720 721 static u_int 722 sk_add_maddr_genesis(void *arg, struct sockaddr_dl *sdl, u_int cnt) 723 { 724 struct sk_add_maddr_genesis_ctx *ctx = arg; 725 int h; 726 727 /* 728 * Program the first XM_RXFILT_MAX multicast groups 729 * into the perfect filter. 730 */ 731 if (cnt + 1 < XM_RXFILT_MAX) { 732 sk_setfilt(ctx->sc_if, (uint16_t *)LLADDR(sdl), cnt + 1); 733 ctx->mode |= XM_MODE_RX_USE_PERFECT; 734 return (1); 735 } 736 h = sk_xmchash((const uint8_t *)LLADDR(sdl)); 737 if (h < 32) 738 ctx->hashes[0] |= (1 << h); 739 else 740 ctx->hashes[1] |= (1 << (h - 32)); 741 ctx->mode |= XM_MODE_RX_USE_HASH; 742 743 return (1); 744 } 745 746 static void 747 sk_rxfilter_genesis(struct sk_if_softc *sc_if) 748 { 749 if_t ifp = sc_if->sk_ifp; 750 struct sk_add_maddr_genesis_ctx ctx = { sc_if, { 0, 0 } }; 751 int i; 752 u_int16_t dummy[] = { 0, 0, 0 }; 753 754 SK_IF_LOCK_ASSERT(sc_if); 755 756 ctx.mode = SK_XM_READ_4(sc_if, XM_MODE); 757 ctx.mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH | 758 XM_MODE_RX_USE_PERFECT); 759 /* First, zot all the existing perfect filters. */ 760 for (i = 1; i < XM_RXFILT_MAX; i++) 761 sk_setfilt(sc_if, dummy, i); 762 763 /* Now program new ones. */ 764 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 765 if (if_getflags(ifp) & IFF_ALLMULTI) 766 ctx.mode |= XM_MODE_RX_USE_HASH; 767 if (if_getflags(ifp) & IFF_PROMISC) 768 ctx.mode |= XM_MODE_RX_PROMISC; 769 ctx.hashes[0] = 0xFFFFFFFF; 770 ctx.hashes[1] = 0xFFFFFFFF; 771 } else 772 /* XXX want to maintain reverse semantics */ 773 if_foreach_llmaddr(ifp, sk_add_maddr_genesis, &ctx); 774 775 SK_XM_WRITE_4(sc_if, XM_MODE, ctx.mode); 776 SK_XM_WRITE_4(sc_if, XM_MAR0, ctx.hashes[0]); 777 SK_XM_WRITE_4(sc_if, XM_MAR2, ctx.hashes[1]); 778 } 779 780 static u_int 781 sk_hash_maddr_yukon(void *arg, struct sockaddr_dl *sdl, u_int cnt) 782 { 783 uint32_t crc, *hashes = arg; 784 785 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 786 /* Just want the 6 least significant bits. */ 787 crc &= 0x3f; 788 /* Set the corresponding bit in the hash table. */ 789 hashes[crc >> 5] |= 1 << (crc & 0x1f); 790 791 return (1); 792 } 793 794 static void 795 sk_rxfilter_yukon(struct sk_if_softc *sc_if) 796 { 797 if_t ifp; 798 uint32_t hashes[2] = { 0, 0 }, mode; 799 800 SK_IF_LOCK_ASSERT(sc_if); 801 802 ifp = sc_if->sk_ifp; 803 mode = SK_YU_READ_2(sc_if, YUKON_RCR); 804 if (if_getflags(ifp) & IFF_PROMISC) 805 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 806 else if (if_getflags(ifp) & IFF_ALLMULTI) { 807 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN; 808 hashes[0] = 0xFFFFFFFF; 809 hashes[1] = 0xFFFFFFFF; 810 } else { 811 mode |= YU_RCR_UFLEN; 812 if_foreach_llmaddr(ifp, sk_hash_maddr_yukon, hashes); 813 if (hashes[0] != 0 || hashes[1] != 0) 814 mode |= YU_RCR_MUFLEN; 815 } 816 817 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 818 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 819 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 820 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 821 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode); 822 } 823 824 static int 825 sk_init_rx_ring(sc_if) 826 struct sk_if_softc *sc_if; 827 { 828 struct sk_ring_data *rd; 829 bus_addr_t addr; 830 u_int32_t csum_start; 831 int i; 832 833 sc_if->sk_cdata.sk_rx_cons = 0; 834 835 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 836 ETHER_HDR_LEN; 837 rd = &sc_if->sk_rdata; 838 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 839 for (i = 0; i < SK_RX_RING_CNT; i++) { 840 if (sk_newbuf(sc_if, i) != 0) 841 return (ENOBUFS); 842 if (i == (SK_RX_RING_CNT - 1)) 843 addr = SK_RX_RING_ADDR(sc_if, 0); 844 else 845 addr = SK_RX_RING_ADDR(sc_if, i + 1); 846 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 847 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 848 } 849 850 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 851 sc_if->sk_cdata.sk_rx_ring_map, 852 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 853 854 return(0); 855 } 856 857 static int 858 sk_init_jumbo_rx_ring(sc_if) 859 struct sk_if_softc *sc_if; 860 { 861 struct sk_ring_data *rd; 862 bus_addr_t addr; 863 u_int32_t csum_start; 864 int i; 865 866 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 867 868 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 869 ETHER_HDR_LEN; 870 rd = &sc_if->sk_rdata; 871 bzero(rd->sk_jumbo_rx_ring, 872 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 873 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 874 if (sk_jumbo_newbuf(sc_if, i) != 0) 875 return (ENOBUFS); 876 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 877 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 878 else 879 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 880 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 881 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 882 } 883 884 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 885 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 886 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 887 888 return (0); 889 } 890 891 static void 892 sk_init_tx_ring(sc_if) 893 struct sk_if_softc *sc_if; 894 { 895 struct sk_ring_data *rd; 896 struct sk_txdesc *txd; 897 bus_addr_t addr; 898 int i; 899 900 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 901 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 902 903 sc_if->sk_cdata.sk_tx_prod = 0; 904 sc_if->sk_cdata.sk_tx_cons = 0; 905 sc_if->sk_cdata.sk_tx_cnt = 0; 906 907 rd = &sc_if->sk_rdata; 908 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 909 for (i = 0; i < SK_TX_RING_CNT; i++) { 910 if (i == (SK_TX_RING_CNT - 1)) 911 addr = SK_TX_RING_ADDR(sc_if, 0); 912 else 913 addr = SK_TX_RING_ADDR(sc_if, i + 1); 914 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 915 txd = &sc_if->sk_cdata.sk_txdesc[i]; 916 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 917 } 918 919 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 920 sc_if->sk_cdata.sk_tx_ring_map, 921 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 922 } 923 924 static __inline void 925 sk_discard_rxbuf(sc_if, idx) 926 struct sk_if_softc *sc_if; 927 int idx; 928 { 929 struct sk_rx_desc *r; 930 struct sk_rxdesc *rxd; 931 struct mbuf *m; 932 933 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 934 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 935 m = rxd->rx_m; 936 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 937 } 938 939 static __inline void 940 sk_discard_jumbo_rxbuf(sc_if, idx) 941 struct sk_if_softc *sc_if; 942 int idx; 943 { 944 struct sk_rx_desc *r; 945 struct sk_rxdesc *rxd; 946 struct mbuf *m; 947 948 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 949 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 950 m = rxd->rx_m; 951 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 952 } 953 954 static int 955 sk_newbuf(sc_if, idx) 956 struct sk_if_softc *sc_if; 957 int idx; 958 { 959 struct sk_rx_desc *r; 960 struct sk_rxdesc *rxd; 961 struct mbuf *m; 962 bus_dma_segment_t segs[1]; 963 bus_dmamap_t map; 964 int nsegs; 965 966 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 967 if (m == NULL) 968 return (ENOBUFS); 969 m->m_len = m->m_pkthdr.len = MCLBYTES; 970 m_adj(m, ETHER_ALIGN); 971 972 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 973 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 974 m_freem(m); 975 return (ENOBUFS); 976 } 977 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 978 979 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 980 if (rxd->rx_m != NULL) { 981 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 982 BUS_DMASYNC_POSTREAD); 983 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 984 } 985 map = rxd->rx_dmamap; 986 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 987 sc_if->sk_cdata.sk_rx_sparemap = map; 988 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 989 BUS_DMASYNC_PREREAD); 990 rxd->rx_m = m; 991 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 992 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 993 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 994 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 995 996 return (0); 997 } 998 999 static int 1000 sk_jumbo_newbuf(sc_if, idx) 1001 struct sk_if_softc *sc_if; 1002 int idx; 1003 { 1004 struct sk_rx_desc *r; 1005 struct sk_rxdesc *rxd; 1006 struct mbuf *m; 1007 bus_dma_segment_t segs[1]; 1008 bus_dmamap_t map; 1009 int nsegs; 1010 1011 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1012 if (m == NULL) 1013 return (ENOBUFS); 1014 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 1015 /* 1016 * Adjust alignment so packet payload begins on a 1017 * longword boundary. Mandatory for Alpha, useful on 1018 * x86 too. 1019 */ 1020 m_adj(m, ETHER_ALIGN); 1021 1022 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 1023 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1024 m_freem(m); 1025 return (ENOBUFS); 1026 } 1027 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1028 1029 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1030 if (rxd->rx_m != NULL) { 1031 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1032 BUS_DMASYNC_POSTREAD); 1033 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 1034 rxd->rx_dmamap); 1035 } 1036 map = rxd->rx_dmamap; 1037 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 1038 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 1039 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1040 BUS_DMASYNC_PREREAD); 1041 rxd->rx_m = m; 1042 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1043 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1044 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1045 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1046 1047 return (0); 1048 } 1049 1050 /* 1051 * Set media options. 1052 */ 1053 static int 1054 sk_ifmedia_upd(ifp) 1055 if_t ifp; 1056 { 1057 struct sk_if_softc *sc_if = if_getsoftc(ifp); 1058 struct mii_data *mii; 1059 1060 mii = device_get_softc(sc_if->sk_miibus); 1061 sk_init(sc_if); 1062 mii_mediachg(mii); 1063 1064 return(0); 1065 } 1066 1067 /* 1068 * Report current media status. 1069 */ 1070 static void 1071 sk_ifmedia_sts(ifp, ifmr) 1072 if_t ifp; 1073 struct ifmediareq *ifmr; 1074 { 1075 struct sk_if_softc *sc_if; 1076 struct mii_data *mii; 1077 1078 sc_if = if_getsoftc(ifp); 1079 mii = device_get_softc(sc_if->sk_miibus); 1080 1081 mii_pollstat(mii); 1082 ifmr->ifm_active = mii->mii_media_active; 1083 ifmr->ifm_status = mii->mii_media_status; 1084 1085 return; 1086 } 1087 1088 static int 1089 sk_ioctl(ifp, command, data) 1090 if_t ifp; 1091 u_long command; 1092 caddr_t data; 1093 { 1094 struct sk_if_softc *sc_if = if_getsoftc(ifp); 1095 struct ifreq *ifr = (struct ifreq *) data; 1096 int error, mask; 1097 struct mii_data *mii; 1098 1099 error = 0; 1100 switch(command) { 1101 case SIOCSIFMTU: 1102 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU) 1103 error = EINVAL; 1104 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1105 if (sc_if->sk_jumbo_disable != 0 && 1106 ifr->ifr_mtu > SK_MAX_FRAMELEN) 1107 error = EINVAL; 1108 else { 1109 SK_IF_LOCK(sc_if); 1110 if_setmtu(ifp, ifr->ifr_mtu); 1111 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1112 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1113 sk_init_locked(sc_if); 1114 } 1115 SK_IF_UNLOCK(sc_if); 1116 } 1117 } 1118 break; 1119 case SIOCSIFFLAGS: 1120 SK_IF_LOCK(sc_if); 1121 if (if_getflags(ifp) & IFF_UP) { 1122 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1123 if ((if_getflags(ifp) ^ sc_if->sk_if_flags) 1124 & (IFF_PROMISC | IFF_ALLMULTI)) 1125 sk_rxfilter(sc_if); 1126 } else 1127 sk_init_locked(sc_if); 1128 } else { 1129 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1130 sk_stop(sc_if); 1131 } 1132 sc_if->sk_if_flags = if_getflags(ifp); 1133 SK_IF_UNLOCK(sc_if); 1134 break; 1135 case SIOCADDMULTI: 1136 case SIOCDELMULTI: 1137 SK_IF_LOCK(sc_if); 1138 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1139 sk_rxfilter(sc_if); 1140 SK_IF_UNLOCK(sc_if); 1141 break; 1142 case SIOCGIFMEDIA: 1143 case SIOCSIFMEDIA: 1144 mii = device_get_softc(sc_if->sk_miibus); 1145 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1146 break; 1147 case SIOCSIFCAP: 1148 SK_IF_LOCK(sc_if); 1149 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1150 SK_IF_UNLOCK(sc_if); 1151 break; 1152 } 1153 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1154 if ((mask & IFCAP_TXCSUM) != 0 && 1155 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1156 if_togglecapenable(ifp, IFCAP_TXCSUM); 1157 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1158 if_sethwassistbits(ifp, SK_CSUM_FEATURES, 0); 1159 else 1160 if_sethwassistbits(ifp, 0, SK_CSUM_FEATURES); 1161 } 1162 if ((mask & IFCAP_RXCSUM) != 0 && 1163 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) 1164 if_togglecapenable(ifp, IFCAP_RXCSUM); 1165 SK_IF_UNLOCK(sc_if); 1166 break; 1167 default: 1168 error = ether_ioctl(ifp, command, data); 1169 break; 1170 } 1171 1172 return (error); 1173 } 1174 1175 /* 1176 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1177 * IDs against our list and return a device name if we find a match. 1178 */ 1179 static int 1180 skc_probe(dev) 1181 device_t dev; 1182 { 1183 const struct sk_type *t = sk_devs; 1184 1185 while(t->sk_name != NULL) { 1186 if ((pci_get_vendor(dev) == t->sk_vid) && 1187 (pci_get_device(dev) == t->sk_did)) { 1188 /* 1189 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1190 * Rev. 3 is supported by re(4). 1191 */ 1192 if ((t->sk_vid == VENDORID_LINKSYS) && 1193 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1194 (pci_get_subdevice(dev) != 1195 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1196 t++; 1197 continue; 1198 } 1199 device_set_desc(dev, t->sk_name); 1200 return (BUS_PROBE_DEFAULT); 1201 } 1202 t++; 1203 } 1204 1205 return(ENXIO); 1206 } 1207 1208 /* 1209 * Force the GEnesis into reset, then bring it out of reset. 1210 */ 1211 static void 1212 sk_reset(sc) 1213 struct sk_softc *sc; 1214 { 1215 1216 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1217 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1218 if (SK_YUKON_FAMILY(sc->sk_type)) 1219 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1220 1221 DELAY(1000); 1222 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1223 DELAY(2); 1224 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1225 if (SK_YUKON_FAMILY(sc->sk_type)) 1226 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1227 1228 if (sc->sk_type == SK_GENESIS) { 1229 /* Configure packet arbiter */ 1230 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1231 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1232 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1233 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1234 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1235 } 1236 1237 /* Enable RAM interface */ 1238 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1239 1240 /* 1241 * Configure interrupt moderation. The moderation timer 1242 * defers interrupts specified in the interrupt moderation 1243 * timer mask based on the timeout specified in the interrupt 1244 * moderation timer init register. Each bit in the timer 1245 * register represents one tick, so to specify a timeout in 1246 * microseconds, we have to multiply by the correct number of 1247 * ticks-per-microsecond. 1248 */ 1249 switch (sc->sk_type) { 1250 case SK_GENESIS: 1251 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1252 break; 1253 default: 1254 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1255 break; 1256 } 1257 if (bootverbose) 1258 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1259 sc->sk_int_mod); 1260 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1261 sc->sk_int_ticks)); 1262 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1263 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1264 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1265 1266 return; 1267 } 1268 1269 static int 1270 sk_probe(dev) 1271 device_t dev; 1272 { 1273 struct sk_softc *sc; 1274 1275 sc = device_get_softc(device_get_parent(dev)); 1276 1277 /* 1278 * Not much to do here. We always know there will be 1279 * at least one XMAC present, and if there are two, 1280 * skc_attach() will create a second device instance 1281 * for us. 1282 */ 1283 switch (sc->sk_type) { 1284 case SK_GENESIS: 1285 device_set_desc(dev, "XaQti Corp. XMAC II"); 1286 break; 1287 case SK_YUKON: 1288 case SK_YUKON_LITE: 1289 case SK_YUKON_LP: 1290 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1291 break; 1292 } 1293 1294 return (BUS_PROBE_DEFAULT); 1295 } 1296 1297 /* 1298 * Each XMAC chip is attached as a separate logical IP interface. 1299 * Single port cards will have only one logical interface of course. 1300 */ 1301 static int 1302 sk_attach(dev) 1303 device_t dev; 1304 { 1305 struct sk_softc *sc; 1306 struct sk_if_softc *sc_if; 1307 if_t ifp; 1308 u_int32_t r; 1309 int error, i, phy, port; 1310 u_char eaddr[6]; 1311 u_char inv_mac[] = {0, 0, 0, 0, 0, 0}; 1312 1313 if (dev == NULL) 1314 return(EINVAL); 1315 1316 error = 0; 1317 sc_if = device_get_softc(dev); 1318 sc = device_get_softc(device_get_parent(dev)); 1319 port = *(int *)device_get_ivars(dev); 1320 1321 sc_if->sk_if_dev = dev; 1322 sc_if->sk_port = port; 1323 sc_if->sk_softc = sc; 1324 sc->sk_if[port] = sc_if; 1325 if (port == SK_PORT_A) 1326 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1327 if (port == SK_PORT_B) 1328 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1329 1330 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1331 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0); 1332 1333 if (sk_dma_alloc(sc_if) != 0) { 1334 error = ENOMEM; 1335 goto fail; 1336 } 1337 sk_dma_jumbo_alloc(sc_if); 1338 1339 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1340 if (ifp == NULL) { 1341 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1342 error = ENOSPC; 1343 goto fail; 1344 } 1345 if_setsoftc(ifp, sc_if); 1346 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1347 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1348 /* 1349 * SK_GENESIS has a bug in checksum offload - From linux. 1350 */ 1351 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1352 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM); 1353 if_sethwassist(ifp, 0); 1354 } else { 1355 if_setcapabilities(ifp, 0); 1356 if_sethwassist(ifp, 0); 1357 } 1358 if_setcapenable(ifp, if_getcapabilities(ifp)); 1359 /* 1360 * Some revision of Yukon controller generates corrupted 1361 * frame when TX checksum offloading is enabled. The 1362 * frame has a valid checksum value so payload might be 1363 * modified during TX checksum calculation. Disable TX 1364 * checksum offloading but give users chance to enable it 1365 * when they know their controller works without problems 1366 * with TX checksum offloading. 1367 */ 1368 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1369 if_setioctlfn(ifp, sk_ioctl); 1370 if_setstartfn(ifp, sk_start); 1371 if_setinitfn(ifp, sk_init); 1372 if_setsendqlen(ifp, SK_TX_RING_CNT - 1); 1373 if_setsendqready(ifp); 1374 1375 /* 1376 * Get station address for this interface. Note that 1377 * dual port cards actually come with three station 1378 * addresses: one for each port, plus an extra. The 1379 * extra one is used by the SysKonnect driver software 1380 * as a 'virtual' station address for when both ports 1381 * are operating in failover mode. Currently we don't 1382 * use this extra address. 1383 */ 1384 SK_IF_LOCK(sc_if); 1385 for (i = 0; i < ETHER_ADDR_LEN; i++) 1386 eaddr[i] = 1387 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1388 1389 /* Verify whether the station address is invalid or not. */ 1390 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) { 1391 device_printf(sc_if->sk_if_dev, 1392 "Generating random ethernet address\n"); 1393 r = arc4random(); 1394 /* 1395 * Set OUI to convenient locally assigned address. 'b' 1396 * is 0x62, which has the locally assigned bit set, and 1397 * the broadcast/multicast bit clear. 1398 */ 1399 eaddr[0] = 'b'; 1400 eaddr[1] = 's'; 1401 eaddr[2] = 'd'; 1402 eaddr[3] = (r >> 16) & 0xff; 1403 eaddr[4] = (r >> 8) & 0xff; 1404 eaddr[5] = (r >> 0) & 0xff; 1405 } 1406 /* 1407 * Set up RAM buffer addresses. The NIC will have a certain 1408 * amount of SRAM on it, somewhere between 512K and 2MB. We 1409 * need to divide this up a) between the transmitter and 1410 * receiver and b) between the two XMACs, if this is a 1411 * dual port NIC. Our algotithm is to divide up the memory 1412 * evenly so that everyone gets a fair share. 1413 * 1414 * Just to be contrary, Yukon2 appears to have separate memory 1415 * for each MAC. 1416 */ 1417 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1418 u_int32_t chunk, val; 1419 1420 chunk = sc->sk_ramsize / 2; 1421 val = sc->sk_rboff / sizeof(u_int64_t); 1422 sc_if->sk_rx_ramstart = val; 1423 val += (chunk / sizeof(u_int64_t)); 1424 sc_if->sk_rx_ramend = val - 1; 1425 sc_if->sk_tx_ramstart = val; 1426 val += (chunk / sizeof(u_int64_t)); 1427 sc_if->sk_tx_ramend = val - 1; 1428 } else { 1429 u_int32_t chunk, val; 1430 1431 chunk = sc->sk_ramsize / 4; 1432 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1433 sizeof(u_int64_t); 1434 sc_if->sk_rx_ramstart = val; 1435 val += (chunk / sizeof(u_int64_t)); 1436 sc_if->sk_rx_ramend = val - 1; 1437 sc_if->sk_tx_ramstart = val; 1438 val += (chunk / sizeof(u_int64_t)); 1439 sc_if->sk_tx_ramend = val - 1; 1440 } 1441 1442 /* Read and save PHY type and set PHY address */ 1443 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1444 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1445 switch(sc_if->sk_phytype) { 1446 case SK_PHYTYPE_XMAC: 1447 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1448 break; 1449 case SK_PHYTYPE_BCOM: 1450 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1451 break; 1452 default: 1453 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1454 sc_if->sk_phytype); 1455 error = ENODEV; 1456 SK_IF_UNLOCK(sc_if); 1457 goto fail; 1458 } 1459 } else { 1460 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1461 sc->sk_pmd != 'S') { 1462 /* not initialized, punt */ 1463 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1464 sc->sk_coppertype = 1; 1465 } 1466 1467 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1468 1469 if (!(sc->sk_coppertype)) 1470 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1471 } 1472 1473 /* 1474 * Call MI attach routine. Can't hold locks when calling into ether_*. 1475 */ 1476 SK_IF_UNLOCK(sc_if); 1477 ether_ifattach(ifp, eaddr); 1478 SK_IF_LOCK(sc_if); 1479 1480 /* 1481 * The hardware should be ready for VLAN_MTU by default: 1482 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1483 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1484 * 1485 */ 1486 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1487 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0); 1488 /* 1489 * Tell the upper layer(s) we support long frames. 1490 * Must appear after the call to ether_ifattach() because 1491 * ether_ifattach() sets ifi_hdrlen to the default value. 1492 */ 1493 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1494 1495 /* 1496 * Do miibus setup. 1497 */ 1498 phy = MII_PHY_ANY; 1499 switch (sc->sk_type) { 1500 case SK_GENESIS: 1501 sk_init_xmac(sc_if); 1502 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 1503 phy = 0; 1504 break; 1505 case SK_YUKON: 1506 case SK_YUKON_LITE: 1507 case SK_YUKON_LP: 1508 sk_init_yukon(sc_if); 1509 phy = 0; 1510 break; 1511 } 1512 1513 SK_IF_UNLOCK(sc_if); 1514 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd, 1515 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1516 if (error != 0) { 1517 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n"); 1518 ether_ifdetach(ifp); 1519 goto fail; 1520 } 1521 1522 fail: 1523 if (error) { 1524 /* Access should be ok even though lock has been dropped */ 1525 sc->sk_if[port] = NULL; 1526 sk_detach(dev); 1527 } 1528 1529 return(error); 1530 } 1531 1532 /* 1533 * Attach the interface. Allocate softc structures, do ifmedia 1534 * setup and ethernet/BPF attach. 1535 */ 1536 static int 1537 skc_attach(dev) 1538 device_t dev; 1539 { 1540 struct sk_softc *sc; 1541 int error = 0, *port; 1542 uint8_t skrs; 1543 const char *pname = NULL; 1544 char *revstr; 1545 1546 sc = device_get_softc(dev); 1547 sc->sk_dev = dev; 1548 1549 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1550 MTX_DEF); 1551 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1552 /* 1553 * Map control/status registers. 1554 */ 1555 pci_enable_busmaster(dev); 1556 1557 /* Allocate resources */ 1558 #ifdef SK_USEIOSPACE 1559 sc->sk_res_spec = sk_res_spec_io; 1560 #else 1561 sc->sk_res_spec = sk_res_spec_mem; 1562 #endif 1563 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1564 if (error) { 1565 if (sc->sk_res_spec == sk_res_spec_mem) 1566 sc->sk_res_spec = sk_res_spec_io; 1567 else 1568 sc->sk_res_spec = sk_res_spec_mem; 1569 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1570 if (error) { 1571 device_printf(dev, "couldn't allocate %s resources\n", 1572 sc->sk_res_spec == sk_res_spec_mem ? "memory" : 1573 "I/O"); 1574 goto fail; 1575 } 1576 } 1577 1578 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1579 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1580 1581 /* Bail out if chip is not recognized. */ 1582 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1583 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1584 sc->sk_type, sc->sk_rev); 1585 error = ENXIO; 1586 goto fail; 1587 } 1588 1589 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1590 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1591 OID_AUTO, "int_mod", 1592 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1593 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1594 "SK interrupt moderation"); 1595 1596 /* Pull in device tunables. */ 1597 sc->sk_int_mod = SK_IM_DEFAULT; 1598 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1599 "int_mod", &sc->sk_int_mod); 1600 if (error == 0) { 1601 if (sc->sk_int_mod < SK_IM_MIN || 1602 sc->sk_int_mod > SK_IM_MAX) { 1603 device_printf(dev, "int_mod value out of range; " 1604 "using default: %d\n", SK_IM_DEFAULT); 1605 sc->sk_int_mod = SK_IM_DEFAULT; 1606 } 1607 } 1608 1609 /* Reset the adapter. */ 1610 sk_reset(sc); 1611 1612 skrs = sk_win_read_1(sc, SK_EPROM0); 1613 if (sc->sk_type == SK_GENESIS) { 1614 /* Read and save RAM size and RAMbuffer offset */ 1615 switch(skrs) { 1616 case SK_RAMSIZE_512K_64: 1617 sc->sk_ramsize = 0x80000; 1618 sc->sk_rboff = SK_RBOFF_0; 1619 break; 1620 case SK_RAMSIZE_1024K_64: 1621 sc->sk_ramsize = 0x100000; 1622 sc->sk_rboff = SK_RBOFF_80000; 1623 break; 1624 case SK_RAMSIZE_1024K_128: 1625 sc->sk_ramsize = 0x100000; 1626 sc->sk_rboff = SK_RBOFF_0; 1627 break; 1628 case SK_RAMSIZE_2048K_128: 1629 sc->sk_ramsize = 0x200000; 1630 sc->sk_rboff = SK_RBOFF_0; 1631 break; 1632 default: 1633 device_printf(dev, "unknown ram size: %d\n", skrs); 1634 error = ENXIO; 1635 goto fail; 1636 } 1637 } else { /* SK_YUKON_FAMILY */ 1638 if (skrs == 0x00) 1639 sc->sk_ramsize = 0x20000; 1640 else 1641 sc->sk_ramsize = skrs * (1<<12); 1642 sc->sk_rboff = SK_RBOFF_0; 1643 } 1644 1645 /* Read and save physical media type */ 1646 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1647 1648 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1649 sc->sk_coppertype = 1; 1650 else 1651 sc->sk_coppertype = 0; 1652 1653 /* Determine whether to name it with VPD PN or just make it up. 1654 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1655 switch (pci_get_device(dev)) { 1656 case DEVICEID_SK_V1: 1657 case DEVICEID_BELKIN_5005: 1658 case DEVICEID_3COM_3C940: 1659 case DEVICEID_LINKSYS_EG1032: 1660 case DEVICEID_DLINK_DGE530T_A1: 1661 case DEVICEID_DLINK_DGE530T_B1: 1662 /* Stay with VPD PN. */ 1663 (void) pci_get_vpd_ident(dev, &pname); 1664 break; 1665 case DEVICEID_SK_V2: 1666 /* YUKON VPD PN might bear no resemblance to reality. */ 1667 switch (sc->sk_type) { 1668 case SK_GENESIS: 1669 /* Stay with VPD PN. */ 1670 (void) pci_get_vpd_ident(dev, &pname); 1671 break; 1672 case SK_YUKON: 1673 pname = "Marvell Yukon Gigabit Ethernet"; 1674 break; 1675 case SK_YUKON_LITE: 1676 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1677 break; 1678 case SK_YUKON_LP: 1679 pname = "Marvell Yukon LP Gigabit Ethernet"; 1680 break; 1681 default: 1682 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1683 break; 1684 } 1685 1686 /* Yukon Lite Rev. A0 needs special test. */ 1687 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1688 u_int32_t far; 1689 u_int8_t testbyte; 1690 1691 /* Save flash address register before testing. */ 1692 far = sk_win_read_4(sc, SK_EP_ADDR); 1693 1694 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1695 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1696 1697 if (testbyte != 0x00) { 1698 /* Yukon Lite Rev. A0 detected. */ 1699 sc->sk_type = SK_YUKON_LITE; 1700 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1701 /* Restore flash address register. */ 1702 sk_win_write_4(sc, SK_EP_ADDR, far); 1703 } 1704 } 1705 break; 1706 default: 1707 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1708 "chipver=%02x, rev=%x\n", 1709 pci_get_vendor(dev), pci_get_device(dev), 1710 sc->sk_type, sc->sk_rev); 1711 error = ENXIO; 1712 goto fail; 1713 } 1714 1715 if (sc->sk_type == SK_YUKON_LITE) { 1716 switch (sc->sk_rev) { 1717 case SK_YUKON_LITE_REV_A0: 1718 revstr = "A0"; 1719 break; 1720 case SK_YUKON_LITE_REV_A1: 1721 revstr = "A1"; 1722 break; 1723 case SK_YUKON_LITE_REV_A3: 1724 revstr = "A3"; 1725 break; 1726 default: 1727 revstr = ""; 1728 break; 1729 } 1730 } else { 1731 revstr = ""; 1732 } 1733 1734 /* Announce the product name and more VPD data if there. */ 1735 if (pname != NULL) 1736 device_printf(dev, "%s rev. %s(0x%x)\n", 1737 pname, revstr, sc->sk_rev); 1738 1739 if (bootverbose) { 1740 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1741 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1742 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1743 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1744 } 1745 1746 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1747 if (sc->sk_devs[SK_PORT_A] == NULL) { 1748 device_printf(dev, "failed to add child for PORT_A\n"); 1749 error = ENXIO; 1750 goto fail; 1751 } 1752 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1753 if (port == NULL) { 1754 device_printf(dev, "failed to allocate memory for " 1755 "ivars of PORT_A\n"); 1756 error = ENXIO; 1757 goto fail; 1758 } 1759 *port = SK_PORT_A; 1760 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1761 1762 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1763 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1764 if (sc->sk_devs[SK_PORT_B] == NULL) { 1765 device_printf(dev, "failed to add child for PORT_B\n"); 1766 error = ENXIO; 1767 goto fail; 1768 } 1769 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1770 if (port == NULL) { 1771 device_printf(dev, "failed to allocate memory for " 1772 "ivars of PORT_B\n"); 1773 error = ENXIO; 1774 goto fail; 1775 } 1776 *port = SK_PORT_B; 1777 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1778 } 1779 1780 /* Turn on the 'driver is loaded' LED. */ 1781 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1782 1783 error = bus_generic_attach(dev); 1784 if (error) { 1785 device_printf(dev, "failed to attach port(s)\n"); 1786 goto fail; 1787 } 1788 1789 /* Hook interrupt last to avoid having to lock softc */ 1790 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE, 1791 NULL, sk_intr, sc, &sc->sk_intrhand); 1792 1793 if (error) { 1794 device_printf(dev, "couldn't set up irq\n"); 1795 goto fail; 1796 } 1797 1798 fail: 1799 if (error) 1800 skc_detach(dev); 1801 1802 return(error); 1803 } 1804 1805 /* 1806 * Shutdown hardware and free up resources. This can be called any 1807 * time after the mutex has been initialized. It is called in both 1808 * the error case in attach and the normal detach case so it needs 1809 * to be careful about only freeing resources that have actually been 1810 * allocated. 1811 */ 1812 static int 1813 sk_detach(dev) 1814 device_t dev; 1815 { 1816 struct sk_if_softc *sc_if; 1817 if_t ifp; 1818 1819 sc_if = device_get_softc(dev); 1820 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1821 ("sk mutex not initialized in sk_detach")); 1822 SK_IF_LOCK(sc_if); 1823 1824 ifp = sc_if->sk_ifp; 1825 /* These should only be active if attach_xmac succeeded */ 1826 if (device_is_attached(dev)) { 1827 sk_stop(sc_if); 1828 /* Can't hold locks while calling detach */ 1829 SK_IF_UNLOCK(sc_if); 1830 callout_drain(&sc_if->sk_tick_ch); 1831 callout_drain(&sc_if->sk_watchdog_ch); 1832 ether_ifdetach(ifp); 1833 SK_IF_LOCK(sc_if); 1834 } 1835 /* 1836 * We're generally called from skc_detach() which is using 1837 * device_delete_child() to get to here. It's already trashed 1838 * miibus for us, so don't do it here or we'll panic. 1839 */ 1840 /* 1841 if (sc_if->sk_miibus != NULL) 1842 device_delete_child(dev, sc_if->sk_miibus); 1843 */ 1844 bus_generic_detach(dev); 1845 sk_dma_jumbo_free(sc_if); 1846 sk_dma_free(sc_if); 1847 SK_IF_UNLOCK(sc_if); 1848 if (ifp) 1849 if_free(ifp); 1850 1851 return(0); 1852 } 1853 1854 static int 1855 skc_detach(dev) 1856 device_t dev; 1857 { 1858 struct sk_softc *sc; 1859 1860 sc = device_get_softc(dev); 1861 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1862 1863 if (device_is_alive(dev)) { 1864 if (sc->sk_devs[SK_PORT_A] != NULL) { 1865 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 1866 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1867 } 1868 if (sc->sk_devs[SK_PORT_B] != NULL) { 1869 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 1870 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1871 } 1872 bus_generic_detach(dev); 1873 } 1874 1875 if (sc->sk_intrhand) 1876 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand); 1877 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res); 1878 1879 mtx_destroy(&sc->sk_mii_mtx); 1880 mtx_destroy(&sc->sk_mtx); 1881 1882 return(0); 1883 } 1884 1885 static bus_dma_tag_t 1886 skc_get_dma_tag(device_t bus, device_t child __unused) 1887 { 1888 1889 return (bus_get_dma_tag(bus)); 1890 } 1891 1892 struct sk_dmamap_arg { 1893 bus_addr_t sk_busaddr; 1894 }; 1895 1896 static void 1897 sk_dmamap_cb(arg, segs, nseg, error) 1898 void *arg; 1899 bus_dma_segment_t *segs; 1900 int nseg; 1901 int error; 1902 { 1903 struct sk_dmamap_arg *ctx; 1904 1905 if (error != 0) 1906 return; 1907 1908 ctx = arg; 1909 ctx->sk_busaddr = segs[0].ds_addr; 1910 } 1911 1912 /* 1913 * Allocate jumbo buffer storage. The SysKonnect adapters support 1914 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1915 * use them in their drivers. In order for us to use them, we need 1916 * large 9K receive buffers, however standard mbuf clusters are only 1917 * 2048 bytes in size. Consequently, we need to allocate and manage 1918 * our own jumbo buffer pool. Fortunately, this does not require an 1919 * excessive amount of additional code. 1920 */ 1921 static int 1922 sk_dma_alloc(sc_if) 1923 struct sk_if_softc *sc_if; 1924 { 1925 struct sk_dmamap_arg ctx; 1926 struct sk_txdesc *txd; 1927 struct sk_rxdesc *rxd; 1928 int error, i; 1929 1930 /* create parent tag */ 1931 /* 1932 * XXX 1933 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 1934 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 1935 * However bz@ reported that it does not work on amd64 with > 4GB 1936 * RAM. Until we have more clues of the breakage, disable DAC mode 1937 * by limiting DMA address to be in 32bit address space. 1938 */ 1939 error = bus_dma_tag_create( 1940 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */ 1941 1, 0, /* algnmnt, boundary */ 1942 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1943 BUS_SPACE_MAXADDR, /* highaddr */ 1944 NULL, NULL, /* filter, filterarg */ 1945 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1946 0, /* nsegments */ 1947 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1948 0, /* flags */ 1949 NULL, NULL, /* lockfunc, lockarg */ 1950 &sc_if->sk_cdata.sk_parent_tag); 1951 if (error != 0) { 1952 device_printf(sc_if->sk_if_dev, 1953 "failed to create parent DMA tag\n"); 1954 goto fail; 1955 } 1956 1957 /* create tag for Tx ring */ 1958 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1959 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1960 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1961 BUS_SPACE_MAXADDR, /* highaddr */ 1962 NULL, NULL, /* filter, filterarg */ 1963 SK_TX_RING_SZ, /* maxsize */ 1964 1, /* nsegments */ 1965 SK_TX_RING_SZ, /* maxsegsize */ 1966 0, /* flags */ 1967 NULL, NULL, /* lockfunc, lockarg */ 1968 &sc_if->sk_cdata.sk_tx_ring_tag); 1969 if (error != 0) { 1970 device_printf(sc_if->sk_if_dev, 1971 "failed to allocate Tx ring DMA tag\n"); 1972 goto fail; 1973 } 1974 1975 /* create tag for Rx ring */ 1976 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1977 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1978 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1979 BUS_SPACE_MAXADDR, /* highaddr */ 1980 NULL, NULL, /* filter, filterarg */ 1981 SK_RX_RING_SZ, /* maxsize */ 1982 1, /* nsegments */ 1983 SK_RX_RING_SZ, /* maxsegsize */ 1984 0, /* flags */ 1985 NULL, NULL, /* lockfunc, lockarg */ 1986 &sc_if->sk_cdata.sk_rx_ring_tag); 1987 if (error != 0) { 1988 device_printf(sc_if->sk_if_dev, 1989 "failed to allocate Rx ring DMA tag\n"); 1990 goto fail; 1991 } 1992 1993 /* create tag for Tx buffers */ 1994 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1995 1, 0, /* algnmnt, boundary */ 1996 BUS_SPACE_MAXADDR, /* lowaddr */ 1997 BUS_SPACE_MAXADDR, /* highaddr */ 1998 NULL, NULL, /* filter, filterarg */ 1999 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 2000 SK_MAXTXSEGS, /* nsegments */ 2001 MCLBYTES, /* maxsegsize */ 2002 0, /* flags */ 2003 NULL, NULL, /* lockfunc, lockarg */ 2004 &sc_if->sk_cdata.sk_tx_tag); 2005 if (error != 0) { 2006 device_printf(sc_if->sk_if_dev, 2007 "failed to allocate Tx DMA tag\n"); 2008 goto fail; 2009 } 2010 2011 /* create tag for Rx buffers */ 2012 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2013 1, 0, /* algnmnt, boundary */ 2014 BUS_SPACE_MAXADDR, /* lowaddr */ 2015 BUS_SPACE_MAXADDR, /* highaddr */ 2016 NULL, NULL, /* filter, filterarg */ 2017 MCLBYTES, /* maxsize */ 2018 1, /* nsegments */ 2019 MCLBYTES, /* maxsegsize */ 2020 0, /* flags */ 2021 NULL, NULL, /* lockfunc, lockarg */ 2022 &sc_if->sk_cdata.sk_rx_tag); 2023 if (error != 0) { 2024 device_printf(sc_if->sk_if_dev, 2025 "failed to allocate Rx DMA tag\n"); 2026 goto fail; 2027 } 2028 2029 /* allocate DMA'able memory and load the DMA map for Tx ring */ 2030 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 2031 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | 2032 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map); 2033 if (error != 0) { 2034 device_printf(sc_if->sk_if_dev, 2035 "failed to allocate DMA'able memory for Tx ring\n"); 2036 goto fail; 2037 } 2038 2039 ctx.sk_busaddr = 0; 2040 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 2041 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 2042 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2043 if (error != 0) { 2044 device_printf(sc_if->sk_if_dev, 2045 "failed to load DMA'able memory for Tx ring\n"); 2046 goto fail; 2047 } 2048 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 2049 2050 /* allocate DMA'able memory and load the DMA map for Rx ring */ 2051 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 2052 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | 2053 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map); 2054 if (error != 0) { 2055 device_printf(sc_if->sk_if_dev, 2056 "failed to allocate DMA'able memory for Rx ring\n"); 2057 goto fail; 2058 } 2059 2060 ctx.sk_busaddr = 0; 2061 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 2062 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 2063 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2064 if (error != 0) { 2065 device_printf(sc_if->sk_if_dev, 2066 "failed to load DMA'able memory for Rx ring\n"); 2067 goto fail; 2068 } 2069 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2070 2071 /* create DMA maps for Tx buffers */ 2072 for (i = 0; i < SK_TX_RING_CNT; i++) { 2073 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2074 txd->tx_m = NULL; 2075 txd->tx_dmamap = NULL; 2076 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2077 &txd->tx_dmamap); 2078 if (error != 0) { 2079 device_printf(sc_if->sk_if_dev, 2080 "failed to create Tx dmamap\n"); 2081 goto fail; 2082 } 2083 } 2084 2085 /* create DMA maps for Rx buffers */ 2086 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2087 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2088 device_printf(sc_if->sk_if_dev, 2089 "failed to create spare Rx dmamap\n"); 2090 goto fail; 2091 } 2092 for (i = 0; i < SK_RX_RING_CNT; i++) { 2093 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2094 rxd->rx_m = NULL; 2095 rxd->rx_dmamap = NULL; 2096 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2097 &rxd->rx_dmamap); 2098 if (error != 0) { 2099 device_printf(sc_if->sk_if_dev, 2100 "failed to create Rx dmamap\n"); 2101 goto fail; 2102 } 2103 } 2104 2105 fail: 2106 return (error); 2107 } 2108 2109 static int 2110 sk_dma_jumbo_alloc(sc_if) 2111 struct sk_if_softc *sc_if; 2112 { 2113 struct sk_dmamap_arg ctx; 2114 struct sk_rxdesc *jrxd; 2115 int error, i; 2116 2117 if (jumbo_disable != 0) { 2118 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n"); 2119 sc_if->sk_jumbo_disable = 1; 2120 return (0); 2121 } 2122 /* create tag for jumbo Rx ring */ 2123 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2124 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2125 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2126 BUS_SPACE_MAXADDR, /* highaddr */ 2127 NULL, NULL, /* filter, filterarg */ 2128 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2129 1, /* nsegments */ 2130 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2131 0, /* flags */ 2132 NULL, NULL, /* lockfunc, lockarg */ 2133 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2134 if (error != 0) { 2135 device_printf(sc_if->sk_if_dev, 2136 "failed to allocate jumbo Rx ring DMA tag\n"); 2137 goto jumbo_fail; 2138 } 2139 2140 /* create tag for jumbo Rx buffers */ 2141 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2142 1, 0, /* algnmnt, boundary */ 2143 BUS_SPACE_MAXADDR, /* lowaddr */ 2144 BUS_SPACE_MAXADDR, /* highaddr */ 2145 NULL, NULL, /* filter, filterarg */ 2146 MJUM9BYTES, /* maxsize */ 2147 1, /* nsegments */ 2148 MJUM9BYTES, /* maxsegsize */ 2149 0, /* flags */ 2150 NULL, NULL, /* lockfunc, lockarg */ 2151 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2152 if (error != 0) { 2153 device_printf(sc_if->sk_if_dev, 2154 "failed to allocate jumbo Rx DMA tag\n"); 2155 goto jumbo_fail; 2156 } 2157 2158 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2159 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2160 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT | 2161 BUS_DMA_COHERENT | BUS_DMA_ZERO, 2162 &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2163 if (error != 0) { 2164 device_printf(sc_if->sk_if_dev, 2165 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2166 goto jumbo_fail; 2167 } 2168 2169 ctx.sk_busaddr = 0; 2170 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2171 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2172 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2173 &ctx, BUS_DMA_NOWAIT); 2174 if (error != 0) { 2175 device_printf(sc_if->sk_if_dev, 2176 "failed to load DMA'able memory for jumbo Rx ring\n"); 2177 goto jumbo_fail; 2178 } 2179 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2180 2181 /* create DMA maps for jumbo Rx buffers */ 2182 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2183 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2184 device_printf(sc_if->sk_if_dev, 2185 "failed to create spare jumbo Rx dmamap\n"); 2186 goto jumbo_fail; 2187 } 2188 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2189 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2190 jrxd->rx_m = NULL; 2191 jrxd->rx_dmamap = NULL; 2192 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2193 &jrxd->rx_dmamap); 2194 if (error != 0) { 2195 device_printf(sc_if->sk_if_dev, 2196 "failed to create jumbo Rx dmamap\n"); 2197 goto jumbo_fail; 2198 } 2199 } 2200 2201 return (0); 2202 2203 jumbo_fail: 2204 sk_dma_jumbo_free(sc_if); 2205 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to " 2206 "resource shortage\n"); 2207 sc_if->sk_jumbo_disable = 1; 2208 return (0); 2209 } 2210 2211 static void 2212 sk_dma_free(sc_if) 2213 struct sk_if_softc *sc_if; 2214 { 2215 struct sk_txdesc *txd; 2216 struct sk_rxdesc *rxd; 2217 int i; 2218 2219 /* Tx ring */ 2220 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2221 if (sc_if->sk_rdata.sk_tx_ring_paddr) 2222 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2223 sc_if->sk_cdata.sk_tx_ring_map); 2224 if (sc_if->sk_rdata.sk_tx_ring) 2225 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2226 sc_if->sk_rdata.sk_tx_ring, 2227 sc_if->sk_cdata.sk_tx_ring_map); 2228 sc_if->sk_rdata.sk_tx_ring = NULL; 2229 sc_if->sk_rdata.sk_tx_ring_paddr = 0; 2230 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2231 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2232 } 2233 /* Rx ring */ 2234 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2235 if (sc_if->sk_rdata.sk_rx_ring_paddr) 2236 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2237 sc_if->sk_cdata.sk_rx_ring_map); 2238 if (sc_if->sk_rdata.sk_rx_ring) 2239 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2240 sc_if->sk_rdata.sk_rx_ring, 2241 sc_if->sk_cdata.sk_rx_ring_map); 2242 sc_if->sk_rdata.sk_rx_ring = NULL; 2243 sc_if->sk_rdata.sk_rx_ring_paddr = 0; 2244 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2245 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2246 } 2247 /* Tx buffers */ 2248 if (sc_if->sk_cdata.sk_tx_tag) { 2249 for (i = 0; i < SK_TX_RING_CNT; i++) { 2250 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2251 if (txd->tx_dmamap) { 2252 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2253 txd->tx_dmamap); 2254 txd->tx_dmamap = NULL; 2255 } 2256 } 2257 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2258 sc_if->sk_cdata.sk_tx_tag = NULL; 2259 } 2260 /* Rx buffers */ 2261 if (sc_if->sk_cdata.sk_rx_tag) { 2262 for (i = 0; i < SK_RX_RING_CNT; i++) { 2263 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2264 if (rxd->rx_dmamap) { 2265 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2266 rxd->rx_dmamap); 2267 rxd->rx_dmamap = NULL; 2268 } 2269 } 2270 if (sc_if->sk_cdata.sk_rx_sparemap) { 2271 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2272 sc_if->sk_cdata.sk_rx_sparemap); 2273 sc_if->sk_cdata.sk_rx_sparemap = NULL; 2274 } 2275 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2276 sc_if->sk_cdata.sk_rx_tag = NULL; 2277 } 2278 2279 if (sc_if->sk_cdata.sk_parent_tag) { 2280 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2281 sc_if->sk_cdata.sk_parent_tag = NULL; 2282 } 2283 } 2284 2285 static void 2286 sk_dma_jumbo_free(sc_if) 2287 struct sk_if_softc *sc_if; 2288 { 2289 struct sk_rxdesc *jrxd; 2290 int i; 2291 2292 /* jumbo Rx ring */ 2293 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2294 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr) 2295 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2296 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2297 if (sc_if->sk_rdata.sk_jumbo_rx_ring) 2298 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2299 sc_if->sk_rdata.sk_jumbo_rx_ring, 2300 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2301 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2302 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0; 2303 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2304 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2305 } 2306 2307 /* jumbo Rx buffers */ 2308 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2309 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2310 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2311 if (jrxd->rx_dmamap) { 2312 bus_dmamap_destroy( 2313 sc_if->sk_cdata.sk_jumbo_rx_tag, 2314 jrxd->rx_dmamap); 2315 jrxd->rx_dmamap = NULL; 2316 } 2317 } 2318 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2319 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2320 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2321 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL; 2322 } 2323 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2324 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2325 } 2326 } 2327 2328 static void 2329 sk_txcksum(ifp, m, f) 2330 if_t ifp; 2331 struct mbuf *m; 2332 struct sk_tx_desc *f; 2333 { 2334 struct ip *ip; 2335 u_int16_t offset; 2336 u_int8_t *p; 2337 2338 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2339 for(; m && m->m_len == 0; m = m->m_next) 2340 ; 2341 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2342 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2343 /* checksum may be corrupted */ 2344 goto sendit; 2345 } 2346 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2347 if (m->m_len != ETHER_HDR_LEN) { 2348 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2349 __func__); 2350 /* checksum may be corrupted */ 2351 goto sendit; 2352 } 2353 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2354 ; 2355 if (m == NULL) { 2356 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2357 /* checksum may be corrupted */ 2358 goto sendit; 2359 } 2360 ip = mtod(m, struct ip *); 2361 } else { 2362 p = mtod(m, u_int8_t *); 2363 p += ETHER_HDR_LEN; 2364 ip = (struct ip *)p; 2365 } 2366 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2367 2368 sendit: 2369 f->sk_csum_startval = 0; 2370 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2371 (offset << 16)); 2372 } 2373 2374 static int 2375 sk_encap(sc_if, m_head) 2376 struct sk_if_softc *sc_if; 2377 struct mbuf **m_head; 2378 { 2379 struct sk_txdesc *txd; 2380 struct sk_tx_desc *f = NULL; 2381 struct mbuf *m; 2382 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2383 u_int32_t cflags, frag, si, sk_ctl; 2384 int error, i, nseg; 2385 2386 SK_IF_LOCK_ASSERT(sc_if); 2387 2388 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2389 return (ENOBUFS); 2390 2391 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2392 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2393 if (error == EFBIG) { 2394 m = m_defrag(*m_head, M_NOWAIT); 2395 if (m == NULL) { 2396 m_freem(*m_head); 2397 *m_head = NULL; 2398 return (ENOMEM); 2399 } 2400 *m_head = m; 2401 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2402 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2403 if (error != 0) { 2404 m_freem(*m_head); 2405 *m_head = NULL; 2406 return (error); 2407 } 2408 } else if (error != 0) 2409 return (error); 2410 if (nseg == 0) { 2411 m_freem(*m_head); 2412 *m_head = NULL; 2413 return (EIO); 2414 } 2415 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2416 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2417 return (ENOBUFS); 2418 } 2419 2420 m = *m_head; 2421 if ((m->m_pkthdr.csum_flags & if_gethwassist(sc_if->sk_ifp)) != 0) 2422 cflags = SK_OPCODE_CSUM; 2423 else 2424 cflags = SK_OPCODE_DEFAULT; 2425 si = frag = sc_if->sk_cdata.sk_tx_prod; 2426 for (i = 0; i < nseg; i++) { 2427 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2428 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2429 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2430 sk_ctl = txsegs[i].ds_len | cflags; 2431 if (i == 0) { 2432 if (cflags == SK_OPCODE_CSUM) 2433 sk_txcksum(sc_if->sk_ifp, m, f); 2434 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2435 } else 2436 sk_ctl |= SK_TXCTL_OWN; 2437 f->sk_ctl = htole32(sk_ctl); 2438 sc_if->sk_cdata.sk_tx_cnt++; 2439 SK_INC(frag, SK_TX_RING_CNT); 2440 } 2441 sc_if->sk_cdata.sk_tx_prod = frag; 2442 2443 /* set EOF on the last descriptor */ 2444 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2445 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2446 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2447 2448 /* turn the first descriptor ownership to NIC */ 2449 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2450 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2451 2452 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2453 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2454 txd->tx_m = m; 2455 2456 /* sync descriptors */ 2457 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2458 BUS_DMASYNC_PREWRITE); 2459 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2460 sc_if->sk_cdata.sk_tx_ring_map, 2461 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2462 2463 return (0); 2464 } 2465 2466 static void 2467 sk_start(ifp) 2468 if_t ifp; 2469 { 2470 struct sk_if_softc *sc_if; 2471 2472 sc_if = if_getsoftc(ifp); 2473 2474 SK_IF_LOCK(sc_if); 2475 sk_start_locked(ifp); 2476 SK_IF_UNLOCK(sc_if); 2477 2478 return; 2479 } 2480 2481 static void 2482 sk_start_locked(ifp) 2483 if_t ifp; 2484 { 2485 struct sk_softc *sc; 2486 struct sk_if_softc *sc_if; 2487 struct mbuf *m_head; 2488 int enq; 2489 2490 sc_if = if_getsoftc(ifp); 2491 sc = sc_if->sk_softc; 2492 2493 SK_IF_LOCK_ASSERT(sc_if); 2494 2495 for (enq = 0; !if_sendq_empty(ifp) && 2496 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2497 m_head = if_dequeue(ifp); 2498 if (m_head == NULL) 2499 break; 2500 2501 /* 2502 * Pack the data into the transmit ring. If we 2503 * don't have room, set the OACTIVE flag and wait 2504 * for the NIC to drain the ring. 2505 */ 2506 if (sk_encap(sc_if, &m_head)) { 2507 if (m_head == NULL) 2508 break; 2509 if_sendq_prepend(ifp, m_head); 2510 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2511 break; 2512 } 2513 2514 enq++; 2515 /* 2516 * If there's a BPF listener, bounce a copy of this frame 2517 * to him. 2518 */ 2519 BPF_MTAP(ifp, m_head); 2520 } 2521 2522 if (enq > 0) { 2523 /* Transmit */ 2524 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2525 2526 /* Set a timeout in case the chip goes out to lunch. */ 2527 sc_if->sk_watchdog_timer = 5; 2528 } 2529 } 2530 2531 static void 2532 sk_watchdog(arg) 2533 void *arg; 2534 { 2535 struct sk_if_softc *sc_if; 2536 if_t ifp; 2537 2538 ifp = arg; 2539 sc_if = if_getsoftc(ifp); 2540 2541 SK_IF_LOCK_ASSERT(sc_if); 2542 2543 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer) 2544 goto done; 2545 2546 /* 2547 * Reclaim first as there is a possibility of losing Tx completion 2548 * interrupts. 2549 */ 2550 sk_txeof(sc_if); 2551 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2552 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2553 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2554 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2555 sk_init_locked(sc_if); 2556 } 2557 2558 done: 2559 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 2560 2561 return; 2562 } 2563 2564 static int 2565 skc_shutdown(dev) 2566 device_t dev; 2567 { 2568 struct sk_softc *sc; 2569 2570 sc = device_get_softc(dev); 2571 SK_LOCK(sc); 2572 2573 /* Turn off the 'driver is loaded' LED. */ 2574 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2575 2576 /* 2577 * Reset the GEnesis controller. Doing this should also 2578 * assert the resets on the attached XMAC(s). 2579 */ 2580 sk_reset(sc); 2581 SK_UNLOCK(sc); 2582 2583 return (0); 2584 } 2585 2586 static int 2587 skc_suspend(dev) 2588 device_t dev; 2589 { 2590 struct sk_softc *sc; 2591 struct sk_if_softc *sc_if0, *sc_if1; 2592 if_t ifp0 = NULL, ifp1 = NULL; 2593 2594 sc = device_get_softc(dev); 2595 2596 SK_LOCK(sc); 2597 2598 sc_if0 = sc->sk_if[SK_PORT_A]; 2599 sc_if1 = sc->sk_if[SK_PORT_B]; 2600 if (sc_if0 != NULL) 2601 ifp0 = sc_if0->sk_ifp; 2602 if (sc_if1 != NULL) 2603 ifp1 = sc_if1->sk_ifp; 2604 if (ifp0 != NULL) 2605 sk_stop(sc_if0); 2606 if (ifp1 != NULL) 2607 sk_stop(sc_if1); 2608 sc->sk_suspended = 1; 2609 2610 SK_UNLOCK(sc); 2611 2612 return (0); 2613 } 2614 2615 static int 2616 skc_resume(dev) 2617 device_t dev; 2618 { 2619 struct sk_softc *sc; 2620 struct sk_if_softc *sc_if0, *sc_if1; 2621 if_t ifp0 = NULL, ifp1 = NULL; 2622 2623 sc = device_get_softc(dev); 2624 2625 SK_LOCK(sc); 2626 2627 sc_if0 = sc->sk_if[SK_PORT_A]; 2628 sc_if1 = sc->sk_if[SK_PORT_B]; 2629 if (sc_if0 != NULL) 2630 ifp0 = sc_if0->sk_ifp; 2631 if (sc_if1 != NULL) 2632 ifp1 = sc_if1->sk_ifp; 2633 if (ifp0 != NULL && if_getflags(ifp0) & IFF_UP) 2634 sk_init_locked(sc_if0); 2635 if (ifp1 != NULL && if_getflags(ifp1) & IFF_UP) 2636 sk_init_locked(sc_if1); 2637 sc->sk_suspended = 0; 2638 2639 SK_UNLOCK(sc); 2640 2641 return (0); 2642 } 2643 2644 /* 2645 * According to the data sheet from SK-NET GENESIS the hardware can compute 2646 * two Rx checksums at the same time(Each checksum start position is 2647 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2648 * does not work at least on my Yukon hardware. I tried every possible ways 2649 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2650 * checksum offload was disabled at the moment and only IP checksum offload 2651 * was enabled. 2652 * As nomral IP header size is 20 bytes I can't expect it would give an 2653 * increase in throughput. However it seems it doesn't hurt performance in 2654 * my testing. If there is a more detailed information for checksum secret 2655 * of the hardware in question please contact yongari@FreeBSD.org to add 2656 * TCP/UDP checksum offload support. 2657 */ 2658 static __inline void 2659 sk_rxcksum(ifp, m, csum) 2660 if_t ifp; 2661 struct mbuf *m; 2662 u_int32_t csum; 2663 { 2664 struct ether_header *eh; 2665 struct ip *ip; 2666 int32_t hlen, len, pktlen; 2667 u_int16_t csum1, csum2, ipcsum; 2668 2669 pktlen = m->m_pkthdr.len; 2670 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2671 return; 2672 eh = mtod(m, struct ether_header *); 2673 if (eh->ether_type != htons(ETHERTYPE_IP)) 2674 return; 2675 ip = (struct ip *)(eh + 1); 2676 if (ip->ip_v != IPVERSION) 2677 return; 2678 hlen = ip->ip_hl << 2; 2679 pktlen -= sizeof(struct ether_header); 2680 if (hlen < sizeof(struct ip)) 2681 return; 2682 if (ntohs(ip->ip_len) < hlen) 2683 return; 2684 if (ntohs(ip->ip_len) != pktlen) 2685 return; 2686 2687 csum1 = htons(csum & 0xffff); 2688 csum2 = htons((csum >> 16) & 0xffff); 2689 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 2690 /* checksum fixup for IP options */ 2691 len = hlen - sizeof(struct ip); 2692 if (len > 0) { 2693 /* 2694 * If the second checksum value is correct we can compute IP 2695 * checksum with simple math. Unfortunately the second checksum 2696 * value is wrong so we can't verify the checksum from the 2697 * value(It seems there is some magic here to get correct 2698 * value). If the second checksum value is correct it also 2699 * means we can get TCP/UDP checksum) here. However, it still 2700 * needs pseudo header checksum calculation due to hardware 2701 * limitations. 2702 */ 2703 return; 2704 } 2705 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 2706 if (ipcsum == 0xffff) 2707 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2708 } 2709 2710 static __inline int 2711 sk_rxvalid(sc, stat, len) 2712 struct sk_softc *sc; 2713 u_int32_t stat, len; 2714 { 2715 2716 if (sc->sk_type == SK_GENESIS) { 2717 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 2718 XM_RXSTAT_BYTES(stat) != len) 2719 return (0); 2720 } else { 2721 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2722 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2723 YU_RXSTAT_JABBER)) != 0 || 2724 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2725 YU_RXSTAT_BYTES(stat) != len) 2726 return (0); 2727 } 2728 2729 return (1); 2730 } 2731 2732 static void 2733 sk_rxeof(sc_if) 2734 struct sk_if_softc *sc_if; 2735 { 2736 struct sk_softc *sc; 2737 struct mbuf *m; 2738 if_t ifp; 2739 struct sk_rx_desc *cur_rx; 2740 struct sk_rxdesc *rxd; 2741 int cons, prog; 2742 u_int32_t csum, rxstat, sk_ctl; 2743 2744 sc = sc_if->sk_softc; 2745 ifp = sc_if->sk_ifp; 2746 2747 SK_IF_LOCK_ASSERT(sc_if); 2748 2749 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2750 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 2751 2752 prog = 0; 2753 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 2754 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 2755 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 2756 sk_ctl = le32toh(cur_rx->sk_ctl); 2757 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2758 break; 2759 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 2760 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2761 2762 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2763 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2764 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2765 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2766 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 2767 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2768 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2769 sk_discard_rxbuf(sc_if, cons); 2770 continue; 2771 } 2772 2773 m = rxd->rx_m; 2774 csum = le32toh(cur_rx->sk_csum); 2775 if (sk_newbuf(sc_if, cons) != 0) { 2776 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2777 /* reuse old buffer */ 2778 sk_discard_rxbuf(sc_if, cons); 2779 continue; 2780 } 2781 m->m_pkthdr.rcvif = ifp; 2782 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2783 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2784 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2785 sk_rxcksum(ifp, m, csum); 2786 SK_IF_UNLOCK(sc_if); 2787 if_input(ifp, m); 2788 SK_IF_LOCK(sc_if); 2789 } 2790 2791 if (prog > 0) { 2792 sc_if->sk_cdata.sk_rx_cons = cons; 2793 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2794 sc_if->sk_cdata.sk_rx_ring_map, 2795 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2796 } 2797 } 2798 2799 static void 2800 sk_jumbo_rxeof(sc_if) 2801 struct sk_if_softc *sc_if; 2802 { 2803 struct sk_softc *sc; 2804 struct mbuf *m; 2805 if_t ifp; 2806 struct sk_rx_desc *cur_rx; 2807 struct sk_rxdesc *jrxd; 2808 int cons, prog; 2809 u_int32_t csum, rxstat, sk_ctl; 2810 2811 sc = sc_if->sk_softc; 2812 ifp = sc_if->sk_ifp; 2813 2814 SK_IF_LOCK_ASSERT(sc_if); 2815 2816 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2817 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 2818 2819 prog = 0; 2820 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 2821 prog < SK_JUMBO_RX_RING_CNT; 2822 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 2823 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 2824 sk_ctl = le32toh(cur_rx->sk_ctl); 2825 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2826 break; 2827 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 2828 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2829 2830 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2831 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2832 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2833 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2834 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 2835 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2836 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2837 sk_discard_jumbo_rxbuf(sc_if, cons); 2838 continue; 2839 } 2840 2841 m = jrxd->rx_m; 2842 csum = le32toh(cur_rx->sk_csum); 2843 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 2844 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2845 /* reuse old buffer */ 2846 sk_discard_jumbo_rxbuf(sc_if, cons); 2847 continue; 2848 } 2849 m->m_pkthdr.rcvif = ifp; 2850 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2851 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2852 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2853 sk_rxcksum(ifp, m, csum); 2854 SK_IF_UNLOCK(sc_if); 2855 if_input(ifp, m); 2856 SK_IF_LOCK(sc_if); 2857 } 2858 2859 if (prog > 0) { 2860 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 2861 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2862 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2863 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2864 } 2865 } 2866 2867 static void 2868 sk_txeof(sc_if) 2869 struct sk_if_softc *sc_if; 2870 { 2871 struct sk_txdesc *txd; 2872 struct sk_tx_desc *cur_tx; 2873 if_t ifp; 2874 u_int32_t idx, sk_ctl; 2875 2876 ifp = sc_if->sk_ifp; 2877 2878 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2879 if (txd == NULL) 2880 return; 2881 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2882 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 2883 /* 2884 * Go through our tx ring and free mbufs for those 2885 * frames that have been sent. 2886 */ 2887 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 2888 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 2889 break; 2890 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 2891 sk_ctl = le32toh(cur_tx->sk_ctl); 2892 if (sk_ctl & SK_TXCTL_OWN) 2893 break; 2894 sc_if->sk_cdata.sk_tx_cnt--; 2895 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2896 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 2897 continue; 2898 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2899 BUS_DMASYNC_POSTWRITE); 2900 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2901 2902 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2903 m_freem(txd->tx_m); 2904 txd->tx_m = NULL; 2905 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 2906 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 2907 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2908 } 2909 sc_if->sk_cdata.sk_tx_cons = idx; 2910 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2911 2912 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2913 sc_if->sk_cdata.sk_tx_ring_map, 2914 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2915 } 2916 2917 static void 2918 sk_tick(xsc_if) 2919 void *xsc_if; 2920 { 2921 struct sk_if_softc *sc_if; 2922 struct mii_data *mii; 2923 if_t ifp; 2924 int i; 2925 2926 sc_if = xsc_if; 2927 ifp = sc_if->sk_ifp; 2928 mii = device_get_softc(sc_if->sk_miibus); 2929 2930 if (!(if_getflags(ifp) & IFF_UP)) 2931 return; 2932 2933 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2934 sk_intr_bcom(sc_if); 2935 return; 2936 } 2937 2938 /* 2939 * According to SysKonnect, the correct way to verify that 2940 * the link has come back up is to poll bit 0 of the GPIO 2941 * register three times. This pin has the signal from the 2942 * link_sync pin connected to it; if we read the same link 2943 * state 3 times in a row, we know the link is up. 2944 */ 2945 for (i = 0; i < 3; i++) { 2946 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2947 break; 2948 } 2949 2950 if (i != 3) { 2951 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2952 return; 2953 } 2954 2955 /* Turn the GP0 interrupt back on. */ 2956 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2957 SK_XM_READ_2(sc_if, XM_ISR); 2958 mii_tick(mii); 2959 callout_stop(&sc_if->sk_tick_ch); 2960 } 2961 2962 static void 2963 sk_yukon_tick(xsc_if) 2964 void *xsc_if; 2965 { 2966 struct sk_if_softc *sc_if; 2967 struct mii_data *mii; 2968 2969 sc_if = xsc_if; 2970 mii = device_get_softc(sc_if->sk_miibus); 2971 2972 mii_tick(mii); 2973 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 2974 } 2975 2976 static void 2977 sk_intr_bcom(sc_if) 2978 struct sk_if_softc *sc_if; 2979 { 2980 struct mii_data *mii; 2981 if_t ifp; 2982 int status; 2983 mii = device_get_softc(sc_if->sk_miibus); 2984 ifp = sc_if->sk_ifp; 2985 2986 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2987 2988 /* 2989 * Read the PHY interrupt register to make sure 2990 * we clear any pending interrupts. 2991 */ 2992 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2993 2994 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 2995 sk_init_xmac(sc_if); 2996 return; 2997 } 2998 2999 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 3000 int lstat; 3001 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 3002 BRGPHY_MII_AUXSTS); 3003 3004 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 3005 mii_mediachg(mii); 3006 /* Turn off the link LED. */ 3007 SK_IF_WRITE_1(sc_if, 0, 3008 SK_LINKLED1_CTL, SK_LINKLED_OFF); 3009 sc_if->sk_link = 0; 3010 } else if (status & BRGPHY_ISR_LNK_CHG) { 3011 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3012 BRGPHY_MII_IMR, 0xFF00); 3013 mii_tick(mii); 3014 sc_if->sk_link = 1; 3015 /* Turn on the link LED. */ 3016 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3017 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 3018 SK_LINKLED_BLINK_OFF); 3019 } else { 3020 mii_tick(mii); 3021 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3022 } 3023 } 3024 3025 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3026 3027 return; 3028 } 3029 3030 static void 3031 sk_intr_xmac(sc_if) 3032 struct sk_if_softc *sc_if; 3033 { 3034 u_int16_t status; 3035 3036 status = SK_XM_READ_2(sc_if, XM_ISR); 3037 3038 /* 3039 * Link has gone down. Start MII tick timeout to 3040 * watch for link resync. 3041 */ 3042 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 3043 if (status & XM_ISR_GP0_SET) { 3044 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3045 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3046 } 3047 3048 if (status & XM_ISR_AUTONEG_DONE) { 3049 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3050 } 3051 } 3052 3053 if (status & XM_IMR_TX_UNDERRUN) 3054 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 3055 3056 if (status & XM_IMR_RX_OVERRUN) 3057 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 3058 3059 status = SK_XM_READ_2(sc_if, XM_ISR); 3060 3061 return; 3062 } 3063 3064 static void 3065 sk_intr_yukon(sc_if) 3066 struct sk_if_softc *sc_if; 3067 { 3068 u_int8_t status; 3069 3070 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 3071 /* RX overrun */ 3072 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 3073 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3074 SK_RFCTL_RX_FIFO_OVER); 3075 } 3076 /* TX underrun */ 3077 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 3078 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3079 SK_TFCTL_TX_FIFO_UNDER); 3080 } 3081 } 3082 3083 static void 3084 sk_intr(xsc) 3085 void *xsc; 3086 { 3087 struct sk_softc *sc = xsc; 3088 struct sk_if_softc *sc_if0, *sc_if1; 3089 if_t ifp0 = NULL, ifp1 = NULL; 3090 u_int32_t status; 3091 3092 SK_LOCK(sc); 3093 3094 status = CSR_READ_4(sc, SK_ISSR); 3095 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3096 goto done_locked; 3097 3098 sc_if0 = sc->sk_if[SK_PORT_A]; 3099 sc_if1 = sc->sk_if[SK_PORT_B]; 3100 3101 if (sc_if0 != NULL) 3102 ifp0 = sc_if0->sk_ifp; 3103 if (sc_if1 != NULL) 3104 ifp1 = sc_if1->sk_ifp; 3105 3106 for (; (status &= sc->sk_intrmask) != 0;) { 3107 /* Handle receive interrupts first. */ 3108 if (status & SK_ISR_RX1_EOF) { 3109 if (if_getmtu(ifp0) > SK_MAX_FRAMELEN) 3110 sk_jumbo_rxeof(sc_if0); 3111 else 3112 sk_rxeof(sc_if0); 3113 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3114 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3115 } 3116 if (status & SK_ISR_RX2_EOF) { 3117 if (if_getflags(ifp1) > SK_MAX_FRAMELEN) 3118 sk_jumbo_rxeof(sc_if1); 3119 else 3120 sk_rxeof(sc_if1); 3121 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3122 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3123 } 3124 3125 /* Then transmit interrupts. */ 3126 if (status & SK_ISR_TX1_S_EOF) { 3127 sk_txeof(sc_if0); 3128 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3129 } 3130 if (status & SK_ISR_TX2_S_EOF) { 3131 sk_txeof(sc_if1); 3132 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3133 } 3134 3135 /* Then MAC interrupts. */ 3136 if (status & SK_ISR_MAC1 && 3137 if_getdrvflags(ifp0) & IFF_DRV_RUNNING) { 3138 if (sc->sk_type == SK_GENESIS) 3139 sk_intr_xmac(sc_if0); 3140 else 3141 sk_intr_yukon(sc_if0); 3142 } 3143 3144 if (status & SK_ISR_MAC2 && 3145 if_getdrvflags(ifp1) & IFF_DRV_RUNNING) { 3146 if (sc->sk_type == SK_GENESIS) 3147 sk_intr_xmac(sc_if1); 3148 else 3149 sk_intr_yukon(sc_if1); 3150 } 3151 3152 if (status & SK_ISR_EXTERNAL_REG) { 3153 if (ifp0 != NULL && 3154 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3155 sk_intr_bcom(sc_if0); 3156 if (ifp1 != NULL && 3157 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3158 sk_intr_bcom(sc_if1); 3159 } 3160 status = CSR_READ_4(sc, SK_ISSR); 3161 } 3162 3163 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3164 3165 if (ifp0 != NULL && !if_sendq_empty(ifp0)) 3166 sk_start_locked(ifp0); 3167 if (ifp1 != NULL && !if_sendq_empty(ifp1)) 3168 sk_start_locked(ifp1); 3169 3170 done_locked: 3171 SK_UNLOCK(sc); 3172 } 3173 3174 static void 3175 sk_init_xmac(sc_if) 3176 struct sk_if_softc *sc_if; 3177 { 3178 struct sk_softc *sc; 3179 if_t ifp; 3180 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3181 static const struct sk_bcom_hack bhack[] = { 3182 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3183 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3184 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3185 { 0, 0 } }; 3186 3187 SK_IF_LOCK_ASSERT(sc_if); 3188 3189 sc = sc_if->sk_softc; 3190 ifp = sc_if->sk_ifp; 3191 3192 /* Unreset the XMAC. */ 3193 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3194 DELAY(1000); 3195 3196 /* Reset the XMAC's internal state. */ 3197 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3198 3199 /* Save the XMAC II revision */ 3200 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3201 3202 /* 3203 * Perform additional initialization for external PHYs, 3204 * namely for the 1000baseTX cards that use the XMAC's 3205 * GMII mode. 3206 */ 3207 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3208 int i = 0; 3209 u_int32_t val; 3210 3211 /* Take PHY out of reset. */ 3212 val = sk_win_read_4(sc, SK_GPIO); 3213 if (sc_if->sk_port == SK_PORT_A) 3214 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3215 else 3216 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3217 sk_win_write_4(sc, SK_GPIO, val); 3218 3219 /* Enable GMII mode on the XMAC. */ 3220 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3221 3222 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3223 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3224 DELAY(10000); 3225 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3226 BRGPHY_MII_IMR, 0xFFF0); 3227 3228 /* 3229 * Early versions of the BCM5400 apparently have 3230 * a bug that requires them to have their reserved 3231 * registers initialized to some magic values. I don't 3232 * know what the numbers do, I'm just the messenger. 3233 */ 3234 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3235 == 0x6041) { 3236 while(bhack[i].reg) { 3237 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3238 bhack[i].reg, bhack[i].val); 3239 i++; 3240 } 3241 } 3242 } 3243 3244 /* Set station address */ 3245 bcopy(if_getlladdr(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3246 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3247 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3248 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3249 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3250 3251 if (if_getflags(ifp) & IFF_BROADCAST) { 3252 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3253 } else { 3254 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3255 } 3256 3257 /* We don't need the FCS appended to the packet. */ 3258 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3259 3260 /* We want short frames padded to 60 bytes. */ 3261 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3262 3263 /* 3264 * Enable the reception of all error frames. This is is 3265 * a necessary evil due to the design of the XMAC. The 3266 * XMAC's receive FIFO is only 8K in size, however jumbo 3267 * frames can be up to 9000 bytes in length. When bad 3268 * frame filtering is enabled, the XMAC's RX FIFO operates 3269 * in 'store and forward' mode. For this to work, the 3270 * entire frame has to fit into the FIFO, but that means 3271 * that jumbo frames larger than 8192 bytes will be 3272 * truncated. Disabling all bad frame filtering causes 3273 * the RX FIFO to operate in streaming mode, in which 3274 * case the XMAC will start transferring frames out of the 3275 * RX FIFO as soon as the FIFO threshold is reached. 3276 */ 3277 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) { 3278 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3279 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3280 XM_MODE_RX_INRANGELEN); 3281 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3282 } else 3283 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3284 3285 /* 3286 * Bump up the transmit threshold. This helps hold off transmit 3287 * underruns when we're blasting traffic from both ports at once. 3288 */ 3289 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3290 3291 /* Set Rx filter */ 3292 sk_rxfilter_genesis(sc_if); 3293 3294 /* Clear and enable interrupts */ 3295 SK_XM_READ_2(sc_if, XM_ISR); 3296 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3297 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3298 else 3299 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3300 3301 /* Configure MAC arbiter */ 3302 switch(sc_if->sk_xmac_rev) { 3303 case XM_XMAC_REV_B2: 3304 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3305 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3306 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3307 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3308 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3309 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3310 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3311 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3312 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3313 break; 3314 case XM_XMAC_REV_C1: 3315 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3316 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3317 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3318 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3319 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3320 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3321 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3322 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3323 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3324 break; 3325 default: 3326 break; 3327 } 3328 sk_win_write_2(sc, SK_MACARB_CTL, 3329 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3330 3331 sc_if->sk_link = 1; 3332 3333 return; 3334 } 3335 3336 static void 3337 sk_init_yukon(sc_if) 3338 struct sk_if_softc *sc_if; 3339 { 3340 u_int32_t phy, v; 3341 u_int16_t reg; 3342 struct sk_softc *sc; 3343 if_t ifp; 3344 u_int8_t *eaddr; 3345 int i; 3346 3347 SK_IF_LOCK_ASSERT(sc_if); 3348 3349 sc = sc_if->sk_softc; 3350 ifp = sc_if->sk_ifp; 3351 3352 if (sc->sk_type == SK_YUKON_LITE && 3353 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3354 /* 3355 * Workaround code for COMA mode, set PHY reset. 3356 * Otherwise it will not correctly take chip out of 3357 * powerdown (coma) 3358 */ 3359 v = sk_win_read_4(sc, SK_GPIO); 3360 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3361 sk_win_write_4(sc, SK_GPIO, v); 3362 } 3363 3364 /* GMAC and GPHY Reset */ 3365 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3366 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3367 DELAY(1000); 3368 3369 if (sc->sk_type == SK_YUKON_LITE && 3370 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3371 /* 3372 * Workaround code for COMA mode, clear PHY reset 3373 */ 3374 v = sk_win_read_4(sc, SK_GPIO); 3375 v |= SK_GPIO_DIR9; 3376 v &= ~SK_GPIO_DAT9; 3377 sk_win_write_4(sc, SK_GPIO, v); 3378 } 3379 3380 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3381 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3382 3383 if (sc->sk_coppertype) 3384 phy |= SK_GPHY_COPPER; 3385 else 3386 phy |= SK_GPHY_FIBER; 3387 3388 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3389 DELAY(1000); 3390 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3391 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3392 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3393 3394 /* unused read of the interrupt source register */ 3395 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3396 3397 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3398 3399 /* MIB Counter Clear Mode set */ 3400 reg |= YU_PAR_MIB_CLR; 3401 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3402 3403 /* MIB Counter Clear Mode clear */ 3404 reg &= ~YU_PAR_MIB_CLR; 3405 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3406 3407 /* receive control reg */ 3408 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3409 3410 /* transmit parameter register */ 3411 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3412 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3413 3414 /* serial mode register */ 3415 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3416 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) 3417 reg |= YU_SMR_MFL_JUMBO; 3418 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3419 3420 /* Setup Yukon's station address */ 3421 eaddr = if_getlladdr(sc_if->sk_ifp); 3422 for (i = 0; i < 3; i++) 3423 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4, 3424 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3425 /* Set GMAC source address of flow control. */ 3426 for (i = 0; i < 3; i++) 3427 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3428 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3429 /* Set GMAC virtual address. */ 3430 for (i = 0; i < 3; i++) 3431 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, 3432 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3433 3434 /* Set Rx filter */ 3435 sk_rxfilter_yukon(sc_if); 3436 3437 /* enable interrupt mask for counter overflows */ 3438 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3439 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3440 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3441 3442 /* Configure RX MAC FIFO Flush Mask */ 3443 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3444 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3445 YU_RXSTAT_JABBER; 3446 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3447 3448 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3449 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3450 v = SK_TFCTL_OPERATION_ON; 3451 else 3452 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3453 /* Configure RX MAC FIFO */ 3454 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3455 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3456 3457 /* Increase flush threshould to 64 bytes */ 3458 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3459 SK_RFCTL_FIFO_THRESHOLD + 1); 3460 3461 /* Configure TX MAC FIFO */ 3462 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3463 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3464 } 3465 3466 /* 3467 * Note that to properly initialize any part of the GEnesis chip, 3468 * you first have to take it out of reset mode. 3469 */ 3470 static void 3471 sk_init(xsc) 3472 void *xsc; 3473 { 3474 struct sk_if_softc *sc_if = xsc; 3475 3476 SK_IF_LOCK(sc_if); 3477 sk_init_locked(sc_if); 3478 SK_IF_UNLOCK(sc_if); 3479 3480 return; 3481 } 3482 3483 static void 3484 sk_init_locked(sc_if) 3485 struct sk_if_softc *sc_if; 3486 { 3487 struct sk_softc *sc; 3488 if_t ifp; 3489 struct mii_data *mii; 3490 u_int16_t reg; 3491 u_int32_t imr; 3492 int error; 3493 3494 SK_IF_LOCK_ASSERT(sc_if); 3495 3496 ifp = sc_if->sk_ifp; 3497 sc = sc_if->sk_softc; 3498 mii = device_get_softc(sc_if->sk_miibus); 3499 3500 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3501 return; 3502 3503 /* Cancel pending I/O and free all RX/TX buffers. */ 3504 sk_stop(sc_if); 3505 3506 if (sc->sk_type == SK_GENESIS) { 3507 /* Configure LINK_SYNC LED */ 3508 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3509 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3510 SK_LINKLED_LINKSYNC_ON); 3511 3512 /* Configure RX LED */ 3513 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3514 SK_RXLEDCTL_COUNTER_START); 3515 3516 /* Configure TX LED */ 3517 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3518 SK_TXLEDCTL_COUNTER_START); 3519 } 3520 3521 /* 3522 * Configure descriptor poll timer 3523 * 3524 * SK-NET GENESIS data sheet says that possibility of losing Start 3525 * transmit command due to CPU/cache related interim storage problems 3526 * under certain conditions. The document recommends a polling 3527 * mechanism to send a Start transmit command to initiate transfer 3528 * of ready descriptors regulary. To cope with this issue sk(4) now 3529 * enables descriptor poll timer to initiate descriptor processing 3530 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3531 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3532 * command instead of waiting for next descriptor polling time. 3533 * The same rule may apply to Rx side too but it seems that is not 3534 * needed at the moment. 3535 * Since sk(4) uses descriptor polling as a last resort there is no 3536 * need to set smaller polling time than maximum allowable one. 3537 */ 3538 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3539 3540 /* Configure I2C registers */ 3541 3542 /* Configure XMAC(s) */ 3543 switch (sc->sk_type) { 3544 case SK_GENESIS: 3545 sk_init_xmac(sc_if); 3546 break; 3547 case SK_YUKON: 3548 case SK_YUKON_LITE: 3549 case SK_YUKON_LP: 3550 sk_init_yukon(sc_if); 3551 break; 3552 } 3553 mii_mediachg(mii); 3554 3555 if (sc->sk_type == SK_GENESIS) { 3556 /* Configure MAC FIFOs */ 3557 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3558 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3559 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3560 3561 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3562 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3563 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3564 } 3565 3566 /* Configure transmit arbiter(s) */ 3567 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3568 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3569 3570 /* Configure RAMbuffers */ 3571 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3572 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3573 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3574 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3575 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3576 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3577 3578 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3579 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3580 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3581 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3582 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3583 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3584 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3585 3586 /* Configure BMUs */ 3587 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3588 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) { 3589 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3590 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3591 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3592 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3593 } else { 3594 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3595 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3596 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3597 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3598 } 3599 3600 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3601 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3602 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3603 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3604 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3605 3606 /* Init descriptors */ 3607 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) 3608 error = sk_init_jumbo_rx_ring(sc_if); 3609 else 3610 error = sk_init_rx_ring(sc_if); 3611 if (error != 0) { 3612 device_printf(sc_if->sk_if_dev, 3613 "initialization failed: no memory for rx buffers\n"); 3614 sk_stop(sc_if); 3615 return; 3616 } 3617 sk_init_tx_ring(sc_if); 3618 3619 /* Set interrupt moderation if changed via sysctl. */ 3620 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3621 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3622 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3623 sc->sk_int_ticks)); 3624 if (bootverbose) 3625 device_printf(sc_if->sk_if_dev, 3626 "interrupt moderation is %d us.\n", 3627 sc->sk_int_mod); 3628 } 3629 3630 /* Configure interrupt handling */ 3631 CSR_READ_4(sc, SK_ISSR); 3632 if (sc_if->sk_port == SK_PORT_A) 3633 sc->sk_intrmask |= SK_INTRS1; 3634 else 3635 sc->sk_intrmask |= SK_INTRS2; 3636 3637 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3638 3639 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3640 3641 /* Start BMUs. */ 3642 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3643 3644 switch(sc->sk_type) { 3645 case SK_GENESIS: 3646 /* Enable XMACs TX and RX state machines */ 3647 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3648 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3649 break; 3650 case SK_YUKON: 3651 case SK_YUKON_LITE: 3652 case SK_YUKON_LP: 3653 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3654 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3655 #if 0 3656 /* XXX disable 100Mbps and full duplex mode? */ 3657 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3658 #endif 3659 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3660 } 3661 3662 /* Activate descriptor polling timer */ 3663 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 3664 /* start transfer of Tx descriptors */ 3665 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 3666 3667 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3668 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3669 3670 switch (sc->sk_type) { 3671 case SK_YUKON: 3672 case SK_YUKON_LITE: 3673 case SK_YUKON_LP: 3674 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3675 break; 3676 } 3677 3678 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 3679 3680 return; 3681 } 3682 3683 static void 3684 sk_stop(sc_if) 3685 struct sk_if_softc *sc_if; 3686 { 3687 int i; 3688 struct sk_softc *sc; 3689 struct sk_txdesc *txd; 3690 struct sk_rxdesc *rxd; 3691 struct sk_rxdesc *jrxd; 3692 if_t ifp; 3693 u_int32_t val; 3694 3695 SK_IF_LOCK_ASSERT(sc_if); 3696 sc = sc_if->sk_softc; 3697 ifp = sc_if->sk_ifp; 3698 3699 callout_stop(&sc_if->sk_tick_ch); 3700 callout_stop(&sc_if->sk_watchdog_ch); 3701 3702 /* stop Tx descriptor polling timer */ 3703 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 3704 /* stop transfer of Tx descriptors */ 3705 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 3706 for (i = 0; i < SK_TIMEOUT; i++) { 3707 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 3708 if ((val & SK_TXBMU_TX_STOP) == 0) 3709 break; 3710 DELAY(1); 3711 } 3712 if (i == SK_TIMEOUT) 3713 device_printf(sc_if->sk_if_dev, 3714 "can not stop transfer of Tx descriptor\n"); 3715 /* stop transfer of Rx descriptors */ 3716 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 3717 for (i = 0; i < SK_TIMEOUT; i++) { 3718 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 3719 if ((val & SK_RXBMU_RX_STOP) == 0) 3720 break; 3721 DELAY(1); 3722 } 3723 if (i == SK_TIMEOUT) 3724 device_printf(sc_if->sk_if_dev, 3725 "can not stop transfer of Rx descriptor\n"); 3726 3727 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3728 /* Put PHY back into reset. */ 3729 val = sk_win_read_4(sc, SK_GPIO); 3730 if (sc_if->sk_port == SK_PORT_A) { 3731 val |= SK_GPIO_DIR0; 3732 val &= ~SK_GPIO_DAT0; 3733 } else { 3734 val |= SK_GPIO_DIR2; 3735 val &= ~SK_GPIO_DAT2; 3736 } 3737 sk_win_write_4(sc, SK_GPIO, val); 3738 } 3739 3740 /* Turn off various components of this interface. */ 3741 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3742 switch (sc->sk_type) { 3743 case SK_GENESIS: 3744 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 3745 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 3746 break; 3747 case SK_YUKON: 3748 case SK_YUKON_LITE: 3749 case SK_YUKON_LP: 3750 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 3751 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 3752 break; 3753 } 3754 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 3755 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3756 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 3757 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3758 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 3759 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3760 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3761 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 3762 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 3763 3764 /* Disable interrupts */ 3765 if (sc_if->sk_port == SK_PORT_A) 3766 sc->sk_intrmask &= ~SK_INTRS1; 3767 else 3768 sc->sk_intrmask &= ~SK_INTRS2; 3769 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3770 3771 SK_XM_READ_2(sc_if, XM_ISR); 3772 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3773 3774 /* Free RX and TX mbufs still in the queues. */ 3775 for (i = 0; i < SK_RX_RING_CNT; i++) { 3776 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 3777 if (rxd->rx_m != NULL) { 3778 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 3779 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3780 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 3781 rxd->rx_dmamap); 3782 m_freem(rxd->rx_m); 3783 rxd->rx_m = NULL; 3784 } 3785 } 3786 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 3787 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 3788 if (jrxd->rx_m != NULL) { 3789 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 3790 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3791 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 3792 jrxd->rx_dmamap); 3793 m_freem(jrxd->rx_m); 3794 jrxd->rx_m = NULL; 3795 } 3796 } 3797 for (i = 0; i < SK_TX_RING_CNT; i++) { 3798 txd = &sc_if->sk_cdata.sk_txdesc[i]; 3799 if (txd->tx_m != NULL) { 3800 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 3801 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3802 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 3803 txd->tx_dmamap); 3804 m_freem(txd->tx_m); 3805 txd->tx_m = NULL; 3806 } 3807 } 3808 3809 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)); 3810 3811 return; 3812 } 3813 3814 static int 3815 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3816 { 3817 int error, value; 3818 3819 if (!arg1) 3820 return (EINVAL); 3821 value = *(int *)arg1; 3822 error = sysctl_handle_int(oidp, &value, 0, req); 3823 if (error || !req->newptr) 3824 return (error); 3825 if (value < low || value > high) 3826 return (EINVAL); 3827 *(int *)arg1 = value; 3828 return (0); 3829 } 3830 3831 static int 3832 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 3833 { 3834 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 3835 } 3836