1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /*- 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 /* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/bus.h> 91 #include <sys/endian.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/module.h> 96 #include <sys/socket.h> 97 #include <sys/sockio.h> 98 #include <sys/queue.h> 99 #include <sys/sysctl.h> 100 101 #include <net/bpf.h> 102 #include <net/ethernet.h> 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/if_vlan_var.h> 109 110 #include <netinet/in.h> 111 #include <netinet/in_systm.h> 112 #include <netinet/ip.h> 113 114 #include <machine/bus.h> 115 #include <machine/in_cksum.h> 116 #include <machine/resource.h> 117 #include <sys/rman.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/brgphyreg.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #if 0 127 #define SK_USEIOSPACE 128 #endif 129 130 #include <dev/sk/if_skreg.h> 131 #include <dev/sk/xmaciireg.h> 132 #include <dev/sk/yukonreg.h> 133 134 MODULE_DEPEND(sk, pci, 1, 1, 1); 135 MODULE_DEPEND(sk, ether, 1, 1, 1); 136 MODULE_DEPEND(sk, miibus, 1, 1, 1); 137 138 /* "device miibus" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 #ifndef lint 142 static const char rcsid[] = 143 "$FreeBSD$"; 144 #endif 145 146 static struct sk_type sk_devs[] = { 147 { 148 VENDORID_SK, 149 DEVICEID_SK_V1, 150 "SysKonnect Gigabit Ethernet (V1.0)" 151 }, 152 { 153 VENDORID_SK, 154 DEVICEID_SK_V2, 155 "SysKonnect Gigabit Ethernet (V2.0)" 156 }, 157 { 158 VENDORID_MARVELL, 159 DEVICEID_SK_V2, 160 "Marvell Gigabit Ethernet" 161 }, 162 { 163 VENDORID_MARVELL, 164 DEVICEID_BELKIN_5005, 165 "Belkin F5D5005 Gigabit Ethernet" 166 }, 167 { 168 VENDORID_3COM, 169 DEVICEID_3COM_3C940, 170 "3Com 3C940 Gigabit Ethernet" 171 }, 172 { 173 VENDORID_LINKSYS, 174 DEVICEID_LINKSYS_EG1032, 175 "Linksys EG1032 Gigabit Ethernet" 176 }, 177 { 178 VENDORID_DLINK, 179 DEVICEID_DLINK_DGE530T_A1, 180 "D-Link DGE-530T Gigabit Ethernet" 181 }, 182 { 183 VENDORID_DLINK, 184 DEVICEID_DLINK_DGE530T_B1, 185 "D-Link DGE-530T Gigabit Ethernet" 186 }, 187 { 0, 0, NULL } 188 }; 189 190 static int skc_probe(device_t); 191 static int skc_attach(device_t); 192 static int skc_detach(device_t); 193 static void skc_shutdown(device_t); 194 static int skc_suspend(device_t); 195 static int skc_resume(device_t); 196 static int sk_detach(device_t); 197 static int sk_probe(device_t); 198 static int sk_attach(device_t); 199 static void sk_tick(void *); 200 static void sk_yukon_tick(void *); 201 static void sk_intr(void *); 202 static void sk_intr_xmac(struct sk_if_softc *); 203 static void sk_intr_bcom(struct sk_if_softc *); 204 static void sk_intr_yukon(struct sk_if_softc *); 205 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t); 206 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 207 static void sk_rxeof(struct sk_if_softc *); 208 static void sk_jumbo_rxeof(struct sk_if_softc *); 209 static void sk_txeof(struct sk_if_softc *); 210 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *); 211 static int sk_encap(struct sk_if_softc *, struct mbuf **); 212 static void sk_start(struct ifnet *); 213 static void sk_start_locked(struct ifnet *); 214 static int sk_ioctl(struct ifnet *, u_long, caddr_t); 215 static void sk_init(void *); 216 static void sk_init_locked(struct sk_if_softc *); 217 static void sk_init_xmac(struct sk_if_softc *); 218 static void sk_init_yukon(struct sk_if_softc *); 219 static void sk_stop(struct sk_if_softc *); 220 static void sk_watchdog(void *); 221 static int sk_ifmedia_upd(struct ifnet *); 222 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 223 static void sk_reset(struct sk_softc *); 224 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 225 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 226 static int sk_newbuf(struct sk_if_softc *, int); 227 static int sk_jumbo_newbuf(struct sk_if_softc *, int); 228 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 229 static int sk_dma_alloc(struct sk_if_softc *); 230 static void sk_dma_free(struct sk_if_softc *); 231 static void *sk_jalloc(struct sk_if_softc *); 232 static void sk_jfree(void *, void *); 233 static int sk_init_rx_ring(struct sk_if_softc *); 234 static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 235 static void sk_init_tx_ring(struct sk_if_softc *); 236 static u_int32_t sk_win_read_4(struct sk_softc *, int); 237 static u_int16_t sk_win_read_2(struct sk_softc *, int); 238 static u_int8_t sk_win_read_1(struct sk_softc *, int); 239 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 240 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 241 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 242 243 static int sk_miibus_readreg(device_t, int, int); 244 static int sk_miibus_writereg(device_t, int, int, int); 245 static void sk_miibus_statchg(device_t); 246 247 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 248 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 249 int); 250 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 251 252 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 253 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 254 int); 255 static void sk_marv_miibus_statchg(struct sk_if_softc *); 256 257 static uint32_t sk_xmchash(const uint8_t *); 258 static uint32_t sk_gmchash(const uint8_t *); 259 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 260 static void sk_setmulti(struct sk_if_softc *); 261 static void sk_setpromisc(struct sk_if_softc *); 262 263 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 264 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 265 266 /* 267 * It seems that SK-NET GENESIS supports very simple checksum offload 268 * capability for Tx and I believe it can generate 0 checksum value for 269 * UDP packets in Tx as the hardware can't differenciate UDP packets from 270 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 271 * means sender didn't perforam checksum computation. For the safety I 272 * disabled UDP checksum offload capability at the moment. Alternatively 273 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum 274 * offload routine. 275 */ 276 #define SK_CSUM_FEATURES (CSUM_TCP) 277 278 /* 279 * Note that we have newbus methods for both the GEnesis controller 280 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 281 * the miibus code is a child of the XMACs. We need to do it this way 282 * so that the miibus drivers can access the PHY registers on the 283 * right PHY. It's not quite what I had in mind, but it's the only 284 * design that achieves the desired effect. 285 */ 286 static device_method_t skc_methods[] = { 287 /* Device interface */ 288 DEVMETHOD(device_probe, skc_probe), 289 DEVMETHOD(device_attach, skc_attach), 290 DEVMETHOD(device_detach, skc_detach), 291 DEVMETHOD(device_suspend, skc_suspend), 292 DEVMETHOD(device_resume, skc_resume), 293 DEVMETHOD(device_shutdown, skc_shutdown), 294 295 /* bus interface */ 296 DEVMETHOD(bus_print_child, bus_generic_print_child), 297 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 298 299 { 0, 0 } 300 }; 301 302 static driver_t skc_driver = { 303 "skc", 304 skc_methods, 305 sizeof(struct sk_softc) 306 }; 307 308 static devclass_t skc_devclass; 309 310 static device_method_t sk_methods[] = { 311 /* Device interface */ 312 DEVMETHOD(device_probe, sk_probe), 313 DEVMETHOD(device_attach, sk_attach), 314 DEVMETHOD(device_detach, sk_detach), 315 DEVMETHOD(device_shutdown, bus_generic_shutdown), 316 317 /* bus interface */ 318 DEVMETHOD(bus_print_child, bus_generic_print_child), 319 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 323 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 324 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 325 326 { 0, 0 } 327 }; 328 329 static driver_t sk_driver = { 330 "sk", 331 sk_methods, 332 sizeof(struct sk_if_softc) 333 }; 334 335 static devclass_t sk_devclass; 336 337 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0); 338 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 339 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 340 341 static struct resource_spec sk_res_spec_io[] = { 342 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 343 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 344 { -1, 0, 0 } 345 }; 346 347 static struct resource_spec sk_res_spec_mem[] = { 348 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 349 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 350 { -1, 0, 0 } 351 }; 352 353 #define SK_SETBIT(sc, reg, x) \ 354 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 355 356 #define SK_CLRBIT(sc, reg, x) \ 357 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 358 359 #define SK_WIN_SETBIT_4(sc, reg, x) \ 360 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 361 362 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 363 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 364 365 #define SK_WIN_SETBIT_2(sc, reg, x) \ 366 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 367 368 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 369 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 370 371 static u_int32_t 372 sk_win_read_4(sc, reg) 373 struct sk_softc *sc; 374 int reg; 375 { 376 #ifdef SK_USEIOSPACE 377 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 378 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 379 #else 380 return(CSR_READ_4(sc, reg)); 381 #endif 382 } 383 384 static u_int16_t 385 sk_win_read_2(sc, reg) 386 struct sk_softc *sc; 387 int reg; 388 { 389 #ifdef SK_USEIOSPACE 390 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 391 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 392 #else 393 return(CSR_READ_2(sc, reg)); 394 #endif 395 } 396 397 static u_int8_t 398 sk_win_read_1(sc, reg) 399 struct sk_softc *sc; 400 int reg; 401 { 402 #ifdef SK_USEIOSPACE 403 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 404 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 405 #else 406 return(CSR_READ_1(sc, reg)); 407 #endif 408 } 409 410 static void 411 sk_win_write_4(sc, reg, val) 412 struct sk_softc *sc; 413 int reg; 414 u_int32_t val; 415 { 416 #ifdef SK_USEIOSPACE 417 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 418 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 419 #else 420 CSR_WRITE_4(sc, reg, val); 421 #endif 422 return; 423 } 424 425 static void 426 sk_win_write_2(sc, reg, val) 427 struct sk_softc *sc; 428 int reg; 429 u_int32_t val; 430 { 431 #ifdef SK_USEIOSPACE 432 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 433 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 434 #else 435 CSR_WRITE_2(sc, reg, val); 436 #endif 437 return; 438 } 439 440 static void 441 sk_win_write_1(sc, reg, val) 442 struct sk_softc *sc; 443 int reg; 444 u_int32_t val; 445 { 446 #ifdef SK_USEIOSPACE 447 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 448 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 449 #else 450 CSR_WRITE_1(sc, reg, val); 451 #endif 452 return; 453 } 454 455 static int 456 sk_miibus_readreg(dev, phy, reg) 457 device_t dev; 458 int phy, reg; 459 { 460 struct sk_if_softc *sc_if; 461 int v; 462 463 sc_if = device_get_softc(dev); 464 465 SK_IF_MII_LOCK(sc_if); 466 switch(sc_if->sk_softc->sk_type) { 467 case SK_GENESIS: 468 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 469 break; 470 case SK_YUKON: 471 case SK_YUKON_LITE: 472 case SK_YUKON_LP: 473 v = sk_marv_miibus_readreg(sc_if, phy, reg); 474 break; 475 default: 476 v = 0; 477 break; 478 } 479 SK_IF_MII_UNLOCK(sc_if); 480 481 return (v); 482 } 483 484 static int 485 sk_miibus_writereg(dev, phy, reg, val) 486 device_t dev; 487 int phy, reg, val; 488 { 489 struct sk_if_softc *sc_if; 490 int v; 491 492 sc_if = device_get_softc(dev); 493 494 SK_IF_MII_LOCK(sc_if); 495 switch(sc_if->sk_softc->sk_type) { 496 case SK_GENESIS: 497 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 498 break; 499 case SK_YUKON: 500 case SK_YUKON_LITE: 501 case SK_YUKON_LP: 502 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 503 break; 504 default: 505 v = 0; 506 break; 507 } 508 SK_IF_MII_UNLOCK(sc_if); 509 510 return (v); 511 } 512 513 static void 514 sk_miibus_statchg(dev) 515 device_t dev; 516 { 517 struct sk_if_softc *sc_if; 518 519 sc_if = device_get_softc(dev); 520 521 SK_IF_MII_LOCK(sc_if); 522 switch(sc_if->sk_softc->sk_type) { 523 case SK_GENESIS: 524 sk_xmac_miibus_statchg(sc_if); 525 break; 526 case SK_YUKON: 527 case SK_YUKON_LITE: 528 case SK_YUKON_LP: 529 sk_marv_miibus_statchg(sc_if); 530 break; 531 } 532 SK_IF_MII_UNLOCK(sc_if); 533 534 return; 535 } 536 537 static int 538 sk_xmac_miibus_readreg(sc_if, phy, reg) 539 struct sk_if_softc *sc_if; 540 int phy, reg; 541 { 542 int i; 543 544 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 545 return(0); 546 547 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 548 SK_XM_READ_2(sc_if, XM_PHY_DATA); 549 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 550 for (i = 0; i < SK_TIMEOUT; i++) { 551 DELAY(1); 552 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 553 XM_MMUCMD_PHYDATARDY) 554 break; 555 } 556 557 if (i == SK_TIMEOUT) { 558 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 559 return(0); 560 } 561 } 562 DELAY(1); 563 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 564 565 return(i); 566 } 567 568 static int 569 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 570 struct sk_if_softc *sc_if; 571 int phy, reg, val; 572 { 573 int i; 574 575 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 576 for (i = 0; i < SK_TIMEOUT; i++) { 577 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 578 break; 579 } 580 581 if (i == SK_TIMEOUT) { 582 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 583 return (ETIMEDOUT); 584 } 585 586 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 587 for (i = 0; i < SK_TIMEOUT; i++) { 588 DELAY(1); 589 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 590 break; 591 } 592 if (i == SK_TIMEOUT) 593 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 594 595 return(0); 596 } 597 598 static void 599 sk_xmac_miibus_statchg(sc_if) 600 struct sk_if_softc *sc_if; 601 { 602 struct mii_data *mii; 603 604 mii = device_get_softc(sc_if->sk_miibus); 605 606 /* 607 * If this is a GMII PHY, manually set the XMAC's 608 * duplex mode accordingly. 609 */ 610 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 611 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 612 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 613 } else { 614 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 615 } 616 } 617 } 618 619 static int 620 sk_marv_miibus_readreg(sc_if, phy, reg) 621 struct sk_if_softc *sc_if; 622 int phy, reg; 623 { 624 u_int16_t val; 625 int i; 626 627 if (phy != 0 || 628 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 629 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 630 return(0); 631 } 632 633 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 634 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 635 636 for (i = 0; i < SK_TIMEOUT; i++) { 637 DELAY(1); 638 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 639 if (val & YU_SMICR_READ_VALID) 640 break; 641 } 642 643 if (i == SK_TIMEOUT) { 644 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 645 return(0); 646 } 647 648 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 649 650 return(val); 651 } 652 653 static int 654 sk_marv_miibus_writereg(sc_if, phy, reg, val) 655 struct sk_if_softc *sc_if; 656 int phy, reg, val; 657 { 658 int i; 659 660 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 661 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 662 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 663 664 for (i = 0; i < SK_TIMEOUT; i++) { 665 DELAY(1); 666 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0) 667 break; 668 } 669 if (i == SK_TIMEOUT) 670 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 671 672 return(0); 673 } 674 675 static void 676 sk_marv_miibus_statchg(sc_if) 677 struct sk_if_softc *sc_if; 678 { 679 return; 680 } 681 682 #define HASH_BITS 6 683 684 static u_int32_t 685 sk_xmchash(addr) 686 const uint8_t *addr; 687 { 688 uint32_t crc; 689 690 /* Compute CRC for the address value. */ 691 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 692 693 return (~crc & ((1 << HASH_BITS) - 1)); 694 } 695 696 /* gmchash is just a big endian crc */ 697 static u_int32_t 698 sk_gmchash(addr) 699 const uint8_t *addr; 700 { 701 uint32_t crc; 702 703 /* Compute CRC for the address value. */ 704 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 705 706 return (crc & ((1 << HASH_BITS) - 1)); 707 } 708 709 static void 710 sk_setfilt(sc_if, addr, slot) 711 struct sk_if_softc *sc_if; 712 u_int16_t *addr; 713 int slot; 714 { 715 int base; 716 717 base = XM_RXFILT_ENTRY(slot); 718 719 SK_XM_WRITE_2(sc_if, base, addr[0]); 720 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 721 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 722 723 return; 724 } 725 726 static void 727 sk_setmulti(sc_if) 728 struct sk_if_softc *sc_if; 729 { 730 struct sk_softc *sc = sc_if->sk_softc; 731 struct ifnet *ifp = sc_if->sk_ifp; 732 u_int32_t hashes[2] = { 0, 0 }; 733 int h = 0, i; 734 struct ifmultiaddr *ifma; 735 u_int16_t dummy[] = { 0, 0, 0 }; 736 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2]; 737 738 SK_IF_LOCK_ASSERT(sc_if); 739 740 /* First, zot all the existing filters. */ 741 switch(sc->sk_type) { 742 case SK_GENESIS: 743 for (i = 1; i < XM_RXFILT_MAX; i++) 744 sk_setfilt(sc_if, dummy, i); 745 746 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 747 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 748 break; 749 case SK_YUKON: 750 case SK_YUKON_LITE: 751 case SK_YUKON_LP: 752 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 753 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 754 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 755 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 756 break; 757 } 758 759 /* Now program new ones. */ 760 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 761 hashes[0] = 0xFFFFFFFF; 762 hashes[1] = 0xFFFFFFFF; 763 } else { 764 i = 1; 765 IF_ADDR_LOCK(ifp); 766 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 767 if (ifma->ifma_addr->sa_family != AF_LINK) 768 continue; 769 /* 770 * Program the first XM_RXFILT_MAX multicast groups 771 * into the perfect filter. For all others, 772 * use the hash table. 773 */ 774 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 775 bcopy(LLADDR( 776 (struct sockaddr_dl *)ifma->ifma_addr), 777 maddr, ETHER_ADDR_LEN); 778 sk_setfilt(sc_if, maddr, i); 779 i++; 780 continue; 781 } 782 783 switch(sc->sk_type) { 784 case SK_GENESIS: 785 bcopy(LLADDR( 786 (struct sockaddr_dl *)ifma->ifma_addr), 787 maddr, ETHER_ADDR_LEN); 788 h = sk_xmchash((const uint8_t *)maddr); 789 break; 790 case SK_YUKON: 791 case SK_YUKON_LITE: 792 case SK_YUKON_LP: 793 bcopy(LLADDR( 794 (struct sockaddr_dl *)ifma->ifma_addr), 795 maddr, ETHER_ADDR_LEN); 796 h = sk_gmchash((const uint8_t *)maddr); 797 break; 798 } 799 if (h < 32) 800 hashes[0] |= (1 << h); 801 else 802 hashes[1] |= (1 << (h - 32)); 803 } 804 IF_ADDR_UNLOCK(ifp); 805 } 806 807 switch(sc->sk_type) { 808 case SK_GENESIS: 809 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 810 XM_MODE_RX_USE_PERFECT); 811 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 812 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 813 break; 814 case SK_YUKON: 815 case SK_YUKON_LITE: 816 case SK_YUKON_LP: 817 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 818 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 819 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 820 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 821 break; 822 } 823 824 return; 825 } 826 827 static void 828 sk_setpromisc(sc_if) 829 struct sk_if_softc *sc_if; 830 { 831 struct sk_softc *sc = sc_if->sk_softc; 832 struct ifnet *ifp = sc_if->sk_ifp; 833 834 SK_IF_LOCK_ASSERT(sc_if); 835 836 switch(sc->sk_type) { 837 case SK_GENESIS: 838 if (ifp->if_flags & IFF_PROMISC) { 839 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 840 } else { 841 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 842 } 843 break; 844 case SK_YUKON: 845 case SK_YUKON_LITE: 846 case SK_YUKON_LP: 847 if (ifp->if_flags & IFF_PROMISC) { 848 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 849 YU_RCR_UFLEN | YU_RCR_MUFLEN); 850 } else { 851 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 852 YU_RCR_UFLEN | YU_RCR_MUFLEN); 853 } 854 break; 855 } 856 857 return; 858 } 859 860 static int 861 sk_init_rx_ring(sc_if) 862 struct sk_if_softc *sc_if; 863 { 864 struct sk_ring_data *rd; 865 bus_addr_t addr; 866 u_int32_t csum_start; 867 int i; 868 869 sc_if->sk_cdata.sk_rx_cons = 0; 870 871 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 872 ETHER_HDR_LEN; 873 rd = &sc_if->sk_rdata; 874 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 875 for (i = 0; i < SK_RX_RING_CNT; i++) { 876 if (sk_newbuf(sc_if, i) != 0) 877 return (ENOBUFS); 878 if (i == (SK_RX_RING_CNT - 1)) 879 addr = SK_RX_RING_ADDR(sc_if, 0); 880 else 881 addr = SK_RX_RING_ADDR(sc_if, i + 1); 882 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 883 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 884 } 885 886 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 887 sc_if->sk_cdata.sk_rx_ring_map, 888 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 889 890 return(0); 891 } 892 893 static int 894 sk_init_jumbo_rx_ring(sc_if) 895 struct sk_if_softc *sc_if; 896 { 897 struct sk_ring_data *rd; 898 bus_addr_t addr; 899 u_int32_t csum_start; 900 int i; 901 902 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 903 904 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 905 ETHER_HDR_LEN; 906 rd = &sc_if->sk_rdata; 907 bzero(rd->sk_jumbo_rx_ring, 908 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 909 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 910 if (sk_jumbo_newbuf(sc_if, i) != 0) 911 return (ENOBUFS); 912 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 913 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 914 else 915 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 916 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 917 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 918 } 919 920 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 921 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 923 924 return (0); 925 } 926 927 static void 928 sk_init_tx_ring(sc_if) 929 struct sk_if_softc *sc_if; 930 { 931 struct sk_ring_data *rd; 932 struct sk_txdesc *txd; 933 bus_addr_t addr; 934 int i; 935 936 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 937 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 938 939 sc_if->sk_cdata.sk_tx_prod = 0; 940 sc_if->sk_cdata.sk_tx_cons = 0; 941 sc_if->sk_cdata.sk_tx_cnt = 0; 942 943 rd = &sc_if->sk_rdata; 944 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 945 for (i = 0; i < SK_TX_RING_CNT; i++) { 946 if (i == (SK_TX_RING_CNT - 1)) 947 addr = SK_TX_RING_ADDR(sc_if, 0); 948 else 949 addr = SK_TX_RING_ADDR(sc_if, i + 1); 950 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 951 txd = &sc_if->sk_cdata.sk_txdesc[i]; 952 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 953 } 954 955 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 956 sc_if->sk_cdata.sk_tx_ring_map, 957 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 958 } 959 960 static __inline void 961 sk_discard_rxbuf(sc_if, idx) 962 struct sk_if_softc *sc_if; 963 int idx; 964 { 965 struct sk_rx_desc *r; 966 struct sk_rxdesc *rxd; 967 struct mbuf *m; 968 969 970 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 971 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 972 m = rxd->rx_m; 973 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 974 } 975 976 static __inline void 977 sk_discard_jumbo_rxbuf(sc_if, idx) 978 struct sk_if_softc *sc_if; 979 int idx; 980 { 981 struct sk_rx_desc *r; 982 struct sk_rxdesc *rxd; 983 struct mbuf *m; 984 985 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 986 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 987 m = rxd->rx_m; 988 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 989 } 990 991 static int 992 sk_newbuf(sc_if, idx) 993 struct sk_if_softc *sc_if; 994 int idx; 995 { 996 struct sk_rx_desc *r; 997 struct sk_rxdesc *rxd; 998 struct mbuf *m; 999 bus_dma_segment_t segs[1]; 1000 bus_dmamap_t map; 1001 int nsegs; 1002 1003 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1004 if (m == NULL) 1005 return (ENOBUFS); 1006 m->m_len = m->m_pkthdr.len = MCLBYTES; 1007 m_adj(m, ETHER_ALIGN); 1008 1009 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 1010 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1011 m_freem(m); 1012 return (ENOBUFS); 1013 } 1014 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1015 1016 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 1017 if (rxd->rx_m != NULL) { 1018 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1019 BUS_DMASYNC_POSTREAD); 1020 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 1021 } 1022 map = rxd->rx_dmamap; 1023 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 1024 sc_if->sk_cdata.sk_rx_sparemap = map; 1025 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1026 BUS_DMASYNC_PREREAD); 1027 rxd->rx_m = m; 1028 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 1029 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1030 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1031 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1032 1033 return (0); 1034 } 1035 1036 static int 1037 sk_jumbo_newbuf(sc_if, idx) 1038 struct sk_if_softc *sc_if; 1039 int idx; 1040 { 1041 struct sk_rx_desc *r; 1042 struct sk_rxdesc *rxd; 1043 struct mbuf *m; 1044 bus_dma_segment_t segs[1]; 1045 bus_dmamap_t map; 1046 int nsegs; 1047 void *buf; 1048 1049 MGETHDR(m, M_DONTWAIT, MT_DATA); 1050 if (m == NULL) 1051 return (ENOBUFS); 1052 buf = sk_jalloc(sc_if); 1053 if (buf == NULL) { 1054 m_freem(m); 1055 return (ENOBUFS); 1056 } 1057 /* Attach the buffer to the mbuf */ 1058 MEXTADD(m, buf, SK_JLEN, sk_jfree, (struct sk_if_softc *)sc_if, 0, 1059 EXT_NET_DRV); 1060 if ((m->m_flags & M_EXT) == 0) { 1061 m_freem(m); 1062 return (ENOBUFS); 1063 } 1064 m->m_pkthdr.len = m->m_len = SK_JLEN; 1065 /* 1066 * Adjust alignment so packet payload begins on a 1067 * longword boundary. Mandatory for Alpha, useful on 1068 * x86 too. 1069 */ 1070 m_adj(m, ETHER_ALIGN); 1071 1072 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 1073 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1074 m_freem(m); 1075 return (ENOBUFS); 1076 } 1077 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1078 1079 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1080 if (rxd->rx_m != NULL) { 1081 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1082 BUS_DMASYNC_POSTREAD); 1083 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 1084 rxd->rx_dmamap); 1085 } 1086 map = rxd->rx_dmamap; 1087 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 1088 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 1089 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1090 BUS_DMASYNC_PREREAD); 1091 rxd->rx_m = m; 1092 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1093 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1094 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1095 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1096 1097 return (0); 1098 } 1099 1100 /* 1101 * Set media options. 1102 */ 1103 static int 1104 sk_ifmedia_upd(ifp) 1105 struct ifnet *ifp; 1106 { 1107 struct sk_if_softc *sc_if = ifp->if_softc; 1108 struct mii_data *mii; 1109 1110 mii = device_get_softc(sc_if->sk_miibus); 1111 sk_init(sc_if); 1112 mii_mediachg(mii); 1113 1114 return(0); 1115 } 1116 1117 /* 1118 * Report current media status. 1119 */ 1120 static void 1121 sk_ifmedia_sts(ifp, ifmr) 1122 struct ifnet *ifp; 1123 struct ifmediareq *ifmr; 1124 { 1125 struct sk_if_softc *sc_if; 1126 struct mii_data *mii; 1127 1128 sc_if = ifp->if_softc; 1129 mii = device_get_softc(sc_if->sk_miibus); 1130 1131 mii_pollstat(mii); 1132 ifmr->ifm_active = mii->mii_media_active; 1133 ifmr->ifm_status = mii->mii_media_status; 1134 1135 return; 1136 } 1137 1138 static int 1139 sk_ioctl(ifp, command, data) 1140 struct ifnet *ifp; 1141 u_long command; 1142 caddr_t data; 1143 { 1144 struct sk_if_softc *sc_if = ifp->if_softc; 1145 struct ifreq *ifr = (struct ifreq *) data; 1146 int error, mask; 1147 struct mii_data *mii; 1148 1149 error = 0; 1150 switch(command) { 1151 case SIOCSIFMTU: 1152 SK_IF_LOCK(sc_if); 1153 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1154 error = EINVAL; 1155 else { 1156 ifp->if_mtu = ifr->ifr_mtu; 1157 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1158 sk_init_locked(sc_if); 1159 } 1160 SK_IF_UNLOCK(sc_if); 1161 break; 1162 case SIOCSIFFLAGS: 1163 SK_IF_LOCK(sc_if); 1164 if (ifp->if_flags & IFF_UP) { 1165 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1166 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1167 & IFF_PROMISC) { 1168 sk_setpromisc(sc_if); 1169 sk_setmulti(sc_if); 1170 } 1171 } else 1172 sk_init_locked(sc_if); 1173 } else { 1174 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1175 sk_stop(sc_if); 1176 } 1177 sc_if->sk_if_flags = ifp->if_flags; 1178 SK_IF_UNLOCK(sc_if); 1179 break; 1180 case SIOCADDMULTI: 1181 case SIOCDELMULTI: 1182 SK_IF_LOCK(sc_if); 1183 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1184 sk_setmulti(sc_if); 1185 SK_IF_UNLOCK(sc_if); 1186 break; 1187 case SIOCGIFMEDIA: 1188 case SIOCSIFMEDIA: 1189 mii = device_get_softc(sc_if->sk_miibus); 1190 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1191 break; 1192 case SIOCSIFCAP: 1193 SK_IF_LOCK(sc_if); 1194 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1195 SK_IF_UNLOCK(sc_if); 1196 break; 1197 } 1198 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1199 if (mask & IFCAP_HWCSUM) { 1200 ifp->if_capenable ^= IFCAP_HWCSUM; 1201 if (IFCAP_HWCSUM & ifp->if_capenable && 1202 IFCAP_HWCSUM & ifp->if_capabilities) 1203 ifp->if_hwassist = SK_CSUM_FEATURES; 1204 else 1205 ifp->if_hwassist = 0; 1206 } 1207 SK_IF_UNLOCK(sc_if); 1208 break; 1209 default: 1210 error = ether_ioctl(ifp, command, data); 1211 break; 1212 } 1213 1214 return (error); 1215 } 1216 1217 /* 1218 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1219 * IDs against our list and return a device name if we find a match. 1220 */ 1221 static int 1222 skc_probe(dev) 1223 device_t dev; 1224 { 1225 struct sk_type *t = sk_devs; 1226 1227 while(t->sk_name != NULL) { 1228 if ((pci_get_vendor(dev) == t->sk_vid) && 1229 (pci_get_device(dev) == t->sk_did)) { 1230 /* 1231 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1232 * Rev. 3 is supported by re(4). 1233 */ 1234 if ((t->sk_vid == VENDORID_LINKSYS) && 1235 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1236 (pci_get_subdevice(dev) != 1237 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1238 t++; 1239 continue; 1240 } 1241 device_set_desc(dev, t->sk_name); 1242 return (BUS_PROBE_DEFAULT); 1243 } 1244 t++; 1245 } 1246 1247 return(ENXIO); 1248 } 1249 1250 /* 1251 * Force the GEnesis into reset, then bring it out of reset. 1252 */ 1253 static void 1254 sk_reset(sc) 1255 struct sk_softc *sc; 1256 { 1257 1258 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1259 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1260 if (SK_YUKON_FAMILY(sc->sk_type)) 1261 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1262 1263 DELAY(1000); 1264 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1265 DELAY(2); 1266 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1267 if (SK_YUKON_FAMILY(sc->sk_type)) 1268 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1269 1270 if (sc->sk_type == SK_GENESIS) { 1271 /* Configure packet arbiter */ 1272 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1273 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1274 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1275 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1276 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1277 } 1278 1279 /* Enable RAM interface */ 1280 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1281 1282 /* 1283 * Configure interrupt moderation. The moderation timer 1284 * defers interrupts specified in the interrupt moderation 1285 * timer mask based on the timeout specified in the interrupt 1286 * moderation timer init register. Each bit in the timer 1287 * register represents one tick, so to specify a timeout in 1288 * microseconds, we have to multiply by the correct number of 1289 * ticks-per-microsecond. 1290 */ 1291 switch (sc->sk_type) { 1292 case SK_GENESIS: 1293 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1294 break; 1295 default: 1296 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1297 break; 1298 } 1299 if (bootverbose) 1300 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1301 sc->sk_int_mod); 1302 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1303 sc->sk_int_ticks)); 1304 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1305 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1306 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1307 1308 return; 1309 } 1310 1311 static int 1312 sk_probe(dev) 1313 device_t dev; 1314 { 1315 struct sk_softc *sc; 1316 1317 sc = device_get_softc(device_get_parent(dev)); 1318 1319 /* 1320 * Not much to do here. We always know there will be 1321 * at least one XMAC present, and if there are two, 1322 * skc_attach() will create a second device instance 1323 * for us. 1324 */ 1325 switch (sc->sk_type) { 1326 case SK_GENESIS: 1327 device_set_desc(dev, "XaQti Corp. XMAC II"); 1328 break; 1329 case SK_YUKON: 1330 case SK_YUKON_LITE: 1331 case SK_YUKON_LP: 1332 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1333 break; 1334 } 1335 1336 return (BUS_PROBE_DEFAULT); 1337 } 1338 1339 /* 1340 * Each XMAC chip is attached as a separate logical IP interface. 1341 * Single port cards will have only one logical interface of course. 1342 */ 1343 static int 1344 sk_attach(dev) 1345 device_t dev; 1346 { 1347 struct sk_softc *sc; 1348 struct sk_if_softc *sc_if; 1349 struct ifnet *ifp; 1350 int i, port, error; 1351 u_char eaddr[6]; 1352 1353 if (dev == NULL) 1354 return(EINVAL); 1355 1356 error = 0; 1357 sc_if = device_get_softc(dev); 1358 sc = device_get_softc(device_get_parent(dev)); 1359 port = *(int *)device_get_ivars(dev); 1360 1361 sc_if->sk_if_dev = dev; 1362 sc_if->sk_port = port; 1363 sc_if->sk_softc = sc; 1364 sc->sk_if[port] = sc_if; 1365 if (port == SK_PORT_A) 1366 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1367 if (port == SK_PORT_B) 1368 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1369 1370 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1371 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0); 1372 1373 if (sk_dma_alloc(sc_if) != 0) { 1374 error = ENOMEM; 1375 goto fail; 1376 } 1377 1378 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1379 if (ifp == NULL) { 1380 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1381 error = ENOSPC; 1382 goto fail; 1383 } 1384 ifp->if_softc = sc_if; 1385 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1386 ifp->if_mtu = ETHERMTU; 1387 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1388 /* 1389 * SK_GENESIS has a bug in checksum offload - From linux. 1390 */ 1391 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1392 ifp->if_capabilities = IFCAP_HWCSUM; 1393 ifp->if_hwassist = SK_CSUM_FEATURES; 1394 } else { 1395 ifp->if_capabilities = 0; 1396 ifp->if_hwassist = 0; 1397 } 1398 ifp->if_capenable = ifp->if_capabilities; 1399 ifp->if_ioctl = sk_ioctl; 1400 ifp->if_start = sk_start; 1401 ifp->if_timer = 0; 1402 ifp->if_watchdog = NULL; 1403 ifp->if_init = sk_init; 1404 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1405 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1406 IFQ_SET_READY(&ifp->if_snd); 1407 1408 /* 1409 * Get station address for this interface. Note that 1410 * dual port cards actually come with three station 1411 * addresses: one for each port, plus an extra. The 1412 * extra one is used by the SysKonnect driver software 1413 * as a 'virtual' station address for when both ports 1414 * are operating in failover mode. Currently we don't 1415 * use this extra address. 1416 */ 1417 SK_IF_LOCK(sc_if); 1418 for (i = 0; i < ETHER_ADDR_LEN; i++) 1419 eaddr[i] = 1420 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1421 1422 /* 1423 * Set up RAM buffer addresses. The NIC will have a certain 1424 * amount of SRAM on it, somewhere between 512K and 2MB. We 1425 * need to divide this up a) between the transmitter and 1426 * receiver and b) between the two XMACs, if this is a 1427 * dual port NIC. Our algotithm is to divide up the memory 1428 * evenly so that everyone gets a fair share. 1429 * 1430 * Just to be contrary, Yukon2 appears to have separate memory 1431 * for each MAC. 1432 */ 1433 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1434 u_int32_t chunk, val; 1435 1436 chunk = sc->sk_ramsize / 2; 1437 val = sc->sk_rboff / sizeof(u_int64_t); 1438 sc_if->sk_rx_ramstart = val; 1439 val += (chunk / sizeof(u_int64_t)); 1440 sc_if->sk_rx_ramend = val - 1; 1441 sc_if->sk_tx_ramstart = val; 1442 val += (chunk / sizeof(u_int64_t)); 1443 sc_if->sk_tx_ramend = val - 1; 1444 } else { 1445 u_int32_t chunk, val; 1446 1447 chunk = sc->sk_ramsize / 4; 1448 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1449 sizeof(u_int64_t); 1450 sc_if->sk_rx_ramstart = val; 1451 val += (chunk / sizeof(u_int64_t)); 1452 sc_if->sk_rx_ramend = val - 1; 1453 sc_if->sk_tx_ramstart = val; 1454 val += (chunk / sizeof(u_int64_t)); 1455 sc_if->sk_tx_ramend = val - 1; 1456 } 1457 1458 /* Read and save PHY type and set PHY address */ 1459 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1460 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1461 switch(sc_if->sk_phytype) { 1462 case SK_PHYTYPE_XMAC: 1463 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1464 break; 1465 case SK_PHYTYPE_BCOM: 1466 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1467 break; 1468 default: 1469 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1470 sc_if->sk_phytype); 1471 error = ENODEV; 1472 SK_IF_UNLOCK(sc_if); 1473 goto fail; 1474 } 1475 } else { 1476 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1477 sc->sk_pmd != 'S') { 1478 /* not initialized, punt */ 1479 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1480 sc->sk_coppertype = 1; 1481 } 1482 1483 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1484 1485 if (!(sc->sk_coppertype)) 1486 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1487 } 1488 1489 /* 1490 * Call MI attach routine. Can't hold locks when calling into ether_*. 1491 */ 1492 SK_IF_UNLOCK(sc_if); 1493 ether_ifattach(ifp, eaddr); 1494 SK_IF_LOCK(sc_if); 1495 1496 /* 1497 * The hardware should be ready for VLAN_MTU by default: 1498 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1499 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1500 * 1501 */ 1502 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1503 ifp->if_capenable |= IFCAP_VLAN_MTU; 1504 /* 1505 * Tell the upper layer(s) we support long frames. 1506 * Must appear after the call to ether_ifattach() because 1507 * ether_ifattach() sets ifi_hdrlen to the default value. 1508 */ 1509 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1510 1511 /* 1512 * Do miibus setup. 1513 */ 1514 switch (sc->sk_type) { 1515 case SK_GENESIS: 1516 sk_init_xmac(sc_if); 1517 break; 1518 case SK_YUKON: 1519 case SK_YUKON_LITE: 1520 case SK_YUKON_LP: 1521 sk_init_yukon(sc_if); 1522 break; 1523 } 1524 1525 SK_IF_UNLOCK(sc_if); 1526 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1527 sk_ifmedia_upd, sk_ifmedia_sts)) { 1528 device_printf(sc_if->sk_if_dev, "no PHY found!\n"); 1529 ether_ifdetach(ifp); 1530 error = ENXIO; 1531 goto fail; 1532 } 1533 1534 fail: 1535 if (error) { 1536 /* Access should be ok even though lock has been dropped */ 1537 sc->sk_if[port] = NULL; 1538 sk_detach(dev); 1539 } 1540 1541 return(error); 1542 } 1543 1544 /* 1545 * Attach the interface. Allocate softc structures, do ifmedia 1546 * setup and ethernet/BPF attach. 1547 */ 1548 static int 1549 skc_attach(dev) 1550 device_t dev; 1551 { 1552 struct sk_softc *sc; 1553 int error = 0, *port; 1554 uint8_t skrs; 1555 const char *pname; 1556 char *revstr; 1557 1558 sc = device_get_softc(dev); 1559 sc->sk_dev = dev; 1560 1561 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1562 MTX_DEF); 1563 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1564 /* 1565 * Map control/status registers. 1566 */ 1567 pci_enable_busmaster(dev); 1568 1569 /* Allocate resources */ 1570 #ifdef SK_USEIOSPACE 1571 sc->sk_res_spec = sk_res_spec_io; 1572 #else 1573 sc->sk_res_spec = sk_res_spec_mem; 1574 #endif 1575 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1576 if (error) { 1577 if (sc->sk_res_spec == sk_res_spec_mem) 1578 sc->sk_res_spec = sk_res_spec_io; 1579 else 1580 sc->sk_res_spec = sk_res_spec_mem; 1581 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1582 if (error) { 1583 device_printf(dev, "couldn't allocate %s resources\n", 1584 sc->sk_res_spec == sk_res_spec_mem ? "memory" : 1585 "I/O"); 1586 goto fail; 1587 } 1588 } 1589 1590 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1591 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1592 1593 /* Bail out if chip is not recognized. */ 1594 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1595 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1596 sc->sk_type, sc->sk_rev); 1597 error = ENXIO; 1598 goto fail; 1599 } 1600 1601 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1602 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1603 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW, 1604 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1605 "SK interrupt moderation"); 1606 1607 /* Pull in device tunables. */ 1608 sc->sk_int_mod = SK_IM_DEFAULT; 1609 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1610 "int_mod", &sc->sk_int_mod); 1611 if (error == 0) { 1612 if (sc->sk_int_mod < SK_IM_MIN || 1613 sc->sk_int_mod > SK_IM_MAX) { 1614 device_printf(dev, "int_mod value out of range; " 1615 "using default: %d\n", SK_IM_DEFAULT); 1616 sc->sk_int_mod = SK_IM_DEFAULT; 1617 } 1618 } 1619 1620 /* Reset the adapter. */ 1621 sk_reset(sc); 1622 1623 skrs = sk_win_read_1(sc, SK_EPROM0); 1624 if (sc->sk_type == SK_GENESIS) { 1625 /* Read and save RAM size and RAMbuffer offset */ 1626 switch(skrs) { 1627 case SK_RAMSIZE_512K_64: 1628 sc->sk_ramsize = 0x80000; 1629 sc->sk_rboff = SK_RBOFF_0; 1630 break; 1631 case SK_RAMSIZE_1024K_64: 1632 sc->sk_ramsize = 0x100000; 1633 sc->sk_rboff = SK_RBOFF_80000; 1634 break; 1635 case SK_RAMSIZE_1024K_128: 1636 sc->sk_ramsize = 0x100000; 1637 sc->sk_rboff = SK_RBOFF_0; 1638 break; 1639 case SK_RAMSIZE_2048K_128: 1640 sc->sk_ramsize = 0x200000; 1641 sc->sk_rboff = SK_RBOFF_0; 1642 break; 1643 default: 1644 device_printf(dev, "unknown ram size: %d\n", skrs); 1645 error = ENXIO; 1646 goto fail; 1647 } 1648 } else { /* SK_YUKON_FAMILY */ 1649 if (skrs == 0x00) 1650 sc->sk_ramsize = 0x20000; 1651 else 1652 sc->sk_ramsize = skrs * (1<<12); 1653 sc->sk_rboff = SK_RBOFF_0; 1654 } 1655 1656 /* Read and save physical media type */ 1657 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1658 1659 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1660 sc->sk_coppertype = 1; 1661 else 1662 sc->sk_coppertype = 0; 1663 1664 /* Determine whether to name it with VPD PN or just make it up. 1665 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1666 switch (pci_get_device(dev)) { 1667 case DEVICEID_SK_V1: 1668 case DEVICEID_BELKIN_5005: 1669 case DEVICEID_3COM_3C940: 1670 case DEVICEID_LINKSYS_EG1032: 1671 case DEVICEID_DLINK_DGE530T_A1: 1672 case DEVICEID_DLINK_DGE530T_B1: 1673 /* Stay with VPD PN. */ 1674 if (pci_get_vpd_ident(dev, &pname)) 1675 goto vpdfailed; 1676 break; 1677 case DEVICEID_SK_V2: 1678 /* YUKON VPD PN might bear no resemblance to reality. */ 1679 switch (sc->sk_type) { 1680 case SK_GENESIS: 1681 /* Stay with VPD PN. */ 1682 if (pci_get_vpd_ident(dev, &pname)) 1683 goto vpdfailed; 1684 break; 1685 case SK_YUKON: 1686 pname = "Marvell Yukon Gigabit Ethernet"; 1687 break; 1688 case SK_YUKON_LITE: 1689 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1690 break; 1691 case SK_YUKON_LP: 1692 pname = "Marvell Yukon LP Gigabit Ethernet"; 1693 break; 1694 default: 1695 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1696 break; 1697 } 1698 1699 /* Yukon Lite Rev. A0 needs special test. */ 1700 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1701 u_int32_t far; 1702 u_int8_t testbyte; 1703 1704 /* Save flash address register before testing. */ 1705 far = sk_win_read_4(sc, SK_EP_ADDR); 1706 1707 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1708 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1709 1710 if (testbyte != 0x00) { 1711 /* Yukon Lite Rev. A0 detected. */ 1712 sc->sk_type = SK_YUKON_LITE; 1713 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1714 /* Restore flash address register. */ 1715 sk_win_write_4(sc, SK_EP_ADDR, far); 1716 } 1717 } 1718 break; 1719 default: 1720 vpdfailed: 1721 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1722 "chipver=%02x, rev=%x\n", 1723 pci_get_vendor(dev), pci_get_device(dev), 1724 sc->sk_type, sc->sk_rev); 1725 error = ENXIO; 1726 goto fail; 1727 } 1728 1729 if (sc->sk_type == SK_YUKON_LITE) { 1730 switch (sc->sk_rev) { 1731 case SK_YUKON_LITE_REV_A0: 1732 revstr = "A0"; 1733 break; 1734 case SK_YUKON_LITE_REV_A1: 1735 revstr = "A1"; 1736 break; 1737 case SK_YUKON_LITE_REV_A3: 1738 revstr = "A3"; 1739 break; 1740 default: 1741 revstr = ""; 1742 break; 1743 } 1744 } else { 1745 revstr = ""; 1746 } 1747 1748 /* Announce the product name and more VPD data if there. */ 1749 device_printf(dev, "%s rev. %s(0x%x)\n", 1750 pname != NULL ? pname : "<unknown>", revstr, sc->sk_rev); 1751 1752 if (bootverbose) { 1753 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1754 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1755 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1756 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1757 } 1758 1759 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1760 if (sc->sk_devs[SK_PORT_A] == NULL) { 1761 device_printf(dev, "failed to add child for PORT_A\n"); 1762 error = ENXIO; 1763 goto fail; 1764 } 1765 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1766 if (port == NULL) { 1767 device_printf(dev, "failed to allocate memory for " 1768 "ivars of PORT_A\n"); 1769 error = ENXIO; 1770 goto fail; 1771 } 1772 *port = SK_PORT_A; 1773 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1774 1775 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1776 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1777 if (sc->sk_devs[SK_PORT_B] == NULL) { 1778 device_printf(dev, "failed to add child for PORT_B\n"); 1779 error = ENXIO; 1780 goto fail; 1781 } 1782 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1783 if (port == NULL) { 1784 device_printf(dev, "failed to allocate memory for " 1785 "ivars of PORT_B\n"); 1786 error = ENXIO; 1787 goto fail; 1788 } 1789 *port = SK_PORT_B; 1790 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1791 } 1792 1793 /* Turn on the 'driver is loaded' LED. */ 1794 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1795 1796 error = bus_generic_attach(dev); 1797 if (error) { 1798 device_printf(dev, "failed to attach port(s)\n"); 1799 goto fail; 1800 } 1801 1802 /* Hook interrupt last to avoid having to lock softc */ 1803 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE, 1804 NULL, sk_intr, sc, &sc->sk_intrhand); 1805 1806 if (error) { 1807 device_printf(dev, "couldn't set up irq\n"); 1808 goto fail; 1809 } 1810 1811 fail: 1812 if (error) 1813 skc_detach(dev); 1814 1815 return(error); 1816 } 1817 1818 /* 1819 * Shutdown hardware and free up resources. This can be called any 1820 * time after the mutex has been initialized. It is called in both 1821 * the error case in attach and the normal detach case so it needs 1822 * to be careful about only freeing resources that have actually been 1823 * allocated. 1824 */ 1825 static int 1826 sk_detach(dev) 1827 device_t dev; 1828 { 1829 struct sk_if_softc *sc_if; 1830 struct ifnet *ifp; 1831 1832 sc_if = device_get_softc(dev); 1833 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1834 ("sk mutex not initialized in sk_detach")); 1835 SK_IF_LOCK(sc_if); 1836 1837 ifp = sc_if->sk_ifp; 1838 /* These should only be active if attach_xmac succeeded */ 1839 if (device_is_attached(dev)) { 1840 sk_stop(sc_if); 1841 /* Can't hold locks while calling detach */ 1842 SK_IF_UNLOCK(sc_if); 1843 callout_drain(&sc_if->sk_tick_ch); 1844 callout_drain(&sc_if->sk_watchdog_ch); 1845 ether_ifdetach(ifp); 1846 SK_IF_LOCK(sc_if); 1847 } 1848 if (ifp) 1849 if_free(ifp); 1850 /* 1851 * We're generally called from skc_detach() which is using 1852 * device_delete_child() to get to here. It's already trashed 1853 * miibus for us, so don't do it here or we'll panic. 1854 */ 1855 /* 1856 if (sc_if->sk_miibus != NULL) 1857 device_delete_child(dev, sc_if->sk_miibus); 1858 */ 1859 bus_generic_detach(dev); 1860 sk_dma_free(sc_if); 1861 SK_IF_UNLOCK(sc_if); 1862 1863 return(0); 1864 } 1865 1866 static int 1867 skc_detach(dev) 1868 device_t dev; 1869 { 1870 struct sk_softc *sc; 1871 1872 sc = device_get_softc(dev); 1873 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1874 1875 if (device_is_alive(dev)) { 1876 if (sc->sk_devs[SK_PORT_A] != NULL) { 1877 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 1878 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1879 } 1880 if (sc->sk_devs[SK_PORT_B] != NULL) { 1881 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 1882 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1883 } 1884 bus_generic_detach(dev); 1885 } 1886 1887 if (sc->sk_intrhand) 1888 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand); 1889 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res); 1890 1891 mtx_destroy(&sc->sk_mii_mtx); 1892 mtx_destroy(&sc->sk_mtx); 1893 1894 return(0); 1895 } 1896 1897 struct sk_dmamap_arg { 1898 bus_addr_t sk_busaddr; 1899 }; 1900 1901 static void 1902 sk_dmamap_cb(arg, segs, nseg, error) 1903 void *arg; 1904 bus_dma_segment_t *segs; 1905 int nseg; 1906 int error; 1907 { 1908 struct sk_dmamap_arg *ctx; 1909 1910 if (error != 0) 1911 return; 1912 1913 ctx = arg; 1914 ctx->sk_busaddr = segs[0].ds_addr; 1915 } 1916 1917 /* 1918 * Allocate jumbo buffer storage. The SysKonnect adapters support 1919 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1920 * use them in their drivers. In order for us to use them, we need 1921 * large 9K receive buffers, however standard mbuf clusters are only 1922 * 2048 bytes in size. Consequently, we need to allocate and manage 1923 * our own jumbo buffer pool. Fortunately, this does not require an 1924 * excessive amount of additional code. 1925 */ 1926 static int 1927 sk_dma_alloc(sc_if) 1928 struct sk_if_softc *sc_if; 1929 { 1930 struct sk_dmamap_arg ctx; 1931 struct sk_txdesc *txd; 1932 struct sk_rxdesc *rxd; 1933 struct sk_rxdesc *jrxd; 1934 u_int8_t *ptr; 1935 struct sk_jpool_entry *entry; 1936 int error, i; 1937 1938 mtx_init(&sc_if->sk_jlist_mtx, "sk_jlist_mtx", NULL, MTX_DEF); 1939 SLIST_INIT(&sc_if->sk_jfree_listhead); 1940 SLIST_INIT(&sc_if->sk_jinuse_listhead); 1941 1942 /* create parent tag */ 1943 /* 1944 * XXX 1945 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 1946 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 1947 * However bz@ reported that it does not work on amd64 with > 4GB 1948 * RAM. Until we have more clues of the breakage, disable DAC mode 1949 * by limiting DMA address to be in 32bit address space. 1950 */ 1951 error = bus_dma_tag_create( 1952 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */ 1953 1, 0, /* algnmnt, boundary */ 1954 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1955 BUS_SPACE_MAXADDR, /* highaddr */ 1956 NULL, NULL, /* filter, filterarg */ 1957 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1958 0, /* nsegments */ 1959 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1960 0, /* flags */ 1961 NULL, NULL, /* lockfunc, lockarg */ 1962 &sc_if->sk_cdata.sk_parent_tag); 1963 if (error != 0) { 1964 device_printf(sc_if->sk_if_dev, 1965 "failed to create parent DMA tag\n"); 1966 goto fail; 1967 } 1968 /* create tag for Tx ring */ 1969 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1970 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1971 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1972 BUS_SPACE_MAXADDR, /* highaddr */ 1973 NULL, NULL, /* filter, filterarg */ 1974 SK_TX_RING_SZ, /* maxsize */ 1975 1, /* nsegments */ 1976 SK_TX_RING_SZ, /* maxsegsize */ 1977 0, /* flags */ 1978 NULL, NULL, /* lockfunc, lockarg */ 1979 &sc_if->sk_cdata.sk_tx_ring_tag); 1980 if (error != 0) { 1981 device_printf(sc_if->sk_if_dev, 1982 "failed to allocate Tx ring DMA tag\n"); 1983 goto fail; 1984 } 1985 1986 /* create tag for Rx ring */ 1987 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1988 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1989 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1990 BUS_SPACE_MAXADDR, /* highaddr */ 1991 NULL, NULL, /* filter, filterarg */ 1992 SK_RX_RING_SZ, /* maxsize */ 1993 1, /* nsegments */ 1994 SK_RX_RING_SZ, /* maxsegsize */ 1995 0, /* flags */ 1996 NULL, NULL, /* lockfunc, lockarg */ 1997 &sc_if->sk_cdata.sk_rx_ring_tag); 1998 if (error != 0) { 1999 device_printf(sc_if->sk_if_dev, 2000 "failed to allocate Rx ring DMA tag\n"); 2001 goto fail; 2002 } 2003 2004 /* create tag for jumbo Rx ring */ 2005 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2006 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2007 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2008 BUS_SPACE_MAXADDR, /* highaddr */ 2009 NULL, NULL, /* filter, filterarg */ 2010 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2011 1, /* nsegments */ 2012 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2013 0, /* flags */ 2014 NULL, NULL, /* lockfunc, lockarg */ 2015 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2016 if (error != 0) { 2017 device_printf(sc_if->sk_if_dev, 2018 "failed to allocate jumbo Rx ring DMA tag\n"); 2019 goto fail; 2020 } 2021 2022 /* create tag for jumbo buffer blocks */ 2023 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2024 PAGE_SIZE, 0, /* algnmnt, boundary */ 2025 BUS_SPACE_MAXADDR, /* lowaddr */ 2026 BUS_SPACE_MAXADDR, /* highaddr */ 2027 NULL, NULL, /* filter, filterarg */ 2028 SK_JMEM, /* maxsize */ 2029 1, /* nsegments */ 2030 SK_JMEM, /* maxsegsize */ 2031 0, /* flags */ 2032 NULL, NULL, /* lockfunc, lockarg */ 2033 &sc_if->sk_cdata.sk_jumbo_tag); 2034 if (error != 0) { 2035 device_printf(sc_if->sk_if_dev, 2036 "failed to allocate jumbo Rx buffer block DMA tag\n"); 2037 goto fail; 2038 } 2039 2040 /* create tag for Tx buffers */ 2041 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2042 1, 0, /* algnmnt, boundary */ 2043 BUS_SPACE_MAXADDR, /* lowaddr */ 2044 BUS_SPACE_MAXADDR, /* highaddr */ 2045 NULL, NULL, /* filter, filterarg */ 2046 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 2047 SK_MAXTXSEGS, /* nsegments */ 2048 MCLBYTES, /* maxsegsize */ 2049 0, /* flags */ 2050 NULL, NULL, /* lockfunc, lockarg */ 2051 &sc_if->sk_cdata.sk_tx_tag); 2052 if (error != 0) { 2053 device_printf(sc_if->sk_if_dev, 2054 "failed to allocate Tx DMA tag\n"); 2055 goto fail; 2056 } 2057 2058 /* create tag for Rx buffers */ 2059 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2060 1, 0, /* algnmnt, boundary */ 2061 BUS_SPACE_MAXADDR, /* lowaddr */ 2062 BUS_SPACE_MAXADDR, /* highaddr */ 2063 NULL, NULL, /* filter, filterarg */ 2064 MCLBYTES, /* maxsize */ 2065 1, /* nsegments */ 2066 MCLBYTES, /* maxsegsize */ 2067 0, /* flags */ 2068 NULL, NULL, /* lockfunc, lockarg */ 2069 &sc_if->sk_cdata.sk_rx_tag); 2070 if (error != 0) { 2071 device_printf(sc_if->sk_if_dev, 2072 "failed to allocate Rx DMA tag\n"); 2073 goto fail; 2074 } 2075 2076 /* create tag for jumbo Rx buffers */ 2077 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2078 PAGE_SIZE, 0, /* algnmnt, boundary */ 2079 BUS_SPACE_MAXADDR, /* lowaddr */ 2080 BUS_SPACE_MAXADDR, /* highaddr */ 2081 NULL, NULL, /* filter, filterarg */ 2082 MCLBYTES * SK_MAXRXSEGS, /* maxsize */ 2083 SK_MAXRXSEGS, /* nsegments */ 2084 SK_JLEN, /* maxsegsize */ 2085 0, /* flags */ 2086 NULL, NULL, /* lockfunc, lockarg */ 2087 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2088 if (error != 0) { 2089 device_printf(sc_if->sk_if_dev, 2090 "failed to allocate jumbo Rx DMA tag\n"); 2091 goto fail; 2092 } 2093 2094 /* allocate DMA'able memory and load the DMA map for Tx ring */ 2095 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 2096 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2097 &sc_if->sk_cdata.sk_tx_ring_map); 2098 if (error != 0) { 2099 device_printf(sc_if->sk_if_dev, 2100 "failed to allocate DMA'able memory for Tx ring\n"); 2101 goto fail; 2102 } 2103 2104 ctx.sk_busaddr = 0; 2105 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 2106 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 2107 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2108 if (error != 0) { 2109 device_printf(sc_if->sk_if_dev, 2110 "failed to load DMA'able memory for Tx ring\n"); 2111 goto fail; 2112 } 2113 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 2114 2115 /* allocate DMA'able memory and load the DMA map for Rx ring */ 2116 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 2117 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2118 &sc_if->sk_cdata.sk_rx_ring_map); 2119 if (error != 0) { 2120 device_printf(sc_if->sk_if_dev, 2121 "failed to allocate DMA'able memory for Rx ring\n"); 2122 goto fail; 2123 } 2124 2125 ctx.sk_busaddr = 0; 2126 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 2127 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 2128 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2129 if (error != 0) { 2130 device_printf(sc_if->sk_if_dev, 2131 "failed to load DMA'able memory for Rx ring\n"); 2132 goto fail; 2133 } 2134 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2135 2136 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2137 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2138 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, 2139 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2140 if (error != 0) { 2141 device_printf(sc_if->sk_if_dev, 2142 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2143 goto fail; 2144 } 2145 2146 ctx.sk_busaddr = 0; 2147 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2148 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2149 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2150 &ctx, BUS_DMA_NOWAIT); 2151 if (error != 0) { 2152 device_printf(sc_if->sk_if_dev, 2153 "failed to load DMA'able memory for jumbo Rx ring\n"); 2154 goto fail; 2155 } 2156 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2157 2158 /* create DMA maps for Tx buffers */ 2159 for (i = 0; i < SK_TX_RING_CNT; i++) { 2160 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2161 txd->tx_m = NULL; 2162 txd->tx_dmamap = 0; 2163 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2164 &txd->tx_dmamap); 2165 if (error != 0) { 2166 device_printf(sc_if->sk_if_dev, 2167 "failed to create Tx dmamap\n"); 2168 goto fail; 2169 } 2170 } 2171 /* create DMA maps for Rx buffers */ 2172 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2173 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2174 device_printf(sc_if->sk_if_dev, 2175 "failed to create spare Rx dmamap\n"); 2176 goto fail; 2177 } 2178 for (i = 0; i < SK_RX_RING_CNT; i++) { 2179 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2180 rxd->rx_m = NULL; 2181 rxd->rx_dmamap = 0; 2182 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2183 &rxd->rx_dmamap); 2184 if (error != 0) { 2185 device_printf(sc_if->sk_if_dev, 2186 "failed to create Rx dmamap\n"); 2187 goto fail; 2188 } 2189 } 2190 /* create DMA maps for jumbo Rx buffers */ 2191 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2192 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2193 device_printf(sc_if->sk_if_dev, 2194 "failed to create spare jumbo Rx dmamap\n"); 2195 goto fail; 2196 } 2197 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2198 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2199 jrxd->rx_m = NULL; 2200 jrxd->rx_dmamap = 0; 2201 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2202 &jrxd->rx_dmamap); 2203 if (error != 0) { 2204 device_printf(sc_if->sk_if_dev, 2205 "failed to create jumbo Rx dmamap\n"); 2206 goto fail; 2207 } 2208 } 2209 2210 /* allocate DMA'able memory and load the DMA map for jumbo buf */ 2211 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_tag, 2212 (void **)&sc_if->sk_rdata.sk_jumbo_buf, 2213 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_map); 2214 if (error != 0) { 2215 device_printf(sc_if->sk_if_dev, 2216 "failed to allocate DMA'able memory for jumbo buf\n"); 2217 goto fail; 2218 } 2219 2220 ctx.sk_busaddr = 0; 2221 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_tag, 2222 sc_if->sk_cdata.sk_jumbo_map, 2223 sc_if->sk_rdata.sk_jumbo_buf, SK_JMEM, sk_dmamap_cb, 2224 &ctx, BUS_DMA_NOWAIT); 2225 if (error != 0) { 2226 device_printf(sc_if->sk_if_dev, 2227 "failed to load DMA'able memory for jumbobuf\n"); 2228 goto fail; 2229 } 2230 sc_if->sk_rdata.sk_jumbo_buf_paddr = ctx.sk_busaddr; 2231 2232 /* 2233 * Now divide it up into 9K pieces and save the addresses 2234 * in an array. 2235 */ 2236 ptr = sc_if->sk_rdata.sk_jumbo_buf; 2237 for (i = 0; i < SK_JSLOTS; i++) { 2238 sc_if->sk_cdata.sk_jslots[i] = ptr; 2239 ptr += SK_JLEN; 2240 entry = malloc(sizeof(struct sk_jpool_entry), 2241 M_DEVBUF, M_NOWAIT); 2242 if (entry == NULL) { 2243 device_printf(sc_if->sk_if_dev, 2244 "no memory for jumbo buffers!\n"); 2245 error = ENOMEM; 2246 goto fail; 2247 } 2248 entry->slot = i; 2249 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2250 jpool_entries); 2251 } 2252 2253 fail: 2254 return (error); 2255 } 2256 2257 static void 2258 sk_dma_free(sc_if) 2259 struct sk_if_softc *sc_if; 2260 { 2261 struct sk_txdesc *txd; 2262 struct sk_rxdesc *rxd; 2263 struct sk_rxdesc *jrxd; 2264 struct sk_jpool_entry *entry; 2265 int i; 2266 2267 SK_JLIST_LOCK(sc_if); 2268 while ((entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead))) { 2269 device_printf(sc_if->sk_if_dev, 2270 "asked to free buffer that is in use!\n"); 2271 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2272 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2273 jpool_entries); 2274 } 2275 2276 while (!SLIST_EMPTY(&sc_if->sk_jfree_listhead)) { 2277 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2278 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2279 free(entry, M_DEVBUF); 2280 } 2281 SK_JLIST_UNLOCK(sc_if); 2282 2283 /* destroy jumbo buffer block */ 2284 if (sc_if->sk_cdata.sk_jumbo_map) 2285 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_tag, 2286 sc_if->sk_cdata.sk_jumbo_map); 2287 2288 if (sc_if->sk_rdata.sk_jumbo_buf) { 2289 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_tag, 2290 sc_if->sk_rdata.sk_jumbo_buf, 2291 sc_if->sk_cdata.sk_jumbo_map); 2292 sc_if->sk_rdata.sk_jumbo_buf = NULL; 2293 sc_if->sk_cdata.sk_jumbo_map = 0; 2294 } 2295 2296 /* Tx ring */ 2297 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2298 if (sc_if->sk_cdata.sk_tx_ring_map) 2299 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2300 sc_if->sk_cdata.sk_tx_ring_map); 2301 if (sc_if->sk_cdata.sk_tx_ring_map && 2302 sc_if->sk_rdata.sk_tx_ring) 2303 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2304 sc_if->sk_rdata.sk_tx_ring, 2305 sc_if->sk_cdata.sk_tx_ring_map); 2306 sc_if->sk_rdata.sk_tx_ring = NULL; 2307 sc_if->sk_cdata.sk_tx_ring_map = 0; 2308 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2309 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2310 } 2311 /* Rx ring */ 2312 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2313 if (sc_if->sk_cdata.sk_rx_ring_map) 2314 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2315 sc_if->sk_cdata.sk_rx_ring_map); 2316 if (sc_if->sk_cdata.sk_rx_ring_map && 2317 sc_if->sk_rdata.sk_rx_ring) 2318 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2319 sc_if->sk_rdata.sk_rx_ring, 2320 sc_if->sk_cdata.sk_rx_ring_map); 2321 sc_if->sk_rdata.sk_rx_ring = NULL; 2322 sc_if->sk_cdata.sk_rx_ring_map = 0; 2323 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2324 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2325 } 2326 /* jumbo Rx ring */ 2327 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2328 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map) 2329 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2330 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2331 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map && 2332 sc_if->sk_rdata.sk_jumbo_rx_ring) 2333 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2334 sc_if->sk_rdata.sk_jumbo_rx_ring, 2335 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2336 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2337 sc_if->sk_cdata.sk_jumbo_rx_ring_map = 0; 2338 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2339 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2340 } 2341 /* Tx buffers */ 2342 if (sc_if->sk_cdata.sk_tx_tag) { 2343 for (i = 0; i < SK_TX_RING_CNT; i++) { 2344 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2345 if (txd->tx_dmamap) { 2346 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2347 txd->tx_dmamap); 2348 txd->tx_dmamap = 0; 2349 } 2350 } 2351 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2352 sc_if->sk_cdata.sk_tx_tag = NULL; 2353 } 2354 /* Rx buffers */ 2355 if (sc_if->sk_cdata.sk_rx_tag) { 2356 for (i = 0; i < SK_RX_RING_CNT; i++) { 2357 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2358 if (rxd->rx_dmamap) { 2359 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2360 rxd->rx_dmamap); 2361 rxd->rx_dmamap = 0; 2362 } 2363 } 2364 if (sc_if->sk_cdata.sk_rx_sparemap) { 2365 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2366 sc_if->sk_cdata.sk_rx_sparemap); 2367 sc_if->sk_cdata.sk_rx_sparemap = 0; 2368 } 2369 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2370 sc_if->sk_cdata.sk_rx_tag = NULL; 2371 } 2372 /* jumbo Rx buffers */ 2373 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2374 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2375 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2376 if (jrxd->rx_dmamap) { 2377 bus_dmamap_destroy( 2378 sc_if->sk_cdata.sk_jumbo_rx_tag, 2379 jrxd->rx_dmamap); 2380 jrxd->rx_dmamap = 0; 2381 } 2382 } 2383 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2384 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2385 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2386 sc_if->sk_cdata.sk_jumbo_rx_sparemap = 0; 2387 } 2388 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2389 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2390 } 2391 2392 if (sc_if->sk_cdata.sk_parent_tag) { 2393 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2394 sc_if->sk_cdata.sk_parent_tag = NULL; 2395 } 2396 mtx_destroy(&sc_if->sk_jlist_mtx); 2397 } 2398 2399 /* 2400 * Allocate a jumbo buffer. 2401 */ 2402 static void * 2403 sk_jalloc(sc_if) 2404 struct sk_if_softc *sc_if; 2405 { 2406 struct sk_jpool_entry *entry; 2407 2408 SK_JLIST_LOCK(sc_if); 2409 2410 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2411 2412 if (entry == NULL) { 2413 SK_JLIST_UNLOCK(sc_if); 2414 return (NULL); 2415 } 2416 2417 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2418 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 2419 2420 SK_JLIST_UNLOCK(sc_if); 2421 2422 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 2423 } 2424 2425 /* 2426 * Release a jumbo buffer. 2427 */ 2428 static void 2429 sk_jfree(buf, args) 2430 void *buf; 2431 void *args; 2432 { 2433 struct sk_if_softc *sc_if; 2434 struct sk_jpool_entry *entry; 2435 int i; 2436 2437 /* Extract the softc struct pointer. */ 2438 sc_if = (struct sk_if_softc *)args; 2439 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2440 2441 SK_JLIST_LOCK(sc_if); 2442 /* calculate the slot this buffer belongs to */ 2443 i = ((vm_offset_t)buf 2444 - (vm_offset_t)sc_if->sk_rdata.sk_jumbo_buf) / SK_JLEN; 2445 KASSERT(i >= 0 && i < SK_JSLOTS, 2446 ("%s: asked to free buffer that we don't manage!", __func__)); 2447 2448 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 2449 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2450 entry->slot = i; 2451 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2452 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 2453 if (SLIST_EMPTY(&sc_if->sk_jinuse_listhead)) 2454 wakeup(sc_if); 2455 2456 SK_JLIST_UNLOCK(sc_if); 2457 } 2458 2459 static void 2460 sk_txcksum(ifp, m, f) 2461 struct ifnet *ifp; 2462 struct mbuf *m; 2463 struct sk_tx_desc *f; 2464 { 2465 struct ip *ip; 2466 u_int16_t offset; 2467 u_int8_t *p; 2468 2469 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2470 for(; m && m->m_len == 0; m = m->m_next) 2471 ; 2472 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2473 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2474 /* checksum may be corrupted */ 2475 goto sendit; 2476 } 2477 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2478 if (m->m_len != ETHER_HDR_LEN) { 2479 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2480 __func__); 2481 /* checksum may be corrupted */ 2482 goto sendit; 2483 } 2484 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2485 ; 2486 if (m == NULL) { 2487 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2488 /* checksum may be corrupted */ 2489 goto sendit; 2490 } 2491 ip = mtod(m, struct ip *); 2492 } else { 2493 p = mtod(m, u_int8_t *); 2494 p += ETHER_HDR_LEN; 2495 ip = (struct ip *)p; 2496 } 2497 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2498 2499 sendit: 2500 f->sk_csum_startval = 0; 2501 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2502 (offset << 16)); 2503 } 2504 2505 static int 2506 sk_encap(sc_if, m_head) 2507 struct sk_if_softc *sc_if; 2508 struct mbuf **m_head; 2509 { 2510 struct sk_txdesc *txd; 2511 struct sk_tx_desc *f = NULL; 2512 struct mbuf *m; 2513 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2514 u_int32_t cflags, frag, si, sk_ctl; 2515 int error, i, nseg; 2516 2517 SK_IF_LOCK_ASSERT(sc_if); 2518 2519 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2520 return (ENOBUFS); 2521 2522 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2523 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2524 if (error == EFBIG) { 2525 m = m_defrag(*m_head, M_DONTWAIT); 2526 if (m == NULL) { 2527 m_freem(*m_head); 2528 *m_head = NULL; 2529 return (ENOMEM); 2530 } 2531 *m_head = m; 2532 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2533 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2534 if (error != 0) { 2535 m_freem(*m_head); 2536 *m_head = NULL; 2537 return (error); 2538 } 2539 } else if (error != 0) 2540 return (error); 2541 if (nseg == 0) { 2542 m_freem(*m_head); 2543 *m_head = NULL; 2544 return (EIO); 2545 } 2546 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2547 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2548 return (ENOBUFS); 2549 } 2550 2551 m = *m_head; 2552 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0) 2553 cflags = SK_OPCODE_CSUM; 2554 else 2555 cflags = SK_OPCODE_DEFAULT; 2556 si = frag = sc_if->sk_cdata.sk_tx_prod; 2557 for (i = 0; i < nseg; i++) { 2558 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2559 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2560 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2561 sk_ctl = txsegs[i].ds_len | cflags; 2562 if (i == 0) { 2563 if (cflags == SK_OPCODE_CSUM) 2564 sk_txcksum(sc_if->sk_ifp, m, f); 2565 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2566 } else 2567 sk_ctl |= SK_TXCTL_OWN; 2568 f->sk_ctl = htole32(sk_ctl); 2569 sc_if->sk_cdata.sk_tx_cnt++; 2570 SK_INC(frag, SK_TX_RING_CNT); 2571 } 2572 sc_if->sk_cdata.sk_tx_prod = frag; 2573 2574 /* set EOF on the last desciptor */ 2575 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2576 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2577 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2578 2579 /* turn the first descriptor ownership to NIC */ 2580 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2581 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2582 2583 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2584 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2585 txd->tx_m = m; 2586 2587 /* sync descriptors */ 2588 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2589 BUS_DMASYNC_PREWRITE); 2590 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2591 sc_if->sk_cdata.sk_tx_ring_map, 2592 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2593 2594 return (0); 2595 } 2596 2597 static void 2598 sk_start(ifp) 2599 struct ifnet *ifp; 2600 { 2601 struct sk_if_softc *sc_if; 2602 2603 sc_if = ifp->if_softc; 2604 2605 SK_IF_LOCK(sc_if); 2606 sk_start_locked(ifp); 2607 SK_IF_UNLOCK(sc_if); 2608 2609 return; 2610 } 2611 2612 static void 2613 sk_start_locked(ifp) 2614 struct ifnet *ifp; 2615 { 2616 struct sk_softc *sc; 2617 struct sk_if_softc *sc_if; 2618 struct mbuf *m_head; 2619 int enq; 2620 2621 sc_if = ifp->if_softc; 2622 sc = sc_if->sk_softc; 2623 2624 SK_IF_LOCK_ASSERT(sc_if); 2625 2626 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2627 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2628 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2629 if (m_head == NULL) 2630 break; 2631 2632 /* 2633 * Pack the data into the transmit ring. If we 2634 * don't have room, set the OACTIVE flag and wait 2635 * for the NIC to drain the ring. 2636 */ 2637 if (sk_encap(sc_if, &m_head)) { 2638 if (m_head == NULL) 2639 break; 2640 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2641 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2642 break; 2643 } 2644 2645 enq++; 2646 /* 2647 * If there's a BPF listener, bounce a copy of this frame 2648 * to him. 2649 */ 2650 BPF_MTAP(ifp, m_head); 2651 } 2652 2653 if (enq > 0) { 2654 /* Transmit */ 2655 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2656 2657 /* Set a timeout in case the chip goes out to lunch. */ 2658 sc_if->sk_watchdog_timer = 5; 2659 } 2660 } 2661 2662 2663 static void 2664 sk_watchdog(arg) 2665 void *arg; 2666 { 2667 struct sk_if_softc *sc_if; 2668 struct ifnet *ifp; 2669 2670 ifp = arg; 2671 sc_if = ifp->if_softc; 2672 2673 SK_IF_LOCK_ASSERT(sc_if); 2674 2675 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer) 2676 goto done; 2677 2678 /* 2679 * Reclaim first as there is a possibility of losing Tx completion 2680 * interrupts. 2681 */ 2682 sk_txeof(sc_if); 2683 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2684 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2685 ifp->if_oerrors++; 2686 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2687 sk_init_locked(sc_if); 2688 } 2689 2690 done: 2691 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 2692 2693 return; 2694 } 2695 2696 static void 2697 skc_shutdown(dev) 2698 device_t dev; 2699 { 2700 struct sk_softc *sc; 2701 2702 sc = device_get_softc(dev); 2703 SK_LOCK(sc); 2704 2705 /* Turn off the 'driver is loaded' LED. */ 2706 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2707 2708 /* 2709 * Reset the GEnesis controller. Doing this should also 2710 * assert the resets on the attached XMAC(s). 2711 */ 2712 sk_reset(sc); 2713 SK_UNLOCK(sc); 2714 2715 return; 2716 } 2717 2718 static int 2719 skc_suspend(dev) 2720 device_t dev; 2721 { 2722 struct sk_softc *sc; 2723 struct sk_if_softc *sc_if0, *sc_if1; 2724 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2725 2726 sc = device_get_softc(dev); 2727 2728 SK_LOCK(sc); 2729 2730 sc_if0 = sc->sk_if[SK_PORT_A]; 2731 sc_if1 = sc->sk_if[SK_PORT_B]; 2732 if (sc_if0 != NULL) 2733 ifp0 = sc_if0->sk_ifp; 2734 if (sc_if1 != NULL) 2735 ifp1 = sc_if1->sk_ifp; 2736 if (ifp0 != NULL) 2737 sk_stop(sc_if0); 2738 if (ifp1 != NULL) 2739 sk_stop(sc_if1); 2740 sc->sk_suspended = 1; 2741 2742 SK_UNLOCK(sc); 2743 2744 return (0); 2745 } 2746 2747 static int 2748 skc_resume(dev) 2749 device_t dev; 2750 { 2751 struct sk_softc *sc; 2752 struct sk_if_softc *sc_if0, *sc_if1; 2753 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2754 2755 sc = device_get_softc(dev); 2756 2757 SK_LOCK(sc); 2758 2759 sc_if0 = sc->sk_if[SK_PORT_A]; 2760 sc_if1 = sc->sk_if[SK_PORT_B]; 2761 if (sc_if0 != NULL) 2762 ifp0 = sc_if0->sk_ifp; 2763 if (sc_if1 != NULL) 2764 ifp1 = sc_if1->sk_ifp; 2765 if (ifp0 != NULL && ifp0->if_flags & IFF_UP) 2766 sk_init_locked(sc_if0); 2767 if (ifp1 != NULL && ifp1->if_flags & IFF_UP) 2768 sk_init_locked(sc_if1); 2769 sc->sk_suspended = 0; 2770 2771 SK_UNLOCK(sc); 2772 2773 return (0); 2774 } 2775 2776 /* 2777 * According to the data sheet from SK-NET GENESIS the hardware can compute 2778 * two Rx checksums at the same time(Each checksum start position is 2779 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2780 * does not work at least on my Yukon hardware. I tried every possible ways 2781 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2782 * checksum offload was disabled at the moment and only IP checksum offload 2783 * was enabled. 2784 * As nomral IP header size is 20 bytes I can't expect it would give an 2785 * increase in throughput. However it seems it doesn't hurt performance in 2786 * my testing. If there is a more detailed information for checksum secret 2787 * of the hardware in question please contact yongari@FreeBSD.org to add 2788 * TCP/UDP checksum offload support. 2789 */ 2790 static __inline void 2791 sk_rxcksum(ifp, m, csum) 2792 struct ifnet *ifp; 2793 struct mbuf *m; 2794 u_int32_t csum; 2795 { 2796 struct ether_header *eh; 2797 struct ip *ip; 2798 int32_t hlen, len, pktlen; 2799 u_int16_t csum1, csum2, ipcsum; 2800 2801 pktlen = m->m_pkthdr.len; 2802 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2803 return; 2804 eh = mtod(m, struct ether_header *); 2805 if (eh->ether_type != htons(ETHERTYPE_IP)) 2806 return; 2807 ip = (struct ip *)(eh + 1); 2808 if (ip->ip_v != IPVERSION) 2809 return; 2810 hlen = ip->ip_hl << 2; 2811 pktlen -= sizeof(struct ether_header); 2812 if (hlen < sizeof(struct ip)) 2813 return; 2814 if (ntohs(ip->ip_len) < hlen) 2815 return; 2816 if (ntohs(ip->ip_len) != pktlen) 2817 return; 2818 2819 csum1 = htons(csum & 0xffff); 2820 csum2 = htons((csum >> 16) & 0xffff); 2821 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 2822 /* checksum fixup for IP options */ 2823 len = hlen - sizeof(struct ip); 2824 if (len > 0) { 2825 /* 2826 * If the second checksum value is correct we can compute IP 2827 * checksum with simple math. Unfortunately the second checksum 2828 * value is wrong so we can't verify the checksum from the 2829 * value(It seems there is some magic here to get correct 2830 * value). If the second checksum value is correct it also 2831 * means we can get TCP/UDP checksum) here. However, it still 2832 * needs pseudo header checksum calculation due to hardware 2833 * limitations. 2834 */ 2835 return; 2836 } 2837 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 2838 if (ipcsum == 0xffff) 2839 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2840 } 2841 2842 static __inline int 2843 sk_rxvalid(sc, stat, len) 2844 struct sk_softc *sc; 2845 u_int32_t stat, len; 2846 { 2847 2848 if (sc->sk_type == SK_GENESIS) { 2849 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 2850 XM_RXSTAT_BYTES(stat) != len) 2851 return (0); 2852 } else { 2853 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2854 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2855 YU_RXSTAT_JABBER)) != 0 || 2856 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2857 YU_RXSTAT_BYTES(stat) != len) 2858 return (0); 2859 } 2860 2861 return (1); 2862 } 2863 2864 static void 2865 sk_rxeof(sc_if) 2866 struct sk_if_softc *sc_if; 2867 { 2868 struct sk_softc *sc; 2869 struct mbuf *m; 2870 struct ifnet *ifp; 2871 struct sk_rx_desc *cur_rx; 2872 struct sk_rxdesc *rxd; 2873 int cons, prog; 2874 u_int32_t csum, rxstat, sk_ctl; 2875 2876 sc = sc_if->sk_softc; 2877 ifp = sc_if->sk_ifp; 2878 2879 SK_IF_LOCK_ASSERT(sc_if); 2880 2881 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2882 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 2883 2884 prog = 0; 2885 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 2886 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 2887 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 2888 sk_ctl = le32toh(cur_rx->sk_ctl); 2889 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2890 break; 2891 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 2892 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2893 2894 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2895 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2896 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2897 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2898 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 2899 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2900 ifp->if_ierrors++; 2901 sk_discard_rxbuf(sc_if, cons); 2902 continue; 2903 } 2904 2905 m = rxd->rx_m; 2906 csum = le32toh(cur_rx->sk_csum); 2907 if (sk_newbuf(sc_if, cons) != 0) { 2908 ifp->if_iqdrops++; 2909 /* reuse old buffer */ 2910 sk_discard_rxbuf(sc_if, cons); 2911 continue; 2912 } 2913 m->m_pkthdr.rcvif = ifp; 2914 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2915 ifp->if_ipackets++; 2916 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2917 sk_rxcksum(ifp, m, csum); 2918 SK_IF_UNLOCK(sc_if); 2919 (*ifp->if_input)(ifp, m); 2920 SK_IF_LOCK(sc_if); 2921 } 2922 2923 if (prog > 0) { 2924 sc_if->sk_cdata.sk_rx_cons = cons; 2925 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2926 sc_if->sk_cdata.sk_rx_ring_map, 2927 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2928 } 2929 } 2930 2931 static void 2932 sk_jumbo_rxeof(sc_if) 2933 struct sk_if_softc *sc_if; 2934 { 2935 struct sk_softc *sc; 2936 struct mbuf *m; 2937 struct ifnet *ifp; 2938 struct sk_rx_desc *cur_rx; 2939 struct sk_rxdesc *jrxd; 2940 int cons, prog; 2941 u_int32_t csum, rxstat, sk_ctl; 2942 2943 sc = sc_if->sk_softc; 2944 ifp = sc_if->sk_ifp; 2945 2946 SK_IF_LOCK_ASSERT(sc_if); 2947 2948 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2949 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 2950 2951 prog = 0; 2952 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 2953 prog < SK_JUMBO_RX_RING_CNT; 2954 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 2955 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 2956 sk_ctl = le32toh(cur_rx->sk_ctl); 2957 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2958 break; 2959 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 2960 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2961 2962 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2963 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2964 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2965 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2966 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 2967 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2968 ifp->if_ierrors++; 2969 sk_discard_jumbo_rxbuf(sc_if, cons); 2970 continue; 2971 } 2972 2973 m = jrxd->rx_m; 2974 csum = le32toh(cur_rx->sk_csum); 2975 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 2976 ifp->if_iqdrops++; 2977 /* reuse old buffer */ 2978 sk_discard_jumbo_rxbuf(sc_if, cons); 2979 continue; 2980 } 2981 m->m_pkthdr.rcvif = ifp; 2982 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2983 ifp->if_ipackets++; 2984 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2985 sk_rxcksum(ifp, m, csum); 2986 SK_IF_UNLOCK(sc_if); 2987 (*ifp->if_input)(ifp, m); 2988 SK_IF_LOCK(sc_if); 2989 } 2990 2991 if (prog > 0) { 2992 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 2993 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2994 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2995 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2996 } 2997 } 2998 2999 static void 3000 sk_txeof(sc_if) 3001 struct sk_if_softc *sc_if; 3002 { 3003 struct sk_softc *sc; 3004 struct sk_txdesc *txd; 3005 struct sk_tx_desc *cur_tx; 3006 struct ifnet *ifp; 3007 u_int32_t idx, sk_ctl; 3008 3009 sc = sc_if->sk_softc; 3010 ifp = sc_if->sk_ifp; 3011 3012 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3013 if (txd == NULL) 3014 return; 3015 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3016 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 3017 /* 3018 * Go through our tx ring and free mbufs for those 3019 * frames that have been sent. 3020 */ 3021 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 3022 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 3023 break; 3024 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 3025 sk_ctl = le32toh(cur_tx->sk_ctl); 3026 if (sk_ctl & SK_TXCTL_OWN) 3027 break; 3028 sc_if->sk_cdata.sk_tx_cnt--; 3029 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3030 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 3031 continue; 3032 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 3033 BUS_DMASYNC_POSTWRITE); 3034 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 3035 3036 ifp->if_opackets++; 3037 m_freem(txd->tx_m); 3038 txd->tx_m = NULL; 3039 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 3040 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 3041 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3042 } 3043 sc_if->sk_cdata.sk_tx_cons = idx; 3044 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 3045 3046 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3047 sc_if->sk_cdata.sk_tx_ring_map, 3048 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3049 } 3050 3051 static void 3052 sk_tick(xsc_if) 3053 void *xsc_if; 3054 { 3055 struct sk_if_softc *sc_if; 3056 struct mii_data *mii; 3057 struct ifnet *ifp; 3058 int i; 3059 3060 sc_if = xsc_if; 3061 ifp = sc_if->sk_ifp; 3062 mii = device_get_softc(sc_if->sk_miibus); 3063 3064 if (!(ifp->if_flags & IFF_UP)) 3065 return; 3066 3067 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3068 sk_intr_bcom(sc_if); 3069 return; 3070 } 3071 3072 /* 3073 * According to SysKonnect, the correct way to verify that 3074 * the link has come back up is to poll bit 0 of the GPIO 3075 * register three times. This pin has the signal from the 3076 * link_sync pin connected to it; if we read the same link 3077 * state 3 times in a row, we know the link is up. 3078 */ 3079 for (i = 0; i < 3; i++) { 3080 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 3081 break; 3082 } 3083 3084 if (i != 3) { 3085 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3086 return; 3087 } 3088 3089 /* Turn the GP0 interrupt back on. */ 3090 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3091 SK_XM_READ_2(sc_if, XM_ISR); 3092 mii_tick(mii); 3093 callout_stop(&sc_if->sk_tick_ch); 3094 } 3095 3096 static void 3097 sk_yukon_tick(xsc_if) 3098 void *xsc_if; 3099 { 3100 struct sk_if_softc *sc_if; 3101 struct mii_data *mii; 3102 3103 sc_if = xsc_if; 3104 mii = device_get_softc(sc_if->sk_miibus); 3105 3106 mii_tick(mii); 3107 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3108 } 3109 3110 static void 3111 sk_intr_bcom(sc_if) 3112 struct sk_if_softc *sc_if; 3113 { 3114 struct mii_data *mii; 3115 struct ifnet *ifp; 3116 int status; 3117 mii = device_get_softc(sc_if->sk_miibus); 3118 ifp = sc_if->sk_ifp; 3119 3120 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3121 3122 /* 3123 * Read the PHY interrupt register to make sure 3124 * we clear any pending interrupts. 3125 */ 3126 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 3127 3128 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3129 sk_init_xmac(sc_if); 3130 return; 3131 } 3132 3133 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 3134 int lstat; 3135 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 3136 BRGPHY_MII_AUXSTS); 3137 3138 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 3139 mii_mediachg(mii); 3140 /* Turn off the link LED. */ 3141 SK_IF_WRITE_1(sc_if, 0, 3142 SK_LINKLED1_CTL, SK_LINKLED_OFF); 3143 sc_if->sk_link = 0; 3144 } else if (status & BRGPHY_ISR_LNK_CHG) { 3145 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3146 BRGPHY_MII_IMR, 0xFF00); 3147 mii_tick(mii); 3148 sc_if->sk_link = 1; 3149 /* Turn on the link LED. */ 3150 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3151 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 3152 SK_LINKLED_BLINK_OFF); 3153 } else { 3154 mii_tick(mii); 3155 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3156 } 3157 } 3158 3159 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3160 3161 return; 3162 } 3163 3164 static void 3165 sk_intr_xmac(sc_if) 3166 struct sk_if_softc *sc_if; 3167 { 3168 struct sk_softc *sc; 3169 u_int16_t status; 3170 3171 sc = sc_if->sk_softc; 3172 status = SK_XM_READ_2(sc_if, XM_ISR); 3173 3174 /* 3175 * Link has gone down. Start MII tick timeout to 3176 * watch for link resync. 3177 */ 3178 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 3179 if (status & XM_ISR_GP0_SET) { 3180 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3181 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3182 } 3183 3184 if (status & XM_ISR_AUTONEG_DONE) { 3185 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3186 } 3187 } 3188 3189 if (status & XM_IMR_TX_UNDERRUN) 3190 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 3191 3192 if (status & XM_IMR_RX_OVERRUN) 3193 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 3194 3195 status = SK_XM_READ_2(sc_if, XM_ISR); 3196 3197 return; 3198 } 3199 3200 static void 3201 sk_intr_yukon(sc_if) 3202 struct sk_if_softc *sc_if; 3203 { 3204 u_int8_t status; 3205 3206 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 3207 /* RX overrun */ 3208 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 3209 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3210 SK_RFCTL_RX_FIFO_OVER); 3211 } 3212 /* TX underrun */ 3213 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 3214 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3215 SK_TFCTL_TX_FIFO_UNDER); 3216 } 3217 } 3218 3219 static void 3220 sk_intr(xsc) 3221 void *xsc; 3222 { 3223 struct sk_softc *sc = xsc; 3224 struct sk_if_softc *sc_if0, *sc_if1; 3225 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 3226 u_int32_t status; 3227 3228 SK_LOCK(sc); 3229 3230 status = CSR_READ_4(sc, SK_ISSR); 3231 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3232 goto done_locked; 3233 3234 sc_if0 = sc->sk_if[SK_PORT_A]; 3235 sc_if1 = sc->sk_if[SK_PORT_B]; 3236 3237 if (sc_if0 != NULL) 3238 ifp0 = sc_if0->sk_ifp; 3239 if (sc_if1 != NULL) 3240 ifp1 = sc_if1->sk_ifp; 3241 3242 for (; (status &= sc->sk_intrmask) != 0;) { 3243 /* Handle receive interrupts first. */ 3244 if (status & SK_ISR_RX1_EOF) { 3245 if (ifp0->if_mtu > SK_MAX_FRAMELEN) 3246 sk_jumbo_rxeof(sc_if0); 3247 else 3248 sk_rxeof(sc_if0); 3249 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3250 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3251 } 3252 if (status & SK_ISR_RX2_EOF) { 3253 if (ifp1->if_mtu > SK_MAX_FRAMELEN) 3254 sk_jumbo_rxeof(sc_if1); 3255 else 3256 sk_rxeof(sc_if1); 3257 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3258 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3259 } 3260 3261 /* Then transmit interrupts. */ 3262 if (status & SK_ISR_TX1_S_EOF) { 3263 sk_txeof(sc_if0); 3264 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3265 } 3266 if (status & SK_ISR_TX2_S_EOF) { 3267 sk_txeof(sc_if1); 3268 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3269 } 3270 3271 /* Then MAC interrupts. */ 3272 if (status & SK_ISR_MAC1 && 3273 ifp0->if_drv_flags & IFF_DRV_RUNNING) { 3274 if (sc->sk_type == SK_GENESIS) 3275 sk_intr_xmac(sc_if0); 3276 else 3277 sk_intr_yukon(sc_if0); 3278 } 3279 3280 if (status & SK_ISR_MAC2 && 3281 ifp1->if_drv_flags & IFF_DRV_RUNNING) { 3282 if (sc->sk_type == SK_GENESIS) 3283 sk_intr_xmac(sc_if1); 3284 else 3285 sk_intr_yukon(sc_if1); 3286 } 3287 3288 if (status & SK_ISR_EXTERNAL_REG) { 3289 if (ifp0 != NULL && 3290 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3291 sk_intr_bcom(sc_if0); 3292 if (ifp1 != NULL && 3293 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3294 sk_intr_bcom(sc_if1); 3295 } 3296 status = CSR_READ_4(sc, SK_ISSR); 3297 } 3298 3299 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3300 3301 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3302 sk_start_locked(ifp0); 3303 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3304 sk_start_locked(ifp1); 3305 3306 done_locked: 3307 SK_UNLOCK(sc); 3308 } 3309 3310 static void 3311 sk_init_xmac(sc_if) 3312 struct sk_if_softc *sc_if; 3313 { 3314 struct sk_softc *sc; 3315 struct ifnet *ifp; 3316 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3317 struct sk_bcom_hack bhack[] = { 3318 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3319 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3320 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3321 { 0, 0 } }; 3322 3323 SK_IF_LOCK_ASSERT(sc_if); 3324 3325 sc = sc_if->sk_softc; 3326 ifp = sc_if->sk_ifp; 3327 3328 /* Unreset the XMAC. */ 3329 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3330 DELAY(1000); 3331 3332 /* Reset the XMAC's internal state. */ 3333 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3334 3335 /* Save the XMAC II revision */ 3336 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3337 3338 /* 3339 * Perform additional initialization for external PHYs, 3340 * namely for the 1000baseTX cards that use the XMAC's 3341 * GMII mode. 3342 */ 3343 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3344 int i = 0; 3345 u_int32_t val; 3346 3347 /* Take PHY out of reset. */ 3348 val = sk_win_read_4(sc, SK_GPIO); 3349 if (sc_if->sk_port == SK_PORT_A) 3350 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3351 else 3352 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3353 sk_win_write_4(sc, SK_GPIO, val); 3354 3355 /* Enable GMII mode on the XMAC. */ 3356 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3357 3358 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3359 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3360 DELAY(10000); 3361 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3362 BRGPHY_MII_IMR, 0xFFF0); 3363 3364 /* 3365 * Early versions of the BCM5400 apparently have 3366 * a bug that requires them to have their reserved 3367 * registers initialized to some magic values. I don't 3368 * know what the numbers do, I'm just the messenger. 3369 */ 3370 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3371 == 0x6041) { 3372 while(bhack[i].reg) { 3373 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3374 bhack[i].reg, bhack[i].val); 3375 i++; 3376 } 3377 } 3378 } 3379 3380 /* Set station address */ 3381 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3382 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3383 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3384 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3385 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3386 3387 if (ifp->if_flags & IFF_BROADCAST) { 3388 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3389 } else { 3390 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3391 } 3392 3393 /* We don't need the FCS appended to the packet. */ 3394 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3395 3396 /* We want short frames padded to 60 bytes. */ 3397 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3398 3399 /* 3400 * Enable the reception of all error frames. This is is 3401 * a necessary evil due to the design of the XMAC. The 3402 * XMAC's receive FIFO is only 8K in size, however jumbo 3403 * frames can be up to 9000 bytes in length. When bad 3404 * frame filtering is enabled, the XMAC's RX FIFO operates 3405 * in 'store and forward' mode. For this to work, the 3406 * entire frame has to fit into the FIFO, but that means 3407 * that jumbo frames larger than 8192 bytes will be 3408 * truncated. Disabling all bad frame filtering causes 3409 * the RX FIFO to operate in streaming mode, in which 3410 * case the XMAC will start transfering frames out of the 3411 * RX FIFO as soon as the FIFO threshold is reached. 3412 */ 3413 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3414 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3415 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3416 XM_MODE_RX_INRANGELEN); 3417 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3418 } else 3419 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3420 3421 /* 3422 * Bump up the transmit threshold. This helps hold off transmit 3423 * underruns when we're blasting traffic from both ports at once. 3424 */ 3425 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3426 3427 /* Set promiscuous mode */ 3428 sk_setpromisc(sc_if); 3429 3430 /* Set multicast filter */ 3431 sk_setmulti(sc_if); 3432 3433 /* Clear and enable interrupts */ 3434 SK_XM_READ_2(sc_if, XM_ISR); 3435 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3436 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3437 else 3438 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3439 3440 /* Configure MAC arbiter */ 3441 switch(sc_if->sk_xmac_rev) { 3442 case XM_XMAC_REV_B2: 3443 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3444 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3445 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3446 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3447 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3448 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3449 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3450 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3451 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3452 break; 3453 case XM_XMAC_REV_C1: 3454 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3455 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3456 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3457 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3458 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3459 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3460 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3461 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3462 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3463 break; 3464 default: 3465 break; 3466 } 3467 sk_win_write_2(sc, SK_MACARB_CTL, 3468 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3469 3470 sc_if->sk_link = 1; 3471 3472 return; 3473 } 3474 3475 static void 3476 sk_init_yukon(sc_if) 3477 struct sk_if_softc *sc_if; 3478 { 3479 u_int32_t phy, v; 3480 u_int16_t reg; 3481 struct sk_softc *sc; 3482 struct ifnet *ifp; 3483 int i; 3484 3485 SK_IF_LOCK_ASSERT(sc_if); 3486 3487 sc = sc_if->sk_softc; 3488 ifp = sc_if->sk_ifp; 3489 3490 if (sc->sk_type == SK_YUKON_LITE && 3491 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3492 /* 3493 * Workaround code for COMA mode, set PHY reset. 3494 * Otherwise it will not correctly take chip out of 3495 * powerdown (coma) 3496 */ 3497 v = sk_win_read_4(sc, SK_GPIO); 3498 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3499 sk_win_write_4(sc, SK_GPIO, v); 3500 } 3501 3502 /* GMAC and GPHY Reset */ 3503 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3504 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3505 DELAY(1000); 3506 3507 if (sc->sk_type == SK_YUKON_LITE && 3508 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3509 /* 3510 * Workaround code for COMA mode, clear PHY reset 3511 */ 3512 v = sk_win_read_4(sc, SK_GPIO); 3513 v |= SK_GPIO_DIR9; 3514 v &= ~SK_GPIO_DAT9; 3515 sk_win_write_4(sc, SK_GPIO, v); 3516 } 3517 3518 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3519 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3520 3521 if (sc->sk_coppertype) 3522 phy |= SK_GPHY_COPPER; 3523 else 3524 phy |= SK_GPHY_FIBER; 3525 3526 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3527 DELAY(1000); 3528 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3529 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3530 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3531 3532 /* unused read of the interrupt source register */ 3533 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3534 3535 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3536 3537 /* MIB Counter Clear Mode set */ 3538 reg |= YU_PAR_MIB_CLR; 3539 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3540 3541 /* MIB Counter Clear Mode clear */ 3542 reg &= ~YU_PAR_MIB_CLR; 3543 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3544 3545 /* receive control reg */ 3546 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3547 3548 /* transmit parameter register */ 3549 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3550 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3551 3552 /* serial mode register */ 3553 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3554 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3555 reg |= YU_SMR_MFL_JUMBO; 3556 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3557 3558 /* Setup Yukon's address */ 3559 for (i = 0; i < 3; i++) { 3560 /* Write Source Address 1 (unicast filter) */ 3561 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3562 IF_LLADDR(sc_if->sk_ifp)[i * 2] | 3563 IF_LLADDR(sc_if->sk_ifp)[i * 2 + 1] << 8); 3564 } 3565 3566 for (i = 0; i < 3; i++) { 3567 reg = sk_win_read_2(sc_if->sk_softc, 3568 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 3569 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 3570 } 3571 3572 /* Set promiscuous mode */ 3573 sk_setpromisc(sc_if); 3574 3575 /* Set multicast filter */ 3576 sk_setmulti(sc_if); 3577 3578 /* enable interrupt mask for counter overflows */ 3579 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3580 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3581 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3582 3583 /* Configure RX MAC FIFO Flush Mask */ 3584 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3585 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3586 YU_RXSTAT_JABBER; 3587 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3588 3589 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3590 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3591 v = SK_TFCTL_OPERATION_ON; 3592 else 3593 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3594 /* Configure RX MAC FIFO */ 3595 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3596 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3597 3598 /* Increase flush threshould to 64 bytes */ 3599 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3600 SK_RFCTL_FIFO_THRESHOLD + 1); 3601 3602 /* Configure TX MAC FIFO */ 3603 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3604 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3605 } 3606 3607 /* 3608 * Note that to properly initialize any part of the GEnesis chip, 3609 * you first have to take it out of reset mode. 3610 */ 3611 static void 3612 sk_init(xsc) 3613 void *xsc; 3614 { 3615 struct sk_if_softc *sc_if = xsc; 3616 3617 SK_IF_LOCK(sc_if); 3618 sk_init_locked(sc_if); 3619 SK_IF_UNLOCK(sc_if); 3620 3621 return; 3622 } 3623 3624 static void 3625 sk_init_locked(sc_if) 3626 struct sk_if_softc *sc_if; 3627 { 3628 struct sk_softc *sc; 3629 struct ifnet *ifp; 3630 struct mii_data *mii; 3631 u_int16_t reg; 3632 u_int32_t imr; 3633 int error; 3634 3635 SK_IF_LOCK_ASSERT(sc_if); 3636 3637 ifp = sc_if->sk_ifp; 3638 sc = sc_if->sk_softc; 3639 mii = device_get_softc(sc_if->sk_miibus); 3640 3641 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3642 return; 3643 3644 /* Cancel pending I/O and free all RX/TX buffers. */ 3645 sk_stop(sc_if); 3646 3647 if (sc->sk_type == SK_GENESIS) { 3648 /* Configure LINK_SYNC LED */ 3649 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3650 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3651 SK_LINKLED_LINKSYNC_ON); 3652 3653 /* Configure RX LED */ 3654 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3655 SK_RXLEDCTL_COUNTER_START); 3656 3657 /* Configure TX LED */ 3658 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3659 SK_TXLEDCTL_COUNTER_START); 3660 } 3661 3662 /* 3663 * Configure descriptor poll timer 3664 * 3665 * SK-NET GENESIS data sheet says that possibility of losing Start 3666 * transmit command due to CPU/cache related interim storage problems 3667 * under certain conditions. The document recommends a polling 3668 * mechanism to send a Start transmit command to initiate transfer 3669 * of ready descriptors regulary. To cope with this issue sk(4) now 3670 * enables descriptor poll timer to initiate descriptor processing 3671 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3672 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3673 * command instead of waiting for next descriptor polling time. 3674 * The same rule may apply to Rx side too but it seems that is not 3675 * needed at the moment. 3676 * Since sk(4) uses descriptor polling as a last resort there is no 3677 * need to set smaller polling time than maximum allowable one. 3678 */ 3679 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3680 3681 /* Configure I2C registers */ 3682 3683 /* Configure XMAC(s) */ 3684 switch (sc->sk_type) { 3685 case SK_GENESIS: 3686 sk_init_xmac(sc_if); 3687 break; 3688 case SK_YUKON: 3689 case SK_YUKON_LITE: 3690 case SK_YUKON_LP: 3691 sk_init_yukon(sc_if); 3692 break; 3693 } 3694 mii_mediachg(mii); 3695 3696 if (sc->sk_type == SK_GENESIS) { 3697 /* Configure MAC FIFOs */ 3698 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3699 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3700 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3701 3702 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3703 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3704 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3705 } 3706 3707 /* Configure transmit arbiter(s) */ 3708 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3709 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3710 3711 /* Configure RAMbuffers */ 3712 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3713 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3714 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3715 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3716 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3717 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3718 3719 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3720 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3721 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3722 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3723 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3724 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3725 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3726 3727 /* Configure BMUs */ 3728 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3729 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3730 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3731 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3732 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3733 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3734 } else { 3735 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3736 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3737 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3738 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3739 } 3740 3741 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3742 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3743 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3744 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3745 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3746 3747 /* Init descriptors */ 3748 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3749 error = sk_init_jumbo_rx_ring(sc_if); 3750 else 3751 error = sk_init_rx_ring(sc_if); 3752 if (error != 0) { 3753 device_printf(sc_if->sk_if_dev, 3754 "initialization failed: no memory for rx buffers\n"); 3755 sk_stop(sc_if); 3756 return; 3757 } 3758 sk_init_tx_ring(sc_if); 3759 3760 /* Set interrupt moderation if changed via sysctl. */ 3761 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3762 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3763 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3764 sc->sk_int_ticks)); 3765 if (bootverbose) 3766 device_printf(sc_if->sk_if_dev, 3767 "interrupt moderation is %d us.\n", 3768 sc->sk_int_mod); 3769 } 3770 3771 /* Configure interrupt handling */ 3772 CSR_READ_4(sc, SK_ISSR); 3773 if (sc_if->sk_port == SK_PORT_A) 3774 sc->sk_intrmask |= SK_INTRS1; 3775 else 3776 sc->sk_intrmask |= SK_INTRS2; 3777 3778 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3779 3780 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3781 3782 /* Start BMUs. */ 3783 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3784 3785 switch(sc->sk_type) { 3786 case SK_GENESIS: 3787 /* Enable XMACs TX and RX state machines */ 3788 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3789 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3790 break; 3791 case SK_YUKON: 3792 case SK_YUKON_LITE: 3793 case SK_YUKON_LP: 3794 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3795 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3796 #if 0 3797 /* XXX disable 100Mbps and full duplex mode? */ 3798 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3799 #endif 3800 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3801 } 3802 3803 /* Activate descriptor polling timer */ 3804 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 3805 /* start transfer of Tx descriptors */ 3806 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 3807 3808 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3809 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3810 3811 switch (sc->sk_type) { 3812 case SK_YUKON: 3813 case SK_YUKON_LITE: 3814 case SK_YUKON_LP: 3815 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3816 break; 3817 } 3818 3819 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 3820 3821 return; 3822 } 3823 3824 static void 3825 sk_stop(sc_if) 3826 struct sk_if_softc *sc_if; 3827 { 3828 int i; 3829 struct sk_softc *sc; 3830 struct sk_txdesc *txd; 3831 struct sk_rxdesc *rxd; 3832 struct sk_rxdesc *jrxd; 3833 struct ifnet *ifp; 3834 u_int32_t val; 3835 3836 SK_IF_LOCK_ASSERT(sc_if); 3837 sc = sc_if->sk_softc; 3838 ifp = sc_if->sk_ifp; 3839 3840 callout_stop(&sc_if->sk_tick_ch); 3841 callout_stop(&sc_if->sk_watchdog_ch); 3842 3843 /* stop Tx descriptor polling timer */ 3844 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 3845 /* stop transfer of Tx descriptors */ 3846 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 3847 for (i = 0; i < SK_TIMEOUT; i++) { 3848 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 3849 if ((val & SK_TXBMU_TX_STOP) == 0) 3850 break; 3851 DELAY(1); 3852 } 3853 if (i == SK_TIMEOUT) 3854 device_printf(sc_if->sk_if_dev, 3855 "can not stop transfer of Tx descriptor\n"); 3856 /* stop transfer of Rx descriptors */ 3857 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 3858 for (i = 0; i < SK_TIMEOUT; i++) { 3859 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 3860 if ((val & SK_RXBMU_RX_STOP) == 0) 3861 break; 3862 DELAY(1); 3863 } 3864 if (i == SK_TIMEOUT) 3865 device_printf(sc_if->sk_if_dev, 3866 "can not stop transfer of Rx descriptor\n"); 3867 3868 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3869 /* Put PHY back into reset. */ 3870 val = sk_win_read_4(sc, SK_GPIO); 3871 if (sc_if->sk_port == SK_PORT_A) { 3872 val |= SK_GPIO_DIR0; 3873 val &= ~SK_GPIO_DAT0; 3874 } else { 3875 val |= SK_GPIO_DIR2; 3876 val &= ~SK_GPIO_DAT2; 3877 } 3878 sk_win_write_4(sc, SK_GPIO, val); 3879 } 3880 3881 /* Turn off various components of this interface. */ 3882 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3883 switch (sc->sk_type) { 3884 case SK_GENESIS: 3885 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 3886 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 3887 break; 3888 case SK_YUKON: 3889 case SK_YUKON_LITE: 3890 case SK_YUKON_LP: 3891 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 3892 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 3893 break; 3894 } 3895 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 3896 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3897 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 3898 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3899 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 3900 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3901 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3902 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 3903 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 3904 3905 /* Disable interrupts */ 3906 if (sc_if->sk_port == SK_PORT_A) 3907 sc->sk_intrmask &= ~SK_INTRS1; 3908 else 3909 sc->sk_intrmask &= ~SK_INTRS2; 3910 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3911 3912 SK_XM_READ_2(sc_if, XM_ISR); 3913 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3914 3915 /* Free RX and TX mbufs still in the queues. */ 3916 for (i = 0; i < SK_RX_RING_CNT; i++) { 3917 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 3918 if (rxd->rx_m != NULL) { 3919 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 3920 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3921 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 3922 rxd->rx_dmamap); 3923 m_freem(rxd->rx_m); 3924 rxd->rx_m = NULL; 3925 } 3926 } 3927 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 3928 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 3929 if (jrxd->rx_m != NULL) { 3930 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 3931 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3932 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 3933 jrxd->rx_dmamap); 3934 m_freem(jrxd->rx_m); 3935 jrxd->rx_m = NULL; 3936 } 3937 } 3938 for (i = 0; i < SK_TX_RING_CNT; i++) { 3939 txd = &sc_if->sk_cdata.sk_txdesc[i]; 3940 if (txd->tx_m != NULL) { 3941 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 3942 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3943 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 3944 txd->tx_dmamap); 3945 m_freem(txd->tx_m); 3946 txd->tx_m = NULL; 3947 } 3948 } 3949 3950 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 3951 3952 return; 3953 } 3954 3955 static int 3956 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3957 { 3958 int error, value; 3959 3960 if (!arg1) 3961 return (EINVAL); 3962 value = *(int *)arg1; 3963 error = sysctl_handle_int(oidp, &value, 0, req); 3964 if (error || !req->newptr) 3965 return (error); 3966 if (value < low || value > high) 3967 return (EINVAL); 3968 *(int *)arg1 = value; 3969 return (0); 3970 } 3971 3972 static int 3973 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 3974 { 3975 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 3976 } 3977