1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /* 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 /* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 97 #include <net/if.h> 98 #include <net/if_arp.h> 99 #include <net/ethernet.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 103 #include <net/bpf.h> 104 105 #include <vm/vm.h> /* for vtophys */ 106 #include <vm/pmap.h> /* for vtophys */ 107 #include <machine/bus_pio.h> 108 #include <machine/bus_memio.h> 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 #include <dev/mii/brgphyreg.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #if 0 122 #define SK_USEIOSPACE 123 #endif 124 125 #include <pci/if_skreg.h> 126 #include <pci/xmaciireg.h> 127 #include <pci/yukonreg.h> 128 129 MODULE_DEPEND(sk, pci, 1, 1, 1); 130 MODULE_DEPEND(sk, ether, 1, 1, 1); 131 MODULE_DEPEND(sk, miibus, 1, 1, 1); 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 #ifndef lint 137 static const char rcsid[] = 138 "$FreeBSD$"; 139 #endif 140 141 static struct sk_type sk_devs[] = { 142 { 143 VENDORID_SK, 144 DEVICEID_SK_V1, 145 "SysKonnect Gigabit Ethernet (V1.0)" 146 }, 147 { 148 VENDORID_SK, 149 DEVICEID_SK_V2, 150 "SysKonnect Gigabit Ethernet (V2.0)" 151 }, 152 { 153 VENDORID_MARVELL, 154 DEVICEID_SK_V2, 155 "Marvell Gigabit Ethernet" 156 }, 157 { 158 VENDORID_3COM, 159 DEVICEID_3COM_3C940, 160 "3Com 3C940 Gigabit Ethernet" 161 }, 162 { 163 VENDORID_LINKSYS, 164 DEVICEID_LINKSYS_EG1032, 165 "Linksys EG1032 Gigabit Ethernet" 166 }, 167 { 168 VENDORID_DLINK, 169 DEVICEID_DLINK_DGE530T, 170 "D-Link DGE-530T Gigabit Ethernet" 171 }, 172 { 0, 0, NULL } 173 }; 174 175 static int skc_probe (device_t); 176 static int skc_attach (device_t); 177 static int skc_detach (device_t); 178 static void skc_shutdown (device_t); 179 static int sk_detach (device_t); 180 static int sk_probe (device_t); 181 static int sk_attach (device_t); 182 static void sk_tick (void *); 183 static void sk_intr (void *); 184 static void sk_intr_xmac (struct sk_if_softc *); 185 static void sk_intr_bcom (struct sk_if_softc *); 186 static void sk_intr_yukon (struct sk_if_softc *); 187 static void sk_rxeof (struct sk_if_softc *); 188 static void sk_txeof (struct sk_if_softc *); 189 static int sk_encap (struct sk_if_softc *, struct mbuf *, 190 u_int32_t *); 191 static void sk_start (struct ifnet *); 192 static int sk_ioctl (struct ifnet *, u_long, caddr_t); 193 static void sk_init (void *); 194 static void sk_init_xmac (struct sk_if_softc *); 195 static void sk_init_yukon (struct sk_if_softc *); 196 static void sk_stop (struct sk_if_softc *); 197 static void sk_watchdog (struct ifnet *); 198 static int sk_ifmedia_upd (struct ifnet *); 199 static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 200 static void sk_reset (struct sk_softc *); 201 static int sk_newbuf (struct sk_if_softc *, 202 struct sk_chain *, struct mbuf *); 203 static int sk_alloc_jumbo_mem (struct sk_if_softc *); 204 static void *sk_jalloc (struct sk_if_softc *); 205 static void sk_jfree (void *, void *); 206 static int sk_init_rx_ring (struct sk_if_softc *); 207 static void sk_init_tx_ring (struct sk_if_softc *); 208 static u_int32_t sk_win_read_4 (struct sk_softc *, int); 209 static u_int16_t sk_win_read_2 (struct sk_softc *, int); 210 static u_int8_t sk_win_read_1 (struct sk_softc *, int); 211 static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 212 static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 213 static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 214 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 215 static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int); 216 static void sk_vpd_read (struct sk_softc *); 217 218 static int sk_miibus_readreg (device_t, int, int); 219 static int sk_miibus_writereg (device_t, int, int, int); 220 static void sk_miibus_statchg (device_t); 221 222 static int sk_xmac_miibus_readreg (struct sk_if_softc *, int, int); 223 static int sk_xmac_miibus_writereg (struct sk_if_softc *, int, int, 224 int); 225 static void sk_xmac_miibus_statchg (struct sk_if_softc *); 226 227 static int sk_marv_miibus_readreg (struct sk_if_softc *, int, int); 228 static int sk_marv_miibus_writereg (struct sk_if_softc *, int, int, 229 int); 230 static void sk_marv_miibus_statchg (struct sk_if_softc *); 231 232 static uint32_t sk_xmchash (const uint8_t *); 233 static uint32_t sk_gmchash (const uint8_t *); 234 static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 235 static void sk_setmulti (struct sk_if_softc *); 236 static void sk_setpromisc (struct sk_if_softc *); 237 238 #ifdef SK_USEIOSPACE 239 #define SK_RES SYS_RES_IOPORT 240 #define SK_RID SK_PCI_LOIO 241 #else 242 #define SK_RES SYS_RES_MEMORY 243 #define SK_RID SK_PCI_LOMEM 244 #endif 245 246 /* 247 * Note that we have newbus methods for both the GEnesis controller 248 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 249 * the miibus code is a child of the XMACs. We need to do it this way 250 * so that the miibus drivers can access the PHY registers on the 251 * right PHY. It's not quite what I had in mind, but it's the only 252 * design that achieves the desired effect. 253 */ 254 static device_method_t skc_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, skc_probe), 257 DEVMETHOD(device_attach, skc_attach), 258 DEVMETHOD(device_detach, skc_detach), 259 DEVMETHOD(device_shutdown, skc_shutdown), 260 261 /* bus interface */ 262 DEVMETHOD(bus_print_child, bus_generic_print_child), 263 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 264 265 { 0, 0 } 266 }; 267 268 static driver_t skc_driver = { 269 "skc", 270 skc_methods, 271 sizeof(struct sk_softc) 272 }; 273 274 static devclass_t skc_devclass; 275 276 static device_method_t sk_methods[] = { 277 /* Device interface */ 278 DEVMETHOD(device_probe, sk_probe), 279 DEVMETHOD(device_attach, sk_attach), 280 DEVMETHOD(device_detach, sk_detach), 281 DEVMETHOD(device_shutdown, bus_generic_shutdown), 282 283 /* bus interface */ 284 DEVMETHOD(bus_print_child, bus_generic_print_child), 285 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 286 287 /* MII interface */ 288 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 289 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 290 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 291 292 { 0, 0 } 293 }; 294 295 static driver_t sk_driver = { 296 "sk", 297 sk_methods, 298 sizeof(struct sk_if_softc) 299 }; 300 301 static devclass_t sk_devclass; 302 303 DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0); 304 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 305 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 306 307 #define SK_SETBIT(sc, reg, x) \ 308 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 309 310 #define SK_CLRBIT(sc, reg, x) \ 311 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 312 313 #define SK_WIN_SETBIT_4(sc, reg, x) \ 314 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 315 316 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 317 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 318 319 #define SK_WIN_SETBIT_2(sc, reg, x) \ 320 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 321 322 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 323 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 324 325 static u_int32_t 326 sk_win_read_4(sc, reg) 327 struct sk_softc *sc; 328 int reg; 329 { 330 #ifdef SK_USEIOSPACE 331 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 332 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 333 #else 334 return(CSR_READ_4(sc, reg)); 335 #endif 336 } 337 338 static u_int16_t 339 sk_win_read_2(sc, reg) 340 struct sk_softc *sc; 341 int reg; 342 { 343 #ifdef SK_USEIOSPACE 344 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 345 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 346 #else 347 return(CSR_READ_2(sc, reg)); 348 #endif 349 } 350 351 static u_int8_t 352 sk_win_read_1(sc, reg) 353 struct sk_softc *sc; 354 int reg; 355 { 356 #ifdef SK_USEIOSPACE 357 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 358 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 359 #else 360 return(CSR_READ_1(sc, reg)); 361 #endif 362 } 363 364 static void 365 sk_win_write_4(sc, reg, val) 366 struct sk_softc *sc; 367 int reg; 368 u_int32_t val; 369 { 370 #ifdef SK_USEIOSPACE 371 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 372 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 373 #else 374 CSR_WRITE_4(sc, reg, val); 375 #endif 376 return; 377 } 378 379 static void 380 sk_win_write_2(sc, reg, val) 381 struct sk_softc *sc; 382 int reg; 383 u_int32_t val; 384 { 385 #ifdef SK_USEIOSPACE 386 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 387 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 388 #else 389 CSR_WRITE_2(sc, reg, val); 390 #endif 391 return; 392 } 393 394 static void 395 sk_win_write_1(sc, reg, val) 396 struct sk_softc *sc; 397 int reg; 398 u_int32_t val; 399 { 400 #ifdef SK_USEIOSPACE 401 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 402 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 403 #else 404 CSR_WRITE_1(sc, reg, val); 405 #endif 406 return; 407 } 408 409 /* 410 * The VPD EEPROM contains Vital Product Data, as suggested in 411 * the PCI 2.1 specification. The VPD data is separared into areas 412 * denoted by resource IDs. The SysKonnect VPD contains an ID string 413 * resource (the name of the adapter), a read-only area resource 414 * containing various key/data fields and a read/write area which 415 * can be used to store asset management information or log messages. 416 * We read the ID string and read-only into buffers attached to 417 * the controller softc structure for later use. At the moment, 418 * we only use the ID string during skc_attach(). 419 */ 420 static u_int8_t 421 sk_vpd_readbyte(sc, addr) 422 struct sk_softc *sc; 423 int addr; 424 { 425 int i; 426 427 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 428 for (i = 0; i < SK_TIMEOUT; i++) { 429 DELAY(1); 430 if (sk_win_read_2(sc, 431 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 432 break; 433 } 434 435 if (i == SK_TIMEOUT) 436 return(0); 437 438 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 439 } 440 441 static void 442 sk_vpd_read_res(sc, res, addr) 443 struct sk_softc *sc; 444 struct vpd_res *res; 445 int addr; 446 { 447 int i; 448 u_int8_t *ptr; 449 450 ptr = (u_int8_t *)res; 451 for (i = 0; i < sizeof(struct vpd_res); i++) 452 ptr[i] = sk_vpd_readbyte(sc, i + addr); 453 454 return; 455 } 456 457 static void 458 sk_vpd_read(sc) 459 struct sk_softc *sc; 460 { 461 int pos = 0, i; 462 struct vpd_res res; 463 464 if (sc->sk_vpd_prodname != NULL) 465 free(sc->sk_vpd_prodname, M_DEVBUF); 466 if (sc->sk_vpd_readonly != NULL) 467 free(sc->sk_vpd_readonly, M_DEVBUF); 468 sc->sk_vpd_prodname = NULL; 469 sc->sk_vpd_readonly = NULL; 470 471 sk_vpd_read_res(sc, &res, pos); 472 473 /* 474 * Bail out quietly if the eeprom appears to be missing or empty. 475 */ 476 if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff) 477 return; 478 479 if (res.vr_id != VPD_RES_ID) { 480 printf("skc%d: bad VPD resource id: expected %x got %x\n", 481 sc->sk_unit, VPD_RES_ID, res.vr_id); 482 return; 483 } 484 485 pos += sizeof(res); 486 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 487 for (i = 0; i < res.vr_len; i++) 488 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 489 sc->sk_vpd_prodname[i] = '\0'; 490 pos += i; 491 492 sk_vpd_read_res(sc, &res, pos); 493 494 if (res.vr_id != VPD_RES_READ) { 495 printf("skc%d: bad VPD resource id: expected %x got %x\n", 496 sc->sk_unit, VPD_RES_READ, res.vr_id); 497 return; 498 } 499 500 pos += sizeof(res); 501 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 502 for (i = 0; i < res.vr_len + 1; i++) 503 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 504 505 return; 506 } 507 508 static int 509 sk_miibus_readreg(dev, phy, reg) 510 device_t dev; 511 int phy, reg; 512 { 513 struct sk_if_softc *sc_if; 514 515 sc_if = device_get_softc(dev); 516 517 switch(sc_if->sk_softc->sk_type) { 518 case SK_GENESIS: 519 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 520 case SK_YUKON: 521 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 522 } 523 524 return(0); 525 } 526 527 static int 528 sk_miibus_writereg(dev, phy, reg, val) 529 device_t dev; 530 int phy, reg, val; 531 { 532 struct sk_if_softc *sc_if; 533 534 sc_if = device_get_softc(dev); 535 536 switch(sc_if->sk_softc->sk_type) { 537 case SK_GENESIS: 538 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 539 case SK_YUKON: 540 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 541 } 542 543 return(0); 544 } 545 546 static void 547 sk_miibus_statchg(dev) 548 device_t dev; 549 { 550 struct sk_if_softc *sc_if; 551 552 sc_if = device_get_softc(dev); 553 554 switch(sc_if->sk_softc->sk_type) { 555 case SK_GENESIS: 556 sk_xmac_miibus_statchg(sc_if); 557 break; 558 case SK_YUKON: 559 sk_marv_miibus_statchg(sc_if); 560 break; 561 } 562 563 return; 564 } 565 566 static int 567 sk_xmac_miibus_readreg(sc_if, phy, reg) 568 struct sk_if_softc *sc_if; 569 int phy, reg; 570 { 571 int i; 572 573 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 574 return(0); 575 576 SK_IF_LOCK(sc_if); 577 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 578 SK_XM_READ_2(sc_if, XM_PHY_DATA); 579 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 580 for (i = 0; i < SK_TIMEOUT; i++) { 581 DELAY(1); 582 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 583 XM_MMUCMD_PHYDATARDY) 584 break; 585 } 586 587 if (i == SK_TIMEOUT) { 588 printf("sk%d: phy failed to come ready\n", 589 sc_if->sk_unit); 590 SK_IF_UNLOCK(sc_if); 591 return(0); 592 } 593 } 594 DELAY(1); 595 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 596 SK_IF_UNLOCK(sc_if); 597 return(i); 598 } 599 600 static int 601 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 602 struct sk_if_softc *sc_if; 603 int phy, reg, val; 604 { 605 int i; 606 607 SK_IF_LOCK(sc_if); 608 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 609 for (i = 0; i < SK_TIMEOUT; i++) { 610 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 611 break; 612 } 613 614 if (i == SK_TIMEOUT) { 615 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 616 SK_IF_UNLOCK(sc_if); 617 return(ETIMEDOUT); 618 } 619 620 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 621 for (i = 0; i < SK_TIMEOUT; i++) { 622 DELAY(1); 623 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 624 break; 625 } 626 SK_IF_UNLOCK(sc_if); 627 if (i == SK_TIMEOUT) 628 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 629 630 return(0); 631 } 632 633 static void 634 sk_xmac_miibus_statchg(sc_if) 635 struct sk_if_softc *sc_if; 636 { 637 struct mii_data *mii; 638 639 mii = device_get_softc(sc_if->sk_miibus); 640 641 SK_IF_LOCK(sc_if); 642 /* 643 * If this is a GMII PHY, manually set the XMAC's 644 * duplex mode accordingly. 645 */ 646 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 647 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 648 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 649 } else { 650 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 651 } 652 } 653 SK_IF_UNLOCK(sc_if); 654 655 return; 656 } 657 658 static int 659 sk_marv_miibus_readreg(sc_if, phy, reg) 660 struct sk_if_softc *sc_if; 661 int phy, reg; 662 { 663 u_int16_t val; 664 int i; 665 666 if (phy != 0 || 667 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 668 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 669 return(0); 670 } 671 672 SK_IF_LOCK(sc_if); 673 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 674 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 675 676 for (i = 0; i < SK_TIMEOUT; i++) { 677 DELAY(1); 678 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 679 if (val & YU_SMICR_READ_VALID) 680 break; 681 } 682 683 if (i == SK_TIMEOUT) { 684 printf("sk%d: phy failed to come ready\n", 685 sc_if->sk_unit); 686 SK_IF_UNLOCK(sc_if); 687 return(0); 688 } 689 690 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 691 SK_IF_UNLOCK(sc_if); 692 693 return(val); 694 } 695 696 static int 697 sk_marv_miibus_writereg(sc_if, phy, reg, val) 698 struct sk_if_softc *sc_if; 699 int phy, reg, val; 700 { 701 int i; 702 703 SK_IF_LOCK(sc_if); 704 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 705 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 706 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 707 708 for (i = 0; i < SK_TIMEOUT; i++) { 709 DELAY(1); 710 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 711 break; 712 } 713 SK_IF_UNLOCK(sc_if); 714 715 return(0); 716 } 717 718 static void 719 sk_marv_miibus_statchg(sc_if) 720 struct sk_if_softc *sc_if; 721 { 722 return; 723 } 724 725 #define XMAC_POLY 0xEDB88320 726 #define GMAC_POLY 0x04C11DB7L 727 #define HASH_BITS 6 728 729 static u_int32_t 730 sk_xmchash(addr) 731 const uint8_t *addr; 732 { 733 uint32_t crc; 734 int idx, bit; 735 uint8_t data; 736 737 /* Compute CRC for the address value. */ 738 crc = 0xFFFFFFFF; /* initial value */ 739 740 for (idx = 0; idx < 6; idx++) { 741 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 742 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? XMAC_POLY : 0); 743 } 744 745 return (~crc & ((1 << HASH_BITS) - 1)); 746 } 747 748 /* gmchash is just a big endian crc */ 749 static u_int32_t 750 sk_gmchash(addr) 751 const uint8_t *addr; 752 { 753 uint32_t crc, carry; 754 int idx, bit; 755 uint8_t data; 756 757 /* Compute CRC for the address value. */ 758 crc = 0xFFFFFFFF; /* initial value */ 759 760 for (idx = 0; idx < 6; idx++) { 761 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 762 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 763 crc <<= 1; 764 if (carry) 765 crc = (crc ^ GMAC_POLY) | carry; 766 } 767 } 768 769 return (crc & ((1 << HASH_BITS) - 1)); 770 } 771 772 static void 773 sk_setfilt(sc_if, addr, slot) 774 struct sk_if_softc *sc_if; 775 caddr_t addr; 776 int slot; 777 { 778 int base; 779 780 base = XM_RXFILT_ENTRY(slot); 781 782 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 783 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 784 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 785 786 return; 787 } 788 789 static void 790 sk_setmulti(sc_if) 791 struct sk_if_softc *sc_if; 792 { 793 struct sk_softc *sc = sc_if->sk_softc; 794 struct ifnet *ifp = &sc_if->arpcom.ac_if; 795 u_int32_t hashes[2] = { 0, 0 }; 796 int h = 0, i; 797 struct ifmultiaddr *ifma; 798 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 799 800 801 /* First, zot all the existing filters. */ 802 switch(sc->sk_type) { 803 case SK_GENESIS: 804 for (i = 1; i < XM_RXFILT_MAX; i++) 805 sk_setfilt(sc_if, (caddr_t)&dummy, i); 806 807 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 808 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 809 break; 810 case SK_YUKON: 811 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 812 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 813 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 814 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 815 break; 816 } 817 818 /* Now program new ones. */ 819 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 820 hashes[0] = 0xFFFFFFFF; 821 hashes[1] = 0xFFFFFFFF; 822 } else { 823 i = 1; 824 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 825 if (ifma->ifma_addr->sa_family != AF_LINK) 826 continue; 827 /* 828 * Program the first XM_RXFILT_MAX multicast groups 829 * into the perfect filter. For all others, 830 * use the hash table. 831 */ 832 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 833 sk_setfilt(sc_if, 834 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 835 i++; 836 continue; 837 } 838 839 switch(sc->sk_type) { 840 case SK_GENESIS: 841 h = sk_xmchash( 842 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 843 break; 844 case SK_YUKON: 845 h = sk_gmchash( 846 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 847 break; 848 } 849 if (h < 32) 850 hashes[0] |= (1 << h); 851 else 852 hashes[1] |= (1 << (h - 32)); 853 } 854 } 855 856 switch(sc->sk_type) { 857 case SK_GENESIS: 858 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 859 XM_MODE_RX_USE_PERFECT); 860 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 861 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 862 break; 863 case SK_YUKON: 864 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 865 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 866 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 867 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 868 break; 869 } 870 871 return; 872 } 873 874 static void 875 sk_setpromisc(sc_if) 876 struct sk_if_softc *sc_if; 877 { 878 struct sk_softc *sc = sc_if->sk_softc; 879 struct ifnet *ifp = &sc_if->arpcom.ac_if; 880 881 switch(sc->sk_type) { 882 case SK_GENESIS: 883 if (ifp->if_flags & IFF_PROMISC) { 884 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 885 } else { 886 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 887 } 888 break; 889 case SK_YUKON: 890 if (ifp->if_flags & IFF_PROMISC) { 891 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 892 YU_RCR_UFLEN | YU_RCR_MUFLEN); 893 } else { 894 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 895 YU_RCR_UFLEN | YU_RCR_MUFLEN); 896 } 897 break; 898 } 899 900 return; 901 } 902 903 static int 904 sk_init_rx_ring(sc_if) 905 struct sk_if_softc *sc_if; 906 { 907 struct sk_chain_data *cd = &sc_if->sk_cdata; 908 struct sk_ring_data *rd = sc_if->sk_rdata; 909 int i; 910 911 bzero((char *)rd->sk_rx_ring, 912 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 913 914 for (i = 0; i < SK_RX_RING_CNT; i++) { 915 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 916 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 917 return(ENOBUFS); 918 if (i == (SK_RX_RING_CNT - 1)) { 919 cd->sk_rx_chain[i].sk_next = 920 &cd->sk_rx_chain[0]; 921 rd->sk_rx_ring[i].sk_next = 922 vtophys(&rd->sk_rx_ring[0]); 923 } else { 924 cd->sk_rx_chain[i].sk_next = 925 &cd->sk_rx_chain[i + 1]; 926 rd->sk_rx_ring[i].sk_next = 927 vtophys(&rd->sk_rx_ring[i + 1]); 928 } 929 } 930 931 sc_if->sk_cdata.sk_rx_prod = 0; 932 sc_if->sk_cdata.sk_rx_cons = 0; 933 934 return(0); 935 } 936 937 static void 938 sk_init_tx_ring(sc_if) 939 struct sk_if_softc *sc_if; 940 { 941 struct sk_chain_data *cd = &sc_if->sk_cdata; 942 struct sk_ring_data *rd = sc_if->sk_rdata; 943 int i; 944 945 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 946 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 947 948 for (i = 0; i < SK_TX_RING_CNT; i++) { 949 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 950 if (i == (SK_TX_RING_CNT - 1)) { 951 cd->sk_tx_chain[i].sk_next = 952 &cd->sk_tx_chain[0]; 953 rd->sk_tx_ring[i].sk_next = 954 vtophys(&rd->sk_tx_ring[0]); 955 } else { 956 cd->sk_tx_chain[i].sk_next = 957 &cd->sk_tx_chain[i + 1]; 958 rd->sk_tx_ring[i].sk_next = 959 vtophys(&rd->sk_tx_ring[i + 1]); 960 } 961 } 962 963 sc_if->sk_cdata.sk_tx_prod = 0; 964 sc_if->sk_cdata.sk_tx_cons = 0; 965 sc_if->sk_cdata.sk_tx_cnt = 0; 966 967 return; 968 } 969 970 static int 971 sk_newbuf(sc_if, c, m) 972 struct sk_if_softc *sc_if; 973 struct sk_chain *c; 974 struct mbuf *m; 975 { 976 struct mbuf *m_new = NULL; 977 struct sk_rx_desc *r; 978 979 if (m == NULL) { 980 caddr_t *buf = NULL; 981 982 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 983 if (m_new == NULL) 984 return(ENOBUFS); 985 986 /* Allocate the jumbo buffer */ 987 buf = sk_jalloc(sc_if); 988 if (buf == NULL) { 989 m_freem(m_new); 990 #ifdef SK_VERBOSE 991 printf("sk%d: jumbo allocation failed " 992 "-- packet dropped!\n", sc_if->sk_unit); 993 #endif 994 return(ENOBUFS); 995 } 996 997 /* Attach the buffer to the mbuf */ 998 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 999 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 1000 m_new->m_data = (void *)buf; 1001 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 1002 } else { 1003 /* 1004 * We're re-using a previously allocated mbuf; 1005 * be sure to re-init pointers and lengths to 1006 * default values. 1007 */ 1008 m_new = m; 1009 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 1010 m_new->m_data = m_new->m_ext.ext_buf; 1011 } 1012 1013 /* 1014 * Adjust alignment so packet payload begins on a 1015 * longword boundary. Mandatory for Alpha, useful on 1016 * x86 too. 1017 */ 1018 m_adj(m_new, ETHER_ALIGN); 1019 1020 r = c->sk_desc; 1021 c->sk_mbuf = m_new; 1022 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 1023 r->sk_ctl = m_new->m_len | SK_RXSTAT; 1024 1025 return(0); 1026 } 1027 1028 /* 1029 * Allocate jumbo buffer storage. The SysKonnect adapters support 1030 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1031 * use them in their drivers. In order for us to use them, we need 1032 * large 9K receive buffers, however standard mbuf clusters are only 1033 * 2048 bytes in size. Consequently, we need to allocate and manage 1034 * our own jumbo buffer pool. Fortunately, this does not require an 1035 * excessive amount of additional code. 1036 */ 1037 static int 1038 sk_alloc_jumbo_mem(sc_if) 1039 struct sk_if_softc *sc_if; 1040 { 1041 caddr_t ptr; 1042 register int i; 1043 struct sk_jpool_entry *entry; 1044 1045 /* Grab a big chunk o' storage. */ 1046 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 1047 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1048 1049 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 1050 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 1051 return(ENOBUFS); 1052 } 1053 1054 SLIST_INIT(&sc_if->sk_jfree_listhead); 1055 SLIST_INIT(&sc_if->sk_jinuse_listhead); 1056 1057 /* 1058 * Now divide it up into 9K pieces and save the addresses 1059 * in an array. 1060 */ 1061 ptr = sc_if->sk_cdata.sk_jumbo_buf; 1062 for (i = 0; i < SK_JSLOTS; i++) { 1063 sc_if->sk_cdata.sk_jslots[i] = ptr; 1064 ptr += SK_JLEN; 1065 entry = malloc(sizeof(struct sk_jpool_entry), 1066 M_DEVBUF, M_NOWAIT); 1067 if (entry == NULL) { 1068 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 1069 sc_if->sk_cdata.sk_jumbo_buf = NULL; 1070 printf("sk%d: no memory for jumbo " 1071 "buffer queue!\n", sc_if->sk_unit); 1072 return(ENOBUFS); 1073 } 1074 entry->slot = i; 1075 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 1076 entry, jpool_entries); 1077 } 1078 1079 return(0); 1080 } 1081 1082 /* 1083 * Allocate a jumbo buffer. 1084 */ 1085 static void * 1086 sk_jalloc(sc_if) 1087 struct sk_if_softc *sc_if; 1088 { 1089 struct sk_jpool_entry *entry; 1090 1091 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1092 1093 if (entry == NULL) { 1094 #ifdef SK_VERBOSE 1095 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 1096 #endif 1097 return(NULL); 1098 } 1099 1100 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1101 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 1102 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 1103 } 1104 1105 /* 1106 * Release a jumbo buffer. 1107 */ 1108 static void 1109 sk_jfree(buf, args) 1110 void *buf; 1111 void *args; 1112 { 1113 struct sk_if_softc *sc_if; 1114 int i; 1115 struct sk_jpool_entry *entry; 1116 1117 /* Extract the softc struct pointer. */ 1118 sc_if = (struct sk_if_softc *)args; 1119 1120 if (sc_if == NULL) 1121 panic("sk_jfree: didn't get softc pointer!"); 1122 1123 /* calculate the slot this buffer belongs to */ 1124 i = ((vm_offset_t)buf 1125 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1126 1127 if ((i < 0) || (i >= SK_JSLOTS)) 1128 panic("sk_jfree: asked to free buffer that we don't manage!"); 1129 1130 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 1131 if (entry == NULL) 1132 panic("sk_jfree: buffer not in use!"); 1133 entry->slot = i; 1134 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 1135 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 1136 1137 return; 1138 } 1139 1140 /* 1141 * Set media options. 1142 */ 1143 static int 1144 sk_ifmedia_upd(ifp) 1145 struct ifnet *ifp; 1146 { 1147 struct sk_if_softc *sc_if = ifp->if_softc; 1148 struct mii_data *mii; 1149 1150 mii = device_get_softc(sc_if->sk_miibus); 1151 sk_init(sc_if); 1152 mii_mediachg(mii); 1153 1154 return(0); 1155 } 1156 1157 /* 1158 * Report current media status. 1159 */ 1160 static void 1161 sk_ifmedia_sts(ifp, ifmr) 1162 struct ifnet *ifp; 1163 struct ifmediareq *ifmr; 1164 { 1165 struct sk_if_softc *sc_if; 1166 struct mii_data *mii; 1167 1168 sc_if = ifp->if_softc; 1169 mii = device_get_softc(sc_if->sk_miibus); 1170 1171 mii_pollstat(mii); 1172 ifmr->ifm_active = mii->mii_media_active; 1173 ifmr->ifm_status = mii->mii_media_status; 1174 1175 return; 1176 } 1177 1178 static int 1179 sk_ioctl(ifp, command, data) 1180 struct ifnet *ifp; 1181 u_long command; 1182 caddr_t data; 1183 { 1184 struct sk_if_softc *sc_if = ifp->if_softc; 1185 struct ifreq *ifr = (struct ifreq *) data; 1186 int error = 0; 1187 struct mii_data *mii; 1188 1189 SK_IF_LOCK(sc_if); 1190 1191 switch(command) { 1192 case SIOCSIFMTU: 1193 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1194 error = EINVAL; 1195 else { 1196 ifp->if_mtu = ifr->ifr_mtu; 1197 sk_init(sc_if); 1198 } 1199 break; 1200 case SIOCSIFFLAGS: 1201 if (ifp->if_flags & IFF_UP) { 1202 if (ifp->if_flags & IFF_RUNNING) { 1203 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1204 & IFF_PROMISC) { 1205 sk_setpromisc(sc_if); 1206 sk_setmulti(sc_if); 1207 } 1208 } else 1209 sk_init(sc_if); 1210 } else { 1211 if (ifp->if_flags & IFF_RUNNING) 1212 sk_stop(sc_if); 1213 } 1214 sc_if->sk_if_flags = ifp->if_flags; 1215 error = 0; 1216 break; 1217 case SIOCADDMULTI: 1218 case SIOCDELMULTI: 1219 sk_setmulti(sc_if); 1220 error = 0; 1221 break; 1222 case SIOCGIFMEDIA: 1223 case SIOCSIFMEDIA: 1224 mii = device_get_softc(sc_if->sk_miibus); 1225 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1226 break; 1227 default: 1228 error = ether_ioctl(ifp, command, data); 1229 break; 1230 } 1231 1232 SK_IF_UNLOCK(sc_if); 1233 1234 return(error); 1235 } 1236 1237 /* 1238 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1239 * IDs against our list and return a device name if we find a match. 1240 */ 1241 static int 1242 skc_probe(dev) 1243 device_t dev; 1244 { 1245 struct sk_softc *sc; 1246 struct sk_type *t = sk_devs; 1247 1248 sc = device_get_softc(dev); 1249 1250 while(t->sk_name != NULL) { 1251 if ((pci_get_vendor(dev) == t->sk_vid) && 1252 (pci_get_device(dev) == t->sk_did)) { 1253 device_set_desc(dev, t->sk_name); 1254 return(0); 1255 } 1256 t++; 1257 } 1258 1259 return(ENXIO); 1260 } 1261 1262 /* 1263 * Force the GEnesis into reset, then bring it out of reset. 1264 */ 1265 static void 1266 sk_reset(sc) 1267 struct sk_softc *sc; 1268 { 1269 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1270 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1271 if (sc->sk_type == SK_YUKON) 1272 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1273 1274 DELAY(1000); 1275 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1276 DELAY(2); 1277 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1278 if (sc->sk_type == SK_YUKON) 1279 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1280 1281 if (sc->sk_type == SK_GENESIS) { 1282 /* Configure packet arbiter */ 1283 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1284 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1285 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1286 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1287 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1288 } 1289 1290 /* Enable RAM interface */ 1291 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1292 1293 /* 1294 * Configure interrupt moderation. The moderation timer 1295 * defers interrupts specified in the interrupt moderation 1296 * timer mask based on the timeout specified in the interrupt 1297 * moderation timer init register. Each bit in the timer 1298 * register represents 18.825ns, so to specify a timeout in 1299 * microseconds, we have to multiply by 54. 1300 */ 1301 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1302 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1303 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1304 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1305 1306 return; 1307 } 1308 1309 static int 1310 sk_probe(dev) 1311 device_t dev; 1312 { 1313 struct sk_softc *sc; 1314 1315 sc = device_get_softc(device_get_parent(dev)); 1316 1317 /* 1318 * Not much to do here. We always know there will be 1319 * at least one XMAC present, and if there are two, 1320 * skc_attach() will create a second device instance 1321 * for us. 1322 */ 1323 switch (sc->sk_type) { 1324 case SK_GENESIS: 1325 device_set_desc(dev, "XaQti Corp. XMAC II"); 1326 break; 1327 case SK_YUKON: 1328 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1329 break; 1330 } 1331 1332 return(0); 1333 } 1334 1335 /* 1336 * Each XMAC chip is attached as a separate logical IP interface. 1337 * Single port cards will have only one logical interface of course. 1338 */ 1339 static int 1340 sk_attach(dev) 1341 device_t dev; 1342 { 1343 struct sk_softc *sc; 1344 struct sk_if_softc *sc_if; 1345 struct ifnet *ifp; 1346 int i, port, error; 1347 1348 if (dev == NULL) 1349 return(EINVAL); 1350 1351 error = 0; 1352 sc_if = device_get_softc(dev); 1353 sc = device_get_softc(device_get_parent(dev)); 1354 SK_LOCK(sc); 1355 port = *(int *)device_get_ivars(dev); 1356 free(device_get_ivars(dev), M_DEVBUF); 1357 device_set_ivars(dev, NULL); 1358 1359 sc_if->sk_dev = dev; 1360 sc_if->sk_unit = device_get_unit(dev); 1361 sc_if->sk_port = port; 1362 sc_if->sk_softc = sc; 1363 sc->sk_if[port] = sc_if; 1364 if (port == SK_PORT_A) 1365 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1366 if (port == SK_PORT_B) 1367 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1368 1369 /* 1370 * Get station address for this interface. Note that 1371 * dual port cards actually come with three station 1372 * addresses: one for each port, plus an extra. The 1373 * extra one is used by the SysKonnect driver software 1374 * as a 'virtual' station address for when both ports 1375 * are operating in failover mode. Currently we don't 1376 * use this extra address. 1377 */ 1378 for (i = 0; i < ETHER_ADDR_LEN; i++) 1379 sc_if->arpcom.ac_enaddr[i] = 1380 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1381 1382 /* 1383 * Set up RAM buffer addresses. The NIC will have a certain 1384 * amount of SRAM on it, somewhere between 512K and 2MB. We 1385 * need to divide this up a) between the transmitter and 1386 * receiver and b) between the two XMACs, if this is a 1387 * dual port NIC. Our algotithm is to divide up the memory 1388 * evenly so that everyone gets a fair share. 1389 */ 1390 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1391 u_int32_t chunk, val; 1392 1393 chunk = sc->sk_ramsize / 2; 1394 val = sc->sk_rboff / sizeof(u_int64_t); 1395 sc_if->sk_rx_ramstart = val; 1396 val += (chunk / sizeof(u_int64_t)); 1397 sc_if->sk_rx_ramend = val - 1; 1398 sc_if->sk_tx_ramstart = val; 1399 val += (chunk / sizeof(u_int64_t)); 1400 sc_if->sk_tx_ramend = val - 1; 1401 } else { 1402 u_int32_t chunk, val; 1403 1404 chunk = sc->sk_ramsize / 4; 1405 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1406 sizeof(u_int64_t); 1407 sc_if->sk_rx_ramstart = val; 1408 val += (chunk / sizeof(u_int64_t)); 1409 sc_if->sk_rx_ramend = val - 1; 1410 sc_if->sk_tx_ramstart = val; 1411 val += (chunk / sizeof(u_int64_t)); 1412 sc_if->sk_tx_ramend = val - 1; 1413 } 1414 1415 /* Read and save PHY type and set PHY address */ 1416 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1417 switch(sc_if->sk_phytype) { 1418 case SK_PHYTYPE_XMAC: 1419 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1420 break; 1421 case SK_PHYTYPE_BCOM: 1422 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1423 break; 1424 case SK_PHYTYPE_MARV_COPPER: 1425 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1426 break; 1427 default: 1428 printf("skc%d: unsupported PHY type: %d\n", 1429 sc->sk_unit, sc_if->sk_phytype); 1430 error = ENODEV; 1431 goto fail; 1432 } 1433 1434 /* Allocate the descriptor queues. */ 1435 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1436 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1437 1438 if (sc_if->sk_rdata == NULL) { 1439 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1440 error = ENOMEM; 1441 goto fail; 1442 } 1443 1444 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1445 1446 /* Try to allocate memory for jumbo buffers. */ 1447 if (sk_alloc_jumbo_mem(sc_if)) { 1448 printf("sk%d: jumbo buffer allocation failed\n", 1449 sc_if->sk_unit); 1450 error = ENOMEM; 1451 goto fail; 1452 } 1453 1454 ifp = &sc_if->arpcom.ac_if; 1455 ifp->if_softc = sc_if; 1456 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1457 ifp->if_mtu = ETHERMTU; 1458 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1459 ifp->if_ioctl = sk_ioctl; 1460 ifp->if_start = sk_start; 1461 ifp->if_watchdog = sk_watchdog; 1462 ifp->if_init = sk_init; 1463 ifp->if_baudrate = 1000000000; 1464 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1465 1466 callout_handle_init(&sc_if->sk_tick_ch); 1467 1468 /* 1469 * Call MI attach routine. 1470 */ 1471 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1472 1473 /* 1474 * Do miibus setup. 1475 */ 1476 switch (sc->sk_type) { 1477 case SK_GENESIS: 1478 sk_init_xmac(sc_if); 1479 break; 1480 case SK_YUKON: 1481 sk_init_yukon(sc_if); 1482 break; 1483 } 1484 1485 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1486 sk_ifmedia_upd, sk_ifmedia_sts)) { 1487 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1488 ether_ifdetach(ifp); 1489 error = ENXIO; 1490 goto fail; 1491 } 1492 1493 fail: 1494 SK_UNLOCK(sc); 1495 if (error) { 1496 /* Access should be ok even though lock has been dropped */ 1497 sc->sk_if[port] = NULL; 1498 sk_detach(dev); 1499 } 1500 1501 return(error); 1502 } 1503 1504 /* 1505 * Attach the interface. Allocate softc structures, do ifmedia 1506 * setup and ethernet/BPF attach. 1507 */ 1508 static int 1509 skc_attach(dev) 1510 device_t dev; 1511 { 1512 struct sk_softc *sc; 1513 int unit, error = 0, rid, *port; 1514 1515 sc = device_get_softc(dev); 1516 unit = device_get_unit(dev); 1517 1518 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1519 MTX_DEF | MTX_RECURSE); 1520 #ifndef BURN_BRIDGES 1521 /* 1522 * Handle power management nonsense. 1523 */ 1524 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1525 u_int32_t iobase, membase, irq; 1526 1527 /* Save important PCI config data. */ 1528 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1529 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1530 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1531 1532 /* Reset the power state. */ 1533 printf("skc%d: chip is in D%d power mode " 1534 "-- setting to D0\n", unit, 1535 pci_get_powerstate(dev)); 1536 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1537 1538 /* Restore PCI config data. */ 1539 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1540 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1541 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1542 } 1543 #endif 1544 /* 1545 * Map control/status registers. 1546 */ 1547 pci_enable_busmaster(dev); 1548 1549 rid = SK_RID; 1550 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1551 1552 if (sc->sk_res == NULL) { 1553 printf("sk%d: couldn't map ports/memory\n", unit); 1554 error = ENXIO; 1555 goto fail; 1556 } 1557 1558 sc->sk_btag = rman_get_bustag(sc->sk_res); 1559 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1560 1561 /* Allocate interrupt */ 1562 rid = 0; 1563 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1564 RF_SHAREABLE | RF_ACTIVE); 1565 1566 if (sc->sk_irq == NULL) { 1567 printf("skc%d: couldn't map interrupt\n", unit); 1568 error = ENXIO; 1569 goto fail; 1570 } 1571 1572 /* Set adapter type */ 1573 switch (pci_get_device(dev)) { 1574 case DEVICEID_SK_V1: 1575 sc->sk_type = SK_GENESIS; 1576 break; 1577 case DEVICEID_SK_V2: 1578 case DEVICEID_3COM_3C940: 1579 case DEVICEID_LINKSYS_EG1032: 1580 case DEVICEID_DLINK_DGE530T: 1581 sc->sk_type = SK_YUKON; 1582 break; 1583 default: 1584 printf("skc%d: unknown device!\n", unit); 1585 error = ENXIO; 1586 goto fail; 1587 } 1588 1589 /* Reset the adapter. */ 1590 sk_reset(sc); 1591 1592 sc->sk_unit = unit; 1593 1594 /* Read and save vital product data from EEPROM. */ 1595 sk_vpd_read(sc); 1596 1597 if (sc->sk_type == SK_GENESIS) { 1598 /* Read and save RAM size and RAMbuffer offset */ 1599 switch(sk_win_read_1(sc, SK_EPROM0)) { 1600 case SK_RAMSIZE_512K_64: 1601 sc->sk_ramsize = 0x80000; 1602 sc->sk_rboff = SK_RBOFF_0; 1603 break; 1604 case SK_RAMSIZE_1024K_64: 1605 sc->sk_ramsize = 0x100000; 1606 sc->sk_rboff = SK_RBOFF_80000; 1607 break; 1608 case SK_RAMSIZE_1024K_128: 1609 sc->sk_ramsize = 0x100000; 1610 sc->sk_rboff = SK_RBOFF_0; 1611 break; 1612 case SK_RAMSIZE_2048K_128: 1613 sc->sk_ramsize = 0x200000; 1614 sc->sk_rboff = SK_RBOFF_0; 1615 break; 1616 default: 1617 printf("skc%d: unknown ram size: %d\n", 1618 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1619 error = ENXIO; 1620 goto fail; 1621 } 1622 } else { 1623 sc->sk_ramsize = 0x20000; 1624 sc->sk_rboff = SK_RBOFF_0; 1625 } 1626 1627 /* Read and save physical media type */ 1628 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1629 case SK_PMD_1000BASESX: 1630 sc->sk_pmd = IFM_1000_SX; 1631 break; 1632 case SK_PMD_1000BASELX: 1633 sc->sk_pmd = IFM_1000_LX; 1634 break; 1635 case SK_PMD_1000BASECX: 1636 sc->sk_pmd = IFM_1000_CX; 1637 break; 1638 case SK_PMD_1000BASETX: 1639 sc->sk_pmd = IFM_1000_T; 1640 break; 1641 default: 1642 printf("skc%d: unknown media type: 0x%x\n", 1643 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1644 error = ENXIO; 1645 goto fail; 1646 } 1647 1648 /* Announce the product name. */ 1649 if (sc->sk_vpd_prodname != NULL) 1650 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1651 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1652 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1653 *port = SK_PORT_A; 1654 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1655 1656 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1657 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1658 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1659 *port = SK_PORT_B; 1660 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1661 } 1662 1663 /* Turn on the 'driver is loaded' LED. */ 1664 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1665 1666 bus_generic_attach(dev); 1667 1668 /* Hook interrupt last to avoid having to lock softc */ 1669 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1670 sk_intr, sc, &sc->sk_intrhand); 1671 1672 if (error) { 1673 printf("skc%d: couldn't set up irq\n", unit); 1674 goto fail; 1675 } 1676 1677 fail: 1678 if (error) 1679 skc_detach(dev); 1680 1681 return(error); 1682 } 1683 1684 /* 1685 * Shutdown hardware and free up resources. This can be called any 1686 * time after the mutex has been initialized. It is called in both 1687 * the error case in attach and the normal detach case so it needs 1688 * to be careful about only freeing resources that have actually been 1689 * allocated. 1690 */ 1691 static int 1692 sk_detach(dev) 1693 device_t dev; 1694 { 1695 struct sk_if_softc *sc_if; 1696 struct ifnet *ifp; 1697 1698 sc_if = device_get_softc(dev); 1699 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1700 ("sk mutex not initialized in sk_detach")); 1701 SK_IF_LOCK(sc_if); 1702 1703 ifp = &sc_if->arpcom.ac_if; 1704 /* These should only be active if attach_xmac succeeded */ 1705 if (device_is_attached(dev)) { 1706 sk_stop(sc_if); 1707 ether_ifdetach(ifp); 1708 } 1709 if (sc_if->sk_miibus) 1710 device_delete_child(dev, sc_if->sk_miibus); 1711 bus_generic_detach(dev); 1712 if (sc_if->sk_cdata.sk_jumbo_buf) 1713 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1714 if (sc_if->sk_rdata) { 1715 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), 1716 M_DEVBUF); 1717 } 1718 SK_IF_UNLOCK(sc_if); 1719 1720 return(0); 1721 } 1722 1723 static int 1724 skc_detach(dev) 1725 device_t dev; 1726 { 1727 struct sk_softc *sc; 1728 1729 sc = device_get_softc(dev); 1730 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1731 SK_LOCK(sc); 1732 1733 if (device_is_alive(dev)) { 1734 if (sc->sk_devs[SK_PORT_A] != NULL) 1735 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1736 if (sc->sk_devs[SK_PORT_B] != NULL) 1737 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1738 bus_generic_detach(dev); 1739 } 1740 1741 if (sc->sk_intrhand) 1742 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1743 if (sc->sk_irq) 1744 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1745 if (sc->sk_res) 1746 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1747 1748 SK_UNLOCK(sc); 1749 mtx_destroy(&sc->sk_mtx); 1750 1751 return(0); 1752 } 1753 1754 static int 1755 sk_encap(sc_if, m_head, txidx) 1756 struct sk_if_softc *sc_if; 1757 struct mbuf *m_head; 1758 u_int32_t *txidx; 1759 { 1760 struct sk_tx_desc *f = NULL; 1761 struct mbuf *m; 1762 u_int32_t frag, cur, cnt = 0; 1763 1764 m = m_head; 1765 cur = frag = *txidx; 1766 1767 /* 1768 * Start packing the mbufs in this chain into 1769 * the fragment pointers. Stop when we run out 1770 * of fragments or hit the end of the mbuf chain. 1771 */ 1772 for (m = m_head; m != NULL; m = m->m_next) { 1773 if (m->m_len != 0) { 1774 if ((SK_TX_RING_CNT - 1775 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1776 return(ENOBUFS); 1777 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1778 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1779 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1780 if (cnt == 0) 1781 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1782 else 1783 f->sk_ctl |= SK_TXCTL_OWN; 1784 cur = frag; 1785 SK_INC(frag, SK_TX_RING_CNT); 1786 cnt++; 1787 } 1788 } 1789 1790 if (m != NULL) 1791 return(ENOBUFS); 1792 1793 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1794 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1795 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1796 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1797 sc_if->sk_cdata.sk_tx_cnt += cnt; 1798 1799 *txidx = frag; 1800 1801 return(0); 1802 } 1803 1804 static void 1805 sk_start(ifp) 1806 struct ifnet *ifp; 1807 { 1808 struct sk_softc *sc; 1809 struct sk_if_softc *sc_if; 1810 struct mbuf *m_head = NULL; 1811 u_int32_t idx; 1812 1813 sc_if = ifp->if_softc; 1814 sc = sc_if->sk_softc; 1815 1816 SK_IF_LOCK(sc_if); 1817 1818 idx = sc_if->sk_cdata.sk_tx_prod; 1819 1820 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1821 IF_DEQUEUE(&ifp->if_snd, m_head); 1822 if (m_head == NULL) 1823 break; 1824 1825 /* 1826 * Pack the data into the transmit ring. If we 1827 * don't have room, set the OACTIVE flag and wait 1828 * for the NIC to drain the ring. 1829 */ 1830 if (sk_encap(sc_if, m_head, &idx)) { 1831 IF_PREPEND(&ifp->if_snd, m_head); 1832 ifp->if_flags |= IFF_OACTIVE; 1833 break; 1834 } 1835 1836 /* 1837 * If there's a BPF listener, bounce a copy of this frame 1838 * to him. 1839 */ 1840 BPF_MTAP(ifp, m_head); 1841 } 1842 1843 /* Transmit */ 1844 sc_if->sk_cdata.sk_tx_prod = idx; 1845 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1846 1847 /* Set a timeout in case the chip goes out to lunch. */ 1848 ifp->if_timer = 5; 1849 SK_IF_UNLOCK(sc_if); 1850 1851 return; 1852 } 1853 1854 1855 static void 1856 sk_watchdog(ifp) 1857 struct ifnet *ifp; 1858 { 1859 struct sk_if_softc *sc_if; 1860 1861 sc_if = ifp->if_softc; 1862 1863 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1864 sk_init(sc_if); 1865 1866 return; 1867 } 1868 1869 static void 1870 skc_shutdown(dev) 1871 device_t dev; 1872 { 1873 struct sk_softc *sc; 1874 1875 sc = device_get_softc(dev); 1876 SK_LOCK(sc); 1877 1878 /* Turn off the 'driver is loaded' LED. */ 1879 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1880 1881 /* 1882 * Reset the GEnesis controller. Doing this should also 1883 * assert the resets on the attached XMAC(s). 1884 */ 1885 sk_reset(sc); 1886 SK_UNLOCK(sc); 1887 1888 return; 1889 } 1890 1891 static void 1892 sk_rxeof(sc_if) 1893 struct sk_if_softc *sc_if; 1894 { 1895 struct sk_softc *sc; 1896 struct mbuf *m; 1897 struct ifnet *ifp; 1898 struct sk_chain *cur_rx; 1899 int total_len = 0; 1900 int i; 1901 u_int32_t rxstat; 1902 1903 sc = sc_if->sk_softc; 1904 ifp = &sc_if->arpcom.ac_if; 1905 i = sc_if->sk_cdata.sk_rx_prod; 1906 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1907 1908 SK_LOCK_ASSERT(sc); 1909 1910 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1911 1912 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1913 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1914 m = cur_rx->sk_mbuf; 1915 cur_rx->sk_mbuf = NULL; 1916 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1917 SK_INC(i, SK_RX_RING_CNT); 1918 1919 if (rxstat & XM_RXSTAT_ERRFRAME) { 1920 ifp->if_ierrors++; 1921 sk_newbuf(sc_if, cur_rx, m); 1922 continue; 1923 } 1924 1925 /* 1926 * Try to allocate a new jumbo buffer. If that 1927 * fails, copy the packet to mbufs and put the 1928 * jumbo buffer back in the ring so it can be 1929 * re-used. If allocating mbufs fails, then we 1930 * have to drop the packet. 1931 */ 1932 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1933 struct mbuf *m0; 1934 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1935 ifp, NULL); 1936 sk_newbuf(sc_if, cur_rx, m); 1937 if (m0 == NULL) { 1938 printf("sk%d: no receive buffers " 1939 "available -- packet dropped!\n", 1940 sc_if->sk_unit); 1941 ifp->if_ierrors++; 1942 continue; 1943 } 1944 m = m0; 1945 } else { 1946 m->m_pkthdr.rcvif = ifp; 1947 m->m_pkthdr.len = m->m_len = total_len; 1948 } 1949 1950 ifp->if_ipackets++; 1951 SK_UNLOCK(sc); 1952 (*ifp->if_input)(ifp, m); 1953 SK_LOCK(sc); 1954 } 1955 1956 sc_if->sk_cdata.sk_rx_prod = i; 1957 1958 return; 1959 } 1960 1961 static void 1962 sk_txeof(sc_if) 1963 struct sk_if_softc *sc_if; 1964 { 1965 struct sk_tx_desc *cur_tx = NULL; 1966 struct ifnet *ifp; 1967 u_int32_t idx; 1968 1969 ifp = &sc_if->arpcom.ac_if; 1970 1971 /* 1972 * Go through our tx ring and free mbufs for those 1973 * frames that have been sent. 1974 */ 1975 idx = sc_if->sk_cdata.sk_tx_cons; 1976 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1977 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1978 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1979 break; 1980 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1981 ifp->if_opackets++; 1982 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1983 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1984 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1985 } 1986 sc_if->sk_cdata.sk_tx_cnt--; 1987 SK_INC(idx, SK_TX_RING_CNT); 1988 ifp->if_timer = 0; 1989 } 1990 1991 sc_if->sk_cdata.sk_tx_cons = idx; 1992 1993 if (cur_tx != NULL) 1994 ifp->if_flags &= ~IFF_OACTIVE; 1995 1996 return; 1997 } 1998 1999 static void 2000 sk_tick(xsc_if) 2001 void *xsc_if; 2002 { 2003 struct sk_if_softc *sc_if; 2004 struct mii_data *mii; 2005 struct ifnet *ifp; 2006 int i; 2007 2008 sc_if = xsc_if; 2009 SK_IF_LOCK(sc_if); 2010 ifp = &sc_if->arpcom.ac_if; 2011 mii = device_get_softc(sc_if->sk_miibus); 2012 2013 if (!(ifp->if_flags & IFF_UP)) { 2014 SK_IF_UNLOCK(sc_if); 2015 return; 2016 } 2017 2018 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2019 sk_intr_bcom(sc_if); 2020 SK_IF_UNLOCK(sc_if); 2021 return; 2022 } 2023 2024 /* 2025 * According to SysKonnect, the correct way to verify that 2026 * the link has come back up is to poll bit 0 of the GPIO 2027 * register three times. This pin has the signal from the 2028 * link_sync pin connected to it; if we read the same link 2029 * state 3 times in a row, we know the link is up. 2030 */ 2031 for (i = 0; i < 3; i++) { 2032 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2033 break; 2034 } 2035 2036 if (i != 3) { 2037 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2038 SK_IF_UNLOCK(sc_if); 2039 return; 2040 } 2041 2042 /* Turn the GP0 interrupt back on. */ 2043 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2044 SK_XM_READ_2(sc_if, XM_ISR); 2045 mii_tick(mii); 2046 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2047 2048 SK_IF_UNLOCK(sc_if); 2049 return; 2050 } 2051 2052 static void 2053 sk_intr_bcom(sc_if) 2054 struct sk_if_softc *sc_if; 2055 { 2056 struct mii_data *mii; 2057 struct ifnet *ifp; 2058 int status; 2059 mii = device_get_softc(sc_if->sk_miibus); 2060 ifp = &sc_if->arpcom.ac_if; 2061 2062 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2063 2064 /* 2065 * Read the PHY interrupt register to make sure 2066 * we clear any pending interrupts. 2067 */ 2068 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2069 2070 if (!(ifp->if_flags & IFF_RUNNING)) { 2071 sk_init_xmac(sc_if); 2072 return; 2073 } 2074 2075 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2076 int lstat; 2077 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2078 BRGPHY_MII_AUXSTS); 2079 2080 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2081 mii_mediachg(mii); 2082 /* Turn off the link LED. */ 2083 SK_IF_WRITE_1(sc_if, 0, 2084 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2085 sc_if->sk_link = 0; 2086 } else if (status & BRGPHY_ISR_LNK_CHG) { 2087 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2088 BRGPHY_MII_IMR, 0xFF00); 2089 mii_tick(mii); 2090 sc_if->sk_link = 1; 2091 /* Turn on the link LED. */ 2092 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2093 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2094 SK_LINKLED_BLINK_OFF); 2095 } else { 2096 mii_tick(mii); 2097 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2098 } 2099 } 2100 2101 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2102 2103 return; 2104 } 2105 2106 static void 2107 sk_intr_xmac(sc_if) 2108 struct sk_if_softc *sc_if; 2109 { 2110 struct sk_softc *sc; 2111 u_int16_t status; 2112 2113 sc = sc_if->sk_softc; 2114 status = SK_XM_READ_2(sc_if, XM_ISR); 2115 2116 /* 2117 * Link has gone down. Start MII tick timeout to 2118 * watch for link resync. 2119 */ 2120 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2121 if (status & XM_ISR_GP0_SET) { 2122 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2123 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2124 } 2125 2126 if (status & XM_ISR_AUTONEG_DONE) { 2127 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2128 } 2129 } 2130 2131 if (status & XM_IMR_TX_UNDERRUN) 2132 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2133 2134 if (status & XM_IMR_RX_OVERRUN) 2135 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2136 2137 status = SK_XM_READ_2(sc_if, XM_ISR); 2138 2139 return; 2140 } 2141 2142 static void 2143 sk_intr_yukon(sc_if) 2144 struct sk_if_softc *sc_if; 2145 { 2146 int status; 2147 2148 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2149 2150 return; 2151 } 2152 2153 static void 2154 sk_intr(xsc) 2155 void *xsc; 2156 { 2157 struct sk_softc *sc = xsc; 2158 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 2159 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2160 u_int32_t status; 2161 2162 SK_LOCK(sc); 2163 2164 sc_if0 = sc->sk_if[SK_PORT_A]; 2165 sc_if1 = sc->sk_if[SK_PORT_B]; 2166 2167 if (sc_if0 != NULL) 2168 ifp0 = &sc_if0->arpcom.ac_if; 2169 if (sc_if1 != NULL) 2170 ifp1 = &sc_if1->arpcom.ac_if; 2171 2172 for (;;) { 2173 status = CSR_READ_4(sc, SK_ISSR); 2174 if (!(status & sc->sk_intrmask)) 2175 break; 2176 2177 /* Handle receive interrupts first. */ 2178 if (status & SK_ISR_RX1_EOF) { 2179 sk_rxeof(sc_if0); 2180 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2181 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2182 } 2183 if (status & SK_ISR_RX2_EOF) { 2184 sk_rxeof(sc_if1); 2185 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2186 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2187 } 2188 2189 /* Then transmit interrupts. */ 2190 if (status & SK_ISR_TX1_S_EOF) { 2191 sk_txeof(sc_if0); 2192 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2193 SK_TXBMU_CLR_IRQ_EOF); 2194 } 2195 if (status & SK_ISR_TX2_S_EOF) { 2196 sk_txeof(sc_if1); 2197 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2198 SK_TXBMU_CLR_IRQ_EOF); 2199 } 2200 2201 /* Then MAC interrupts. */ 2202 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 2203 if (sc->sk_type == SK_GENESIS) 2204 sk_intr_xmac(sc_if0); 2205 else 2206 sk_intr_yukon(sc_if0); 2207 } 2208 2209 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 2210 if (sc->sk_type == SK_GENESIS) 2211 sk_intr_xmac(sc_if1); 2212 else 2213 sk_intr_yukon(sc_if1); 2214 } 2215 2216 if (status & SK_ISR_EXTERNAL_REG) { 2217 if (ifp0 != NULL && 2218 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2219 sk_intr_bcom(sc_if0); 2220 if (ifp1 != NULL && 2221 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2222 sk_intr_bcom(sc_if1); 2223 } 2224 } 2225 2226 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2227 2228 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 2229 sk_start(ifp0); 2230 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 2231 sk_start(ifp1); 2232 2233 SK_UNLOCK(sc); 2234 2235 return; 2236 } 2237 2238 static void 2239 sk_init_xmac(sc_if) 2240 struct sk_if_softc *sc_if; 2241 { 2242 struct sk_softc *sc; 2243 struct ifnet *ifp; 2244 struct sk_bcom_hack bhack[] = { 2245 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2246 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2247 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2248 { 0, 0 } }; 2249 2250 sc = sc_if->sk_softc; 2251 ifp = &sc_if->arpcom.ac_if; 2252 2253 /* Unreset the XMAC. */ 2254 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2255 DELAY(1000); 2256 2257 /* Reset the XMAC's internal state. */ 2258 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2259 2260 /* Save the XMAC II revision */ 2261 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2262 2263 /* 2264 * Perform additional initialization for external PHYs, 2265 * namely for the 1000baseTX cards that use the XMAC's 2266 * GMII mode. 2267 */ 2268 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2269 int i = 0; 2270 u_int32_t val; 2271 2272 /* Take PHY out of reset. */ 2273 val = sk_win_read_4(sc, SK_GPIO); 2274 if (sc_if->sk_port == SK_PORT_A) 2275 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2276 else 2277 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2278 sk_win_write_4(sc, SK_GPIO, val); 2279 2280 /* Enable GMII mode on the XMAC. */ 2281 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2282 2283 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2284 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2285 DELAY(10000); 2286 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2287 BRGPHY_MII_IMR, 0xFFF0); 2288 2289 /* 2290 * Early versions of the BCM5400 apparently have 2291 * a bug that requires them to have their reserved 2292 * registers initialized to some magic values. I don't 2293 * know what the numbers do, I'm just the messenger. 2294 */ 2295 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2296 == 0x6041) { 2297 while(bhack[i].reg) { 2298 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2299 bhack[i].reg, bhack[i].val); 2300 i++; 2301 } 2302 } 2303 } 2304 2305 /* Set station address */ 2306 SK_XM_WRITE_2(sc_if, XM_PAR0, 2307 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2308 SK_XM_WRITE_2(sc_if, XM_PAR1, 2309 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2310 SK_XM_WRITE_2(sc_if, XM_PAR2, 2311 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2312 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2313 2314 if (ifp->if_flags & IFF_BROADCAST) { 2315 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2316 } else { 2317 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2318 } 2319 2320 /* We don't need the FCS appended to the packet. */ 2321 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2322 2323 /* We want short frames padded to 60 bytes. */ 2324 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2325 2326 /* 2327 * Enable the reception of all error frames. This is is 2328 * a necessary evil due to the design of the XMAC. The 2329 * XMAC's receive FIFO is only 8K in size, however jumbo 2330 * frames can be up to 9000 bytes in length. When bad 2331 * frame filtering is enabled, the XMAC's RX FIFO operates 2332 * in 'store and forward' mode. For this to work, the 2333 * entire frame has to fit into the FIFO, but that means 2334 * that jumbo frames larger than 8192 bytes will be 2335 * truncated. Disabling all bad frame filtering causes 2336 * the RX FIFO to operate in streaming mode, in which 2337 * case the XMAC will start transfering frames out of the 2338 * RX FIFO as soon as the FIFO threshold is reached. 2339 */ 2340 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2341 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2342 XM_MODE_RX_INRANGELEN); 2343 2344 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2345 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2346 else 2347 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2348 2349 /* 2350 * Bump up the transmit threshold. This helps hold off transmit 2351 * underruns when we're blasting traffic from both ports at once. 2352 */ 2353 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2354 2355 /* Set promiscuous mode */ 2356 sk_setpromisc(sc_if); 2357 2358 /* Set multicast filter */ 2359 sk_setmulti(sc_if); 2360 2361 /* Clear and enable interrupts */ 2362 SK_XM_READ_2(sc_if, XM_ISR); 2363 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2364 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2365 else 2366 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2367 2368 /* Configure MAC arbiter */ 2369 switch(sc_if->sk_xmac_rev) { 2370 case XM_XMAC_REV_B2: 2371 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2372 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2373 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2374 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2375 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2376 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2377 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2378 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2379 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2380 break; 2381 case XM_XMAC_REV_C1: 2382 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2383 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2384 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2385 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2386 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2387 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2388 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2389 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2390 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2391 break; 2392 default: 2393 break; 2394 } 2395 sk_win_write_2(sc, SK_MACARB_CTL, 2396 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2397 2398 sc_if->sk_link = 1; 2399 2400 return; 2401 } 2402 2403 static void sk_init_yukon(sc_if) 2404 struct sk_if_softc *sc_if; 2405 { 2406 u_int32_t phy; 2407 u_int16_t reg; 2408 int i; 2409 2410 /* GMAC and GPHY Reset */ 2411 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2412 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2413 DELAY(1000); 2414 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2415 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2416 DELAY(1000); 2417 2418 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2419 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2420 2421 switch(sc_if->sk_softc->sk_pmd) { 2422 case IFM_1000_SX: 2423 case IFM_1000_LX: 2424 phy |= SK_GPHY_FIBER; 2425 break; 2426 2427 case IFM_1000_CX: 2428 case IFM_1000_T: 2429 phy |= SK_GPHY_COPPER; 2430 break; 2431 } 2432 2433 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2434 DELAY(1000); 2435 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2436 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2437 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2438 2439 /* unused read of the interrupt source register */ 2440 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2441 2442 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2443 2444 /* MIB Counter Clear Mode set */ 2445 reg |= YU_PAR_MIB_CLR; 2446 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2447 2448 /* MIB Counter Clear Mode clear */ 2449 reg &= ~YU_PAR_MIB_CLR; 2450 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2451 2452 /* receive control reg */ 2453 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2454 2455 /* transmit parameter register */ 2456 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2457 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2458 2459 /* serial mode register */ 2460 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2461 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2462 2463 /* Setup Yukon's address */ 2464 for (i = 0; i < 3; i++) { 2465 /* Write Source Address 1 (unicast filter) */ 2466 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2467 sc_if->arpcom.ac_enaddr[i * 2] | 2468 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2469 } 2470 2471 for (i = 0; i < 3; i++) { 2472 reg = sk_win_read_2(sc_if->sk_softc, 2473 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2474 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2475 } 2476 2477 /* Set promiscuous mode */ 2478 sk_setpromisc(sc_if); 2479 2480 /* Set multicast filter */ 2481 sk_setmulti(sc_if); 2482 2483 /* enable interrupt mask for counter overflows */ 2484 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2485 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2486 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2487 2488 /* Configure RX MAC FIFO */ 2489 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2490 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2491 2492 /* Configure TX MAC FIFO */ 2493 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2494 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2495 } 2496 2497 /* 2498 * Note that to properly initialize any part of the GEnesis chip, 2499 * you first have to take it out of reset mode. 2500 */ 2501 static void 2502 sk_init(xsc) 2503 void *xsc; 2504 { 2505 struct sk_if_softc *sc_if = xsc; 2506 struct sk_softc *sc; 2507 struct ifnet *ifp; 2508 struct mii_data *mii; 2509 u_int16_t reg; 2510 2511 SK_IF_LOCK(sc_if); 2512 2513 ifp = &sc_if->arpcom.ac_if; 2514 sc = sc_if->sk_softc; 2515 mii = device_get_softc(sc_if->sk_miibus); 2516 2517 /* Cancel pending I/O and free all RX/TX buffers. */ 2518 sk_stop(sc_if); 2519 2520 if (sc->sk_type == SK_GENESIS) { 2521 /* Configure LINK_SYNC LED */ 2522 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2523 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2524 SK_LINKLED_LINKSYNC_ON); 2525 2526 /* Configure RX LED */ 2527 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2528 SK_RXLEDCTL_COUNTER_START); 2529 2530 /* Configure TX LED */ 2531 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2532 SK_TXLEDCTL_COUNTER_START); 2533 } 2534 2535 /* Configure I2C registers */ 2536 2537 /* Configure XMAC(s) */ 2538 switch (sc->sk_type) { 2539 case SK_GENESIS: 2540 sk_init_xmac(sc_if); 2541 break; 2542 case SK_YUKON: 2543 sk_init_yukon(sc_if); 2544 break; 2545 } 2546 mii_mediachg(mii); 2547 2548 if (sc->sk_type == SK_GENESIS) { 2549 /* Configure MAC FIFOs */ 2550 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2551 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2552 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2553 2554 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2555 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2556 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2557 } 2558 2559 /* Configure transmit arbiter(s) */ 2560 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2561 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2562 2563 /* Configure RAMbuffers */ 2564 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2565 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2566 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2567 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2568 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2569 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2570 2571 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2572 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2573 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2574 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2575 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2576 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2577 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2578 2579 /* Configure BMUs */ 2580 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2581 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2582 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2583 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2584 2585 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2586 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2587 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2588 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2589 2590 /* Init descriptors */ 2591 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2592 printf("sk%d: initialization failed: no " 2593 "memory for rx buffers\n", sc_if->sk_unit); 2594 sk_stop(sc_if); 2595 SK_IF_UNLOCK(sc_if); 2596 return; 2597 } 2598 sk_init_tx_ring(sc_if); 2599 2600 /* Configure interrupt handling */ 2601 CSR_READ_4(sc, SK_ISSR); 2602 if (sc_if->sk_port == SK_PORT_A) 2603 sc->sk_intrmask |= SK_INTRS1; 2604 else 2605 sc->sk_intrmask |= SK_INTRS2; 2606 2607 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2608 2609 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2610 2611 /* Start BMUs. */ 2612 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2613 2614 switch(sc->sk_type) { 2615 case SK_GENESIS: 2616 /* Enable XMACs TX and RX state machines */ 2617 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2618 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2619 break; 2620 case SK_YUKON: 2621 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2622 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2623 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2624 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2625 } 2626 2627 ifp->if_flags |= IFF_RUNNING; 2628 ifp->if_flags &= ~IFF_OACTIVE; 2629 2630 SK_IF_UNLOCK(sc_if); 2631 2632 return; 2633 } 2634 2635 static void 2636 sk_stop(sc_if) 2637 struct sk_if_softc *sc_if; 2638 { 2639 int i; 2640 struct sk_softc *sc; 2641 struct ifnet *ifp; 2642 2643 SK_IF_LOCK(sc_if); 2644 sc = sc_if->sk_softc; 2645 ifp = &sc_if->arpcom.ac_if; 2646 2647 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2648 2649 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2650 u_int32_t val; 2651 2652 /* Put PHY back into reset. */ 2653 val = sk_win_read_4(sc, SK_GPIO); 2654 if (sc_if->sk_port == SK_PORT_A) { 2655 val |= SK_GPIO_DIR0; 2656 val &= ~SK_GPIO_DAT0; 2657 } else { 2658 val |= SK_GPIO_DIR2; 2659 val &= ~SK_GPIO_DAT2; 2660 } 2661 sk_win_write_4(sc, SK_GPIO, val); 2662 } 2663 2664 /* Turn off various components of this interface. */ 2665 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2666 switch (sc->sk_type) { 2667 case SK_GENESIS: 2668 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2669 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2670 break; 2671 case SK_YUKON: 2672 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2673 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2674 break; 2675 } 2676 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2677 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2678 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2679 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2680 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2681 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2682 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2683 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2684 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2685 2686 /* Disable interrupts */ 2687 if (sc_if->sk_port == SK_PORT_A) 2688 sc->sk_intrmask &= ~SK_INTRS1; 2689 else 2690 sc->sk_intrmask &= ~SK_INTRS2; 2691 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2692 2693 SK_XM_READ_2(sc_if, XM_ISR); 2694 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2695 2696 /* Free RX and TX mbufs still in the queues. */ 2697 for (i = 0; i < SK_RX_RING_CNT; i++) { 2698 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2699 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2700 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2701 } 2702 } 2703 2704 for (i = 0; i < SK_TX_RING_CNT; i++) { 2705 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2706 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2707 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2708 } 2709 } 2710 2711 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2712 SK_IF_UNLOCK(sc_if); 2713 return; 2714 } 2715