1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /*- 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 /* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/module.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/sysctl.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/bus_pio.h> 110 #include <machine/bus_memio.h> 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #include <dev/mii/brgphyreg.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 123 #if 0 124 #define SK_USEIOSPACE 125 #endif 126 127 #include <pci/if_skreg.h> 128 #include <pci/xmaciireg.h> 129 #include <pci/yukonreg.h> 130 131 MODULE_DEPEND(sk, pci, 1, 1, 1); 132 MODULE_DEPEND(sk, ether, 1, 1, 1); 133 MODULE_DEPEND(sk, miibus, 1, 1, 1); 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 #ifndef lint 139 static const char rcsid[] = 140 "$FreeBSD$"; 141 #endif 142 143 static struct sk_type sk_devs[] = { 144 { 145 VENDORID_SK, 146 DEVICEID_SK_V1, 147 "SysKonnect Gigabit Ethernet (V1.0)" 148 }, 149 { 150 VENDORID_SK, 151 DEVICEID_SK_V2, 152 "SysKonnect Gigabit Ethernet (V2.0)" 153 }, 154 { 155 VENDORID_MARVELL, 156 DEVICEID_SK_V2, 157 "Marvell Gigabit Ethernet" 158 }, 159 { 160 VENDORID_MARVELL, 161 DEVICEID_BELKIN_5005, 162 "Belkin F5D5005 Gigabit Ethernet" 163 }, 164 { 165 VENDORID_3COM, 166 DEVICEID_3COM_3C940, 167 "3Com 3C940 Gigabit Ethernet" 168 }, 169 { 170 VENDORID_LINKSYS, 171 DEVICEID_LINKSYS_EG1032, 172 "Linksys EG1032 Gigabit Ethernet" 173 }, 174 { 175 VENDORID_DLINK, 176 DEVICEID_DLINK_DGE530T, 177 "D-Link DGE-530T Gigabit Ethernet" 178 }, 179 { 0, 0, NULL } 180 }; 181 182 static int skc_probe(device_t); 183 static int skc_attach(device_t); 184 static int skc_detach(device_t); 185 static void skc_shutdown(device_t); 186 static int sk_detach(device_t); 187 static int sk_probe(device_t); 188 static int sk_attach(device_t); 189 static void sk_tick(void *); 190 static void sk_intr(void *); 191 static void sk_intr_xmac(struct sk_if_softc *); 192 static void sk_intr_bcom(struct sk_if_softc *); 193 static void sk_intr_yukon(struct sk_if_softc *); 194 static void sk_rxeof(struct sk_if_softc *); 195 static void sk_txeof(struct sk_if_softc *); 196 static int sk_encap(struct sk_if_softc *, struct mbuf *, 197 u_int32_t *); 198 static void sk_start(struct ifnet *); 199 static int sk_ioctl(struct ifnet *, u_long, caddr_t); 200 static void sk_init(void *); 201 static void sk_init_xmac(struct sk_if_softc *); 202 static void sk_init_yukon(struct sk_if_softc *); 203 static void sk_stop(struct sk_if_softc *); 204 static void sk_watchdog(struct ifnet *); 205 static int sk_ifmedia_upd(struct ifnet *); 206 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 207 static void sk_reset(struct sk_softc *); 208 static int sk_newbuf(struct sk_if_softc *, 209 struct sk_chain *, struct mbuf *); 210 static int sk_alloc_jumbo_mem(struct sk_if_softc *); 211 static void sk_free_jumbo_mem(struct sk_if_softc *); 212 static void *sk_jalloc(struct sk_if_softc *); 213 static void sk_jfree(void *, void *); 214 static int sk_init_rx_ring(struct sk_if_softc *); 215 static void sk_init_tx_ring(struct sk_if_softc *); 216 static u_int32_t sk_win_read_4(struct sk_softc *, int); 217 static u_int16_t sk_win_read_2(struct sk_softc *, int); 218 static u_int8_t sk_win_read_1(struct sk_softc *, int); 219 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 220 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 221 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 222 static u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 223 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 224 static void sk_vpd_read(struct sk_softc *); 225 226 static int sk_miibus_readreg(device_t, int, int); 227 static int sk_miibus_writereg(device_t, int, int, int); 228 static void sk_miibus_statchg(device_t); 229 230 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 231 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 232 int); 233 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 234 235 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 236 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 237 int); 238 static void sk_marv_miibus_statchg(struct sk_if_softc *); 239 240 static uint32_t sk_xmchash(const uint8_t *); 241 static uint32_t sk_gmchash(const uint8_t *); 242 static void sk_setfilt(struct sk_if_softc *, caddr_t, int); 243 static void sk_setmulti(struct sk_if_softc *); 244 static void sk_setpromisc(struct sk_if_softc *); 245 246 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 247 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 248 249 #ifdef SK_USEIOSPACE 250 #define SK_RES SYS_RES_IOPORT 251 #define SK_RID SK_PCI_LOIO 252 #else 253 #define SK_RES SYS_RES_MEMORY 254 #define SK_RID SK_PCI_LOMEM 255 #endif 256 257 /* 258 * Note that we have newbus methods for both the GEnesis controller 259 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 260 * the miibus code is a child of the XMACs. We need to do it this way 261 * so that the miibus drivers can access the PHY registers on the 262 * right PHY. It's not quite what I had in mind, but it's the only 263 * design that achieves the desired effect. 264 */ 265 static device_method_t skc_methods[] = { 266 /* Device interface */ 267 DEVMETHOD(device_probe, skc_probe), 268 DEVMETHOD(device_attach, skc_attach), 269 DEVMETHOD(device_detach, skc_detach), 270 DEVMETHOD(device_shutdown, skc_shutdown), 271 272 /* bus interface */ 273 DEVMETHOD(bus_print_child, bus_generic_print_child), 274 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 275 276 { 0, 0 } 277 }; 278 279 static driver_t skc_driver = { 280 "skc", 281 skc_methods, 282 sizeof(struct sk_softc) 283 }; 284 285 static devclass_t skc_devclass; 286 287 static device_method_t sk_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, sk_probe), 290 DEVMETHOD(device_attach, sk_attach), 291 DEVMETHOD(device_detach, sk_detach), 292 DEVMETHOD(device_shutdown, bus_generic_shutdown), 293 294 /* bus interface */ 295 DEVMETHOD(bus_print_child, bus_generic_print_child), 296 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 297 298 /* MII interface */ 299 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 300 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 301 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 302 303 { 0, 0 } 304 }; 305 306 static driver_t sk_driver = { 307 "sk", 308 sk_methods, 309 sizeof(struct sk_if_softc) 310 }; 311 312 static devclass_t sk_devclass; 313 314 DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0); 315 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 316 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 317 318 #define SK_SETBIT(sc, reg, x) \ 319 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 320 321 #define SK_CLRBIT(sc, reg, x) \ 322 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 323 324 #define SK_WIN_SETBIT_4(sc, reg, x) \ 325 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 326 327 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 328 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 329 330 #define SK_WIN_SETBIT_2(sc, reg, x) \ 331 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 332 333 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 334 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 335 336 static u_int32_t 337 sk_win_read_4(sc, reg) 338 struct sk_softc *sc; 339 int reg; 340 { 341 #ifdef SK_USEIOSPACE 342 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 343 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 344 #else 345 return(CSR_READ_4(sc, reg)); 346 #endif 347 } 348 349 static u_int16_t 350 sk_win_read_2(sc, reg) 351 struct sk_softc *sc; 352 int reg; 353 { 354 #ifdef SK_USEIOSPACE 355 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 356 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 357 #else 358 return(CSR_READ_2(sc, reg)); 359 #endif 360 } 361 362 static u_int8_t 363 sk_win_read_1(sc, reg) 364 struct sk_softc *sc; 365 int reg; 366 { 367 #ifdef SK_USEIOSPACE 368 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 369 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 370 #else 371 return(CSR_READ_1(sc, reg)); 372 #endif 373 } 374 375 static void 376 sk_win_write_4(sc, reg, val) 377 struct sk_softc *sc; 378 int reg; 379 u_int32_t val; 380 { 381 #ifdef SK_USEIOSPACE 382 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 383 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 384 #else 385 CSR_WRITE_4(sc, reg, val); 386 #endif 387 return; 388 } 389 390 static void 391 sk_win_write_2(sc, reg, val) 392 struct sk_softc *sc; 393 int reg; 394 u_int32_t val; 395 { 396 #ifdef SK_USEIOSPACE 397 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 398 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 399 #else 400 CSR_WRITE_2(sc, reg, val); 401 #endif 402 return; 403 } 404 405 static void 406 sk_win_write_1(sc, reg, val) 407 struct sk_softc *sc; 408 int reg; 409 u_int32_t val; 410 { 411 #ifdef SK_USEIOSPACE 412 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 413 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 414 #else 415 CSR_WRITE_1(sc, reg, val); 416 #endif 417 return; 418 } 419 420 /* 421 * The VPD EEPROM contains Vital Product Data, as suggested in 422 * the PCI 2.1 specification. The VPD data is separared into areas 423 * denoted by resource IDs. The SysKonnect VPD contains an ID string 424 * resource (the name of the adapter), a read-only area resource 425 * containing various key/data fields and a read/write area which 426 * can be used to store asset management information or log messages. 427 * We read the ID string and read-only into buffers attached to 428 * the controller softc structure for later use. At the moment, 429 * we only use the ID string during skc_attach(). 430 */ 431 static u_int8_t 432 sk_vpd_readbyte(sc, addr) 433 struct sk_softc *sc; 434 int addr; 435 { 436 int i; 437 438 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 439 for (i = 0; i < SK_TIMEOUT; i++) { 440 DELAY(1); 441 if (sk_win_read_2(sc, 442 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 443 break; 444 } 445 446 if (i == SK_TIMEOUT) 447 return(0); 448 449 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 450 } 451 452 static void 453 sk_vpd_read_res(sc, res, addr) 454 struct sk_softc *sc; 455 struct vpd_res *res; 456 int addr; 457 { 458 int i; 459 u_int8_t *ptr; 460 461 ptr = (u_int8_t *)res; 462 for (i = 0; i < sizeof(struct vpd_res); i++) 463 ptr[i] = sk_vpd_readbyte(sc, i + addr); 464 465 return; 466 } 467 468 static void 469 sk_vpd_read(sc) 470 struct sk_softc *sc; 471 { 472 int pos = 0, i; 473 struct vpd_res res; 474 475 if (sc->sk_vpd_prodname != NULL) 476 free(sc->sk_vpd_prodname, M_DEVBUF); 477 if (sc->sk_vpd_readonly != NULL) 478 free(sc->sk_vpd_readonly, M_DEVBUF); 479 sc->sk_vpd_prodname = NULL; 480 sc->sk_vpd_readonly = NULL; 481 sc->sk_vpd_readonly_len = 0; 482 483 sk_vpd_read_res(sc, &res, pos); 484 485 /* 486 * Bail out quietly if the eeprom appears to be missing or empty. 487 */ 488 if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff) 489 return; 490 491 if (res.vr_id != VPD_RES_ID) { 492 printf("skc%d: bad VPD resource id: expected %x got %x\n", 493 sc->sk_unit, VPD_RES_ID, res.vr_id); 494 return; 495 } 496 497 pos += sizeof(res); 498 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 499 if (sc->sk_vpd_prodname != NULL) { 500 for (i = 0; i < res.vr_len; i++) 501 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 502 sc->sk_vpd_prodname[i] = '\0'; 503 } 504 pos += res.vr_len; 505 506 sk_vpd_read_res(sc, &res, pos); 507 508 if (res.vr_id != VPD_RES_READ) { 509 printf("skc%d: bad VPD resource id: expected %x got %x\n", 510 sc->sk_unit, VPD_RES_READ, res.vr_id); 511 return; 512 } 513 514 pos += sizeof(res); 515 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 516 for (i = 0; i < res.vr_len; i++) 517 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 518 sc->sk_vpd_readonly_len = res.vr_len; 519 520 return; 521 } 522 523 static int 524 sk_miibus_readreg(dev, phy, reg) 525 device_t dev; 526 int phy, reg; 527 { 528 struct sk_if_softc *sc_if; 529 530 sc_if = device_get_softc(dev); 531 532 switch(sc_if->sk_softc->sk_type) { 533 case SK_GENESIS: 534 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 535 case SK_YUKON: 536 case SK_YUKON_LITE: 537 case SK_YUKON_LP: 538 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 539 } 540 541 return(0); 542 } 543 544 static int 545 sk_miibus_writereg(dev, phy, reg, val) 546 device_t dev; 547 int phy, reg, val; 548 { 549 struct sk_if_softc *sc_if; 550 551 sc_if = device_get_softc(dev); 552 553 switch(sc_if->sk_softc->sk_type) { 554 case SK_GENESIS: 555 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 556 case SK_YUKON: 557 case SK_YUKON_LITE: 558 case SK_YUKON_LP: 559 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 560 } 561 562 return(0); 563 } 564 565 static void 566 sk_miibus_statchg(dev) 567 device_t dev; 568 { 569 struct sk_if_softc *sc_if; 570 571 sc_if = device_get_softc(dev); 572 573 switch(sc_if->sk_softc->sk_type) { 574 case SK_GENESIS: 575 sk_xmac_miibus_statchg(sc_if); 576 break; 577 case SK_YUKON: 578 case SK_YUKON_LITE: 579 case SK_YUKON_LP: 580 sk_marv_miibus_statchg(sc_if); 581 break; 582 } 583 584 return; 585 } 586 587 static int 588 sk_xmac_miibus_readreg(sc_if, phy, reg) 589 struct sk_if_softc *sc_if; 590 int phy, reg; 591 { 592 int i; 593 594 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 595 return(0); 596 597 SK_IF_LOCK(sc_if); 598 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 599 SK_XM_READ_2(sc_if, XM_PHY_DATA); 600 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 601 for (i = 0; i < SK_TIMEOUT; i++) { 602 DELAY(1); 603 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 604 XM_MMUCMD_PHYDATARDY) 605 break; 606 } 607 608 if (i == SK_TIMEOUT) { 609 printf("sk%d: phy failed to come ready\n", 610 sc_if->sk_unit); 611 SK_IF_UNLOCK(sc_if); 612 return(0); 613 } 614 } 615 DELAY(1); 616 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 617 SK_IF_UNLOCK(sc_if); 618 return(i); 619 } 620 621 static int 622 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 623 struct sk_if_softc *sc_if; 624 int phy, reg, val; 625 { 626 int i; 627 628 SK_IF_LOCK(sc_if); 629 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 630 for (i = 0; i < SK_TIMEOUT; i++) { 631 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 632 break; 633 } 634 635 if (i == SK_TIMEOUT) { 636 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 637 SK_IF_UNLOCK(sc_if); 638 return(ETIMEDOUT); 639 } 640 641 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 642 for (i = 0; i < SK_TIMEOUT; i++) { 643 DELAY(1); 644 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 645 break; 646 } 647 SK_IF_UNLOCK(sc_if); 648 if (i == SK_TIMEOUT) 649 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 650 651 return(0); 652 } 653 654 static void 655 sk_xmac_miibus_statchg(sc_if) 656 struct sk_if_softc *sc_if; 657 { 658 struct mii_data *mii; 659 660 mii = device_get_softc(sc_if->sk_miibus); 661 662 SK_IF_LOCK(sc_if); 663 /* 664 * If this is a GMII PHY, manually set the XMAC's 665 * duplex mode accordingly. 666 */ 667 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 668 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 669 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 670 } else { 671 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 672 } 673 } 674 SK_IF_UNLOCK(sc_if); 675 676 return; 677 } 678 679 static int 680 sk_marv_miibus_readreg(sc_if, phy, reg) 681 struct sk_if_softc *sc_if; 682 int phy, reg; 683 { 684 u_int16_t val; 685 int i; 686 687 if (phy != 0 || 688 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 689 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 690 return(0); 691 } 692 693 SK_IF_LOCK(sc_if); 694 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 695 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 696 697 for (i = 0; i < SK_TIMEOUT; i++) { 698 DELAY(1); 699 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 700 if (val & YU_SMICR_READ_VALID) 701 break; 702 } 703 704 if (i == SK_TIMEOUT) { 705 printf("sk%d: phy failed to come ready\n", 706 sc_if->sk_unit); 707 SK_IF_UNLOCK(sc_if); 708 return(0); 709 } 710 711 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 712 SK_IF_UNLOCK(sc_if); 713 714 return(val); 715 } 716 717 static int 718 sk_marv_miibus_writereg(sc_if, phy, reg, val) 719 struct sk_if_softc *sc_if; 720 int phy, reg, val; 721 { 722 int i; 723 724 SK_IF_LOCK(sc_if); 725 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 726 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 727 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 728 729 for (i = 0; i < SK_TIMEOUT; i++) { 730 DELAY(1); 731 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 732 break; 733 } 734 SK_IF_UNLOCK(sc_if); 735 736 return(0); 737 } 738 739 static void 740 sk_marv_miibus_statchg(sc_if) 741 struct sk_if_softc *sc_if; 742 { 743 return; 744 } 745 746 #define HASH_BITS 6 747 748 static u_int32_t 749 sk_xmchash(addr) 750 const uint8_t *addr; 751 { 752 uint32_t crc; 753 754 /* Compute CRC for the address value. */ 755 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 756 757 return (~crc & ((1 << HASH_BITS) - 1)); 758 } 759 760 /* gmchash is just a big endian crc */ 761 static u_int32_t 762 sk_gmchash(addr) 763 const uint8_t *addr; 764 { 765 uint32_t crc; 766 767 /* Compute CRC for the address value. */ 768 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 769 770 return (crc & ((1 << HASH_BITS) - 1)); 771 } 772 773 static void 774 sk_setfilt(sc_if, addr, slot) 775 struct sk_if_softc *sc_if; 776 caddr_t addr; 777 int slot; 778 { 779 int base; 780 781 base = XM_RXFILT_ENTRY(slot); 782 783 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 784 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 785 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 786 787 return; 788 } 789 790 static void 791 sk_setmulti(sc_if) 792 struct sk_if_softc *sc_if; 793 { 794 struct sk_softc *sc = sc_if->sk_softc; 795 struct ifnet *ifp = &sc_if->arpcom.ac_if; 796 u_int32_t hashes[2] = { 0, 0 }; 797 int h = 0, i; 798 struct ifmultiaddr *ifma; 799 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 800 801 802 /* First, zot all the existing filters. */ 803 switch(sc->sk_type) { 804 case SK_GENESIS: 805 for (i = 1; i < XM_RXFILT_MAX; i++) 806 sk_setfilt(sc_if, (caddr_t)&dummy, i); 807 808 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 809 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 810 break; 811 case SK_YUKON: 812 case SK_YUKON_LITE: 813 case SK_YUKON_LP: 814 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 815 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 816 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 817 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 818 break; 819 } 820 821 /* Now program new ones. */ 822 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 823 hashes[0] = 0xFFFFFFFF; 824 hashes[1] = 0xFFFFFFFF; 825 } else { 826 i = 1; 827 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 828 if (ifma->ifma_addr->sa_family != AF_LINK) 829 continue; 830 /* 831 * Program the first XM_RXFILT_MAX multicast groups 832 * into the perfect filter. For all others, 833 * use the hash table. 834 */ 835 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 836 sk_setfilt(sc_if, 837 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 838 i++; 839 continue; 840 } 841 842 switch(sc->sk_type) { 843 case SK_GENESIS: 844 h = sk_xmchash( 845 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 846 break; 847 case SK_YUKON: 848 case SK_YUKON_LITE: 849 case SK_YUKON_LP: 850 h = sk_gmchash( 851 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 852 break; 853 } 854 if (h < 32) 855 hashes[0] |= (1 << h); 856 else 857 hashes[1] |= (1 << (h - 32)); 858 } 859 } 860 861 switch(sc->sk_type) { 862 case SK_GENESIS: 863 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 864 XM_MODE_RX_USE_PERFECT); 865 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 866 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 867 break; 868 case SK_YUKON: 869 case SK_YUKON_LITE: 870 case SK_YUKON_LP: 871 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 872 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 873 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 874 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 875 break; 876 } 877 878 return; 879 } 880 881 static void 882 sk_setpromisc(sc_if) 883 struct sk_if_softc *sc_if; 884 { 885 struct sk_softc *sc = sc_if->sk_softc; 886 struct ifnet *ifp = &sc_if->arpcom.ac_if; 887 888 switch(sc->sk_type) { 889 case SK_GENESIS: 890 if (ifp->if_flags & IFF_PROMISC) { 891 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 892 } else { 893 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 894 } 895 break; 896 case SK_YUKON: 897 case SK_YUKON_LITE: 898 case SK_YUKON_LP: 899 if (ifp->if_flags & IFF_PROMISC) { 900 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 901 YU_RCR_UFLEN | YU_RCR_MUFLEN); 902 } else { 903 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 904 YU_RCR_UFLEN | YU_RCR_MUFLEN); 905 } 906 break; 907 } 908 909 return; 910 } 911 912 static int 913 sk_init_rx_ring(sc_if) 914 struct sk_if_softc *sc_if; 915 { 916 struct sk_chain_data *cd = &sc_if->sk_cdata; 917 struct sk_ring_data *rd = sc_if->sk_rdata; 918 int i; 919 920 bzero((char *)rd->sk_rx_ring, 921 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 922 923 for (i = 0; i < SK_RX_RING_CNT; i++) { 924 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 925 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 926 return(ENOBUFS); 927 if (i == (SK_RX_RING_CNT - 1)) { 928 cd->sk_rx_chain[i].sk_next = 929 &cd->sk_rx_chain[0]; 930 rd->sk_rx_ring[i].sk_next = 931 vtophys(&rd->sk_rx_ring[0]); 932 } else { 933 cd->sk_rx_chain[i].sk_next = 934 &cd->sk_rx_chain[i + 1]; 935 rd->sk_rx_ring[i].sk_next = 936 vtophys(&rd->sk_rx_ring[i + 1]); 937 } 938 } 939 940 sc_if->sk_cdata.sk_rx_prod = 0; 941 sc_if->sk_cdata.sk_rx_cons = 0; 942 943 return(0); 944 } 945 946 static void 947 sk_init_tx_ring(sc_if) 948 struct sk_if_softc *sc_if; 949 { 950 struct sk_chain_data *cd = &sc_if->sk_cdata; 951 struct sk_ring_data *rd = sc_if->sk_rdata; 952 int i; 953 954 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 955 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 956 957 for (i = 0; i < SK_TX_RING_CNT; i++) { 958 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 959 if (i == (SK_TX_RING_CNT - 1)) { 960 cd->sk_tx_chain[i].sk_next = 961 &cd->sk_tx_chain[0]; 962 rd->sk_tx_ring[i].sk_next = 963 vtophys(&rd->sk_tx_ring[0]); 964 } else { 965 cd->sk_tx_chain[i].sk_next = 966 &cd->sk_tx_chain[i + 1]; 967 rd->sk_tx_ring[i].sk_next = 968 vtophys(&rd->sk_tx_ring[i + 1]); 969 } 970 } 971 972 sc_if->sk_cdata.sk_tx_prod = 0; 973 sc_if->sk_cdata.sk_tx_cons = 0; 974 sc_if->sk_cdata.sk_tx_cnt = 0; 975 976 return; 977 } 978 979 static int 980 sk_newbuf(sc_if, c, m) 981 struct sk_if_softc *sc_if; 982 struct sk_chain *c; 983 struct mbuf *m; 984 { 985 struct mbuf *m_new = NULL; 986 struct sk_rx_desc *r; 987 988 if (m == NULL) { 989 caddr_t *buf = NULL; 990 991 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 992 if (m_new == NULL) 993 return(ENOBUFS); 994 995 /* Allocate the jumbo buffer */ 996 buf = sk_jalloc(sc_if); 997 if (buf == NULL) { 998 m_freem(m_new); 999 #ifdef SK_VERBOSE 1000 printf("sk%d: jumbo allocation failed " 1001 "-- packet dropped!\n", sc_if->sk_unit); 1002 #endif 1003 return(ENOBUFS); 1004 } 1005 1006 /* Attach the buffer to the mbuf */ 1007 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 1008 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 1009 m_new->m_data = (void *)buf; 1010 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 1011 } else { 1012 /* 1013 * We're re-using a previously allocated mbuf; 1014 * be sure to re-init pointers and lengths to 1015 * default values. 1016 */ 1017 m_new = m; 1018 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 1019 m_new->m_data = m_new->m_ext.ext_buf; 1020 } 1021 1022 /* 1023 * Adjust alignment so packet payload begins on a 1024 * longword boundary. Mandatory for Alpha, useful on 1025 * x86 too. 1026 */ 1027 m_adj(m_new, ETHER_ALIGN); 1028 1029 r = c->sk_desc; 1030 c->sk_mbuf = m_new; 1031 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 1032 r->sk_ctl = m_new->m_len | SK_RXSTAT; 1033 1034 return(0); 1035 } 1036 1037 /* 1038 * Allocate jumbo buffer storage. The SysKonnect adapters support 1039 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1040 * use them in their drivers. In order for us to use them, we need 1041 * large 9K receive buffers, however standard mbuf clusters are only 1042 * 2048 bytes in size. Consequently, we need to allocate and manage 1043 * our own jumbo buffer pool. Fortunately, this does not require an 1044 * excessive amount of additional code. 1045 */ 1046 static int 1047 sk_alloc_jumbo_mem(sc_if) 1048 struct sk_if_softc *sc_if; 1049 { 1050 caddr_t ptr; 1051 register int i; 1052 struct sk_jpool_entry *entry; 1053 1054 /* Grab a big chunk o' storage. */ 1055 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 1056 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1057 1058 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 1059 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 1060 return(ENOBUFS); 1061 } 1062 1063 mtx_init(&sc_if->sk_jlist_mtx, "sk_jlist_mtx", NULL, MTX_DEF); 1064 1065 SLIST_INIT(&sc_if->sk_jfree_listhead); 1066 SLIST_INIT(&sc_if->sk_jinuse_listhead); 1067 1068 /* 1069 * Now divide it up into 9K pieces and save the addresses 1070 * in an array. 1071 */ 1072 ptr = sc_if->sk_cdata.sk_jumbo_buf; 1073 for (i = 0; i < SK_JSLOTS; i++) { 1074 sc_if->sk_cdata.sk_jslots[i] = ptr; 1075 ptr += SK_JLEN; 1076 entry = malloc(sizeof(struct sk_jpool_entry), 1077 M_DEVBUF, M_NOWAIT); 1078 if (entry == NULL) { 1079 sk_free_jumbo_mem(sc_if); 1080 sc_if->sk_cdata.sk_jumbo_buf = NULL; 1081 printf("sk%d: no memory for jumbo " 1082 "buffer queue!\n", sc_if->sk_unit); 1083 return(ENOBUFS); 1084 } 1085 entry->slot = i; 1086 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 1087 entry, jpool_entries); 1088 } 1089 1090 return(0); 1091 } 1092 1093 static void 1094 sk_free_jumbo_mem(sc_if) 1095 struct sk_if_softc *sc_if; 1096 { 1097 struct sk_jpool_entry *entry; 1098 1099 SK_JLIST_LOCK(sc_if); 1100 1101 /* We cannot release external mbuf storage while in use. */ 1102 if (!SLIST_EMPTY(&sc_if->sk_jinuse_listhead)) { 1103 printf("sk%d: will leak jumbo buffer memory!\n", sc_if->sk_unit); 1104 SK_JLIST_UNLOCK(sc_if); 1105 return; 1106 } 1107 1108 while (!SLIST_EMPTY(&sc_if->sk_jfree_listhead)) { 1109 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1110 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1111 free(entry, M_DEVBUF); 1112 } 1113 1114 SK_JLIST_UNLOCK(sc_if); 1115 1116 mtx_destroy(&sc_if->sk_jlist_mtx); 1117 1118 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1119 1120 return; 1121 } 1122 1123 /* 1124 * Allocate a jumbo buffer. 1125 */ 1126 static void * 1127 sk_jalloc(sc_if) 1128 struct sk_if_softc *sc_if; 1129 { 1130 struct sk_jpool_entry *entry; 1131 1132 SK_JLIST_LOCK(sc_if); 1133 1134 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1135 1136 if (entry == NULL) { 1137 #ifdef SK_VERBOSE 1138 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 1139 #endif 1140 SK_JLIST_UNLOCK(sc_if); 1141 return(NULL); 1142 } 1143 1144 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1145 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 1146 1147 SK_JLIST_UNLOCK(sc_if); 1148 1149 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 1150 } 1151 1152 /* 1153 * Release a jumbo buffer. 1154 */ 1155 static void 1156 sk_jfree(buf, args) 1157 void *buf; 1158 void *args; 1159 { 1160 struct sk_if_softc *sc_if; 1161 int i; 1162 struct sk_jpool_entry *entry; 1163 1164 /* Extract the softc struct pointer. */ 1165 sc_if = (struct sk_if_softc *)args; 1166 if (sc_if == NULL) 1167 panic("sk_jfree: didn't get softc pointer!"); 1168 1169 SK_JLIST_LOCK(sc_if); 1170 1171 /* calculate the slot this buffer belongs to */ 1172 i = ((vm_offset_t)buf 1173 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1174 1175 if ((i < 0) || (i >= SK_JSLOTS)) 1176 panic("sk_jfree: asked to free buffer that we don't manage!"); 1177 1178 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 1179 if (entry == NULL) 1180 panic("sk_jfree: buffer not in use!"); 1181 entry->slot = i; 1182 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 1183 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 1184 if (SLIST_EMPTY(&sc_if->sk_jinuse_listhead)) 1185 wakeup(sc_if); 1186 1187 SK_JLIST_UNLOCK(sc_if); 1188 return; 1189 } 1190 1191 /* 1192 * Set media options. 1193 */ 1194 static int 1195 sk_ifmedia_upd(ifp) 1196 struct ifnet *ifp; 1197 { 1198 struct sk_if_softc *sc_if = ifp->if_softc; 1199 struct mii_data *mii; 1200 1201 mii = device_get_softc(sc_if->sk_miibus); 1202 sk_init(sc_if); 1203 mii_mediachg(mii); 1204 1205 return(0); 1206 } 1207 1208 /* 1209 * Report current media status. 1210 */ 1211 static void 1212 sk_ifmedia_sts(ifp, ifmr) 1213 struct ifnet *ifp; 1214 struct ifmediareq *ifmr; 1215 { 1216 struct sk_if_softc *sc_if; 1217 struct mii_data *mii; 1218 1219 sc_if = ifp->if_softc; 1220 mii = device_get_softc(sc_if->sk_miibus); 1221 1222 mii_pollstat(mii); 1223 ifmr->ifm_active = mii->mii_media_active; 1224 ifmr->ifm_status = mii->mii_media_status; 1225 1226 return; 1227 } 1228 1229 static int 1230 sk_ioctl(ifp, command, data) 1231 struct ifnet *ifp; 1232 u_long command; 1233 caddr_t data; 1234 { 1235 struct sk_if_softc *sc_if = ifp->if_softc; 1236 struct ifreq *ifr = (struct ifreq *) data; 1237 int error = 0; 1238 struct mii_data *mii; 1239 1240 switch(command) { 1241 case SIOCSIFMTU: 1242 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1243 error = EINVAL; 1244 else { 1245 ifp->if_mtu = ifr->ifr_mtu; 1246 ifp->if_flags &= ~IFF_RUNNING; 1247 sk_init(sc_if); 1248 } 1249 break; 1250 case SIOCSIFFLAGS: 1251 SK_IF_LOCK(sc_if); 1252 if (ifp->if_flags & IFF_UP) { 1253 if (ifp->if_flags & IFF_RUNNING) { 1254 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1255 & IFF_PROMISC) { 1256 sk_setpromisc(sc_if); 1257 sk_setmulti(sc_if); 1258 } 1259 } else 1260 sk_init(sc_if); 1261 } else { 1262 if (ifp->if_flags & IFF_RUNNING) 1263 sk_stop(sc_if); 1264 } 1265 sc_if->sk_if_flags = ifp->if_flags; 1266 SK_IF_UNLOCK(sc_if); 1267 error = 0; 1268 break; 1269 case SIOCADDMULTI: 1270 case SIOCDELMULTI: 1271 if (ifp->if_flags & IFF_RUNNING) { 1272 SK_IF_LOCK(sc_if); 1273 sk_setmulti(sc_if); 1274 SK_IF_UNLOCK(sc_if); 1275 error = 0; 1276 } 1277 break; 1278 case SIOCGIFMEDIA: 1279 case SIOCSIFMEDIA: 1280 mii = device_get_softc(sc_if->sk_miibus); 1281 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1282 break; 1283 default: 1284 error = ether_ioctl(ifp, command, data); 1285 break; 1286 } 1287 1288 return(error); 1289 } 1290 1291 /* 1292 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1293 * IDs against our list and return a device name if we find a match. 1294 */ 1295 static int 1296 skc_probe(dev) 1297 device_t dev; 1298 { 1299 struct sk_softc *sc; 1300 struct sk_type *t = sk_devs; 1301 1302 sc = device_get_softc(dev); 1303 1304 while(t->sk_name != NULL) { 1305 if ((pci_get_vendor(dev) == t->sk_vid) && 1306 (pci_get_device(dev) == t->sk_did)) { 1307 device_set_desc(dev, t->sk_name); 1308 return (BUS_PROBE_DEFAULT); 1309 } 1310 t++; 1311 } 1312 1313 return(ENXIO); 1314 } 1315 1316 /* 1317 * Force the GEnesis into reset, then bring it out of reset. 1318 */ 1319 static void 1320 sk_reset(sc) 1321 struct sk_softc *sc; 1322 { 1323 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1324 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1325 if (SK_YUKON_FAMILY(sc->sk_type)) 1326 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1327 1328 DELAY(1000); 1329 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1330 DELAY(2); 1331 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1332 if (SK_YUKON_FAMILY(sc->sk_type)) 1333 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1334 1335 if (sc->sk_type == SK_GENESIS) { 1336 /* Configure packet arbiter */ 1337 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1338 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1339 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1340 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1341 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1342 } 1343 1344 /* Enable RAM interface */ 1345 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1346 1347 /* 1348 * Configure interrupt moderation. The moderation timer 1349 * defers interrupts specified in the interrupt moderation 1350 * timer mask based on the timeout specified in the interrupt 1351 * moderation timer init register. Each bit in the timer 1352 * register represents 18.825ns, so to specify a timeout in 1353 * microseconds, we have to multiply by 54. 1354 */ 1355 printf("skc%d: interrupt moderation is %d us\n", 1356 sc->sk_unit, sc->sk_int_mod); 1357 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1358 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1359 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1360 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1361 1362 return; 1363 } 1364 1365 static int 1366 sk_probe(dev) 1367 device_t dev; 1368 { 1369 struct sk_softc *sc; 1370 1371 sc = device_get_softc(device_get_parent(dev)); 1372 1373 /* 1374 * Not much to do here. We always know there will be 1375 * at least one XMAC present, and if there are two, 1376 * skc_attach() will create a second device instance 1377 * for us. 1378 */ 1379 switch (sc->sk_type) { 1380 case SK_GENESIS: 1381 device_set_desc(dev, "XaQti Corp. XMAC II"); 1382 break; 1383 case SK_YUKON: 1384 case SK_YUKON_LITE: 1385 case SK_YUKON_LP: 1386 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1387 break; 1388 } 1389 1390 return (BUS_PROBE_DEFAULT); 1391 } 1392 1393 /* 1394 * Each XMAC chip is attached as a separate logical IP interface. 1395 * Single port cards will have only one logical interface of course. 1396 */ 1397 static int 1398 sk_attach(dev) 1399 device_t dev; 1400 { 1401 struct sk_softc *sc; 1402 struct sk_if_softc *sc_if; 1403 struct ifnet *ifp; 1404 int i, port, error; 1405 1406 if (dev == NULL) 1407 return(EINVAL); 1408 1409 error = 0; 1410 sc_if = device_get_softc(dev); 1411 sc = device_get_softc(device_get_parent(dev)); 1412 port = *(int *)device_get_ivars(dev); 1413 1414 sc_if->sk_dev = dev; 1415 sc_if->sk_unit = device_get_unit(dev); 1416 sc_if->sk_port = port; 1417 sc_if->sk_softc = sc; 1418 sc->sk_if[port] = sc_if; 1419 if (port == SK_PORT_A) 1420 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1421 if (port == SK_PORT_B) 1422 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1423 1424 /* Allocate the descriptor queues. */ 1425 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1426 M_NOWAIT, M_ZERO, 0xffffffff, PAGE_SIZE, 0); 1427 1428 if (sc_if->sk_rdata == NULL) { 1429 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1430 error = ENOMEM; 1431 goto fail; 1432 } 1433 1434 /* Try to allocate memory for jumbo buffers. */ 1435 if (sk_alloc_jumbo_mem(sc_if)) { 1436 printf("sk%d: jumbo buffer allocation failed\n", 1437 sc_if->sk_unit); 1438 error = ENOMEM; 1439 goto fail; 1440 } 1441 1442 ifp = &sc_if->arpcom.ac_if; 1443 ifp->if_softc = sc_if; 1444 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1445 ifp->if_mtu = ETHERMTU; 1446 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1447 ifp->if_ioctl = sk_ioctl; 1448 ifp->if_start = sk_start; 1449 ifp->if_watchdog = sk_watchdog; 1450 ifp->if_init = sk_init; 1451 ifp->if_baudrate = 1000000000; 1452 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1453 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1454 IFQ_SET_READY(&ifp->if_snd); 1455 1456 callout_handle_init(&sc_if->sk_tick_ch); 1457 1458 /* 1459 * Get station address for this interface. Note that 1460 * dual port cards actually come with three station 1461 * addresses: one for each port, plus an extra. The 1462 * extra one is used by the SysKonnect driver software 1463 * as a 'virtual' station address for when both ports 1464 * are operating in failover mode. Currently we don't 1465 * use this extra address. 1466 */ 1467 SK_LOCK(sc); 1468 for (i = 0; i < ETHER_ADDR_LEN; i++) 1469 sc_if->arpcom.ac_enaddr[i] = 1470 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1471 1472 /* 1473 * Set up RAM buffer addresses. The NIC will have a certain 1474 * amount of SRAM on it, somewhere between 512K and 2MB. We 1475 * need to divide this up a) between the transmitter and 1476 * receiver and b) between the two XMACs, if this is a 1477 * dual port NIC. Our algotithm is to divide up the memory 1478 * evenly so that everyone gets a fair share. 1479 */ 1480 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1481 u_int32_t chunk, val; 1482 1483 chunk = sc->sk_ramsize / 2; 1484 val = sc->sk_rboff / sizeof(u_int64_t); 1485 sc_if->sk_rx_ramstart = val; 1486 val += (chunk / sizeof(u_int64_t)); 1487 sc_if->sk_rx_ramend = val - 1; 1488 sc_if->sk_tx_ramstart = val; 1489 val += (chunk / sizeof(u_int64_t)); 1490 sc_if->sk_tx_ramend = val - 1; 1491 } else { 1492 u_int32_t chunk, val; 1493 1494 chunk = sc->sk_ramsize / 4; 1495 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1496 sizeof(u_int64_t); 1497 sc_if->sk_rx_ramstart = val; 1498 val += (chunk / sizeof(u_int64_t)); 1499 sc_if->sk_rx_ramend = val - 1; 1500 sc_if->sk_tx_ramstart = val; 1501 val += (chunk / sizeof(u_int64_t)); 1502 sc_if->sk_tx_ramend = val - 1; 1503 } 1504 1505 /* Read and save PHY type and set PHY address */ 1506 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1507 switch(sc_if->sk_phytype) { 1508 case SK_PHYTYPE_XMAC: 1509 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1510 break; 1511 case SK_PHYTYPE_BCOM: 1512 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1513 break; 1514 case SK_PHYTYPE_MARV_COPPER: 1515 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1516 break; 1517 default: 1518 printf("skc%d: unsupported PHY type: %d\n", 1519 sc->sk_unit, sc_if->sk_phytype); 1520 error = ENODEV; 1521 SK_UNLOCK(sc); 1522 goto fail; 1523 } 1524 1525 1526 /* 1527 * Call MI attach routine. Can't hold locks when calling into ether_*. 1528 */ 1529 SK_UNLOCK(sc); 1530 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1531 SK_LOCK(sc); 1532 1533 /* 1534 * Do miibus setup. 1535 */ 1536 switch (sc->sk_type) { 1537 case SK_GENESIS: 1538 sk_init_xmac(sc_if); 1539 break; 1540 case SK_YUKON: 1541 case SK_YUKON_LITE: 1542 case SK_YUKON_LP: 1543 sk_init_yukon(sc_if); 1544 break; 1545 } 1546 1547 SK_UNLOCK(sc); 1548 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1549 sk_ifmedia_upd, sk_ifmedia_sts)) { 1550 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1551 ether_ifdetach(ifp); 1552 error = ENXIO; 1553 goto fail; 1554 } 1555 1556 fail: 1557 if (error) { 1558 /* Access should be ok even though lock has been dropped */ 1559 sc->sk_if[port] = NULL; 1560 sk_detach(dev); 1561 } 1562 1563 return(error); 1564 } 1565 1566 /* 1567 * Attach the interface. Allocate softc structures, do ifmedia 1568 * setup and ethernet/BPF attach. 1569 */ 1570 static int 1571 skc_attach(dev) 1572 device_t dev; 1573 { 1574 struct sk_softc *sc; 1575 int unit, error = 0, rid, *port; 1576 uint8_t skrs; 1577 char *pname, *revstr; 1578 1579 sc = device_get_softc(dev); 1580 unit = device_get_unit(dev); 1581 1582 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1583 MTX_DEF | MTX_RECURSE); 1584 /* 1585 * Map control/status registers. 1586 */ 1587 pci_enable_busmaster(dev); 1588 1589 rid = SK_RID; 1590 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1591 1592 if (sc->sk_res == NULL) { 1593 printf("sk%d: couldn't map ports/memory\n", unit); 1594 error = ENXIO; 1595 goto fail; 1596 } 1597 1598 sc->sk_btag = rman_get_bustag(sc->sk_res); 1599 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1600 1601 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1602 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1603 1604 /* Bail out if chip is not recognized. */ 1605 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1606 printf("skc%d: unknown device: chipver=%02x, rev=%x\n", 1607 unit, sc->sk_type, sc->sk_rev); 1608 error = ENXIO; 1609 goto fail; 1610 } 1611 1612 /* Allocate interrupt */ 1613 rid = 0; 1614 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1615 RF_SHAREABLE | RF_ACTIVE); 1616 1617 if (sc->sk_irq == NULL) { 1618 printf("skc%d: couldn't map interrupt\n", unit); 1619 error = ENXIO; 1620 goto fail; 1621 } 1622 1623 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1624 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1625 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW, 1626 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1627 "SK interrupt moderation"); 1628 1629 /* Pull in device tunables. */ 1630 sc->sk_int_mod = SK_IM_DEFAULT; 1631 error = resource_int_value(device_get_name(dev), unit, 1632 "int_mod", &sc->sk_int_mod); 1633 if (error == 0) { 1634 if (sc->sk_int_mod < SK_IM_MIN || 1635 sc->sk_int_mod > SK_IM_MAX) { 1636 printf("skc%d: int_mod value out of range; " 1637 "using default: %d\n", unit, SK_IM_DEFAULT); 1638 sc->sk_int_mod = SK_IM_DEFAULT; 1639 } 1640 } 1641 1642 /* Reset the adapter. */ 1643 sk_reset(sc); 1644 1645 sc->sk_unit = unit; 1646 1647 /* Read and save vital product data from EEPROM. */ 1648 sk_vpd_read(sc); 1649 1650 skrs = sk_win_read_1(sc, SK_EPROM0); 1651 if (sc->sk_type == SK_GENESIS) { 1652 /* Read and save RAM size and RAMbuffer offset */ 1653 switch(skrs) { 1654 case SK_RAMSIZE_512K_64: 1655 sc->sk_ramsize = 0x80000; 1656 sc->sk_rboff = SK_RBOFF_0; 1657 break; 1658 case SK_RAMSIZE_1024K_64: 1659 sc->sk_ramsize = 0x100000; 1660 sc->sk_rboff = SK_RBOFF_80000; 1661 break; 1662 case SK_RAMSIZE_1024K_128: 1663 sc->sk_ramsize = 0x100000; 1664 sc->sk_rboff = SK_RBOFF_0; 1665 break; 1666 case SK_RAMSIZE_2048K_128: 1667 sc->sk_ramsize = 0x200000; 1668 sc->sk_rboff = SK_RBOFF_0; 1669 break; 1670 default: 1671 printf("skc%d: unknown ram size: %d\n", 1672 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1673 error = ENXIO; 1674 goto fail; 1675 } 1676 } else { /* SK_YUKON_FAMILY */ 1677 if (skrs == 0x00) 1678 sc->sk_ramsize = 0x20000; 1679 else 1680 sc->sk_ramsize = skrs * (1<<12); 1681 sc->sk_rboff = SK_RBOFF_0; 1682 } 1683 1684 /* Read and save physical media type */ 1685 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1686 case SK_PMD_1000BASESX: 1687 sc->sk_pmd = IFM_1000_SX; 1688 break; 1689 case SK_PMD_1000BASELX: 1690 sc->sk_pmd = IFM_1000_LX; 1691 break; 1692 case SK_PMD_1000BASECX: 1693 sc->sk_pmd = IFM_1000_CX; 1694 break; 1695 case SK_PMD_1000BASETX: 1696 sc->sk_pmd = IFM_1000_T; 1697 break; 1698 default: 1699 printf("skc%d: unknown media type: 0x%x\n", 1700 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1701 error = ENXIO; 1702 goto fail; 1703 } 1704 1705 /* Determine whether to name it with VPD PN or just make it up. 1706 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1707 switch (pci_get_device(dev)) { 1708 case DEVICEID_SK_V1: 1709 case DEVICEID_BELKIN_5005: 1710 case DEVICEID_3COM_3C940: 1711 case DEVICEID_LINKSYS_EG1032: 1712 case DEVICEID_DLINK_DGE530T: 1713 /* Stay with VPD PN. */ 1714 pname = sc->sk_vpd_prodname; 1715 break; 1716 case DEVICEID_SK_V2: 1717 /* YUKON VPD PN might bear no resemblance to reality. */ 1718 switch (sc->sk_type) { 1719 case SK_GENESIS: 1720 /* Stay with VPD PN. */ 1721 pname = sc->sk_vpd_prodname; 1722 break; 1723 case SK_YUKON: 1724 pname = "Marvell Yukon Gigabit Ethernet"; 1725 break; 1726 case SK_YUKON_LITE: 1727 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1728 break; 1729 case SK_YUKON_LP: 1730 pname = "Marvell Yukon LP Gigabit Ethernet"; 1731 break; 1732 default: 1733 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1734 break; 1735 } 1736 1737 /* Yukon Lite Rev. A0 needs special test. */ 1738 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1739 u_int32_t far; 1740 u_int8_t testbyte; 1741 1742 /* Save flash address register before testing. */ 1743 far = sk_win_read_4(sc, SK_EP_ADDR); 1744 1745 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1746 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1747 1748 if (testbyte != 0x00) { 1749 /* Yukon Lite Rev. A0 detected. */ 1750 sc->sk_type = SK_YUKON_LITE; 1751 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1752 /* Restore flash address register. */ 1753 sk_win_write_4(sc, SK_EP_ADDR, far); 1754 } 1755 } 1756 break; 1757 default: 1758 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1759 "chipver=%02x, rev=%x\n", 1760 pci_get_vendor(dev), pci_get_device(dev), 1761 sc->sk_type, sc->sk_rev); 1762 error = ENXIO; 1763 goto fail; 1764 } 1765 1766 if (sc->sk_type == SK_YUKON_LITE) { 1767 switch (sc->sk_rev) { 1768 case SK_YUKON_LITE_REV_A0: 1769 revstr = "A0"; 1770 break; 1771 case SK_YUKON_LITE_REV_A1: 1772 revstr = "A1"; 1773 break; 1774 case SK_YUKON_LITE_REV_A3: 1775 revstr = "A3"; 1776 break; 1777 default: 1778 revstr = ""; 1779 break; 1780 } 1781 } else { 1782 revstr = ""; 1783 } 1784 1785 /* Announce the product name and more VPD data if there. */ 1786 device_printf(dev, "%s rev. %s(0x%x)\n", 1787 pname != NULL ? pname : "<unknown>", revstr, sc->sk_rev); 1788 1789 if (bootverbose) { 1790 if (sc->sk_vpd_readonly != NULL && 1791 sc->sk_vpd_readonly_len != 0) { 1792 char buf[256]; 1793 char *dp = sc->sk_vpd_readonly; 1794 uint16_t l, len = sc->sk_vpd_readonly_len; 1795 1796 while (len >= 3) { 1797 if ((*dp == 'P' && *(dp+1) == 'N') || 1798 (*dp == 'E' && *(dp+1) == 'C') || 1799 (*dp == 'M' && *(dp+1) == 'N') || 1800 (*dp == 'S' && *(dp+1) == 'N')) { 1801 l = 0; 1802 while (l < *(dp+2)) { 1803 buf[l] = *(dp+3+l); 1804 ++l; 1805 } 1806 buf[l] = '\0'; 1807 device_printf(dev, "%c%c: %s\n", 1808 *dp, *(dp+1), buf); 1809 len -= (3 + l); 1810 dp += (3 + l); 1811 } else { 1812 len -= (3 + *(dp+2)); 1813 dp += (3 + *(dp+2)); 1814 } 1815 } 1816 } 1817 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1818 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1819 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1820 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1821 } 1822 1823 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1824 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1825 *port = SK_PORT_A; 1826 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1827 1828 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1829 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1830 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1831 *port = SK_PORT_B; 1832 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1833 } 1834 1835 /* Turn on the 'driver is loaded' LED. */ 1836 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1837 1838 bus_generic_attach(dev); 1839 1840 /* Hook interrupt last to avoid having to lock softc */ 1841 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET|INTR_MPSAFE, 1842 sk_intr, sc, &sc->sk_intrhand); 1843 1844 if (error) { 1845 printf("skc%d: couldn't set up irq\n", unit); 1846 goto fail; 1847 } 1848 1849 fail: 1850 if (error) 1851 skc_detach(dev); 1852 1853 return(error); 1854 } 1855 1856 /* 1857 * Shutdown hardware and free up resources. This can be called any 1858 * time after the mutex has been initialized. It is called in both 1859 * the error case in attach and the normal detach case so it needs 1860 * to be careful about only freeing resources that have actually been 1861 * allocated. 1862 */ 1863 static int 1864 sk_detach(dev) 1865 device_t dev; 1866 { 1867 struct sk_if_softc *sc_if; 1868 struct ifnet *ifp; 1869 1870 sc_if = device_get_softc(dev); 1871 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1872 ("sk mutex not initialized in sk_detach")); 1873 SK_IF_LOCK(sc_if); 1874 1875 ifp = &sc_if->arpcom.ac_if; 1876 /* These should only be active if attach_xmac succeeded */ 1877 if (device_is_attached(dev)) { 1878 sk_stop(sc_if); 1879 /* Can't hold locks while calling detach */ 1880 SK_IF_UNLOCK(sc_if); 1881 ether_ifdetach(ifp); 1882 SK_IF_LOCK(sc_if); 1883 } 1884 /* 1885 * We're generally called from skc_detach() which is using 1886 * device_delete_child() to get to here. It's already trashed 1887 * miibus for us, so don't do it here or we'll panic. 1888 */ 1889 /* 1890 if (sc_if->sk_miibus != NULL) 1891 device_delete_child(dev, sc_if->sk_miibus); 1892 */ 1893 bus_generic_detach(dev); 1894 if (sc_if->sk_cdata.sk_jumbo_buf != NULL) 1895 sk_free_jumbo_mem(sc_if); 1896 if (sc_if->sk_rdata != NULL) { 1897 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), 1898 M_DEVBUF); 1899 } 1900 SK_IF_UNLOCK(sc_if); 1901 1902 return(0); 1903 } 1904 1905 static int 1906 skc_detach(dev) 1907 device_t dev; 1908 { 1909 struct sk_softc *sc; 1910 1911 sc = device_get_softc(dev); 1912 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1913 1914 if (device_is_alive(dev)) { 1915 if (sc->sk_devs[SK_PORT_A] != NULL) { 1916 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 1917 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1918 } 1919 if (sc->sk_devs[SK_PORT_B] != NULL) { 1920 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 1921 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1922 } 1923 bus_generic_detach(dev); 1924 } 1925 1926 if (sc->sk_vpd_prodname != NULL) 1927 free(sc->sk_vpd_prodname, M_DEVBUF); 1928 if (sc->sk_vpd_readonly != NULL) 1929 free(sc->sk_vpd_readonly, M_DEVBUF); 1930 1931 if (sc->sk_intrhand) 1932 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1933 if (sc->sk_irq) 1934 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1935 if (sc->sk_res) 1936 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1937 1938 mtx_destroy(&sc->sk_mtx); 1939 1940 return(0); 1941 } 1942 1943 static int 1944 sk_encap(sc_if, m_head, txidx) 1945 struct sk_if_softc *sc_if; 1946 struct mbuf *m_head; 1947 u_int32_t *txidx; 1948 { 1949 struct sk_tx_desc *f = NULL; 1950 struct mbuf *m; 1951 u_int32_t frag, cur, cnt = 0; 1952 1953 SK_IF_LOCK_ASSERT(sc_if); 1954 1955 m = m_head; 1956 cur = frag = *txidx; 1957 1958 /* 1959 * Start packing the mbufs in this chain into 1960 * the fragment pointers. Stop when we run out 1961 * of fragments or hit the end of the mbuf chain. 1962 */ 1963 for (m = m_head; m != NULL; m = m->m_next) { 1964 if (m->m_len != 0) { 1965 if ((SK_TX_RING_CNT - 1966 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1967 return(ENOBUFS); 1968 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1969 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1970 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1971 if (cnt == 0) 1972 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1973 else 1974 f->sk_ctl |= SK_TXCTL_OWN; 1975 cur = frag; 1976 SK_INC(frag, SK_TX_RING_CNT); 1977 cnt++; 1978 } 1979 } 1980 1981 if (m != NULL) 1982 return(ENOBUFS); 1983 1984 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1985 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1986 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1987 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1988 sc_if->sk_cdata.sk_tx_cnt += cnt; 1989 1990 *txidx = frag; 1991 1992 return(0); 1993 } 1994 1995 static void 1996 sk_start(ifp) 1997 struct ifnet *ifp; 1998 { 1999 struct sk_softc *sc; 2000 struct sk_if_softc *sc_if; 2001 struct mbuf *m_head = NULL; 2002 u_int32_t idx; 2003 2004 sc_if = ifp->if_softc; 2005 sc = sc_if->sk_softc; 2006 2007 SK_IF_LOCK(sc_if); 2008 2009 idx = sc_if->sk_cdata.sk_tx_prod; 2010 2011 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 2012 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2013 if (m_head == NULL) 2014 break; 2015 2016 /* 2017 * Pack the data into the transmit ring. If we 2018 * don't have room, set the OACTIVE flag and wait 2019 * for the NIC to drain the ring. 2020 */ 2021 if (sk_encap(sc_if, m_head, &idx)) { 2022 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2023 ifp->if_flags |= IFF_OACTIVE; 2024 break; 2025 } 2026 2027 /* 2028 * If there's a BPF listener, bounce a copy of this frame 2029 * to him. 2030 */ 2031 BPF_MTAP(ifp, m_head); 2032 } 2033 2034 /* Transmit */ 2035 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2036 sc_if->sk_cdata.sk_tx_prod = idx; 2037 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2038 2039 /* Set a timeout in case the chip goes out to lunch. */ 2040 ifp->if_timer = 5; 2041 } 2042 SK_IF_UNLOCK(sc_if); 2043 2044 return; 2045 } 2046 2047 2048 static void 2049 sk_watchdog(ifp) 2050 struct ifnet *ifp; 2051 { 2052 struct sk_if_softc *sc_if; 2053 2054 sc_if = ifp->if_softc; 2055 2056 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 2057 ifp->if_flags &= ~IFF_RUNNING; 2058 sk_init(sc_if); 2059 2060 return; 2061 } 2062 2063 static void 2064 skc_shutdown(dev) 2065 device_t dev; 2066 { 2067 struct sk_softc *sc; 2068 2069 sc = device_get_softc(dev); 2070 SK_LOCK(sc); 2071 2072 /* Turn off the 'driver is loaded' LED. */ 2073 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2074 2075 /* 2076 * Reset the GEnesis controller. Doing this should also 2077 * assert the resets on the attached XMAC(s). 2078 */ 2079 sk_reset(sc); 2080 SK_UNLOCK(sc); 2081 2082 return; 2083 } 2084 2085 static void 2086 sk_rxeof(sc_if) 2087 struct sk_if_softc *sc_if; 2088 { 2089 struct sk_softc *sc; 2090 struct mbuf *m; 2091 struct ifnet *ifp; 2092 struct sk_chain *cur_rx; 2093 int total_len = 0; 2094 int i; 2095 u_int32_t rxstat; 2096 2097 sc = sc_if->sk_softc; 2098 ifp = &sc_if->arpcom.ac_if; 2099 i = sc_if->sk_cdata.sk_rx_prod; 2100 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 2101 2102 SK_LOCK_ASSERT(sc); 2103 2104 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 2105 2106 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 2107 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 2108 m = cur_rx->sk_mbuf; 2109 cur_rx->sk_mbuf = NULL; 2110 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 2111 SK_INC(i, SK_RX_RING_CNT); 2112 2113 if (rxstat & XM_RXSTAT_ERRFRAME) { 2114 ifp->if_ierrors++; 2115 sk_newbuf(sc_if, cur_rx, m); 2116 continue; 2117 } 2118 2119 /* 2120 * Try to allocate a new jumbo buffer. If that 2121 * fails, copy the packet to mbufs and put the 2122 * jumbo buffer back in the ring so it can be 2123 * re-used. If allocating mbufs fails, then we 2124 * have to drop the packet. 2125 */ 2126 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 2127 struct mbuf *m0; 2128 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 2129 ifp, NULL); 2130 sk_newbuf(sc_if, cur_rx, m); 2131 if (m0 == NULL) { 2132 printf("sk%d: no receive buffers " 2133 "available -- packet dropped!\n", 2134 sc_if->sk_unit); 2135 ifp->if_ierrors++; 2136 continue; 2137 } 2138 m = m0; 2139 } else { 2140 m->m_pkthdr.rcvif = ifp; 2141 m->m_pkthdr.len = m->m_len = total_len; 2142 } 2143 2144 ifp->if_ipackets++; 2145 SK_UNLOCK(sc); 2146 (*ifp->if_input)(ifp, m); 2147 SK_LOCK(sc); 2148 } 2149 2150 sc_if->sk_cdata.sk_rx_prod = i; 2151 2152 return; 2153 } 2154 2155 static void 2156 sk_txeof(sc_if) 2157 struct sk_if_softc *sc_if; 2158 { 2159 struct sk_softc *sc; 2160 struct sk_tx_desc *cur_tx; 2161 struct ifnet *ifp; 2162 u_int32_t idx; 2163 2164 sc = sc_if->sk_softc; 2165 ifp = &sc_if->arpcom.ac_if; 2166 2167 /* 2168 * Go through our tx ring and free mbufs for those 2169 * frames that have been sent. 2170 */ 2171 idx = sc_if->sk_cdata.sk_tx_cons; 2172 while(idx != sc_if->sk_cdata.sk_tx_prod) { 2173 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2174 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 2175 break; 2176 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 2177 ifp->if_opackets++; 2178 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2179 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2180 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2181 } 2182 sc_if->sk_cdata.sk_tx_cnt--; 2183 SK_INC(idx, SK_TX_RING_CNT); 2184 } 2185 2186 if (sc_if->sk_cdata.sk_tx_cnt == 0) { 2187 ifp->if_timer = 0; 2188 } else /* nudge chip to keep tx ring moving */ 2189 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2190 2191 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2192 ifp->if_flags &= ~IFF_OACTIVE; 2193 2194 sc_if->sk_cdata.sk_tx_cons = idx; 2195 } 2196 2197 static void 2198 sk_tick(xsc_if) 2199 void *xsc_if; 2200 { 2201 struct sk_if_softc *sc_if; 2202 struct mii_data *mii; 2203 struct ifnet *ifp; 2204 int i; 2205 2206 sc_if = xsc_if; 2207 SK_IF_LOCK(sc_if); 2208 ifp = &sc_if->arpcom.ac_if; 2209 mii = device_get_softc(sc_if->sk_miibus); 2210 2211 if (!(ifp->if_flags & IFF_UP)) { 2212 SK_IF_UNLOCK(sc_if); 2213 return; 2214 } 2215 2216 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2217 sk_intr_bcom(sc_if); 2218 SK_IF_UNLOCK(sc_if); 2219 return; 2220 } 2221 2222 /* 2223 * According to SysKonnect, the correct way to verify that 2224 * the link has come back up is to poll bit 0 of the GPIO 2225 * register three times. This pin has the signal from the 2226 * link_sync pin connected to it; if we read the same link 2227 * state 3 times in a row, we know the link is up. 2228 */ 2229 for (i = 0; i < 3; i++) { 2230 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2231 break; 2232 } 2233 2234 if (i != 3) { 2235 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2236 SK_IF_UNLOCK(sc_if); 2237 return; 2238 } 2239 2240 /* Turn the GP0 interrupt back on. */ 2241 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2242 SK_XM_READ_2(sc_if, XM_ISR); 2243 mii_tick(mii); 2244 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2245 2246 SK_IF_UNLOCK(sc_if); 2247 return; 2248 } 2249 2250 static void 2251 sk_intr_bcom(sc_if) 2252 struct sk_if_softc *sc_if; 2253 { 2254 struct mii_data *mii; 2255 struct ifnet *ifp; 2256 int status; 2257 mii = device_get_softc(sc_if->sk_miibus); 2258 ifp = &sc_if->arpcom.ac_if; 2259 2260 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2261 2262 /* 2263 * Read the PHY interrupt register to make sure 2264 * we clear any pending interrupts. 2265 */ 2266 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2267 2268 if (!(ifp->if_flags & IFF_RUNNING)) { 2269 sk_init_xmac(sc_if); 2270 return; 2271 } 2272 2273 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2274 int lstat; 2275 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2276 BRGPHY_MII_AUXSTS); 2277 2278 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2279 mii_mediachg(mii); 2280 /* Turn off the link LED. */ 2281 SK_IF_WRITE_1(sc_if, 0, 2282 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2283 sc_if->sk_link = 0; 2284 } else if (status & BRGPHY_ISR_LNK_CHG) { 2285 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2286 BRGPHY_MII_IMR, 0xFF00); 2287 mii_tick(mii); 2288 sc_if->sk_link = 1; 2289 /* Turn on the link LED. */ 2290 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2291 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2292 SK_LINKLED_BLINK_OFF); 2293 } else { 2294 mii_tick(mii); 2295 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2296 } 2297 } 2298 2299 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2300 2301 return; 2302 } 2303 2304 static void 2305 sk_intr_xmac(sc_if) 2306 struct sk_if_softc *sc_if; 2307 { 2308 struct sk_softc *sc; 2309 u_int16_t status; 2310 2311 sc = sc_if->sk_softc; 2312 status = SK_XM_READ_2(sc_if, XM_ISR); 2313 2314 /* 2315 * Link has gone down. Start MII tick timeout to 2316 * watch for link resync. 2317 */ 2318 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2319 if (status & XM_ISR_GP0_SET) { 2320 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2321 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2322 } 2323 2324 if (status & XM_ISR_AUTONEG_DONE) { 2325 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2326 } 2327 } 2328 2329 if (status & XM_IMR_TX_UNDERRUN) 2330 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2331 2332 if (status & XM_IMR_RX_OVERRUN) 2333 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2334 2335 status = SK_XM_READ_2(sc_if, XM_ISR); 2336 2337 return; 2338 } 2339 2340 static void 2341 sk_intr_yukon(sc_if) 2342 struct sk_if_softc *sc_if; 2343 { 2344 int status; 2345 2346 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2347 2348 return; 2349 } 2350 2351 static void 2352 sk_intr(xsc) 2353 void *xsc; 2354 { 2355 struct sk_softc *sc = xsc; 2356 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 2357 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2358 u_int32_t status; 2359 2360 SK_LOCK(sc); 2361 2362 sc_if0 = sc->sk_if[SK_PORT_A]; 2363 sc_if1 = sc->sk_if[SK_PORT_B]; 2364 2365 if (sc_if0 != NULL) 2366 ifp0 = &sc_if0->arpcom.ac_if; 2367 if (sc_if1 != NULL) 2368 ifp1 = &sc_if1->arpcom.ac_if; 2369 2370 for (;;) { 2371 status = CSR_READ_4(sc, SK_ISSR); 2372 if (!(status & sc->sk_intrmask)) 2373 break; 2374 2375 /* Handle receive interrupts first. */ 2376 if (status & SK_ISR_RX1_EOF) { 2377 sk_rxeof(sc_if0); 2378 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2379 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2380 } 2381 if (status & SK_ISR_RX2_EOF) { 2382 sk_rxeof(sc_if1); 2383 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2384 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2385 } 2386 2387 /* Then transmit interrupts. */ 2388 if (status & SK_ISR_TX1_S_EOF) { 2389 sk_txeof(sc_if0); 2390 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2391 SK_TXBMU_CLR_IRQ_EOF); 2392 } 2393 if (status & SK_ISR_TX2_S_EOF) { 2394 sk_txeof(sc_if1); 2395 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2396 SK_TXBMU_CLR_IRQ_EOF); 2397 } 2398 2399 /* Then MAC interrupts. */ 2400 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 2401 if (sc->sk_type == SK_GENESIS) 2402 sk_intr_xmac(sc_if0); 2403 else 2404 sk_intr_yukon(sc_if0); 2405 } 2406 2407 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 2408 if (sc->sk_type == SK_GENESIS) 2409 sk_intr_xmac(sc_if1); 2410 else 2411 sk_intr_yukon(sc_if1); 2412 } 2413 2414 if (status & SK_ISR_EXTERNAL_REG) { 2415 if (ifp0 != NULL && 2416 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2417 sk_intr_bcom(sc_if0); 2418 if (ifp1 != NULL && 2419 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2420 sk_intr_bcom(sc_if1); 2421 } 2422 } 2423 2424 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2425 2426 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 2427 sk_start(ifp0); 2428 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 2429 sk_start(ifp1); 2430 2431 SK_UNLOCK(sc); 2432 2433 return; 2434 } 2435 2436 static void 2437 sk_init_xmac(sc_if) 2438 struct sk_if_softc *sc_if; 2439 { 2440 struct sk_softc *sc; 2441 struct ifnet *ifp; 2442 struct sk_bcom_hack bhack[] = { 2443 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2444 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2445 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2446 { 0, 0 } }; 2447 2448 sc = sc_if->sk_softc; 2449 ifp = &sc_if->arpcom.ac_if; 2450 2451 /* Unreset the XMAC. */ 2452 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2453 DELAY(1000); 2454 2455 /* Reset the XMAC's internal state. */ 2456 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2457 2458 /* Save the XMAC II revision */ 2459 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2460 2461 /* 2462 * Perform additional initialization for external PHYs, 2463 * namely for the 1000baseTX cards that use the XMAC's 2464 * GMII mode. 2465 */ 2466 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2467 int i = 0; 2468 u_int32_t val; 2469 2470 /* Take PHY out of reset. */ 2471 val = sk_win_read_4(sc, SK_GPIO); 2472 if (sc_if->sk_port == SK_PORT_A) 2473 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2474 else 2475 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2476 sk_win_write_4(sc, SK_GPIO, val); 2477 2478 /* Enable GMII mode on the XMAC. */ 2479 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2480 2481 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2482 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2483 DELAY(10000); 2484 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2485 BRGPHY_MII_IMR, 0xFFF0); 2486 2487 /* 2488 * Early versions of the BCM5400 apparently have 2489 * a bug that requires them to have their reserved 2490 * registers initialized to some magic values. I don't 2491 * know what the numbers do, I'm just the messenger. 2492 */ 2493 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2494 == 0x6041) { 2495 while(bhack[i].reg) { 2496 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2497 bhack[i].reg, bhack[i].val); 2498 i++; 2499 } 2500 } 2501 } 2502 2503 /* Set station address */ 2504 SK_XM_WRITE_2(sc_if, XM_PAR0, 2505 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2506 SK_XM_WRITE_2(sc_if, XM_PAR1, 2507 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2508 SK_XM_WRITE_2(sc_if, XM_PAR2, 2509 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2510 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2511 2512 if (ifp->if_flags & IFF_BROADCAST) { 2513 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2514 } else { 2515 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2516 } 2517 2518 /* We don't need the FCS appended to the packet. */ 2519 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2520 2521 /* We want short frames padded to 60 bytes. */ 2522 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2523 2524 /* 2525 * Enable the reception of all error frames. This is is 2526 * a necessary evil due to the design of the XMAC. The 2527 * XMAC's receive FIFO is only 8K in size, however jumbo 2528 * frames can be up to 9000 bytes in length. When bad 2529 * frame filtering is enabled, the XMAC's RX FIFO operates 2530 * in 'store and forward' mode. For this to work, the 2531 * entire frame has to fit into the FIFO, but that means 2532 * that jumbo frames larger than 8192 bytes will be 2533 * truncated. Disabling all bad frame filtering causes 2534 * the RX FIFO to operate in streaming mode, in which 2535 * case the XMAC will start transfering frames out of the 2536 * RX FIFO as soon as the FIFO threshold is reached. 2537 */ 2538 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2539 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2540 XM_MODE_RX_INRANGELEN); 2541 2542 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2543 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2544 else 2545 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2546 2547 /* 2548 * Bump up the transmit threshold. This helps hold off transmit 2549 * underruns when we're blasting traffic from both ports at once. 2550 */ 2551 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2552 2553 /* Set promiscuous mode */ 2554 sk_setpromisc(sc_if); 2555 2556 /* Set multicast filter */ 2557 sk_setmulti(sc_if); 2558 2559 /* Clear and enable interrupts */ 2560 SK_XM_READ_2(sc_if, XM_ISR); 2561 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2562 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2563 else 2564 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2565 2566 /* Configure MAC arbiter */ 2567 switch(sc_if->sk_xmac_rev) { 2568 case XM_XMAC_REV_B2: 2569 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2570 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2571 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2572 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2573 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2574 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2575 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2576 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2577 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2578 break; 2579 case XM_XMAC_REV_C1: 2580 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2581 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2582 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2583 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2584 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2585 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2586 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2587 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2588 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2589 break; 2590 default: 2591 break; 2592 } 2593 sk_win_write_2(sc, SK_MACARB_CTL, 2594 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2595 2596 sc_if->sk_link = 1; 2597 2598 return; 2599 } 2600 2601 static void 2602 sk_init_yukon(sc_if) 2603 struct sk_if_softc *sc_if; 2604 { 2605 u_int32_t phy; 2606 u_int16_t reg; 2607 struct sk_softc *sc; 2608 struct ifnet *ifp; 2609 int i; 2610 2611 sc = sc_if->sk_softc; 2612 ifp = &sc_if->arpcom.ac_if; 2613 2614 if (sc->sk_type == SK_YUKON_LITE && 2615 sc->sk_rev == SK_YUKON_LITE_REV_A3) { 2616 /* Take PHY out of reset. */ 2617 sk_win_write_4(sc, SK_GPIO, 2618 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2619 } 2620 2621 /* GMAC and GPHY Reset */ 2622 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2623 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2624 DELAY(1000); 2625 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2626 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2627 DELAY(1000); 2628 2629 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2630 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2631 2632 switch(sc_if->sk_softc->sk_pmd) { 2633 case IFM_1000_SX: 2634 case IFM_1000_LX: 2635 phy |= SK_GPHY_FIBER; 2636 break; 2637 2638 case IFM_1000_CX: 2639 case IFM_1000_T: 2640 phy |= SK_GPHY_COPPER; 2641 break; 2642 } 2643 2644 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2645 DELAY(1000); 2646 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2647 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2648 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2649 2650 /* unused read of the interrupt source register */ 2651 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2652 2653 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2654 2655 /* MIB Counter Clear Mode set */ 2656 reg |= YU_PAR_MIB_CLR; 2657 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2658 2659 /* MIB Counter Clear Mode clear */ 2660 reg &= ~YU_PAR_MIB_CLR; 2661 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2662 2663 /* receive control reg */ 2664 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2665 2666 /* transmit parameter register */ 2667 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2668 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2669 2670 /* serial mode register */ 2671 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 2672 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2673 reg |= YU_SMR_MFL_JUMBO; 2674 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 2675 2676 /* Setup Yukon's address */ 2677 for (i = 0; i < 3; i++) { 2678 /* Write Source Address 1 (unicast filter) */ 2679 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2680 sc_if->arpcom.ac_enaddr[i * 2] | 2681 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2682 } 2683 2684 for (i = 0; i < 3; i++) { 2685 reg = sk_win_read_2(sc_if->sk_softc, 2686 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2687 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2688 } 2689 2690 /* Set promiscuous mode */ 2691 sk_setpromisc(sc_if); 2692 2693 /* Set multicast filter */ 2694 sk_setmulti(sc_if); 2695 2696 /* enable interrupt mask for counter overflows */ 2697 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2698 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2699 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2700 2701 /* Configure RX MAC FIFO */ 2702 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2703 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2704 2705 /* Configure TX MAC FIFO */ 2706 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2707 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2708 } 2709 2710 /* 2711 * Note that to properly initialize any part of the GEnesis chip, 2712 * you first have to take it out of reset mode. 2713 */ 2714 static void 2715 sk_init(xsc) 2716 void *xsc; 2717 { 2718 struct sk_if_softc *sc_if = xsc; 2719 struct sk_softc *sc; 2720 struct ifnet *ifp; 2721 struct mii_data *mii; 2722 u_int16_t reg; 2723 u_int32_t imr; 2724 2725 SK_IF_LOCK(sc_if); 2726 2727 ifp = &sc_if->arpcom.ac_if; 2728 sc = sc_if->sk_softc; 2729 mii = device_get_softc(sc_if->sk_miibus); 2730 2731 if (ifp->if_flags & IFF_RUNNING) { 2732 SK_IF_UNLOCK(sc_if); 2733 return; 2734 } 2735 2736 /* Cancel pending I/O and free all RX/TX buffers. */ 2737 sk_stop(sc_if); 2738 2739 if (sc->sk_type == SK_GENESIS) { 2740 /* Configure LINK_SYNC LED */ 2741 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2742 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2743 SK_LINKLED_LINKSYNC_ON); 2744 2745 /* Configure RX LED */ 2746 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2747 SK_RXLEDCTL_COUNTER_START); 2748 2749 /* Configure TX LED */ 2750 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2751 SK_TXLEDCTL_COUNTER_START); 2752 } 2753 2754 /* Configure I2C registers */ 2755 2756 /* Configure XMAC(s) */ 2757 switch (sc->sk_type) { 2758 case SK_GENESIS: 2759 sk_init_xmac(sc_if); 2760 break; 2761 case SK_YUKON: 2762 case SK_YUKON_LITE: 2763 case SK_YUKON_LP: 2764 sk_init_yukon(sc_if); 2765 break; 2766 } 2767 mii_mediachg(mii); 2768 2769 if (sc->sk_type == SK_GENESIS) { 2770 /* Configure MAC FIFOs */ 2771 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2772 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2773 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2774 2775 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2776 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2777 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2778 } 2779 2780 /* Configure transmit arbiter(s) */ 2781 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2782 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2783 2784 /* Configure RAMbuffers */ 2785 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2786 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2787 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2788 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2789 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2790 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2791 2792 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2793 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2794 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2795 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2796 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2797 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2798 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2799 2800 /* Configure BMUs */ 2801 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2802 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2803 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2804 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2805 2806 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2807 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2808 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2809 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2810 2811 /* Init descriptors */ 2812 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2813 printf("sk%d: initialization failed: no " 2814 "memory for rx buffers\n", sc_if->sk_unit); 2815 sk_stop(sc_if); 2816 SK_IF_UNLOCK(sc_if); 2817 return; 2818 } 2819 sk_init_tx_ring(sc_if); 2820 2821 /* Set interrupt moderation if changed via sysctl. */ 2822 /* SK_LOCK(sc); */ 2823 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2824 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2825 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 2826 printf("skc%d: interrupt moderation is %d us\n", 2827 sc->sk_unit, sc->sk_int_mod); 2828 } 2829 /* SK_UNLOCK(sc); */ 2830 2831 /* Configure interrupt handling */ 2832 CSR_READ_4(sc, SK_ISSR); 2833 if (sc_if->sk_port == SK_PORT_A) 2834 sc->sk_intrmask |= SK_INTRS1; 2835 else 2836 sc->sk_intrmask |= SK_INTRS2; 2837 2838 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2839 2840 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2841 2842 /* Start BMUs. */ 2843 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2844 2845 switch(sc->sk_type) { 2846 case SK_GENESIS: 2847 /* Enable XMACs TX and RX state machines */ 2848 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2849 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2850 break; 2851 case SK_YUKON: 2852 case SK_YUKON_LITE: 2853 case SK_YUKON_LP: 2854 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2855 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2856 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2857 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2858 } 2859 2860 ifp->if_flags |= IFF_RUNNING; 2861 ifp->if_flags &= ~IFF_OACTIVE; 2862 2863 SK_IF_UNLOCK(sc_if); 2864 2865 return; 2866 } 2867 2868 static void 2869 sk_stop(sc_if) 2870 struct sk_if_softc *sc_if; 2871 { 2872 int i; 2873 struct sk_softc *sc; 2874 struct ifnet *ifp; 2875 2876 SK_IF_LOCK(sc_if); 2877 sc = sc_if->sk_softc; 2878 ifp = &sc_if->arpcom.ac_if; 2879 2880 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2881 2882 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2883 u_int32_t val; 2884 2885 /* Put PHY back into reset. */ 2886 val = sk_win_read_4(sc, SK_GPIO); 2887 if (sc_if->sk_port == SK_PORT_A) { 2888 val |= SK_GPIO_DIR0; 2889 val &= ~SK_GPIO_DAT0; 2890 } else { 2891 val |= SK_GPIO_DIR2; 2892 val &= ~SK_GPIO_DAT2; 2893 } 2894 sk_win_write_4(sc, SK_GPIO, val); 2895 } 2896 2897 /* Turn off various components of this interface. */ 2898 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2899 switch (sc->sk_type) { 2900 case SK_GENESIS: 2901 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2902 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2903 break; 2904 case SK_YUKON: 2905 case SK_YUKON_LITE: 2906 case SK_YUKON_LP: 2907 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2908 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2909 break; 2910 } 2911 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2912 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2913 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2914 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2915 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2916 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2917 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2918 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2919 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2920 2921 /* Disable interrupts */ 2922 if (sc_if->sk_port == SK_PORT_A) 2923 sc->sk_intrmask &= ~SK_INTRS1; 2924 else 2925 sc->sk_intrmask &= ~SK_INTRS2; 2926 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2927 2928 SK_XM_READ_2(sc_if, XM_ISR); 2929 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2930 2931 /* Free RX and TX mbufs still in the queues. */ 2932 for (i = 0; i < SK_RX_RING_CNT; i++) { 2933 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2934 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2935 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2936 } 2937 } 2938 2939 for (i = 0; i < SK_TX_RING_CNT; i++) { 2940 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2941 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2942 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2943 } 2944 } 2945 2946 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2947 SK_IF_UNLOCK(sc_if); 2948 return; 2949 } 2950 2951 static int 2952 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2953 { 2954 int error, value; 2955 2956 if (!arg1) 2957 return (EINVAL); 2958 value = *(int *)arg1; 2959 error = sysctl_handle_int(oidp, &value, 0, req); 2960 if (error || !req->newptr) 2961 return (error); 2962 if (value < low || value > high) 2963 return (EINVAL); 2964 *(int *)arg1 = value; 2965 return (0); 2966 } 2967 2968 static int 2969 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 2970 { 2971 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 2972 } 2973