1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /*- 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 /* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/bus.h> 91 #include <sys/endian.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/module.h> 96 #include <sys/socket.h> 97 #include <sys/sockio.h> 98 #include <sys/queue.h> 99 #include <sys/sysctl.h> 100 101 #include <net/bpf.h> 102 #include <net/ethernet.h> 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/if_vlan_var.h> 109 110 #include <netinet/in.h> 111 #include <netinet/in_systm.h> 112 #include <netinet/ip.h> 113 114 #include <machine/bus.h> 115 #include <machine/in_cksum.h> 116 #include <machine/resource.h> 117 #include <sys/rman.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/brgphyreg.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #if 0 127 #define SK_USEIOSPACE 128 #endif 129 130 #include <dev/sk/if_skreg.h> 131 #include <dev/sk/xmaciireg.h> 132 #include <dev/sk/yukonreg.h> 133 134 MODULE_DEPEND(sk, pci, 1, 1, 1); 135 MODULE_DEPEND(sk, ether, 1, 1, 1); 136 MODULE_DEPEND(sk, miibus, 1, 1, 1); 137 138 /* "device miibus" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 #ifndef lint 142 static const char rcsid[] = 143 "$FreeBSD$"; 144 #endif 145 146 static struct sk_type sk_devs[] = { 147 { 148 VENDORID_SK, 149 DEVICEID_SK_V1, 150 "SysKonnect Gigabit Ethernet (V1.0)" 151 }, 152 { 153 VENDORID_SK, 154 DEVICEID_SK_V2, 155 "SysKonnect Gigabit Ethernet (V2.0)" 156 }, 157 { 158 VENDORID_MARVELL, 159 DEVICEID_SK_V2, 160 "Marvell Gigabit Ethernet" 161 }, 162 { 163 VENDORID_MARVELL, 164 DEVICEID_BELKIN_5005, 165 "Belkin F5D5005 Gigabit Ethernet" 166 }, 167 { 168 VENDORID_3COM, 169 DEVICEID_3COM_3C940, 170 "3Com 3C940 Gigabit Ethernet" 171 }, 172 { 173 VENDORID_LINKSYS, 174 DEVICEID_LINKSYS_EG1032, 175 "Linksys EG1032 Gigabit Ethernet" 176 }, 177 { 178 VENDORID_DLINK, 179 DEVICEID_DLINK_DGE530T_A1, 180 "D-Link DGE-530T Gigabit Ethernet" 181 }, 182 { 183 VENDORID_DLINK, 184 DEVICEID_DLINK_DGE530T_B1, 185 "D-Link DGE-530T Gigabit Ethernet" 186 }, 187 { 0, 0, NULL } 188 }; 189 190 static int skc_probe(device_t); 191 static int skc_attach(device_t); 192 static int skc_detach(device_t); 193 static void skc_shutdown(device_t); 194 static int skc_suspend(device_t); 195 static int skc_resume(device_t); 196 static int sk_detach(device_t); 197 static int sk_probe(device_t); 198 static int sk_attach(device_t); 199 static void sk_tick(void *); 200 static void sk_yukon_tick(void *); 201 static void sk_intr(void *); 202 static void sk_intr_xmac(struct sk_if_softc *); 203 static void sk_intr_bcom(struct sk_if_softc *); 204 static void sk_intr_yukon(struct sk_if_softc *); 205 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t); 206 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 207 static void sk_rxeof(struct sk_if_softc *); 208 static void sk_jumbo_rxeof(struct sk_if_softc *); 209 static void sk_txeof(struct sk_if_softc *); 210 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *); 211 static int sk_encap(struct sk_if_softc *, struct mbuf **); 212 static void sk_start(struct ifnet *); 213 static void sk_start_locked(struct ifnet *); 214 static int sk_ioctl(struct ifnet *, u_long, caddr_t); 215 static void sk_init(void *); 216 static void sk_init_locked(struct sk_if_softc *); 217 static void sk_init_xmac(struct sk_if_softc *); 218 static void sk_init_yukon(struct sk_if_softc *); 219 static void sk_stop(struct sk_if_softc *); 220 static void sk_watchdog(struct ifnet *); 221 static int sk_ifmedia_upd(struct ifnet *); 222 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 223 static void sk_reset(struct sk_softc *); 224 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 225 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 226 static int sk_newbuf(struct sk_if_softc *, int); 227 static int sk_jumbo_newbuf(struct sk_if_softc *, int); 228 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 229 static int sk_dma_alloc(struct sk_if_softc *); 230 static void sk_dma_free(struct sk_if_softc *); 231 static void *sk_jalloc(struct sk_if_softc *); 232 static void sk_jfree(void *, void *); 233 static int sk_init_rx_ring(struct sk_if_softc *); 234 static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 235 static void sk_init_tx_ring(struct sk_if_softc *); 236 static u_int32_t sk_win_read_4(struct sk_softc *, int); 237 static u_int16_t sk_win_read_2(struct sk_softc *, int); 238 static u_int8_t sk_win_read_1(struct sk_softc *, int); 239 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 240 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 241 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 242 243 static int sk_miibus_readreg(device_t, int, int); 244 static int sk_miibus_writereg(device_t, int, int, int); 245 static void sk_miibus_statchg(device_t); 246 247 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 248 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 249 int); 250 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 251 252 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 253 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 254 int); 255 static void sk_marv_miibus_statchg(struct sk_if_softc *); 256 257 static uint32_t sk_xmchash(const uint8_t *); 258 static uint32_t sk_gmchash(const uint8_t *); 259 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 260 static void sk_setmulti(struct sk_if_softc *); 261 static void sk_setpromisc(struct sk_if_softc *); 262 263 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 264 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 265 266 /* 267 * It seems that SK-NET GENESIS supports very simple checksum offload 268 * capability for Tx and I believe it can generate 0 checksum value for 269 * UDP packets in Tx as the hardware can't differenciate UDP packets from 270 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 271 * means sender didn't perforam checksum computation. For the safety I 272 * disabled UDP checksum offload capability at the moment. Alternatively 273 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum 274 * offload routine. 275 */ 276 #define SK_CSUM_FEATURES (CSUM_TCP) 277 278 /* 279 * Note that we have newbus methods for both the GEnesis controller 280 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 281 * the miibus code is a child of the XMACs. We need to do it this way 282 * so that the miibus drivers can access the PHY registers on the 283 * right PHY. It's not quite what I had in mind, but it's the only 284 * design that achieves the desired effect. 285 */ 286 static device_method_t skc_methods[] = { 287 /* Device interface */ 288 DEVMETHOD(device_probe, skc_probe), 289 DEVMETHOD(device_attach, skc_attach), 290 DEVMETHOD(device_detach, skc_detach), 291 DEVMETHOD(device_suspend, skc_suspend), 292 DEVMETHOD(device_resume, skc_resume), 293 DEVMETHOD(device_shutdown, skc_shutdown), 294 295 /* bus interface */ 296 DEVMETHOD(bus_print_child, bus_generic_print_child), 297 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 298 299 { 0, 0 } 300 }; 301 302 static driver_t skc_driver = { 303 "skc", 304 skc_methods, 305 sizeof(struct sk_softc) 306 }; 307 308 static devclass_t skc_devclass; 309 310 static device_method_t sk_methods[] = { 311 /* Device interface */ 312 DEVMETHOD(device_probe, sk_probe), 313 DEVMETHOD(device_attach, sk_attach), 314 DEVMETHOD(device_detach, sk_detach), 315 DEVMETHOD(device_shutdown, bus_generic_shutdown), 316 317 /* bus interface */ 318 DEVMETHOD(bus_print_child, bus_generic_print_child), 319 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 323 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 324 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 325 326 { 0, 0 } 327 }; 328 329 static driver_t sk_driver = { 330 "sk", 331 sk_methods, 332 sizeof(struct sk_if_softc) 333 }; 334 335 static devclass_t sk_devclass; 336 337 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0); 338 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 339 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 340 341 static struct resource_spec sk_res_spec_io[] = { 342 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 343 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 344 { -1, 0, 0 } 345 }; 346 347 static struct resource_spec sk_res_spec_mem[] = { 348 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 349 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 350 { -1, 0, 0 } 351 }; 352 353 #define SK_SETBIT(sc, reg, x) \ 354 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 355 356 #define SK_CLRBIT(sc, reg, x) \ 357 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 358 359 #define SK_WIN_SETBIT_4(sc, reg, x) \ 360 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 361 362 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 363 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 364 365 #define SK_WIN_SETBIT_2(sc, reg, x) \ 366 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 367 368 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 369 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 370 371 static u_int32_t 372 sk_win_read_4(sc, reg) 373 struct sk_softc *sc; 374 int reg; 375 { 376 #ifdef SK_USEIOSPACE 377 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 378 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 379 #else 380 return(CSR_READ_4(sc, reg)); 381 #endif 382 } 383 384 static u_int16_t 385 sk_win_read_2(sc, reg) 386 struct sk_softc *sc; 387 int reg; 388 { 389 #ifdef SK_USEIOSPACE 390 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 391 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 392 #else 393 return(CSR_READ_2(sc, reg)); 394 #endif 395 } 396 397 static u_int8_t 398 sk_win_read_1(sc, reg) 399 struct sk_softc *sc; 400 int reg; 401 { 402 #ifdef SK_USEIOSPACE 403 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 404 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 405 #else 406 return(CSR_READ_1(sc, reg)); 407 #endif 408 } 409 410 static void 411 sk_win_write_4(sc, reg, val) 412 struct sk_softc *sc; 413 int reg; 414 u_int32_t val; 415 { 416 #ifdef SK_USEIOSPACE 417 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 418 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 419 #else 420 CSR_WRITE_4(sc, reg, val); 421 #endif 422 return; 423 } 424 425 static void 426 sk_win_write_2(sc, reg, val) 427 struct sk_softc *sc; 428 int reg; 429 u_int32_t val; 430 { 431 #ifdef SK_USEIOSPACE 432 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 433 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 434 #else 435 CSR_WRITE_2(sc, reg, val); 436 #endif 437 return; 438 } 439 440 static void 441 sk_win_write_1(sc, reg, val) 442 struct sk_softc *sc; 443 int reg; 444 u_int32_t val; 445 { 446 #ifdef SK_USEIOSPACE 447 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 448 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 449 #else 450 CSR_WRITE_1(sc, reg, val); 451 #endif 452 return; 453 } 454 455 static int 456 sk_miibus_readreg(dev, phy, reg) 457 device_t dev; 458 int phy, reg; 459 { 460 struct sk_if_softc *sc_if; 461 int v; 462 463 sc_if = device_get_softc(dev); 464 465 SK_IF_MII_LOCK(sc_if); 466 switch(sc_if->sk_softc->sk_type) { 467 case SK_GENESIS: 468 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 469 break; 470 case SK_YUKON: 471 case SK_YUKON_LITE: 472 case SK_YUKON_LP: 473 v = sk_marv_miibus_readreg(sc_if, phy, reg); 474 break; 475 default: 476 v = 0; 477 break; 478 } 479 SK_IF_MII_UNLOCK(sc_if); 480 481 return (v); 482 } 483 484 static int 485 sk_miibus_writereg(dev, phy, reg, val) 486 device_t dev; 487 int phy, reg, val; 488 { 489 struct sk_if_softc *sc_if; 490 int v; 491 492 sc_if = device_get_softc(dev); 493 494 SK_IF_MII_LOCK(sc_if); 495 switch(sc_if->sk_softc->sk_type) { 496 case SK_GENESIS: 497 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 498 break; 499 case SK_YUKON: 500 case SK_YUKON_LITE: 501 case SK_YUKON_LP: 502 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 503 break; 504 default: 505 v = 0; 506 break; 507 } 508 SK_IF_MII_UNLOCK(sc_if); 509 510 return (v); 511 } 512 513 static void 514 sk_miibus_statchg(dev) 515 device_t dev; 516 { 517 struct sk_if_softc *sc_if; 518 519 sc_if = device_get_softc(dev); 520 521 SK_IF_MII_LOCK(sc_if); 522 switch(sc_if->sk_softc->sk_type) { 523 case SK_GENESIS: 524 sk_xmac_miibus_statchg(sc_if); 525 break; 526 case SK_YUKON: 527 case SK_YUKON_LITE: 528 case SK_YUKON_LP: 529 sk_marv_miibus_statchg(sc_if); 530 break; 531 } 532 SK_IF_MII_UNLOCK(sc_if); 533 534 return; 535 } 536 537 static int 538 sk_xmac_miibus_readreg(sc_if, phy, reg) 539 struct sk_if_softc *sc_if; 540 int phy, reg; 541 { 542 int i; 543 544 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 545 return(0); 546 547 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 548 SK_XM_READ_2(sc_if, XM_PHY_DATA); 549 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 550 for (i = 0; i < SK_TIMEOUT; i++) { 551 DELAY(1); 552 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 553 XM_MMUCMD_PHYDATARDY) 554 break; 555 } 556 557 if (i == SK_TIMEOUT) { 558 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 559 return(0); 560 } 561 } 562 DELAY(1); 563 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 564 565 return(i); 566 } 567 568 static int 569 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 570 struct sk_if_softc *sc_if; 571 int phy, reg, val; 572 { 573 int i; 574 575 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 576 for (i = 0; i < SK_TIMEOUT; i++) { 577 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 578 break; 579 } 580 581 if (i == SK_TIMEOUT) { 582 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 583 return (ETIMEDOUT); 584 } 585 586 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 587 for (i = 0; i < SK_TIMEOUT; i++) { 588 DELAY(1); 589 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 590 break; 591 } 592 if (i == SK_TIMEOUT) 593 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 594 595 return(0); 596 } 597 598 static void 599 sk_xmac_miibus_statchg(sc_if) 600 struct sk_if_softc *sc_if; 601 { 602 struct mii_data *mii; 603 604 mii = device_get_softc(sc_if->sk_miibus); 605 606 /* 607 * If this is a GMII PHY, manually set the XMAC's 608 * duplex mode accordingly. 609 */ 610 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 611 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 612 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 613 } else { 614 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 615 } 616 } 617 } 618 619 static int 620 sk_marv_miibus_readreg(sc_if, phy, reg) 621 struct sk_if_softc *sc_if; 622 int phy, reg; 623 { 624 u_int16_t val; 625 int i; 626 627 if (phy != 0 || 628 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 629 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 630 return(0); 631 } 632 633 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 634 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 635 636 for (i = 0; i < SK_TIMEOUT; i++) { 637 DELAY(1); 638 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 639 if (val & YU_SMICR_READ_VALID) 640 break; 641 } 642 643 if (i == SK_TIMEOUT) { 644 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 645 return(0); 646 } 647 648 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 649 650 return(val); 651 } 652 653 static int 654 sk_marv_miibus_writereg(sc_if, phy, reg, val) 655 struct sk_if_softc *sc_if; 656 int phy, reg, val; 657 { 658 int i; 659 660 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 661 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 662 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 663 664 for (i = 0; i < SK_TIMEOUT; i++) { 665 DELAY(1); 666 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0) 667 break; 668 } 669 if (i == SK_TIMEOUT) 670 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 671 672 return(0); 673 } 674 675 static void 676 sk_marv_miibus_statchg(sc_if) 677 struct sk_if_softc *sc_if; 678 { 679 return; 680 } 681 682 #define HASH_BITS 6 683 684 static u_int32_t 685 sk_xmchash(addr) 686 const uint8_t *addr; 687 { 688 uint32_t crc; 689 690 /* Compute CRC for the address value. */ 691 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 692 693 return (~crc & ((1 << HASH_BITS) - 1)); 694 } 695 696 /* gmchash is just a big endian crc */ 697 static u_int32_t 698 sk_gmchash(addr) 699 const uint8_t *addr; 700 { 701 uint32_t crc; 702 703 /* Compute CRC for the address value. */ 704 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 705 706 return (crc & ((1 << HASH_BITS) - 1)); 707 } 708 709 static void 710 sk_setfilt(sc_if, addr, slot) 711 struct sk_if_softc *sc_if; 712 u_int16_t *addr; 713 int slot; 714 { 715 int base; 716 717 base = XM_RXFILT_ENTRY(slot); 718 719 SK_XM_WRITE_2(sc_if, base, addr[0]); 720 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 721 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 722 723 return; 724 } 725 726 static void 727 sk_setmulti(sc_if) 728 struct sk_if_softc *sc_if; 729 { 730 struct sk_softc *sc = sc_if->sk_softc; 731 struct ifnet *ifp = sc_if->sk_ifp; 732 u_int32_t hashes[2] = { 0, 0 }; 733 int h = 0, i; 734 struct ifmultiaddr *ifma; 735 u_int16_t dummy[] = { 0, 0, 0 }; 736 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2]; 737 738 SK_IF_LOCK_ASSERT(sc_if); 739 740 /* First, zot all the existing filters. */ 741 switch(sc->sk_type) { 742 case SK_GENESIS: 743 for (i = 1; i < XM_RXFILT_MAX; i++) 744 sk_setfilt(sc_if, dummy, i); 745 746 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 747 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 748 break; 749 case SK_YUKON: 750 case SK_YUKON_LITE: 751 case SK_YUKON_LP: 752 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 753 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 754 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 755 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 756 break; 757 } 758 759 /* Now program new ones. */ 760 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 761 hashes[0] = 0xFFFFFFFF; 762 hashes[1] = 0xFFFFFFFF; 763 } else { 764 i = 1; 765 IF_ADDR_LOCK(ifp); 766 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 767 if (ifma->ifma_addr->sa_family != AF_LINK) 768 continue; 769 /* 770 * Program the first XM_RXFILT_MAX multicast groups 771 * into the perfect filter. For all others, 772 * use the hash table. 773 */ 774 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 775 bcopy(LLADDR( 776 (struct sockaddr_dl *)ifma->ifma_addr), 777 maddr, ETHER_ADDR_LEN); 778 sk_setfilt(sc_if, maddr, i); 779 i++; 780 continue; 781 } 782 783 switch(sc->sk_type) { 784 case SK_GENESIS: 785 bcopy(LLADDR( 786 (struct sockaddr_dl *)ifma->ifma_addr), 787 maddr, ETHER_ADDR_LEN); 788 h = sk_xmchash((const uint8_t *)maddr); 789 break; 790 case SK_YUKON: 791 case SK_YUKON_LITE: 792 case SK_YUKON_LP: 793 bcopy(LLADDR( 794 (struct sockaddr_dl *)ifma->ifma_addr), 795 maddr, ETHER_ADDR_LEN); 796 h = sk_gmchash((const uint8_t *)maddr); 797 break; 798 } 799 if (h < 32) 800 hashes[0] |= (1 << h); 801 else 802 hashes[1] |= (1 << (h - 32)); 803 } 804 IF_ADDR_UNLOCK(ifp); 805 } 806 807 switch(sc->sk_type) { 808 case SK_GENESIS: 809 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 810 XM_MODE_RX_USE_PERFECT); 811 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 812 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 813 break; 814 case SK_YUKON: 815 case SK_YUKON_LITE: 816 case SK_YUKON_LP: 817 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 818 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 819 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 820 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 821 break; 822 } 823 824 return; 825 } 826 827 static void 828 sk_setpromisc(sc_if) 829 struct sk_if_softc *sc_if; 830 { 831 struct sk_softc *sc = sc_if->sk_softc; 832 struct ifnet *ifp = sc_if->sk_ifp; 833 834 SK_IF_LOCK_ASSERT(sc_if); 835 836 switch(sc->sk_type) { 837 case SK_GENESIS: 838 if (ifp->if_flags & IFF_PROMISC) { 839 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 840 } else { 841 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 842 } 843 break; 844 case SK_YUKON: 845 case SK_YUKON_LITE: 846 case SK_YUKON_LP: 847 if (ifp->if_flags & IFF_PROMISC) { 848 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 849 YU_RCR_UFLEN | YU_RCR_MUFLEN); 850 } else { 851 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 852 YU_RCR_UFLEN | YU_RCR_MUFLEN); 853 } 854 break; 855 } 856 857 return; 858 } 859 860 static int 861 sk_init_rx_ring(sc_if) 862 struct sk_if_softc *sc_if; 863 { 864 struct sk_ring_data *rd; 865 bus_addr_t addr; 866 u_int32_t csum_start; 867 int i; 868 869 sc_if->sk_cdata.sk_rx_cons = 0; 870 871 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 872 ETHER_HDR_LEN; 873 rd = &sc_if->sk_rdata; 874 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 875 for (i = 0; i < SK_RX_RING_CNT; i++) { 876 if (sk_newbuf(sc_if, i) != 0) 877 return (ENOBUFS); 878 if (i == (SK_RX_RING_CNT - 1)) 879 addr = SK_RX_RING_ADDR(sc_if, 0); 880 else 881 addr = SK_RX_RING_ADDR(sc_if, i + 1); 882 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 883 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 884 } 885 886 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 887 sc_if->sk_cdata.sk_rx_ring_map, 888 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 889 890 return(0); 891 } 892 893 static int 894 sk_init_jumbo_rx_ring(sc_if) 895 struct sk_if_softc *sc_if; 896 { 897 struct sk_ring_data *rd; 898 bus_addr_t addr; 899 u_int32_t csum_start; 900 int i; 901 902 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 903 904 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 905 ETHER_HDR_LEN; 906 rd = &sc_if->sk_rdata; 907 bzero(rd->sk_jumbo_rx_ring, 908 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 909 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 910 if (sk_jumbo_newbuf(sc_if, i) != 0) 911 return (ENOBUFS); 912 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 913 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 914 else 915 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 916 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 917 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 918 } 919 920 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 921 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 923 924 return (0); 925 } 926 927 static void 928 sk_init_tx_ring(sc_if) 929 struct sk_if_softc *sc_if; 930 { 931 struct sk_ring_data *rd; 932 struct sk_txdesc *txd; 933 bus_addr_t addr; 934 int i; 935 936 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 937 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 938 939 sc_if->sk_cdata.sk_tx_prod = 0; 940 sc_if->sk_cdata.sk_tx_cons = 0; 941 sc_if->sk_cdata.sk_tx_cnt = 0; 942 943 rd = &sc_if->sk_rdata; 944 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 945 for (i = 0; i < SK_TX_RING_CNT; i++) { 946 if (i == (SK_TX_RING_CNT - 1)) 947 addr = SK_TX_RING_ADDR(sc_if, 0); 948 else 949 addr = SK_TX_RING_ADDR(sc_if, i + 1); 950 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 951 txd = &sc_if->sk_cdata.sk_txdesc[i]; 952 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 953 } 954 955 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 956 sc_if->sk_cdata.sk_tx_ring_map, 957 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 958 } 959 960 static __inline void 961 sk_discard_rxbuf(sc_if, idx) 962 struct sk_if_softc *sc_if; 963 int idx; 964 { 965 struct sk_rx_desc *r; 966 struct sk_rxdesc *rxd; 967 struct mbuf *m; 968 969 970 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 971 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 972 m = rxd->rx_m; 973 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 974 } 975 976 static __inline void 977 sk_discard_jumbo_rxbuf(sc_if, idx) 978 struct sk_if_softc *sc_if; 979 int idx; 980 { 981 struct sk_rx_desc *r; 982 struct sk_rxdesc *rxd; 983 struct mbuf *m; 984 985 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 986 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 987 m = rxd->rx_m; 988 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 989 } 990 991 static int 992 sk_newbuf(sc_if, idx) 993 struct sk_if_softc *sc_if; 994 int idx; 995 { 996 struct sk_rx_desc *r; 997 struct sk_rxdesc *rxd; 998 struct mbuf *m; 999 bus_dma_segment_t segs[1]; 1000 bus_dmamap_t map; 1001 int nsegs; 1002 1003 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1004 if (m == NULL) 1005 return (ENOBUFS); 1006 m->m_len = m->m_pkthdr.len = MCLBYTES; 1007 m_adj(m, ETHER_ALIGN); 1008 1009 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 1010 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1011 m_freem(m); 1012 return (ENOBUFS); 1013 } 1014 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1015 1016 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 1017 if (rxd->rx_m != NULL) { 1018 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1019 BUS_DMASYNC_POSTREAD); 1020 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 1021 } 1022 map = rxd->rx_dmamap; 1023 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 1024 sc_if->sk_cdata.sk_rx_sparemap = map; 1025 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1026 BUS_DMASYNC_PREREAD); 1027 rxd->rx_m = m; 1028 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 1029 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1030 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1031 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1032 1033 return (0); 1034 } 1035 1036 static int 1037 sk_jumbo_newbuf(sc_if, idx) 1038 struct sk_if_softc *sc_if; 1039 int idx; 1040 { 1041 struct sk_rx_desc *r; 1042 struct sk_rxdesc *rxd; 1043 struct mbuf *m; 1044 bus_dma_segment_t segs[1]; 1045 bus_dmamap_t map; 1046 int nsegs; 1047 void *buf; 1048 1049 MGETHDR(m, M_DONTWAIT, MT_DATA); 1050 if (m == NULL) 1051 return (ENOBUFS); 1052 buf = sk_jalloc(sc_if); 1053 if (buf == NULL) { 1054 m_freem(m); 1055 return (ENOBUFS); 1056 } 1057 /* Attach the buffer to the mbuf */ 1058 MEXTADD(m, buf, SK_JLEN, sk_jfree, (struct sk_if_softc *)sc_if, 0, 1059 EXT_NET_DRV); 1060 if ((m->m_flags & M_EXT) == 0) { 1061 m_freem(m); 1062 return (ENOBUFS); 1063 } 1064 m->m_pkthdr.len = m->m_len = SK_JLEN; 1065 /* 1066 * Adjust alignment so packet payload begins on a 1067 * longword boundary. Mandatory for Alpha, useful on 1068 * x86 too. 1069 */ 1070 m_adj(m, ETHER_ALIGN); 1071 1072 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 1073 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1074 m_freem(m); 1075 return (ENOBUFS); 1076 } 1077 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1078 1079 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1080 if (rxd->rx_m != NULL) { 1081 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1082 BUS_DMASYNC_POSTREAD); 1083 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 1084 rxd->rx_dmamap); 1085 } 1086 map = rxd->rx_dmamap; 1087 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 1088 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 1089 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1090 BUS_DMASYNC_PREREAD); 1091 rxd->rx_m = m; 1092 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1093 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1094 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1095 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1096 1097 return (0); 1098 } 1099 1100 /* 1101 * Set media options. 1102 */ 1103 static int 1104 sk_ifmedia_upd(ifp) 1105 struct ifnet *ifp; 1106 { 1107 struct sk_if_softc *sc_if = ifp->if_softc; 1108 struct mii_data *mii; 1109 1110 mii = device_get_softc(sc_if->sk_miibus); 1111 sk_init(sc_if); 1112 mii_mediachg(mii); 1113 1114 return(0); 1115 } 1116 1117 /* 1118 * Report current media status. 1119 */ 1120 static void 1121 sk_ifmedia_sts(ifp, ifmr) 1122 struct ifnet *ifp; 1123 struct ifmediareq *ifmr; 1124 { 1125 struct sk_if_softc *sc_if; 1126 struct mii_data *mii; 1127 1128 sc_if = ifp->if_softc; 1129 mii = device_get_softc(sc_if->sk_miibus); 1130 1131 mii_pollstat(mii); 1132 ifmr->ifm_active = mii->mii_media_active; 1133 ifmr->ifm_status = mii->mii_media_status; 1134 1135 return; 1136 } 1137 1138 static int 1139 sk_ioctl(ifp, command, data) 1140 struct ifnet *ifp; 1141 u_long command; 1142 caddr_t data; 1143 { 1144 struct sk_if_softc *sc_if = ifp->if_softc; 1145 struct ifreq *ifr = (struct ifreq *) data; 1146 int error, mask; 1147 struct mii_data *mii; 1148 1149 error = 0; 1150 switch(command) { 1151 case SIOCSIFMTU: 1152 SK_IF_LOCK(sc_if); 1153 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1154 error = EINVAL; 1155 else { 1156 ifp->if_mtu = ifr->ifr_mtu; 1157 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1158 sk_init_locked(sc_if); 1159 } 1160 SK_IF_UNLOCK(sc_if); 1161 break; 1162 case SIOCSIFFLAGS: 1163 SK_IF_LOCK(sc_if); 1164 if (ifp->if_flags & IFF_UP) { 1165 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1166 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1167 & IFF_PROMISC) { 1168 sk_setpromisc(sc_if); 1169 sk_setmulti(sc_if); 1170 } 1171 } else 1172 sk_init_locked(sc_if); 1173 } else { 1174 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1175 sk_stop(sc_if); 1176 } 1177 sc_if->sk_if_flags = ifp->if_flags; 1178 SK_IF_UNLOCK(sc_if); 1179 break; 1180 case SIOCADDMULTI: 1181 case SIOCDELMULTI: 1182 SK_IF_LOCK(sc_if); 1183 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1184 sk_setmulti(sc_if); 1185 SK_IF_UNLOCK(sc_if); 1186 break; 1187 case SIOCGIFMEDIA: 1188 case SIOCSIFMEDIA: 1189 mii = device_get_softc(sc_if->sk_miibus); 1190 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1191 break; 1192 case SIOCSIFCAP: 1193 SK_IF_LOCK(sc_if); 1194 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1195 SK_IF_UNLOCK(sc_if); 1196 break; 1197 } 1198 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1199 if (mask & IFCAP_HWCSUM) { 1200 ifp->if_capenable ^= IFCAP_HWCSUM; 1201 if (IFCAP_HWCSUM & ifp->if_capenable && 1202 IFCAP_HWCSUM & ifp->if_capabilities) 1203 ifp->if_hwassist = SK_CSUM_FEATURES; 1204 else 1205 ifp->if_hwassist = 0; 1206 } 1207 SK_IF_UNLOCK(sc_if); 1208 break; 1209 default: 1210 error = ether_ioctl(ifp, command, data); 1211 break; 1212 } 1213 1214 return (error); 1215 } 1216 1217 /* 1218 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1219 * IDs against our list and return a device name if we find a match. 1220 */ 1221 static int 1222 skc_probe(dev) 1223 device_t dev; 1224 { 1225 struct sk_type *t = sk_devs; 1226 1227 while(t->sk_name != NULL) { 1228 if ((pci_get_vendor(dev) == t->sk_vid) && 1229 (pci_get_device(dev) == t->sk_did)) { 1230 /* 1231 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1232 * Rev. 3 is supported by re(4). 1233 */ 1234 if ((t->sk_vid == VENDORID_LINKSYS) && 1235 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1236 (pci_get_subdevice(dev) != 1237 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1238 t++; 1239 continue; 1240 } 1241 device_set_desc(dev, t->sk_name); 1242 return (BUS_PROBE_DEFAULT); 1243 } 1244 t++; 1245 } 1246 1247 return(ENXIO); 1248 } 1249 1250 /* 1251 * Force the GEnesis into reset, then bring it out of reset. 1252 */ 1253 static void 1254 sk_reset(sc) 1255 struct sk_softc *sc; 1256 { 1257 1258 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1259 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1260 if (SK_YUKON_FAMILY(sc->sk_type)) 1261 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1262 1263 DELAY(1000); 1264 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1265 DELAY(2); 1266 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1267 if (SK_YUKON_FAMILY(sc->sk_type)) 1268 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1269 1270 if (sc->sk_type == SK_GENESIS) { 1271 /* Configure packet arbiter */ 1272 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1273 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1274 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1275 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1276 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1277 } 1278 1279 /* Enable RAM interface */ 1280 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1281 1282 /* 1283 * Configure interrupt moderation. The moderation timer 1284 * defers interrupts specified in the interrupt moderation 1285 * timer mask based on the timeout specified in the interrupt 1286 * moderation timer init register. Each bit in the timer 1287 * register represents one tick, so to specify a timeout in 1288 * microseconds, we have to multiply by the correct number of 1289 * ticks-per-microsecond. 1290 */ 1291 switch (sc->sk_type) { 1292 case SK_GENESIS: 1293 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1294 break; 1295 default: 1296 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1297 break; 1298 } 1299 if (bootverbose) 1300 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1301 sc->sk_int_mod); 1302 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1303 sc->sk_int_ticks)); 1304 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1305 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1306 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1307 1308 return; 1309 } 1310 1311 static int 1312 sk_probe(dev) 1313 device_t dev; 1314 { 1315 struct sk_softc *sc; 1316 1317 sc = device_get_softc(device_get_parent(dev)); 1318 1319 /* 1320 * Not much to do here. We always know there will be 1321 * at least one XMAC present, and if there are two, 1322 * skc_attach() will create a second device instance 1323 * for us. 1324 */ 1325 switch (sc->sk_type) { 1326 case SK_GENESIS: 1327 device_set_desc(dev, "XaQti Corp. XMAC II"); 1328 break; 1329 case SK_YUKON: 1330 case SK_YUKON_LITE: 1331 case SK_YUKON_LP: 1332 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1333 break; 1334 } 1335 1336 return (BUS_PROBE_DEFAULT); 1337 } 1338 1339 /* 1340 * Each XMAC chip is attached as a separate logical IP interface. 1341 * Single port cards will have only one logical interface of course. 1342 */ 1343 static int 1344 sk_attach(dev) 1345 device_t dev; 1346 { 1347 struct sk_softc *sc; 1348 struct sk_if_softc *sc_if; 1349 struct ifnet *ifp; 1350 int i, port, error; 1351 u_char eaddr[6]; 1352 1353 if (dev == NULL) 1354 return(EINVAL); 1355 1356 error = 0; 1357 sc_if = device_get_softc(dev); 1358 sc = device_get_softc(device_get_parent(dev)); 1359 port = *(int *)device_get_ivars(dev); 1360 1361 sc_if->sk_if_dev = dev; 1362 sc_if->sk_port = port; 1363 sc_if->sk_softc = sc; 1364 sc->sk_if[port] = sc_if; 1365 if (port == SK_PORT_A) 1366 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1367 if (port == SK_PORT_B) 1368 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1369 1370 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1371 1372 if (sk_dma_alloc(sc_if) != 0) { 1373 error = ENOMEM; 1374 goto fail; 1375 } 1376 1377 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1378 if (ifp == NULL) { 1379 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1380 error = ENOSPC; 1381 goto fail; 1382 } 1383 ifp->if_softc = sc_if; 1384 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1385 ifp->if_mtu = ETHERMTU; 1386 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1387 /* 1388 * SK_GENESIS has a bug in checksum offload - From linux. 1389 */ 1390 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1391 ifp->if_capabilities = IFCAP_HWCSUM; 1392 ifp->if_hwassist = SK_CSUM_FEATURES; 1393 } else { 1394 ifp->if_capabilities = 0; 1395 ifp->if_hwassist = 0; 1396 } 1397 ifp->if_capenable = ifp->if_capabilities; 1398 ifp->if_ioctl = sk_ioctl; 1399 ifp->if_start = sk_start; 1400 ifp->if_watchdog = sk_watchdog; 1401 ifp->if_init = sk_init; 1402 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1403 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1404 IFQ_SET_READY(&ifp->if_snd); 1405 1406 /* 1407 * Get station address for this interface. Note that 1408 * dual port cards actually come with three station 1409 * addresses: one for each port, plus an extra. The 1410 * extra one is used by the SysKonnect driver software 1411 * as a 'virtual' station address for when both ports 1412 * are operating in failover mode. Currently we don't 1413 * use this extra address. 1414 */ 1415 SK_IF_LOCK(sc_if); 1416 for (i = 0; i < ETHER_ADDR_LEN; i++) 1417 eaddr[i] = 1418 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1419 1420 /* 1421 * Set up RAM buffer addresses. The NIC will have a certain 1422 * amount of SRAM on it, somewhere between 512K and 2MB. We 1423 * need to divide this up a) between the transmitter and 1424 * receiver and b) between the two XMACs, if this is a 1425 * dual port NIC. Our algotithm is to divide up the memory 1426 * evenly so that everyone gets a fair share. 1427 * 1428 * Just to be contrary, Yukon2 appears to have separate memory 1429 * for each MAC. 1430 */ 1431 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1432 u_int32_t chunk, val; 1433 1434 chunk = sc->sk_ramsize / 2; 1435 val = sc->sk_rboff / sizeof(u_int64_t); 1436 sc_if->sk_rx_ramstart = val; 1437 val += (chunk / sizeof(u_int64_t)); 1438 sc_if->sk_rx_ramend = val - 1; 1439 sc_if->sk_tx_ramstart = val; 1440 val += (chunk / sizeof(u_int64_t)); 1441 sc_if->sk_tx_ramend = val - 1; 1442 } else { 1443 u_int32_t chunk, val; 1444 1445 chunk = sc->sk_ramsize / 4; 1446 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1447 sizeof(u_int64_t); 1448 sc_if->sk_rx_ramstart = val; 1449 val += (chunk / sizeof(u_int64_t)); 1450 sc_if->sk_rx_ramend = val - 1; 1451 sc_if->sk_tx_ramstart = val; 1452 val += (chunk / sizeof(u_int64_t)); 1453 sc_if->sk_tx_ramend = val - 1; 1454 } 1455 1456 /* Read and save PHY type and set PHY address */ 1457 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1458 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1459 switch(sc_if->sk_phytype) { 1460 case SK_PHYTYPE_XMAC: 1461 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1462 break; 1463 case SK_PHYTYPE_BCOM: 1464 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1465 break; 1466 default: 1467 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1468 sc_if->sk_phytype); 1469 error = ENODEV; 1470 SK_IF_UNLOCK(sc_if); 1471 goto fail; 1472 } 1473 } else { 1474 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1475 sc->sk_pmd != 'S') { 1476 /* not initialized, punt */ 1477 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1478 sc->sk_coppertype = 1; 1479 } 1480 1481 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1482 1483 if (!(sc->sk_coppertype)) 1484 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1485 } 1486 1487 /* 1488 * Call MI attach routine. Can't hold locks when calling into ether_*. 1489 */ 1490 SK_IF_UNLOCK(sc_if); 1491 ether_ifattach(ifp, eaddr); 1492 SK_IF_LOCK(sc_if); 1493 1494 /* 1495 * The hardware should be ready for VLAN_MTU by default: 1496 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1497 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1498 * 1499 */ 1500 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1501 ifp->if_capenable |= IFCAP_VLAN_MTU; 1502 /* 1503 * Tell the upper layer(s) we support long frames. 1504 * Must appear after the call to ether_ifattach() because 1505 * ether_ifattach() sets ifi_hdrlen to the default value. 1506 */ 1507 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1508 1509 /* 1510 * Do miibus setup. 1511 */ 1512 switch (sc->sk_type) { 1513 case SK_GENESIS: 1514 sk_init_xmac(sc_if); 1515 break; 1516 case SK_YUKON: 1517 case SK_YUKON_LITE: 1518 case SK_YUKON_LP: 1519 sk_init_yukon(sc_if); 1520 break; 1521 } 1522 1523 SK_IF_UNLOCK(sc_if); 1524 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1525 sk_ifmedia_upd, sk_ifmedia_sts)) { 1526 device_printf(sc_if->sk_if_dev, "no PHY found!\n"); 1527 ether_ifdetach(ifp); 1528 error = ENXIO; 1529 goto fail; 1530 } 1531 1532 fail: 1533 if (error) { 1534 /* Access should be ok even though lock has been dropped */ 1535 sc->sk_if[port] = NULL; 1536 sk_detach(dev); 1537 } 1538 1539 return(error); 1540 } 1541 1542 /* 1543 * Attach the interface. Allocate softc structures, do ifmedia 1544 * setup and ethernet/BPF attach. 1545 */ 1546 static int 1547 skc_attach(dev) 1548 device_t dev; 1549 { 1550 struct sk_softc *sc; 1551 int error = 0, *port; 1552 uint8_t skrs; 1553 const char *pname; 1554 char *revstr; 1555 1556 sc = device_get_softc(dev); 1557 sc->sk_dev = dev; 1558 1559 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1560 MTX_DEF); 1561 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1562 /* 1563 * Map control/status registers. 1564 */ 1565 pci_enable_busmaster(dev); 1566 1567 /* Allocate resources */ 1568 #ifdef SK_USEIOSPACE 1569 sc->sk_res_spec = sk_res_spec_io; 1570 #else 1571 sc->sk_res_spec = sk_res_spec_mem; 1572 #endif 1573 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1574 if (error) { 1575 if (sc->sk_res_spec == sk_res_spec_mem) 1576 sc->sk_res_spec = sk_res_spec_io; 1577 else 1578 sc->sk_res_spec = sk_res_spec_mem; 1579 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1580 if (error) { 1581 device_printf(dev, "couldn't allocate %s resources\n", 1582 sc->sk_res_spec == sk_res_spec_mem ? "memory" : 1583 "I/O"); 1584 goto fail; 1585 } 1586 } 1587 1588 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1589 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1590 1591 /* Bail out if chip is not recognized. */ 1592 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1593 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1594 sc->sk_type, sc->sk_rev); 1595 error = ENXIO; 1596 goto fail; 1597 } 1598 1599 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1600 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1601 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW, 1602 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1603 "SK interrupt moderation"); 1604 1605 /* Pull in device tunables. */ 1606 sc->sk_int_mod = SK_IM_DEFAULT; 1607 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1608 "int_mod", &sc->sk_int_mod); 1609 if (error == 0) { 1610 if (sc->sk_int_mod < SK_IM_MIN || 1611 sc->sk_int_mod > SK_IM_MAX) { 1612 device_printf(dev, "int_mod value out of range; " 1613 "using default: %d\n", SK_IM_DEFAULT); 1614 sc->sk_int_mod = SK_IM_DEFAULT; 1615 } 1616 } 1617 1618 /* Reset the adapter. */ 1619 sk_reset(sc); 1620 1621 skrs = sk_win_read_1(sc, SK_EPROM0); 1622 if (sc->sk_type == SK_GENESIS) { 1623 /* Read and save RAM size and RAMbuffer offset */ 1624 switch(skrs) { 1625 case SK_RAMSIZE_512K_64: 1626 sc->sk_ramsize = 0x80000; 1627 sc->sk_rboff = SK_RBOFF_0; 1628 break; 1629 case SK_RAMSIZE_1024K_64: 1630 sc->sk_ramsize = 0x100000; 1631 sc->sk_rboff = SK_RBOFF_80000; 1632 break; 1633 case SK_RAMSIZE_1024K_128: 1634 sc->sk_ramsize = 0x100000; 1635 sc->sk_rboff = SK_RBOFF_0; 1636 break; 1637 case SK_RAMSIZE_2048K_128: 1638 sc->sk_ramsize = 0x200000; 1639 sc->sk_rboff = SK_RBOFF_0; 1640 break; 1641 default: 1642 device_printf(dev, "unknown ram size: %d\n", skrs); 1643 error = ENXIO; 1644 goto fail; 1645 } 1646 } else { /* SK_YUKON_FAMILY */ 1647 if (skrs == 0x00) 1648 sc->sk_ramsize = 0x20000; 1649 else 1650 sc->sk_ramsize = skrs * (1<<12); 1651 sc->sk_rboff = SK_RBOFF_0; 1652 } 1653 1654 /* Read and save physical media type */ 1655 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1656 1657 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1658 sc->sk_coppertype = 1; 1659 else 1660 sc->sk_coppertype = 0; 1661 1662 /* Determine whether to name it with VPD PN or just make it up. 1663 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1664 switch (pci_get_device(dev)) { 1665 case DEVICEID_SK_V1: 1666 case DEVICEID_BELKIN_5005: 1667 case DEVICEID_3COM_3C940: 1668 case DEVICEID_LINKSYS_EG1032: 1669 case DEVICEID_DLINK_DGE530T_A1: 1670 case DEVICEID_DLINK_DGE530T_B1: 1671 /* Stay with VPD PN. */ 1672 if (pci_get_vpd_ident(dev, &pname)) 1673 goto vpdfailed; 1674 break; 1675 case DEVICEID_SK_V2: 1676 /* YUKON VPD PN might bear no resemblance to reality. */ 1677 switch (sc->sk_type) { 1678 case SK_GENESIS: 1679 /* Stay with VPD PN. */ 1680 if (pci_get_vpd_ident(dev, &pname)) 1681 goto vpdfailed; 1682 break; 1683 case SK_YUKON: 1684 pname = "Marvell Yukon Gigabit Ethernet"; 1685 break; 1686 case SK_YUKON_LITE: 1687 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1688 break; 1689 case SK_YUKON_LP: 1690 pname = "Marvell Yukon LP Gigabit Ethernet"; 1691 break; 1692 default: 1693 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1694 break; 1695 } 1696 1697 /* Yukon Lite Rev. A0 needs special test. */ 1698 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1699 u_int32_t far; 1700 u_int8_t testbyte; 1701 1702 /* Save flash address register before testing. */ 1703 far = sk_win_read_4(sc, SK_EP_ADDR); 1704 1705 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1706 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1707 1708 if (testbyte != 0x00) { 1709 /* Yukon Lite Rev. A0 detected. */ 1710 sc->sk_type = SK_YUKON_LITE; 1711 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1712 /* Restore flash address register. */ 1713 sk_win_write_4(sc, SK_EP_ADDR, far); 1714 } 1715 } 1716 break; 1717 default: 1718 vpdfailed: 1719 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1720 "chipver=%02x, rev=%x\n", 1721 pci_get_vendor(dev), pci_get_device(dev), 1722 sc->sk_type, sc->sk_rev); 1723 error = ENXIO; 1724 goto fail; 1725 } 1726 1727 if (sc->sk_type == SK_YUKON_LITE) { 1728 switch (sc->sk_rev) { 1729 case SK_YUKON_LITE_REV_A0: 1730 revstr = "A0"; 1731 break; 1732 case SK_YUKON_LITE_REV_A1: 1733 revstr = "A1"; 1734 break; 1735 case SK_YUKON_LITE_REV_A3: 1736 revstr = "A3"; 1737 break; 1738 default: 1739 revstr = ""; 1740 break; 1741 } 1742 } else { 1743 revstr = ""; 1744 } 1745 1746 /* Announce the product name and more VPD data if there. */ 1747 device_printf(dev, "%s rev. %s(0x%x)\n", 1748 pname != NULL ? pname : "<unknown>", revstr, sc->sk_rev); 1749 1750 if (bootverbose) { 1751 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1752 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1753 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1754 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1755 } 1756 1757 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1758 if (sc->sk_devs[SK_PORT_A] == NULL) { 1759 device_printf(dev, "failed to add child for PORT_A\n"); 1760 error = ENXIO; 1761 goto fail; 1762 } 1763 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1764 if (port == NULL) { 1765 device_printf(dev, "failed to allocate memory for " 1766 "ivars of PORT_A\n"); 1767 error = ENXIO; 1768 goto fail; 1769 } 1770 *port = SK_PORT_A; 1771 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1772 1773 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1774 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1775 if (sc->sk_devs[SK_PORT_B] == NULL) { 1776 device_printf(dev, "failed to add child for PORT_B\n"); 1777 error = ENXIO; 1778 goto fail; 1779 } 1780 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1781 if (port == NULL) { 1782 device_printf(dev, "failed to allocate memory for " 1783 "ivars of PORT_B\n"); 1784 error = ENXIO; 1785 goto fail; 1786 } 1787 *port = SK_PORT_B; 1788 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1789 } 1790 1791 /* Turn on the 'driver is loaded' LED. */ 1792 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1793 1794 error = bus_generic_attach(dev); 1795 if (error) { 1796 device_printf(dev, "failed to attach port(s)\n"); 1797 goto fail; 1798 } 1799 1800 /* Hook interrupt last to avoid having to lock softc */ 1801 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE, 1802 sk_intr, sc, &sc->sk_intrhand); 1803 1804 if (error) { 1805 device_printf(dev, "couldn't set up irq\n"); 1806 goto fail; 1807 } 1808 1809 fail: 1810 if (error) 1811 skc_detach(dev); 1812 1813 return(error); 1814 } 1815 1816 /* 1817 * Shutdown hardware and free up resources. This can be called any 1818 * time after the mutex has been initialized. It is called in both 1819 * the error case in attach and the normal detach case so it needs 1820 * to be careful about only freeing resources that have actually been 1821 * allocated. 1822 */ 1823 static int 1824 sk_detach(dev) 1825 device_t dev; 1826 { 1827 struct sk_if_softc *sc_if; 1828 struct ifnet *ifp; 1829 1830 sc_if = device_get_softc(dev); 1831 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1832 ("sk mutex not initialized in sk_detach")); 1833 SK_IF_LOCK(sc_if); 1834 1835 ifp = sc_if->sk_ifp; 1836 /* These should only be active if attach_xmac succeeded */ 1837 if (device_is_attached(dev)) { 1838 sk_stop(sc_if); 1839 /* Can't hold locks while calling detach */ 1840 SK_IF_UNLOCK(sc_if); 1841 callout_drain(&sc_if->sk_tick_ch); 1842 ether_ifdetach(ifp); 1843 SK_IF_LOCK(sc_if); 1844 } 1845 if (ifp) 1846 if_free(ifp); 1847 /* 1848 * We're generally called from skc_detach() which is using 1849 * device_delete_child() to get to here. It's already trashed 1850 * miibus for us, so don't do it here or we'll panic. 1851 */ 1852 /* 1853 if (sc_if->sk_miibus != NULL) 1854 device_delete_child(dev, sc_if->sk_miibus); 1855 */ 1856 bus_generic_detach(dev); 1857 sk_dma_free(sc_if); 1858 SK_IF_UNLOCK(sc_if); 1859 1860 return(0); 1861 } 1862 1863 static int 1864 skc_detach(dev) 1865 device_t dev; 1866 { 1867 struct sk_softc *sc; 1868 1869 sc = device_get_softc(dev); 1870 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1871 1872 if (device_is_alive(dev)) { 1873 if (sc->sk_devs[SK_PORT_A] != NULL) { 1874 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 1875 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1876 } 1877 if (sc->sk_devs[SK_PORT_B] != NULL) { 1878 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 1879 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1880 } 1881 bus_generic_detach(dev); 1882 } 1883 1884 if (sc->sk_intrhand) 1885 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand); 1886 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res); 1887 1888 mtx_destroy(&sc->sk_mii_mtx); 1889 mtx_destroy(&sc->sk_mtx); 1890 1891 return(0); 1892 } 1893 1894 struct sk_dmamap_arg { 1895 bus_addr_t sk_busaddr; 1896 }; 1897 1898 static void 1899 sk_dmamap_cb(arg, segs, nseg, error) 1900 void *arg; 1901 bus_dma_segment_t *segs; 1902 int nseg; 1903 int error; 1904 { 1905 struct sk_dmamap_arg *ctx; 1906 1907 if (error != 0) 1908 return; 1909 1910 ctx = arg; 1911 ctx->sk_busaddr = segs[0].ds_addr; 1912 } 1913 1914 /* 1915 * Allocate jumbo buffer storage. The SysKonnect adapters support 1916 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1917 * use them in their drivers. In order for us to use them, we need 1918 * large 9K receive buffers, however standard mbuf clusters are only 1919 * 2048 bytes in size. Consequently, we need to allocate and manage 1920 * our own jumbo buffer pool. Fortunately, this does not require an 1921 * excessive amount of additional code. 1922 */ 1923 static int 1924 sk_dma_alloc(sc_if) 1925 struct sk_if_softc *sc_if; 1926 { 1927 struct sk_dmamap_arg ctx; 1928 struct sk_txdesc *txd; 1929 struct sk_rxdesc *rxd; 1930 struct sk_rxdesc *jrxd; 1931 u_int8_t *ptr; 1932 struct sk_jpool_entry *entry; 1933 int error, i; 1934 1935 mtx_init(&sc_if->sk_jlist_mtx, "sk_jlist_mtx", NULL, MTX_DEF); 1936 SLIST_INIT(&sc_if->sk_jfree_listhead); 1937 SLIST_INIT(&sc_if->sk_jinuse_listhead); 1938 1939 /* create parent tag */ 1940 /* 1941 * XXX 1942 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 1943 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 1944 * However bz@ reported that it does not work on amd64 with > 4GB 1945 * RAM. Until we have more clues of the breakage, disable DAC mode 1946 * by limiting DMA address to be in 32bit address space. 1947 */ 1948 error = bus_dma_tag_create( 1949 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */ 1950 1, 0, /* algnmnt, boundary */ 1951 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1952 BUS_SPACE_MAXADDR, /* highaddr */ 1953 NULL, NULL, /* filter, filterarg */ 1954 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1955 0, /* nsegments */ 1956 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1957 0, /* flags */ 1958 NULL, NULL, /* lockfunc, lockarg */ 1959 &sc_if->sk_cdata.sk_parent_tag); 1960 if (error != 0) { 1961 device_printf(sc_if->sk_if_dev, 1962 "failed to create parent DMA tag\n"); 1963 goto fail; 1964 } 1965 /* create tag for Tx ring */ 1966 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1967 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1968 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1969 BUS_SPACE_MAXADDR, /* highaddr */ 1970 NULL, NULL, /* filter, filterarg */ 1971 SK_TX_RING_SZ, /* maxsize */ 1972 1, /* nsegments */ 1973 SK_TX_RING_SZ, /* maxsegsize */ 1974 0, /* flags */ 1975 NULL, NULL, /* lockfunc, lockarg */ 1976 &sc_if->sk_cdata.sk_tx_ring_tag); 1977 if (error != 0) { 1978 device_printf(sc_if->sk_if_dev, 1979 "failed to allocate Tx ring DMA tag\n"); 1980 goto fail; 1981 } 1982 1983 /* create tag for Rx ring */ 1984 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1985 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1986 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1987 BUS_SPACE_MAXADDR, /* highaddr */ 1988 NULL, NULL, /* filter, filterarg */ 1989 SK_RX_RING_SZ, /* maxsize */ 1990 1, /* nsegments */ 1991 SK_RX_RING_SZ, /* maxsegsize */ 1992 0, /* flags */ 1993 NULL, NULL, /* lockfunc, lockarg */ 1994 &sc_if->sk_cdata.sk_rx_ring_tag); 1995 if (error != 0) { 1996 device_printf(sc_if->sk_if_dev, 1997 "failed to allocate Rx ring DMA tag\n"); 1998 goto fail; 1999 } 2000 2001 /* create tag for jumbo Rx ring */ 2002 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2003 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2004 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2005 BUS_SPACE_MAXADDR, /* highaddr */ 2006 NULL, NULL, /* filter, filterarg */ 2007 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2008 1, /* nsegments */ 2009 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2010 0, /* flags */ 2011 NULL, NULL, /* lockfunc, lockarg */ 2012 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2013 if (error != 0) { 2014 device_printf(sc_if->sk_if_dev, 2015 "failed to allocate jumbo Rx ring DMA tag\n"); 2016 goto fail; 2017 } 2018 2019 /* create tag for jumbo buffer blocks */ 2020 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2021 PAGE_SIZE, 0, /* algnmnt, boundary */ 2022 BUS_SPACE_MAXADDR, /* lowaddr */ 2023 BUS_SPACE_MAXADDR, /* highaddr */ 2024 NULL, NULL, /* filter, filterarg */ 2025 SK_JMEM, /* maxsize */ 2026 1, /* nsegments */ 2027 SK_JMEM, /* maxsegsize */ 2028 0, /* flags */ 2029 NULL, NULL, /* lockfunc, lockarg */ 2030 &sc_if->sk_cdata.sk_jumbo_tag); 2031 if (error != 0) { 2032 device_printf(sc_if->sk_if_dev, 2033 "failed to allocate jumbo Rx buffer block DMA tag\n"); 2034 goto fail; 2035 } 2036 2037 /* create tag for Tx buffers */ 2038 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2039 1, 0, /* algnmnt, boundary */ 2040 BUS_SPACE_MAXADDR, /* lowaddr */ 2041 BUS_SPACE_MAXADDR, /* highaddr */ 2042 NULL, NULL, /* filter, filterarg */ 2043 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 2044 SK_MAXTXSEGS, /* nsegments */ 2045 MCLBYTES, /* maxsegsize */ 2046 0, /* flags */ 2047 NULL, NULL, /* lockfunc, lockarg */ 2048 &sc_if->sk_cdata.sk_tx_tag); 2049 if (error != 0) { 2050 device_printf(sc_if->sk_if_dev, 2051 "failed to allocate Tx DMA tag\n"); 2052 goto fail; 2053 } 2054 2055 /* create tag for Rx buffers */ 2056 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2057 1, 0, /* algnmnt, boundary */ 2058 BUS_SPACE_MAXADDR, /* lowaddr */ 2059 BUS_SPACE_MAXADDR, /* highaddr */ 2060 NULL, NULL, /* filter, filterarg */ 2061 MCLBYTES, /* maxsize */ 2062 1, /* nsegments */ 2063 MCLBYTES, /* maxsegsize */ 2064 0, /* flags */ 2065 NULL, NULL, /* lockfunc, lockarg */ 2066 &sc_if->sk_cdata.sk_rx_tag); 2067 if (error != 0) { 2068 device_printf(sc_if->sk_if_dev, 2069 "failed to allocate Rx DMA tag\n"); 2070 goto fail; 2071 } 2072 2073 /* create tag for jumbo Rx buffers */ 2074 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2075 PAGE_SIZE, 0, /* algnmnt, boundary */ 2076 BUS_SPACE_MAXADDR, /* lowaddr */ 2077 BUS_SPACE_MAXADDR, /* highaddr */ 2078 NULL, NULL, /* filter, filterarg */ 2079 MCLBYTES * SK_MAXRXSEGS, /* maxsize */ 2080 SK_MAXRXSEGS, /* nsegments */ 2081 SK_JLEN, /* maxsegsize */ 2082 0, /* flags */ 2083 NULL, NULL, /* lockfunc, lockarg */ 2084 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2085 if (error != 0) { 2086 device_printf(sc_if->sk_if_dev, 2087 "failed to allocate jumbo Rx DMA tag\n"); 2088 goto fail; 2089 } 2090 2091 /* allocate DMA'able memory and load the DMA map for Tx ring */ 2092 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 2093 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2094 &sc_if->sk_cdata.sk_tx_ring_map); 2095 if (error != 0) { 2096 device_printf(sc_if->sk_if_dev, 2097 "failed to allocate DMA'able memory for Tx ring\n"); 2098 goto fail; 2099 } 2100 2101 ctx.sk_busaddr = 0; 2102 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 2103 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 2104 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2105 if (error != 0) { 2106 device_printf(sc_if->sk_if_dev, 2107 "failed to load DMA'able memory for Tx ring\n"); 2108 goto fail; 2109 } 2110 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 2111 2112 /* allocate DMA'able memory and load the DMA map for Rx ring */ 2113 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 2114 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2115 &sc_if->sk_cdata.sk_rx_ring_map); 2116 if (error != 0) { 2117 device_printf(sc_if->sk_if_dev, 2118 "failed to allocate DMA'able memory for Rx ring\n"); 2119 goto fail; 2120 } 2121 2122 ctx.sk_busaddr = 0; 2123 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 2124 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 2125 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2126 if (error != 0) { 2127 device_printf(sc_if->sk_if_dev, 2128 "failed to load DMA'able memory for Rx ring\n"); 2129 goto fail; 2130 } 2131 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2132 2133 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2134 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2135 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, 2136 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2137 if (error != 0) { 2138 device_printf(sc_if->sk_if_dev, 2139 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2140 goto fail; 2141 } 2142 2143 ctx.sk_busaddr = 0; 2144 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2145 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2146 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2147 &ctx, BUS_DMA_NOWAIT); 2148 if (error != 0) { 2149 device_printf(sc_if->sk_if_dev, 2150 "failed to load DMA'able memory for jumbo Rx ring\n"); 2151 goto fail; 2152 } 2153 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2154 2155 /* create DMA maps for Tx buffers */ 2156 for (i = 0; i < SK_TX_RING_CNT; i++) { 2157 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2158 txd->tx_m = NULL; 2159 txd->tx_dmamap = 0; 2160 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2161 &txd->tx_dmamap); 2162 if (error != 0) { 2163 device_printf(sc_if->sk_if_dev, 2164 "failed to create Tx dmamap\n"); 2165 goto fail; 2166 } 2167 } 2168 /* create DMA maps for Rx buffers */ 2169 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2170 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2171 device_printf(sc_if->sk_if_dev, 2172 "failed to create spare Rx dmamap\n"); 2173 goto fail; 2174 } 2175 for (i = 0; i < SK_RX_RING_CNT; i++) { 2176 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2177 rxd->rx_m = NULL; 2178 rxd->rx_dmamap = 0; 2179 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2180 &rxd->rx_dmamap); 2181 if (error != 0) { 2182 device_printf(sc_if->sk_if_dev, 2183 "failed to create Rx dmamap\n"); 2184 goto fail; 2185 } 2186 } 2187 /* create DMA maps for jumbo Rx buffers */ 2188 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2189 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2190 device_printf(sc_if->sk_if_dev, 2191 "failed to create spare jumbo Rx dmamap\n"); 2192 goto fail; 2193 } 2194 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2195 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2196 jrxd->rx_m = NULL; 2197 jrxd->rx_dmamap = 0; 2198 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2199 &jrxd->rx_dmamap); 2200 if (error != 0) { 2201 device_printf(sc_if->sk_if_dev, 2202 "failed to create jumbo Rx dmamap\n"); 2203 goto fail; 2204 } 2205 } 2206 2207 /* allocate DMA'able memory and load the DMA map for jumbo buf */ 2208 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_tag, 2209 (void **)&sc_if->sk_rdata.sk_jumbo_buf, 2210 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_map); 2211 if (error != 0) { 2212 device_printf(sc_if->sk_if_dev, 2213 "failed to allocate DMA'able memory for jumbo buf\n"); 2214 goto fail; 2215 } 2216 2217 ctx.sk_busaddr = 0; 2218 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_tag, 2219 sc_if->sk_cdata.sk_jumbo_map, 2220 sc_if->sk_rdata.sk_jumbo_buf, SK_JMEM, sk_dmamap_cb, 2221 &ctx, BUS_DMA_NOWAIT); 2222 if (error != 0) { 2223 device_printf(sc_if->sk_if_dev, 2224 "failed to load DMA'able memory for jumbobuf\n"); 2225 goto fail; 2226 } 2227 sc_if->sk_rdata.sk_jumbo_buf_paddr = ctx.sk_busaddr; 2228 2229 /* 2230 * Now divide it up into 9K pieces and save the addresses 2231 * in an array. 2232 */ 2233 ptr = sc_if->sk_rdata.sk_jumbo_buf; 2234 for (i = 0; i < SK_JSLOTS; i++) { 2235 sc_if->sk_cdata.sk_jslots[i] = ptr; 2236 ptr += SK_JLEN; 2237 entry = malloc(sizeof(struct sk_jpool_entry), 2238 M_DEVBUF, M_NOWAIT); 2239 if (entry == NULL) { 2240 device_printf(sc_if->sk_if_dev, 2241 "no memory for jumbo buffers!\n"); 2242 error = ENOMEM; 2243 goto fail; 2244 } 2245 entry->slot = i; 2246 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2247 jpool_entries); 2248 } 2249 2250 fail: 2251 return (error); 2252 } 2253 2254 static void 2255 sk_dma_free(sc_if) 2256 struct sk_if_softc *sc_if; 2257 { 2258 struct sk_txdesc *txd; 2259 struct sk_rxdesc *rxd; 2260 struct sk_rxdesc *jrxd; 2261 struct sk_jpool_entry *entry; 2262 int i; 2263 2264 SK_JLIST_LOCK(sc_if); 2265 while ((entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead))) { 2266 device_printf(sc_if->sk_if_dev, 2267 "asked to free buffer that is in use!\n"); 2268 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2269 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2270 jpool_entries); 2271 } 2272 2273 while (!SLIST_EMPTY(&sc_if->sk_jfree_listhead)) { 2274 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2275 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2276 free(entry, M_DEVBUF); 2277 } 2278 SK_JLIST_UNLOCK(sc_if); 2279 2280 /* destroy jumbo buffer block */ 2281 if (sc_if->sk_cdata.sk_jumbo_map) 2282 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_tag, 2283 sc_if->sk_cdata.sk_jumbo_map); 2284 2285 if (sc_if->sk_rdata.sk_jumbo_buf) { 2286 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_tag, 2287 sc_if->sk_rdata.sk_jumbo_buf, 2288 sc_if->sk_cdata.sk_jumbo_map); 2289 sc_if->sk_rdata.sk_jumbo_buf = NULL; 2290 sc_if->sk_cdata.sk_jumbo_map = 0; 2291 } 2292 2293 /* Tx ring */ 2294 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2295 if (sc_if->sk_cdata.sk_tx_ring_map) 2296 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2297 sc_if->sk_cdata.sk_tx_ring_map); 2298 if (sc_if->sk_cdata.sk_tx_ring_map && 2299 sc_if->sk_rdata.sk_tx_ring) 2300 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2301 sc_if->sk_rdata.sk_tx_ring, 2302 sc_if->sk_cdata.sk_tx_ring_map); 2303 sc_if->sk_rdata.sk_tx_ring = NULL; 2304 sc_if->sk_cdata.sk_tx_ring_map = 0; 2305 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2306 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2307 } 2308 /* Rx ring */ 2309 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2310 if (sc_if->sk_cdata.sk_rx_ring_map) 2311 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2312 sc_if->sk_cdata.sk_rx_ring_map); 2313 if (sc_if->sk_cdata.sk_rx_ring_map && 2314 sc_if->sk_rdata.sk_rx_ring) 2315 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2316 sc_if->sk_rdata.sk_rx_ring, 2317 sc_if->sk_cdata.sk_rx_ring_map); 2318 sc_if->sk_rdata.sk_rx_ring = NULL; 2319 sc_if->sk_cdata.sk_rx_ring_map = 0; 2320 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2321 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2322 } 2323 /* jumbo Rx ring */ 2324 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2325 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map) 2326 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2327 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2328 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map && 2329 sc_if->sk_rdata.sk_jumbo_rx_ring) 2330 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2331 sc_if->sk_rdata.sk_jumbo_rx_ring, 2332 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2333 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2334 sc_if->sk_cdata.sk_jumbo_rx_ring_map = 0; 2335 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2336 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2337 } 2338 /* Tx buffers */ 2339 if (sc_if->sk_cdata.sk_tx_tag) { 2340 for (i = 0; i < SK_TX_RING_CNT; i++) { 2341 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2342 if (txd->tx_dmamap) { 2343 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2344 txd->tx_dmamap); 2345 txd->tx_dmamap = 0; 2346 } 2347 } 2348 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2349 sc_if->sk_cdata.sk_tx_tag = NULL; 2350 } 2351 /* Rx buffers */ 2352 if (sc_if->sk_cdata.sk_rx_tag) { 2353 for (i = 0; i < SK_RX_RING_CNT; i++) { 2354 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2355 if (rxd->rx_dmamap) { 2356 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2357 rxd->rx_dmamap); 2358 rxd->rx_dmamap = 0; 2359 } 2360 } 2361 if (sc_if->sk_cdata.sk_rx_sparemap) { 2362 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2363 sc_if->sk_cdata.sk_rx_sparemap); 2364 sc_if->sk_cdata.sk_rx_sparemap = 0; 2365 } 2366 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2367 sc_if->sk_cdata.sk_rx_tag = NULL; 2368 } 2369 /* jumbo Rx buffers */ 2370 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2371 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2372 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2373 if (jrxd->rx_dmamap) { 2374 bus_dmamap_destroy( 2375 sc_if->sk_cdata.sk_jumbo_rx_tag, 2376 jrxd->rx_dmamap); 2377 jrxd->rx_dmamap = 0; 2378 } 2379 } 2380 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2381 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2382 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2383 sc_if->sk_cdata.sk_jumbo_rx_sparemap = 0; 2384 } 2385 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2386 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2387 } 2388 2389 if (sc_if->sk_cdata.sk_parent_tag) { 2390 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2391 sc_if->sk_cdata.sk_parent_tag = NULL; 2392 } 2393 mtx_destroy(&sc_if->sk_jlist_mtx); 2394 } 2395 2396 /* 2397 * Allocate a jumbo buffer. 2398 */ 2399 static void * 2400 sk_jalloc(sc_if) 2401 struct sk_if_softc *sc_if; 2402 { 2403 struct sk_jpool_entry *entry; 2404 2405 SK_JLIST_LOCK(sc_if); 2406 2407 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2408 2409 if (entry == NULL) { 2410 SK_JLIST_UNLOCK(sc_if); 2411 return (NULL); 2412 } 2413 2414 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2415 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 2416 2417 SK_JLIST_UNLOCK(sc_if); 2418 2419 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 2420 } 2421 2422 /* 2423 * Release a jumbo buffer. 2424 */ 2425 static void 2426 sk_jfree(buf, args) 2427 void *buf; 2428 void *args; 2429 { 2430 struct sk_if_softc *sc_if; 2431 struct sk_jpool_entry *entry; 2432 int i; 2433 2434 /* Extract the softc struct pointer. */ 2435 sc_if = (struct sk_if_softc *)args; 2436 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2437 2438 SK_JLIST_LOCK(sc_if); 2439 /* calculate the slot this buffer belongs to */ 2440 i = ((vm_offset_t)buf 2441 - (vm_offset_t)sc_if->sk_rdata.sk_jumbo_buf) / SK_JLEN; 2442 KASSERT(i >= 0 && i < SK_JSLOTS, 2443 ("%s: asked to free buffer that we don't manage!", __func__)); 2444 2445 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 2446 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2447 entry->slot = i; 2448 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2449 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 2450 if (SLIST_EMPTY(&sc_if->sk_jinuse_listhead)) 2451 wakeup(sc_if); 2452 2453 SK_JLIST_UNLOCK(sc_if); 2454 } 2455 2456 static void 2457 sk_txcksum(ifp, m, f) 2458 struct ifnet *ifp; 2459 struct mbuf *m; 2460 struct sk_tx_desc *f; 2461 { 2462 struct ip *ip; 2463 u_int16_t offset; 2464 u_int8_t *p; 2465 2466 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2467 for(; m && m->m_len == 0; m = m->m_next) 2468 ; 2469 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2470 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2471 /* checksum may be corrupted */ 2472 goto sendit; 2473 } 2474 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2475 if (m->m_len != ETHER_HDR_LEN) { 2476 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2477 __func__); 2478 /* checksum may be corrupted */ 2479 goto sendit; 2480 } 2481 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2482 ; 2483 if (m == NULL) { 2484 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2485 /* checksum may be corrupted */ 2486 goto sendit; 2487 } 2488 ip = mtod(m, struct ip *); 2489 } else { 2490 p = mtod(m, u_int8_t *); 2491 p += ETHER_HDR_LEN; 2492 ip = (struct ip *)p; 2493 } 2494 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2495 2496 sendit: 2497 f->sk_csum_startval = 0; 2498 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2499 (offset << 16)); 2500 } 2501 2502 static int 2503 sk_encap(sc_if, m_head) 2504 struct sk_if_softc *sc_if; 2505 struct mbuf **m_head; 2506 { 2507 struct sk_txdesc *txd; 2508 struct sk_tx_desc *f = NULL; 2509 struct mbuf *m; 2510 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2511 u_int32_t cflags, frag, si, sk_ctl; 2512 int error, i, nseg; 2513 2514 SK_IF_LOCK_ASSERT(sc_if); 2515 2516 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2517 return (ENOBUFS); 2518 2519 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2520 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2521 if (error == EFBIG) { 2522 m = m_defrag(*m_head, M_DONTWAIT); 2523 if (m == NULL) { 2524 m_freem(*m_head); 2525 *m_head = NULL; 2526 return (ENOMEM); 2527 } 2528 *m_head = m; 2529 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2530 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2531 if (error != 0) { 2532 m_freem(*m_head); 2533 *m_head = NULL; 2534 return (error); 2535 } 2536 } else if (error != 0) 2537 return (error); 2538 if (nseg == 0) { 2539 m_freem(*m_head); 2540 *m_head = NULL; 2541 return (EIO); 2542 } 2543 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2544 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2545 return (ENOBUFS); 2546 } 2547 2548 m = *m_head; 2549 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0) 2550 cflags = SK_OPCODE_CSUM; 2551 else 2552 cflags = SK_OPCODE_DEFAULT; 2553 si = frag = sc_if->sk_cdata.sk_tx_prod; 2554 for (i = 0; i < nseg; i++) { 2555 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2556 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2557 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2558 sk_ctl = txsegs[i].ds_len | cflags; 2559 if (i == 0) { 2560 if (cflags == SK_OPCODE_CSUM) 2561 sk_txcksum(sc_if->sk_ifp, m, f); 2562 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2563 } else 2564 sk_ctl |= SK_TXCTL_OWN; 2565 f->sk_ctl = htole32(sk_ctl); 2566 sc_if->sk_cdata.sk_tx_cnt++; 2567 SK_INC(frag, SK_TX_RING_CNT); 2568 } 2569 sc_if->sk_cdata.sk_tx_prod = frag; 2570 2571 /* set EOF on the last desciptor */ 2572 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2573 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2574 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2575 2576 /* turn the first descriptor ownership to NIC */ 2577 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2578 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2579 2580 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2581 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2582 txd->tx_m = m; 2583 2584 /* sync descriptors */ 2585 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2586 BUS_DMASYNC_PREWRITE); 2587 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2588 sc_if->sk_cdata.sk_tx_ring_map, 2589 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2590 2591 return (0); 2592 } 2593 2594 static void 2595 sk_start(ifp) 2596 struct ifnet *ifp; 2597 { 2598 struct sk_if_softc *sc_if; 2599 2600 sc_if = ifp->if_softc; 2601 2602 SK_IF_LOCK(sc_if); 2603 sk_start_locked(ifp); 2604 SK_IF_UNLOCK(sc_if); 2605 2606 return; 2607 } 2608 2609 static void 2610 sk_start_locked(ifp) 2611 struct ifnet *ifp; 2612 { 2613 struct sk_softc *sc; 2614 struct sk_if_softc *sc_if; 2615 struct mbuf *m_head; 2616 int enq; 2617 2618 sc_if = ifp->if_softc; 2619 sc = sc_if->sk_softc; 2620 2621 SK_IF_LOCK_ASSERT(sc_if); 2622 2623 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2624 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2625 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2626 if (m_head == NULL) 2627 break; 2628 2629 /* 2630 * Pack the data into the transmit ring. If we 2631 * don't have room, set the OACTIVE flag and wait 2632 * for the NIC to drain the ring. 2633 */ 2634 if (sk_encap(sc_if, &m_head)) { 2635 if (m_head == NULL) 2636 break; 2637 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2638 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2639 break; 2640 } 2641 2642 enq++; 2643 /* 2644 * If there's a BPF listener, bounce a copy of this frame 2645 * to him. 2646 */ 2647 BPF_MTAP(ifp, m_head); 2648 } 2649 2650 if (enq > 0) { 2651 /* Transmit */ 2652 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2653 2654 /* Set a timeout in case the chip goes out to lunch. */ 2655 ifp->if_timer = 5; 2656 } 2657 } 2658 2659 2660 static void 2661 sk_watchdog(ifp) 2662 struct ifnet *ifp; 2663 { 2664 struct sk_if_softc *sc_if; 2665 2666 sc_if = ifp->if_softc; 2667 2668 SK_IF_LOCK(sc_if); 2669 /* 2670 * Reclaim first as there is a possibility of losing Tx completion 2671 * interrupts. 2672 */ 2673 sk_txeof(sc_if); 2674 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2675 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2676 ifp->if_oerrors++; 2677 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2678 sk_init_locked(sc_if); 2679 } 2680 SK_IF_UNLOCK(sc_if); 2681 2682 return; 2683 } 2684 2685 static void 2686 skc_shutdown(dev) 2687 device_t dev; 2688 { 2689 struct sk_softc *sc; 2690 2691 sc = device_get_softc(dev); 2692 SK_LOCK(sc); 2693 2694 /* Turn off the 'driver is loaded' LED. */ 2695 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2696 2697 /* 2698 * Reset the GEnesis controller. Doing this should also 2699 * assert the resets on the attached XMAC(s). 2700 */ 2701 sk_reset(sc); 2702 SK_UNLOCK(sc); 2703 2704 return; 2705 } 2706 2707 static int 2708 skc_suspend(dev) 2709 device_t dev; 2710 { 2711 struct sk_softc *sc; 2712 struct sk_if_softc *sc_if0, *sc_if1; 2713 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2714 2715 sc = device_get_softc(dev); 2716 2717 SK_LOCK(sc); 2718 2719 sc_if0 = sc->sk_if[SK_PORT_A]; 2720 sc_if1 = sc->sk_if[SK_PORT_B]; 2721 if (sc_if0 != NULL) 2722 ifp0 = sc_if0->sk_ifp; 2723 if (sc_if1 != NULL) 2724 ifp1 = sc_if1->sk_ifp; 2725 if (ifp0 != NULL) 2726 sk_stop(sc_if0); 2727 if (ifp1 != NULL) 2728 sk_stop(sc_if1); 2729 sc->sk_suspended = 1; 2730 2731 SK_UNLOCK(sc); 2732 2733 return (0); 2734 } 2735 2736 static int 2737 skc_resume(dev) 2738 device_t dev; 2739 { 2740 struct sk_softc *sc; 2741 struct sk_if_softc *sc_if0, *sc_if1; 2742 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2743 2744 sc = device_get_softc(dev); 2745 2746 SK_LOCK(sc); 2747 2748 sc_if0 = sc->sk_if[SK_PORT_A]; 2749 sc_if1 = sc->sk_if[SK_PORT_B]; 2750 if (sc_if0 != NULL) 2751 ifp0 = sc_if0->sk_ifp; 2752 if (sc_if1 != NULL) 2753 ifp1 = sc_if1->sk_ifp; 2754 if (ifp0 != NULL && ifp0->if_flags & IFF_UP) 2755 sk_init_locked(sc_if0); 2756 if (ifp1 != NULL && ifp1->if_flags & IFF_UP) 2757 sk_init_locked(sc_if1); 2758 sc->sk_suspended = 0; 2759 2760 SK_UNLOCK(sc); 2761 2762 return (0); 2763 } 2764 2765 /* 2766 * According to the data sheet from SK-NET GENESIS the hardware can compute 2767 * two Rx checksums at the same time(Each checksum start position is 2768 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2769 * does not work at least on my Yukon hardware. I tried every possible ways 2770 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2771 * checksum offload was disabled at the moment and only IP checksum offload 2772 * was enabled. 2773 * As nomral IP header size is 20 bytes I can't expect it would give an 2774 * increase in throughput. However it seems it doesn't hurt performance in 2775 * my testing. If there is a more detailed information for checksum secret 2776 * of the hardware in question please contact yongari@FreeBSD.org to add 2777 * TCP/UDP checksum offload support. 2778 */ 2779 static __inline void 2780 sk_rxcksum(ifp, m, csum) 2781 struct ifnet *ifp; 2782 struct mbuf *m; 2783 u_int32_t csum; 2784 { 2785 struct ether_header *eh; 2786 struct ip *ip; 2787 int32_t hlen, len, pktlen; 2788 u_int16_t csum1, csum2, ipcsum; 2789 2790 pktlen = m->m_pkthdr.len; 2791 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2792 return; 2793 eh = mtod(m, struct ether_header *); 2794 if (eh->ether_type != htons(ETHERTYPE_IP)) 2795 return; 2796 ip = (struct ip *)(eh + 1); 2797 if (ip->ip_v != IPVERSION) 2798 return; 2799 hlen = ip->ip_hl << 2; 2800 pktlen -= sizeof(struct ether_header); 2801 if (hlen < sizeof(struct ip)) 2802 return; 2803 if (ntohs(ip->ip_len) < hlen) 2804 return; 2805 if (ntohs(ip->ip_len) != pktlen) 2806 return; 2807 2808 csum1 = htons(csum & 0xffff); 2809 csum2 = htons((csum >> 16) & 0xffff); 2810 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 2811 /* checksum fixup for IP options */ 2812 len = hlen - sizeof(struct ip); 2813 if (len > 0) { 2814 /* 2815 * If the second checksum value is correct we can compute IP 2816 * checksum with simple math. Unfortunately the second checksum 2817 * value is wrong so we can't verify the checksum from the 2818 * value(It seems there is some magic here to get correct 2819 * value). If the second checksum value is correct it also 2820 * means we can get TCP/UDP checksum) here. However, it still 2821 * needs pseudo header checksum calculation due to hardware 2822 * limitations. 2823 */ 2824 return; 2825 } 2826 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 2827 if (ipcsum == 0xffff) 2828 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2829 } 2830 2831 static __inline int 2832 sk_rxvalid(sc, stat, len) 2833 struct sk_softc *sc; 2834 u_int32_t stat, len; 2835 { 2836 2837 if (sc->sk_type == SK_GENESIS) { 2838 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 2839 XM_RXSTAT_BYTES(stat) != len) 2840 return (0); 2841 } else { 2842 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2843 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2844 YU_RXSTAT_JABBER)) != 0 || 2845 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2846 YU_RXSTAT_BYTES(stat) != len) 2847 return (0); 2848 } 2849 2850 return (1); 2851 } 2852 2853 static void 2854 sk_rxeof(sc_if) 2855 struct sk_if_softc *sc_if; 2856 { 2857 struct sk_softc *sc; 2858 struct mbuf *m; 2859 struct ifnet *ifp; 2860 struct sk_rx_desc *cur_rx; 2861 struct sk_rxdesc *rxd; 2862 int cons, prog; 2863 u_int32_t csum, rxstat, sk_ctl; 2864 2865 sc = sc_if->sk_softc; 2866 ifp = sc_if->sk_ifp; 2867 2868 SK_IF_LOCK_ASSERT(sc_if); 2869 2870 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2871 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 2872 2873 prog = 0; 2874 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 2875 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 2876 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 2877 sk_ctl = le32toh(cur_rx->sk_ctl); 2878 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2879 break; 2880 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 2881 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2882 2883 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2884 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2885 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2886 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2887 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 2888 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2889 ifp->if_ierrors++; 2890 sk_discard_rxbuf(sc_if, cons); 2891 continue; 2892 } 2893 2894 m = rxd->rx_m; 2895 csum = le32toh(cur_rx->sk_csum); 2896 if (sk_newbuf(sc_if, cons) != 0) { 2897 ifp->if_iqdrops++; 2898 /* reuse old buffer */ 2899 sk_discard_rxbuf(sc_if, cons); 2900 continue; 2901 } 2902 m->m_pkthdr.rcvif = ifp; 2903 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2904 ifp->if_ipackets++; 2905 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2906 sk_rxcksum(ifp, m, csum); 2907 SK_IF_UNLOCK(sc_if); 2908 (*ifp->if_input)(ifp, m); 2909 SK_IF_LOCK(sc_if); 2910 } 2911 2912 if (prog > 0) { 2913 sc_if->sk_cdata.sk_rx_cons = cons; 2914 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2915 sc_if->sk_cdata.sk_rx_ring_map, 2916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2917 } 2918 } 2919 2920 static void 2921 sk_jumbo_rxeof(sc_if) 2922 struct sk_if_softc *sc_if; 2923 { 2924 struct sk_softc *sc; 2925 struct mbuf *m; 2926 struct ifnet *ifp; 2927 struct sk_rx_desc *cur_rx; 2928 struct sk_rxdesc *jrxd; 2929 int cons, prog; 2930 u_int32_t csum, rxstat, sk_ctl; 2931 2932 sc = sc_if->sk_softc; 2933 ifp = sc_if->sk_ifp; 2934 2935 SK_IF_LOCK_ASSERT(sc_if); 2936 2937 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2938 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 2939 2940 prog = 0; 2941 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 2942 prog < SK_JUMBO_RX_RING_CNT; 2943 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 2944 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 2945 sk_ctl = le32toh(cur_rx->sk_ctl); 2946 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2947 break; 2948 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 2949 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2950 2951 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2952 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2953 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2954 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2955 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 2956 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2957 ifp->if_ierrors++; 2958 sk_discard_jumbo_rxbuf(sc_if, cons); 2959 continue; 2960 } 2961 2962 m = jrxd->rx_m; 2963 csum = le32toh(cur_rx->sk_csum); 2964 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 2965 ifp->if_iqdrops++; 2966 /* reuse old buffer */ 2967 sk_discard_jumbo_rxbuf(sc_if, cons); 2968 continue; 2969 } 2970 m->m_pkthdr.rcvif = ifp; 2971 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2972 ifp->if_ipackets++; 2973 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2974 sk_rxcksum(ifp, m, csum); 2975 SK_IF_UNLOCK(sc_if); 2976 (*ifp->if_input)(ifp, m); 2977 SK_IF_LOCK(sc_if); 2978 } 2979 2980 if (prog > 0) { 2981 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 2982 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2983 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2984 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2985 } 2986 } 2987 2988 static void 2989 sk_txeof(sc_if) 2990 struct sk_if_softc *sc_if; 2991 { 2992 struct sk_softc *sc; 2993 struct sk_txdesc *txd; 2994 struct sk_tx_desc *cur_tx; 2995 struct ifnet *ifp; 2996 u_int32_t idx, sk_ctl; 2997 2998 sc = sc_if->sk_softc; 2999 ifp = sc_if->sk_ifp; 3000 3001 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3002 if (txd == NULL) 3003 return; 3004 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3005 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 3006 /* 3007 * Go through our tx ring and free mbufs for those 3008 * frames that have been sent. 3009 */ 3010 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 3011 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 3012 break; 3013 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 3014 sk_ctl = le32toh(cur_tx->sk_ctl); 3015 if (sk_ctl & SK_TXCTL_OWN) 3016 break; 3017 sc_if->sk_cdata.sk_tx_cnt--; 3018 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3019 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 3020 continue; 3021 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 3022 BUS_DMASYNC_POSTWRITE); 3023 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 3024 3025 ifp->if_opackets++; 3026 m_freem(txd->tx_m); 3027 txd->tx_m = NULL; 3028 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 3029 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 3030 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3031 } 3032 sc_if->sk_cdata.sk_tx_cons = idx; 3033 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 3034 3035 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3036 sc_if->sk_cdata.sk_tx_ring_map, 3037 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3038 } 3039 3040 static void 3041 sk_tick(xsc_if) 3042 void *xsc_if; 3043 { 3044 struct sk_if_softc *sc_if; 3045 struct mii_data *mii; 3046 struct ifnet *ifp; 3047 int i; 3048 3049 sc_if = xsc_if; 3050 ifp = sc_if->sk_ifp; 3051 mii = device_get_softc(sc_if->sk_miibus); 3052 3053 if (!(ifp->if_flags & IFF_UP)) 3054 return; 3055 3056 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3057 sk_intr_bcom(sc_if); 3058 return; 3059 } 3060 3061 /* 3062 * According to SysKonnect, the correct way to verify that 3063 * the link has come back up is to poll bit 0 of the GPIO 3064 * register three times. This pin has the signal from the 3065 * link_sync pin connected to it; if we read the same link 3066 * state 3 times in a row, we know the link is up. 3067 */ 3068 for (i = 0; i < 3; i++) { 3069 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 3070 break; 3071 } 3072 3073 if (i != 3) { 3074 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3075 return; 3076 } 3077 3078 /* Turn the GP0 interrupt back on. */ 3079 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3080 SK_XM_READ_2(sc_if, XM_ISR); 3081 mii_tick(mii); 3082 callout_stop(&sc_if->sk_tick_ch); 3083 } 3084 3085 static void 3086 sk_yukon_tick(xsc_if) 3087 void *xsc_if; 3088 { 3089 struct sk_if_softc *sc_if; 3090 struct mii_data *mii; 3091 3092 sc_if = xsc_if; 3093 mii = device_get_softc(sc_if->sk_miibus); 3094 3095 mii_tick(mii); 3096 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3097 } 3098 3099 static void 3100 sk_intr_bcom(sc_if) 3101 struct sk_if_softc *sc_if; 3102 { 3103 struct mii_data *mii; 3104 struct ifnet *ifp; 3105 int status; 3106 mii = device_get_softc(sc_if->sk_miibus); 3107 ifp = sc_if->sk_ifp; 3108 3109 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3110 3111 /* 3112 * Read the PHY interrupt register to make sure 3113 * we clear any pending interrupts. 3114 */ 3115 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 3116 3117 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3118 sk_init_xmac(sc_if); 3119 return; 3120 } 3121 3122 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 3123 int lstat; 3124 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 3125 BRGPHY_MII_AUXSTS); 3126 3127 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 3128 mii_mediachg(mii); 3129 /* Turn off the link LED. */ 3130 SK_IF_WRITE_1(sc_if, 0, 3131 SK_LINKLED1_CTL, SK_LINKLED_OFF); 3132 sc_if->sk_link = 0; 3133 } else if (status & BRGPHY_ISR_LNK_CHG) { 3134 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3135 BRGPHY_MII_IMR, 0xFF00); 3136 mii_tick(mii); 3137 sc_if->sk_link = 1; 3138 /* Turn on the link LED. */ 3139 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3140 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 3141 SK_LINKLED_BLINK_OFF); 3142 } else { 3143 mii_tick(mii); 3144 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3145 } 3146 } 3147 3148 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3149 3150 return; 3151 } 3152 3153 static void 3154 sk_intr_xmac(sc_if) 3155 struct sk_if_softc *sc_if; 3156 { 3157 struct sk_softc *sc; 3158 u_int16_t status; 3159 3160 sc = sc_if->sk_softc; 3161 status = SK_XM_READ_2(sc_if, XM_ISR); 3162 3163 /* 3164 * Link has gone down. Start MII tick timeout to 3165 * watch for link resync. 3166 */ 3167 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 3168 if (status & XM_ISR_GP0_SET) { 3169 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3170 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3171 } 3172 3173 if (status & XM_ISR_AUTONEG_DONE) { 3174 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3175 } 3176 } 3177 3178 if (status & XM_IMR_TX_UNDERRUN) 3179 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 3180 3181 if (status & XM_IMR_RX_OVERRUN) 3182 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 3183 3184 status = SK_XM_READ_2(sc_if, XM_ISR); 3185 3186 return; 3187 } 3188 3189 static void 3190 sk_intr_yukon(sc_if) 3191 struct sk_if_softc *sc_if; 3192 { 3193 u_int8_t status; 3194 3195 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 3196 /* RX overrun */ 3197 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 3198 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3199 SK_RFCTL_RX_FIFO_OVER); 3200 } 3201 /* TX underrun */ 3202 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 3203 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3204 SK_TFCTL_TX_FIFO_UNDER); 3205 } 3206 } 3207 3208 static void 3209 sk_intr(xsc) 3210 void *xsc; 3211 { 3212 struct sk_softc *sc = xsc; 3213 struct sk_if_softc *sc_if0, *sc_if1; 3214 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 3215 u_int32_t status; 3216 3217 SK_LOCK(sc); 3218 3219 status = CSR_READ_4(sc, SK_ISSR); 3220 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3221 goto done_locked; 3222 3223 sc_if0 = sc->sk_if[SK_PORT_A]; 3224 sc_if1 = sc->sk_if[SK_PORT_B]; 3225 3226 if (sc_if0 != NULL) 3227 ifp0 = sc_if0->sk_ifp; 3228 if (sc_if1 != NULL) 3229 ifp1 = sc_if1->sk_ifp; 3230 3231 for (; (status &= sc->sk_intrmask) != 0;) { 3232 /* Handle receive interrupts first. */ 3233 if (status & SK_ISR_RX1_EOF) { 3234 if (ifp0->if_mtu > SK_MAX_FRAMELEN) 3235 sk_jumbo_rxeof(sc_if0); 3236 else 3237 sk_rxeof(sc_if0); 3238 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3239 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3240 } 3241 if (status & SK_ISR_RX2_EOF) { 3242 if (ifp1->if_mtu > SK_MAX_FRAMELEN) 3243 sk_jumbo_rxeof(sc_if1); 3244 else 3245 sk_rxeof(sc_if1); 3246 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3247 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3248 } 3249 3250 /* Then transmit interrupts. */ 3251 if (status & SK_ISR_TX1_S_EOF) { 3252 sk_txeof(sc_if0); 3253 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3254 } 3255 if (status & SK_ISR_TX2_S_EOF) { 3256 sk_txeof(sc_if1); 3257 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3258 } 3259 3260 /* Then MAC interrupts. */ 3261 if (status & SK_ISR_MAC1 && 3262 ifp0->if_drv_flags & IFF_DRV_RUNNING) { 3263 if (sc->sk_type == SK_GENESIS) 3264 sk_intr_xmac(sc_if0); 3265 else 3266 sk_intr_yukon(sc_if0); 3267 } 3268 3269 if (status & SK_ISR_MAC2 && 3270 ifp1->if_drv_flags & IFF_DRV_RUNNING) { 3271 if (sc->sk_type == SK_GENESIS) 3272 sk_intr_xmac(sc_if1); 3273 else 3274 sk_intr_yukon(sc_if1); 3275 } 3276 3277 if (status & SK_ISR_EXTERNAL_REG) { 3278 if (ifp0 != NULL && 3279 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3280 sk_intr_bcom(sc_if0); 3281 if (ifp1 != NULL && 3282 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3283 sk_intr_bcom(sc_if1); 3284 } 3285 status = CSR_READ_4(sc, SK_ISSR); 3286 } 3287 3288 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3289 3290 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3291 sk_start_locked(ifp0); 3292 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3293 sk_start_locked(ifp1); 3294 3295 done_locked: 3296 SK_UNLOCK(sc); 3297 } 3298 3299 static void 3300 sk_init_xmac(sc_if) 3301 struct sk_if_softc *sc_if; 3302 { 3303 struct sk_softc *sc; 3304 struct ifnet *ifp; 3305 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3306 struct sk_bcom_hack bhack[] = { 3307 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3308 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3309 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3310 { 0, 0 } }; 3311 3312 SK_IF_LOCK_ASSERT(sc_if); 3313 3314 sc = sc_if->sk_softc; 3315 ifp = sc_if->sk_ifp; 3316 3317 /* Unreset the XMAC. */ 3318 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3319 DELAY(1000); 3320 3321 /* Reset the XMAC's internal state. */ 3322 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3323 3324 /* Save the XMAC II revision */ 3325 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3326 3327 /* 3328 * Perform additional initialization for external PHYs, 3329 * namely for the 1000baseTX cards that use the XMAC's 3330 * GMII mode. 3331 */ 3332 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3333 int i = 0; 3334 u_int32_t val; 3335 3336 /* Take PHY out of reset. */ 3337 val = sk_win_read_4(sc, SK_GPIO); 3338 if (sc_if->sk_port == SK_PORT_A) 3339 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3340 else 3341 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3342 sk_win_write_4(sc, SK_GPIO, val); 3343 3344 /* Enable GMII mode on the XMAC. */ 3345 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3346 3347 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3348 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3349 DELAY(10000); 3350 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3351 BRGPHY_MII_IMR, 0xFFF0); 3352 3353 /* 3354 * Early versions of the BCM5400 apparently have 3355 * a bug that requires them to have their reserved 3356 * registers initialized to some magic values. I don't 3357 * know what the numbers do, I'm just the messenger. 3358 */ 3359 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3360 == 0x6041) { 3361 while(bhack[i].reg) { 3362 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3363 bhack[i].reg, bhack[i].val); 3364 i++; 3365 } 3366 } 3367 } 3368 3369 /* Set station address */ 3370 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3371 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3372 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3373 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3374 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3375 3376 if (ifp->if_flags & IFF_BROADCAST) { 3377 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3378 } else { 3379 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3380 } 3381 3382 /* We don't need the FCS appended to the packet. */ 3383 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3384 3385 /* We want short frames padded to 60 bytes. */ 3386 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3387 3388 /* 3389 * Enable the reception of all error frames. This is is 3390 * a necessary evil due to the design of the XMAC. The 3391 * XMAC's receive FIFO is only 8K in size, however jumbo 3392 * frames can be up to 9000 bytes in length. When bad 3393 * frame filtering is enabled, the XMAC's RX FIFO operates 3394 * in 'store and forward' mode. For this to work, the 3395 * entire frame has to fit into the FIFO, but that means 3396 * that jumbo frames larger than 8192 bytes will be 3397 * truncated. Disabling all bad frame filtering causes 3398 * the RX FIFO to operate in streaming mode, in which 3399 * case the XMAC will start transfering frames out of the 3400 * RX FIFO as soon as the FIFO threshold is reached. 3401 */ 3402 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3403 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3404 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3405 XM_MODE_RX_INRANGELEN); 3406 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3407 } else 3408 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3409 3410 /* 3411 * Bump up the transmit threshold. This helps hold off transmit 3412 * underruns when we're blasting traffic from both ports at once. 3413 */ 3414 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3415 3416 /* Set promiscuous mode */ 3417 sk_setpromisc(sc_if); 3418 3419 /* Set multicast filter */ 3420 sk_setmulti(sc_if); 3421 3422 /* Clear and enable interrupts */ 3423 SK_XM_READ_2(sc_if, XM_ISR); 3424 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3425 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3426 else 3427 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3428 3429 /* Configure MAC arbiter */ 3430 switch(sc_if->sk_xmac_rev) { 3431 case XM_XMAC_REV_B2: 3432 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3433 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3434 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3435 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3436 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3437 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3438 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3439 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3440 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3441 break; 3442 case XM_XMAC_REV_C1: 3443 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3444 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3445 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3446 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3447 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3448 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3449 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3450 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3451 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3452 break; 3453 default: 3454 break; 3455 } 3456 sk_win_write_2(sc, SK_MACARB_CTL, 3457 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3458 3459 sc_if->sk_link = 1; 3460 3461 return; 3462 } 3463 3464 static void 3465 sk_init_yukon(sc_if) 3466 struct sk_if_softc *sc_if; 3467 { 3468 u_int32_t phy, v; 3469 u_int16_t reg; 3470 struct sk_softc *sc; 3471 struct ifnet *ifp; 3472 int i; 3473 3474 SK_IF_LOCK_ASSERT(sc_if); 3475 3476 sc = sc_if->sk_softc; 3477 ifp = sc_if->sk_ifp; 3478 3479 if (sc->sk_type == SK_YUKON_LITE && 3480 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3481 /* 3482 * Workaround code for COMA mode, set PHY reset. 3483 * Otherwise it will not correctly take chip out of 3484 * powerdown (coma) 3485 */ 3486 v = sk_win_read_4(sc, SK_GPIO); 3487 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3488 sk_win_write_4(sc, SK_GPIO, v); 3489 } 3490 3491 /* GMAC and GPHY Reset */ 3492 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3493 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3494 DELAY(1000); 3495 3496 if (sc->sk_type == SK_YUKON_LITE && 3497 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3498 /* 3499 * Workaround code for COMA mode, clear PHY reset 3500 */ 3501 v = sk_win_read_4(sc, SK_GPIO); 3502 v |= SK_GPIO_DIR9; 3503 v &= ~SK_GPIO_DAT9; 3504 sk_win_write_4(sc, SK_GPIO, v); 3505 } 3506 3507 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3508 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3509 3510 if (sc->sk_coppertype) 3511 phy |= SK_GPHY_COPPER; 3512 else 3513 phy |= SK_GPHY_FIBER; 3514 3515 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3516 DELAY(1000); 3517 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3518 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3519 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3520 3521 /* unused read of the interrupt source register */ 3522 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3523 3524 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3525 3526 /* MIB Counter Clear Mode set */ 3527 reg |= YU_PAR_MIB_CLR; 3528 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3529 3530 /* MIB Counter Clear Mode clear */ 3531 reg &= ~YU_PAR_MIB_CLR; 3532 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3533 3534 /* receive control reg */ 3535 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3536 3537 /* transmit parameter register */ 3538 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3539 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3540 3541 /* serial mode register */ 3542 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3543 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3544 reg |= YU_SMR_MFL_JUMBO; 3545 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3546 3547 /* Setup Yukon's address */ 3548 for (i = 0; i < 3; i++) { 3549 /* Write Source Address 1 (unicast filter) */ 3550 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3551 IF_LLADDR(sc_if->sk_ifp)[i * 2] | 3552 IF_LLADDR(sc_if->sk_ifp)[i * 2 + 1] << 8); 3553 } 3554 3555 for (i = 0; i < 3; i++) { 3556 reg = sk_win_read_2(sc_if->sk_softc, 3557 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 3558 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 3559 } 3560 3561 /* Set promiscuous mode */ 3562 sk_setpromisc(sc_if); 3563 3564 /* Set multicast filter */ 3565 sk_setmulti(sc_if); 3566 3567 /* enable interrupt mask for counter overflows */ 3568 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3569 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3570 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3571 3572 /* Configure RX MAC FIFO Flush Mask */ 3573 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3574 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3575 YU_RXSTAT_JABBER; 3576 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3577 3578 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3579 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3580 v = SK_TFCTL_OPERATION_ON; 3581 else 3582 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3583 /* Configure RX MAC FIFO */ 3584 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3585 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3586 3587 /* Increase flush threshould to 64 bytes */ 3588 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3589 SK_RFCTL_FIFO_THRESHOLD + 1); 3590 3591 /* Configure TX MAC FIFO */ 3592 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3593 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3594 } 3595 3596 /* 3597 * Note that to properly initialize any part of the GEnesis chip, 3598 * you first have to take it out of reset mode. 3599 */ 3600 static void 3601 sk_init(xsc) 3602 void *xsc; 3603 { 3604 struct sk_if_softc *sc_if = xsc; 3605 3606 SK_IF_LOCK(sc_if); 3607 sk_init_locked(sc_if); 3608 SK_IF_UNLOCK(sc_if); 3609 3610 return; 3611 } 3612 3613 static void 3614 sk_init_locked(sc_if) 3615 struct sk_if_softc *sc_if; 3616 { 3617 struct sk_softc *sc; 3618 struct ifnet *ifp; 3619 struct mii_data *mii; 3620 u_int16_t reg; 3621 u_int32_t imr; 3622 int error; 3623 3624 SK_IF_LOCK_ASSERT(sc_if); 3625 3626 ifp = sc_if->sk_ifp; 3627 sc = sc_if->sk_softc; 3628 mii = device_get_softc(sc_if->sk_miibus); 3629 3630 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3631 return; 3632 3633 /* Cancel pending I/O and free all RX/TX buffers. */ 3634 sk_stop(sc_if); 3635 3636 if (sc->sk_type == SK_GENESIS) { 3637 /* Configure LINK_SYNC LED */ 3638 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3639 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3640 SK_LINKLED_LINKSYNC_ON); 3641 3642 /* Configure RX LED */ 3643 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3644 SK_RXLEDCTL_COUNTER_START); 3645 3646 /* Configure TX LED */ 3647 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3648 SK_TXLEDCTL_COUNTER_START); 3649 } 3650 3651 /* 3652 * Configure descriptor poll timer 3653 * 3654 * SK-NET GENESIS data sheet says that possibility of losing Start 3655 * transmit command due to CPU/cache related interim storage problems 3656 * under certain conditions. The document recommends a polling 3657 * mechanism to send a Start transmit command to initiate transfer 3658 * of ready descriptors regulary. To cope with this issue sk(4) now 3659 * enables descriptor poll timer to initiate descriptor processing 3660 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3661 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3662 * command instead of waiting for next descriptor polling time. 3663 * The same rule may apply to Rx side too but it seems that is not 3664 * needed at the moment. 3665 * Since sk(4) uses descriptor polling as a last resort there is no 3666 * need to set smaller polling time than maximum allowable one. 3667 */ 3668 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3669 3670 /* Configure I2C registers */ 3671 3672 /* Configure XMAC(s) */ 3673 switch (sc->sk_type) { 3674 case SK_GENESIS: 3675 sk_init_xmac(sc_if); 3676 break; 3677 case SK_YUKON: 3678 case SK_YUKON_LITE: 3679 case SK_YUKON_LP: 3680 sk_init_yukon(sc_if); 3681 break; 3682 } 3683 mii_mediachg(mii); 3684 3685 if (sc->sk_type == SK_GENESIS) { 3686 /* Configure MAC FIFOs */ 3687 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3688 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3689 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3690 3691 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3692 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3693 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3694 } 3695 3696 /* Configure transmit arbiter(s) */ 3697 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3698 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3699 3700 /* Configure RAMbuffers */ 3701 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3702 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3703 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3704 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3705 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3706 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3707 3708 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3709 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3710 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3711 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3712 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3713 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3714 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3715 3716 /* Configure BMUs */ 3717 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3718 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3719 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3720 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3721 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3722 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3723 } else { 3724 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3725 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3726 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3727 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3728 } 3729 3730 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3731 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3732 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3733 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3734 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3735 3736 /* Init descriptors */ 3737 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3738 error = sk_init_jumbo_rx_ring(sc_if); 3739 else 3740 error = sk_init_rx_ring(sc_if); 3741 if (error != 0) { 3742 device_printf(sc_if->sk_if_dev, 3743 "initialization failed: no memory for rx buffers\n"); 3744 sk_stop(sc_if); 3745 return; 3746 } 3747 sk_init_tx_ring(sc_if); 3748 3749 /* Set interrupt moderation if changed via sysctl. */ 3750 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3751 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3752 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3753 sc->sk_int_ticks)); 3754 if (bootverbose) 3755 device_printf(sc_if->sk_if_dev, 3756 "interrupt moderation is %d us.\n", 3757 sc->sk_int_mod); 3758 } 3759 3760 /* Configure interrupt handling */ 3761 CSR_READ_4(sc, SK_ISSR); 3762 if (sc_if->sk_port == SK_PORT_A) 3763 sc->sk_intrmask |= SK_INTRS1; 3764 else 3765 sc->sk_intrmask |= SK_INTRS2; 3766 3767 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3768 3769 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3770 3771 /* Start BMUs. */ 3772 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3773 3774 switch(sc->sk_type) { 3775 case SK_GENESIS: 3776 /* Enable XMACs TX and RX state machines */ 3777 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3778 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3779 break; 3780 case SK_YUKON: 3781 case SK_YUKON_LITE: 3782 case SK_YUKON_LP: 3783 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3784 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3785 #if 0 3786 /* XXX disable 100Mbps and full duplex mode? */ 3787 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3788 #endif 3789 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3790 } 3791 3792 /* Activate descriptor polling timer */ 3793 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 3794 /* start transfer of Tx descriptors */ 3795 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 3796 3797 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3798 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3799 3800 switch (sc->sk_type) { 3801 case SK_YUKON: 3802 case SK_YUKON_LITE: 3803 case SK_YUKON_LP: 3804 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3805 break; 3806 } 3807 3808 return; 3809 } 3810 3811 static void 3812 sk_stop(sc_if) 3813 struct sk_if_softc *sc_if; 3814 { 3815 int i; 3816 struct sk_softc *sc; 3817 struct sk_txdesc *txd; 3818 struct sk_rxdesc *rxd; 3819 struct sk_rxdesc *jrxd; 3820 struct ifnet *ifp; 3821 u_int32_t val; 3822 3823 SK_IF_LOCK_ASSERT(sc_if); 3824 sc = sc_if->sk_softc; 3825 ifp = sc_if->sk_ifp; 3826 3827 callout_stop(&sc_if->sk_tick_ch); 3828 3829 /* stop Tx descriptor polling timer */ 3830 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 3831 /* stop transfer of Tx descriptors */ 3832 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 3833 for (i = 0; i < SK_TIMEOUT; i++) { 3834 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 3835 if ((val & SK_TXBMU_TX_STOP) == 0) 3836 break; 3837 DELAY(1); 3838 } 3839 if (i == SK_TIMEOUT) 3840 device_printf(sc_if->sk_if_dev, 3841 "can not stop transfer of Tx descriptor\n"); 3842 /* stop transfer of Rx descriptors */ 3843 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 3844 for (i = 0; i < SK_TIMEOUT; i++) { 3845 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 3846 if ((val & SK_RXBMU_RX_STOP) == 0) 3847 break; 3848 DELAY(1); 3849 } 3850 if (i == SK_TIMEOUT) 3851 device_printf(sc_if->sk_if_dev, 3852 "can not stop transfer of Rx descriptor\n"); 3853 3854 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3855 /* Put PHY back into reset. */ 3856 val = sk_win_read_4(sc, SK_GPIO); 3857 if (sc_if->sk_port == SK_PORT_A) { 3858 val |= SK_GPIO_DIR0; 3859 val &= ~SK_GPIO_DAT0; 3860 } else { 3861 val |= SK_GPIO_DIR2; 3862 val &= ~SK_GPIO_DAT2; 3863 } 3864 sk_win_write_4(sc, SK_GPIO, val); 3865 } 3866 3867 /* Turn off various components of this interface. */ 3868 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3869 switch (sc->sk_type) { 3870 case SK_GENESIS: 3871 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 3872 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 3873 break; 3874 case SK_YUKON: 3875 case SK_YUKON_LITE: 3876 case SK_YUKON_LP: 3877 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 3878 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 3879 break; 3880 } 3881 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 3882 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3883 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 3884 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3885 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 3886 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3887 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3888 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 3889 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 3890 3891 /* Disable interrupts */ 3892 if (sc_if->sk_port == SK_PORT_A) 3893 sc->sk_intrmask &= ~SK_INTRS1; 3894 else 3895 sc->sk_intrmask &= ~SK_INTRS2; 3896 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3897 3898 SK_XM_READ_2(sc_if, XM_ISR); 3899 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3900 3901 /* Free RX and TX mbufs still in the queues. */ 3902 for (i = 0; i < SK_RX_RING_CNT; i++) { 3903 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 3904 if (rxd->rx_m != NULL) { 3905 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 3906 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3907 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 3908 rxd->rx_dmamap); 3909 m_freem(rxd->rx_m); 3910 rxd->rx_m = NULL; 3911 } 3912 } 3913 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 3914 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 3915 if (jrxd->rx_m != NULL) { 3916 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 3917 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3918 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 3919 jrxd->rx_dmamap); 3920 m_freem(jrxd->rx_m); 3921 jrxd->rx_m = NULL; 3922 } 3923 } 3924 for (i = 0; i < SK_TX_RING_CNT; i++) { 3925 txd = &sc_if->sk_cdata.sk_txdesc[i]; 3926 if (txd->tx_m != NULL) { 3927 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 3928 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3929 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 3930 txd->tx_dmamap); 3931 m_freem(txd->tx_m); 3932 txd->tx_m = NULL; 3933 } 3934 } 3935 3936 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 3937 3938 return; 3939 } 3940 3941 static int 3942 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3943 { 3944 int error, value; 3945 3946 if (!arg1) 3947 return (EINVAL); 3948 value = *(int *)arg1; 3949 error = sysctl_handle_int(oidp, &value, 0, req); 3950 if (error || !req->newptr) 3951 return (error); 3952 if (value < low || value > high) 3953 return (EINVAL); 3954 *(int *)arg1 = value; 3955 return (0); 3956 } 3957 3958 static int 3959 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 3960 { 3961 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 3962 } 3963