1 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 37 * 38 * Permission to use, copy, modify, and distribute this software for any 39 * purpose with or without fee is hereby granted, provided that the above 40 * copyright notice and this permission notice appear in all copies. 41 * 42 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 43 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 44 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 45 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 46 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 47 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 48 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 49 */ 50 51 /* 52 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 53 * the SK-984x series adapters, both single port and dual port. 54 * References: 55 * The XaQti XMAC II datasheet, 56 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 57 * The SysKonnect GEnesis manual, http://www.syskonnect.com 58 * 59 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 60 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 61 * convenience to others until Vitesse corrects this problem: 62 * 63 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 64 * 65 * Written by Bill Paul <wpaul@ee.columbia.edu> 66 * Department of Electrical Engineering 67 * Columbia University, New York City 68 */ 69 70 /* 71 * The SysKonnect gigabit ethernet adapters consist of two main 72 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 73 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 74 * components and a PHY while the GEnesis controller provides a PCI 75 * interface with DMA support. Each card may have between 512K and 76 * 2MB of SRAM on board depending on the configuration. 77 * 78 * The SysKonnect GEnesis controller can have either one or two XMAC 79 * chips connected to it, allowing single or dual port NIC configurations. 80 * SysKonnect has the distinction of being the only vendor on the market 81 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 82 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 83 * XMAC registers. This driver takes advantage of these features to allow 84 * both XMACs to operate as independent interfaces. 85 */ 86 87 #include <sys/cdefs.h> 88 __FBSDID("$FreeBSD$"); 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/bus_pio.h> 110 #include <machine/bus_memio.h> 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #include <dev/mii/brgphyreg.h> 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 123 #if 0 124 #define SK_USEIOSPACE 125 #endif 126 127 #include <pci/if_skreg.h> 128 #include <pci/xmaciireg.h> 129 #include <pci/yukonreg.h> 130 131 MODULE_DEPEND(sk, pci, 1, 1, 1); 132 MODULE_DEPEND(sk, ether, 1, 1, 1); 133 MODULE_DEPEND(sk, miibus, 1, 1, 1); 134 135 /* "controller miibus0" required. See GENERIC if you get errors here. */ 136 #include "miibus_if.h" 137 138 #ifndef lint 139 static const char rcsid[] = 140 "$FreeBSD$"; 141 #endif 142 143 static struct sk_type sk_devs[] = { 144 { 145 VENDORID_SK, 146 DEVICEID_SK_V1, 147 "SysKonnect Gigabit Ethernet (V1.0)" 148 }, 149 { 150 VENDORID_SK, 151 DEVICEID_SK_V2, 152 "SysKonnect Gigabit Ethernet (V2.0)" 153 }, 154 { 155 VENDORID_3COM, 156 DEVICEID_3COM_3C940, 157 "3Com 3C940 Gigabit Ethernet" 158 }, 159 { 0, 0, NULL } 160 }; 161 162 static int skc_probe (device_t); 163 static int skc_attach (device_t); 164 static int skc_detach (device_t); 165 static void skc_shutdown (device_t); 166 static int sk_detach (device_t); 167 static int sk_probe (device_t); 168 static int sk_attach (device_t); 169 static void sk_tick (void *); 170 static void sk_intr (void *); 171 static void sk_intr_xmac (struct sk_if_softc *); 172 static void sk_intr_bcom (struct sk_if_softc *); 173 static void sk_intr_yukon (struct sk_if_softc *); 174 static void sk_rxeof (struct sk_if_softc *); 175 static void sk_txeof (struct sk_if_softc *); 176 static int sk_encap (struct sk_if_softc *, struct mbuf *, 177 u_int32_t *); 178 static void sk_start (struct ifnet *); 179 static int sk_ioctl (struct ifnet *, u_long, caddr_t); 180 static void sk_init (void *); 181 static void sk_init_xmac (struct sk_if_softc *); 182 static void sk_init_yukon (struct sk_if_softc *); 183 static void sk_stop (struct sk_if_softc *); 184 static void sk_watchdog (struct ifnet *); 185 static int sk_ifmedia_upd (struct ifnet *); 186 static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 187 static void sk_reset (struct sk_softc *); 188 static int sk_newbuf (struct sk_if_softc *, 189 struct sk_chain *, struct mbuf *); 190 static int sk_alloc_jumbo_mem (struct sk_if_softc *); 191 static void *sk_jalloc (struct sk_if_softc *); 192 static void sk_jfree (void *, void *); 193 static int sk_init_rx_ring (struct sk_if_softc *); 194 static void sk_init_tx_ring (struct sk_if_softc *); 195 static u_int32_t sk_win_read_4 (struct sk_softc *, int); 196 static u_int16_t sk_win_read_2 (struct sk_softc *, int); 197 static u_int8_t sk_win_read_1 (struct sk_softc *, int); 198 static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 199 static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 200 static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 201 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 202 static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int); 203 static void sk_vpd_read (struct sk_softc *); 204 205 static int sk_miibus_readreg (device_t, int, int); 206 static int sk_miibus_writereg (device_t, int, int, int); 207 static void sk_miibus_statchg (device_t); 208 209 static int sk_xmac_miibus_readreg (struct sk_if_softc *, int, int); 210 static int sk_xmac_miibus_writereg (struct sk_if_softc *, int, int, 211 int); 212 static void sk_xmac_miibus_statchg (struct sk_if_softc *); 213 214 static int sk_marv_miibus_readreg (struct sk_if_softc *, int, int); 215 static int sk_marv_miibus_writereg (struct sk_if_softc *, int, int, 216 int); 217 static void sk_marv_miibus_statchg (struct sk_if_softc *); 218 219 static u_int32_t sk_calchash (caddr_t); 220 static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 221 static void sk_setmulti (struct sk_if_softc *); 222 223 #ifdef SK_USEIOSPACE 224 #define SK_RES SYS_RES_IOPORT 225 #define SK_RID SK_PCI_LOIO 226 #else 227 #define SK_RES SYS_RES_MEMORY 228 #define SK_RID SK_PCI_LOMEM 229 #endif 230 231 /* 232 * Note that we have newbus methods for both the GEnesis controller 233 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 234 * the miibus code is a child of the XMACs. We need to do it this way 235 * so that the miibus drivers can access the PHY registers on the 236 * right PHY. It's not quite what I had in mind, but it's the only 237 * design that achieves the desired effect. 238 */ 239 static device_method_t skc_methods[] = { 240 /* Device interface */ 241 DEVMETHOD(device_probe, skc_probe), 242 DEVMETHOD(device_attach, skc_attach), 243 DEVMETHOD(device_detach, skc_detach), 244 DEVMETHOD(device_shutdown, skc_shutdown), 245 246 /* bus interface */ 247 DEVMETHOD(bus_print_child, bus_generic_print_child), 248 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 249 250 { 0, 0 } 251 }; 252 253 static driver_t skc_driver = { 254 "skc", 255 skc_methods, 256 sizeof(struct sk_softc) 257 }; 258 259 static devclass_t skc_devclass; 260 261 static device_method_t sk_methods[] = { 262 /* Device interface */ 263 DEVMETHOD(device_probe, sk_probe), 264 DEVMETHOD(device_attach, sk_attach), 265 DEVMETHOD(device_detach, sk_detach), 266 DEVMETHOD(device_shutdown, bus_generic_shutdown), 267 268 /* bus interface */ 269 DEVMETHOD(bus_print_child, bus_generic_print_child), 270 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 271 272 /* MII interface */ 273 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 274 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 275 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 276 277 { 0, 0 } 278 }; 279 280 static driver_t sk_driver = { 281 "sk", 282 sk_methods, 283 sizeof(struct sk_if_softc) 284 }; 285 286 static devclass_t sk_devclass; 287 288 DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0); 289 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 290 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 291 292 #define SK_SETBIT(sc, reg, x) \ 293 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 294 295 #define SK_CLRBIT(sc, reg, x) \ 296 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 297 298 #define SK_WIN_SETBIT_4(sc, reg, x) \ 299 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 300 301 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 302 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 303 304 #define SK_WIN_SETBIT_2(sc, reg, x) \ 305 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 306 307 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 308 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 309 310 static u_int32_t 311 sk_win_read_4(sc, reg) 312 struct sk_softc *sc; 313 int reg; 314 { 315 #ifdef SK_USEIOSPACE 316 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 317 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 318 #else 319 return(CSR_READ_4(sc, reg)); 320 #endif 321 } 322 323 static u_int16_t 324 sk_win_read_2(sc, reg) 325 struct sk_softc *sc; 326 int reg; 327 { 328 #ifdef SK_USEIOSPACE 329 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 330 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 331 #else 332 return(CSR_READ_2(sc, reg)); 333 #endif 334 } 335 336 static u_int8_t 337 sk_win_read_1(sc, reg) 338 struct sk_softc *sc; 339 int reg; 340 { 341 #ifdef SK_USEIOSPACE 342 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 343 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 344 #else 345 return(CSR_READ_1(sc, reg)); 346 #endif 347 } 348 349 static void 350 sk_win_write_4(sc, reg, val) 351 struct sk_softc *sc; 352 int reg; 353 u_int32_t val; 354 { 355 #ifdef SK_USEIOSPACE 356 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 357 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 358 #else 359 CSR_WRITE_4(sc, reg, val); 360 #endif 361 return; 362 } 363 364 static void 365 sk_win_write_2(sc, reg, val) 366 struct sk_softc *sc; 367 int reg; 368 u_int32_t val; 369 { 370 #ifdef SK_USEIOSPACE 371 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 372 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 373 #else 374 CSR_WRITE_2(sc, reg, val); 375 #endif 376 return; 377 } 378 379 static void 380 sk_win_write_1(sc, reg, val) 381 struct sk_softc *sc; 382 int reg; 383 u_int32_t val; 384 { 385 #ifdef SK_USEIOSPACE 386 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 387 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 388 #else 389 CSR_WRITE_1(sc, reg, val); 390 #endif 391 return; 392 } 393 394 /* 395 * The VPD EEPROM contains Vital Product Data, as suggested in 396 * the PCI 2.1 specification. The VPD data is separared into areas 397 * denoted by resource IDs. The SysKonnect VPD contains an ID string 398 * resource (the name of the adapter), a read-only area resource 399 * containing various key/data fields and a read/write area which 400 * can be used to store asset management information or log messages. 401 * We read the ID string and read-only into buffers attached to 402 * the controller softc structure for later use. At the moment, 403 * we only use the ID string during skc_attach(). 404 */ 405 static u_int8_t 406 sk_vpd_readbyte(sc, addr) 407 struct sk_softc *sc; 408 int addr; 409 { 410 int i; 411 412 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 413 for (i = 0; i < SK_TIMEOUT; i++) { 414 DELAY(1); 415 if (sk_win_read_2(sc, 416 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 417 break; 418 } 419 420 if (i == SK_TIMEOUT) 421 return(0); 422 423 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 424 } 425 426 static void 427 sk_vpd_read_res(sc, res, addr) 428 struct sk_softc *sc; 429 struct vpd_res *res; 430 int addr; 431 { 432 int i; 433 u_int8_t *ptr; 434 435 ptr = (u_int8_t *)res; 436 for (i = 0; i < sizeof(struct vpd_res); i++) 437 ptr[i] = sk_vpd_readbyte(sc, i + addr); 438 439 return; 440 } 441 442 static void 443 sk_vpd_read(sc) 444 struct sk_softc *sc; 445 { 446 int pos = 0, i; 447 struct vpd_res res; 448 449 if (sc->sk_vpd_prodname != NULL) 450 free(sc->sk_vpd_prodname, M_DEVBUF); 451 if (sc->sk_vpd_readonly != NULL) 452 free(sc->sk_vpd_readonly, M_DEVBUF); 453 sc->sk_vpd_prodname = NULL; 454 sc->sk_vpd_readonly = NULL; 455 456 sk_vpd_read_res(sc, &res, pos); 457 458 if (res.vr_id != VPD_RES_ID) { 459 printf("skc%d: bad VPD resource id: expected %x got %x\n", 460 sc->sk_unit, VPD_RES_ID, res.vr_id); 461 return; 462 } 463 464 pos += sizeof(res); 465 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 466 for (i = 0; i < res.vr_len; i++) 467 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 468 sc->sk_vpd_prodname[i] = '\0'; 469 pos += i; 470 471 sk_vpd_read_res(sc, &res, pos); 472 473 if (res.vr_id != VPD_RES_READ) { 474 printf("skc%d: bad VPD resource id: expected %x got %x\n", 475 sc->sk_unit, VPD_RES_READ, res.vr_id); 476 return; 477 } 478 479 pos += sizeof(res); 480 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 481 for (i = 0; i < res.vr_len + 1; i++) 482 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 483 484 return; 485 } 486 487 static int 488 sk_miibus_readreg(dev, phy, reg) 489 device_t dev; 490 int phy, reg; 491 { 492 struct sk_if_softc *sc_if; 493 494 sc_if = device_get_softc(dev); 495 496 switch(sc_if->sk_softc->sk_type) { 497 case SK_GENESIS: 498 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 499 case SK_YUKON: 500 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 501 } 502 503 return(0); 504 } 505 506 static int 507 sk_miibus_writereg(dev, phy, reg, val) 508 device_t dev; 509 int phy, reg, val; 510 { 511 struct sk_if_softc *sc_if; 512 513 sc_if = device_get_softc(dev); 514 515 switch(sc_if->sk_softc->sk_type) { 516 case SK_GENESIS: 517 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 518 case SK_YUKON: 519 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 520 } 521 522 return(0); 523 } 524 525 static void 526 sk_miibus_statchg(dev) 527 device_t dev; 528 { 529 struct sk_if_softc *sc_if; 530 531 sc_if = device_get_softc(dev); 532 533 switch(sc_if->sk_softc->sk_type) { 534 case SK_GENESIS: 535 sk_xmac_miibus_statchg(sc_if); 536 break; 537 case SK_YUKON: 538 sk_marv_miibus_statchg(sc_if); 539 break; 540 } 541 542 return; 543 } 544 545 static int 546 sk_xmac_miibus_readreg(sc_if, phy, reg) 547 struct sk_if_softc *sc_if; 548 int phy, reg; 549 { 550 int i; 551 552 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 553 return(0); 554 555 SK_IF_LOCK(sc_if); 556 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 557 SK_XM_READ_2(sc_if, XM_PHY_DATA); 558 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 559 for (i = 0; i < SK_TIMEOUT; i++) { 560 DELAY(1); 561 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 562 XM_MMUCMD_PHYDATARDY) 563 break; 564 } 565 566 if (i == SK_TIMEOUT) { 567 printf("sk%d: phy failed to come ready\n", 568 sc_if->sk_unit); 569 SK_IF_UNLOCK(sc_if); 570 return(0); 571 } 572 } 573 DELAY(1); 574 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 575 SK_IF_UNLOCK(sc_if); 576 return(i); 577 } 578 579 static int 580 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 581 struct sk_if_softc *sc_if; 582 int phy, reg, val; 583 { 584 int i; 585 586 SK_IF_LOCK(sc_if); 587 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 588 for (i = 0; i < SK_TIMEOUT; i++) { 589 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 590 break; 591 } 592 593 if (i == SK_TIMEOUT) { 594 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 595 SK_IF_UNLOCK(sc_if); 596 return(ETIMEDOUT); 597 } 598 599 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 600 for (i = 0; i < SK_TIMEOUT; i++) { 601 DELAY(1); 602 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 603 break; 604 } 605 SK_IF_UNLOCK(sc_if); 606 if (i == SK_TIMEOUT) 607 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 608 609 return(0); 610 } 611 612 static void 613 sk_xmac_miibus_statchg(sc_if) 614 struct sk_if_softc *sc_if; 615 { 616 struct mii_data *mii; 617 618 mii = device_get_softc(sc_if->sk_miibus); 619 620 SK_IF_LOCK(sc_if); 621 /* 622 * If this is a GMII PHY, manually set the XMAC's 623 * duplex mode accordingly. 624 */ 625 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 626 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 627 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 628 } else { 629 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 630 } 631 } 632 SK_IF_UNLOCK(sc_if); 633 634 return; 635 } 636 637 static int 638 sk_marv_miibus_readreg(sc_if, phy, reg) 639 struct sk_if_softc *sc_if; 640 int phy, reg; 641 { 642 u_int16_t val; 643 int i; 644 645 if (phy != 0 || 646 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 647 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 648 return(0); 649 } 650 651 SK_IF_LOCK(sc_if); 652 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 653 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 654 655 for (i = 0; i < SK_TIMEOUT; i++) { 656 DELAY(1); 657 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 658 if (val & YU_SMICR_READ_VALID) 659 break; 660 } 661 662 if (i == SK_TIMEOUT) { 663 printf("sk%d: phy failed to come ready\n", 664 sc_if->sk_unit); 665 SK_IF_UNLOCK(sc_if); 666 return(0); 667 } 668 669 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 670 SK_IF_UNLOCK(sc_if); 671 672 return(val); 673 } 674 675 static int 676 sk_marv_miibus_writereg(sc_if, phy, reg, val) 677 struct sk_if_softc *sc_if; 678 int phy, reg, val; 679 { 680 int i; 681 682 SK_IF_LOCK(sc_if); 683 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 684 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 685 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 686 687 for (i = 0; i < SK_TIMEOUT; i++) { 688 DELAY(1); 689 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 690 break; 691 } 692 SK_IF_UNLOCK(sc_if); 693 694 return(0); 695 } 696 697 static void 698 sk_marv_miibus_statchg(sc_if) 699 struct sk_if_softc *sc_if; 700 { 701 return; 702 } 703 704 #define SK_POLY 0xEDB88320 705 #define SK_BITS 6 706 707 static u_int32_t 708 sk_calchash(addr) 709 caddr_t addr; 710 { 711 u_int32_t idx, bit, data, crc; 712 713 /* Compute CRC for the address value. */ 714 crc = 0xFFFFFFFF; /* initial value */ 715 716 for (idx = 0; idx < 6; idx++) { 717 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 718 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 719 } 720 721 return (~crc & ((1 << SK_BITS) - 1)); 722 } 723 724 static void 725 sk_setfilt(sc_if, addr, slot) 726 struct sk_if_softc *sc_if; 727 caddr_t addr; 728 int slot; 729 { 730 int base; 731 732 base = XM_RXFILT_ENTRY(slot); 733 734 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 735 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 736 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 737 738 return; 739 } 740 741 static void 742 sk_setmulti(sc_if) 743 struct sk_if_softc *sc_if; 744 { 745 struct sk_softc *sc = sc_if->sk_softc; 746 struct ifnet *ifp = &sc_if->arpcom.ac_if; 747 u_int32_t hashes[2] = { 0, 0 }; 748 int h, i; 749 struct ifmultiaddr *ifma; 750 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 751 752 753 /* First, zot all the existing filters. */ 754 switch(sc->sk_type) { 755 case SK_GENESIS: 756 for (i = 1; i < XM_RXFILT_MAX; i++) 757 sk_setfilt(sc_if, (caddr_t)&dummy, i); 758 759 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 760 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 761 break; 762 case SK_YUKON: 763 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 764 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 765 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 766 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 767 break; 768 } 769 770 /* Now program new ones. */ 771 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 772 hashes[0] = 0xFFFFFFFF; 773 hashes[1] = 0xFFFFFFFF; 774 } else { 775 i = 1; 776 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 777 if (ifma->ifma_addr->sa_family != AF_LINK) 778 continue; 779 /* 780 * Program the first XM_RXFILT_MAX multicast groups 781 * into the perfect filter. For all others, 782 * use the hash table. 783 */ 784 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 785 sk_setfilt(sc_if, 786 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 787 i++; 788 continue; 789 } 790 791 h = sk_calchash( 792 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 793 if (h < 32) 794 hashes[0] |= (1 << h); 795 else 796 hashes[1] |= (1 << (h - 32)); 797 } 798 } 799 800 switch(sc->sk_type) { 801 case SK_GENESIS: 802 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 803 XM_MODE_RX_USE_PERFECT); 804 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 805 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 806 break; 807 case SK_YUKON: 808 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 809 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 810 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 811 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 812 break; 813 } 814 815 return; 816 } 817 818 static int 819 sk_init_rx_ring(sc_if) 820 struct sk_if_softc *sc_if; 821 { 822 struct sk_chain_data *cd = &sc_if->sk_cdata; 823 struct sk_ring_data *rd = sc_if->sk_rdata; 824 int i; 825 826 bzero((char *)rd->sk_rx_ring, 827 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 828 829 for (i = 0; i < SK_RX_RING_CNT; i++) { 830 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 831 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 832 return(ENOBUFS); 833 if (i == (SK_RX_RING_CNT - 1)) { 834 cd->sk_rx_chain[i].sk_next = 835 &cd->sk_rx_chain[0]; 836 rd->sk_rx_ring[i].sk_next = 837 vtophys(&rd->sk_rx_ring[0]); 838 } else { 839 cd->sk_rx_chain[i].sk_next = 840 &cd->sk_rx_chain[i + 1]; 841 rd->sk_rx_ring[i].sk_next = 842 vtophys(&rd->sk_rx_ring[i + 1]); 843 } 844 } 845 846 sc_if->sk_cdata.sk_rx_prod = 0; 847 sc_if->sk_cdata.sk_rx_cons = 0; 848 849 return(0); 850 } 851 852 static void 853 sk_init_tx_ring(sc_if) 854 struct sk_if_softc *sc_if; 855 { 856 struct sk_chain_data *cd = &sc_if->sk_cdata; 857 struct sk_ring_data *rd = sc_if->sk_rdata; 858 int i; 859 860 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 861 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 862 863 for (i = 0; i < SK_TX_RING_CNT; i++) { 864 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 865 if (i == (SK_TX_RING_CNT - 1)) { 866 cd->sk_tx_chain[i].sk_next = 867 &cd->sk_tx_chain[0]; 868 rd->sk_tx_ring[i].sk_next = 869 vtophys(&rd->sk_tx_ring[0]); 870 } else { 871 cd->sk_tx_chain[i].sk_next = 872 &cd->sk_tx_chain[i + 1]; 873 rd->sk_tx_ring[i].sk_next = 874 vtophys(&rd->sk_tx_ring[i + 1]); 875 } 876 } 877 878 sc_if->sk_cdata.sk_tx_prod = 0; 879 sc_if->sk_cdata.sk_tx_cons = 0; 880 sc_if->sk_cdata.sk_tx_cnt = 0; 881 882 return; 883 } 884 885 static int 886 sk_newbuf(sc_if, c, m) 887 struct sk_if_softc *sc_if; 888 struct sk_chain *c; 889 struct mbuf *m; 890 { 891 struct mbuf *m_new = NULL; 892 struct sk_rx_desc *r; 893 894 if (m == NULL) { 895 caddr_t *buf = NULL; 896 897 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 898 if (m_new == NULL) 899 return(ENOBUFS); 900 901 /* Allocate the jumbo buffer */ 902 buf = sk_jalloc(sc_if); 903 if (buf == NULL) { 904 m_freem(m_new); 905 #ifdef SK_VERBOSE 906 printf("sk%d: jumbo allocation failed " 907 "-- packet dropped!\n", sc_if->sk_unit); 908 #endif 909 return(ENOBUFS); 910 } 911 912 /* Attach the buffer to the mbuf */ 913 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 914 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 915 m_new->m_data = (void *)buf; 916 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 917 } else { 918 /* 919 * We're re-using a previously allocated mbuf; 920 * be sure to re-init pointers and lengths to 921 * default values. 922 */ 923 m_new = m; 924 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 925 m_new->m_data = m_new->m_ext.ext_buf; 926 } 927 928 /* 929 * Adjust alignment so packet payload begins on a 930 * longword boundary. Mandatory for Alpha, useful on 931 * x86 too. 932 */ 933 m_adj(m_new, ETHER_ALIGN); 934 935 r = c->sk_desc; 936 c->sk_mbuf = m_new; 937 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 938 r->sk_ctl = m_new->m_len | SK_RXSTAT; 939 940 return(0); 941 } 942 943 /* 944 * Allocate jumbo buffer storage. The SysKonnect adapters support 945 * "jumbograms" (9K frames), although SysKonnect doesn't currently 946 * use them in their drivers. In order for us to use them, we need 947 * large 9K receive buffers, however standard mbuf clusters are only 948 * 2048 bytes in size. Consequently, we need to allocate and manage 949 * our own jumbo buffer pool. Fortunately, this does not require an 950 * excessive amount of additional code. 951 */ 952 static int 953 sk_alloc_jumbo_mem(sc_if) 954 struct sk_if_softc *sc_if; 955 { 956 caddr_t ptr; 957 register int i; 958 struct sk_jpool_entry *entry; 959 960 /* Grab a big chunk o' storage. */ 961 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 962 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 963 964 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 965 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 966 return(ENOBUFS); 967 } 968 969 SLIST_INIT(&sc_if->sk_jfree_listhead); 970 SLIST_INIT(&sc_if->sk_jinuse_listhead); 971 972 /* 973 * Now divide it up into 9K pieces and save the addresses 974 * in an array. 975 */ 976 ptr = sc_if->sk_cdata.sk_jumbo_buf; 977 for (i = 0; i < SK_JSLOTS; i++) { 978 sc_if->sk_cdata.sk_jslots[i] = ptr; 979 ptr += SK_JLEN; 980 entry = malloc(sizeof(struct sk_jpool_entry), 981 M_DEVBUF, M_NOWAIT); 982 if (entry == NULL) { 983 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 984 sc_if->sk_cdata.sk_jumbo_buf = NULL; 985 printf("sk%d: no memory for jumbo " 986 "buffer queue!\n", sc_if->sk_unit); 987 return(ENOBUFS); 988 } 989 entry->slot = i; 990 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 991 entry, jpool_entries); 992 } 993 994 return(0); 995 } 996 997 /* 998 * Allocate a jumbo buffer. 999 */ 1000 static void * 1001 sk_jalloc(sc_if) 1002 struct sk_if_softc *sc_if; 1003 { 1004 struct sk_jpool_entry *entry; 1005 1006 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1007 1008 if (entry == NULL) { 1009 #ifdef SK_VERBOSE 1010 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 1011 #endif 1012 return(NULL); 1013 } 1014 1015 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1016 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 1017 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 1018 } 1019 1020 /* 1021 * Release a jumbo buffer. 1022 */ 1023 static void 1024 sk_jfree(buf, args) 1025 void *buf; 1026 void *args; 1027 { 1028 struct sk_if_softc *sc_if; 1029 int i; 1030 struct sk_jpool_entry *entry; 1031 1032 /* Extract the softc struct pointer. */ 1033 sc_if = (struct sk_if_softc *)args; 1034 1035 if (sc_if == NULL) 1036 panic("sk_jfree: didn't get softc pointer!"); 1037 1038 /* calculate the slot this buffer belongs to */ 1039 i = ((vm_offset_t)buf 1040 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1041 1042 if ((i < 0) || (i >= SK_JSLOTS)) 1043 panic("sk_jfree: asked to free buffer that we don't manage!"); 1044 1045 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 1046 if (entry == NULL) 1047 panic("sk_jfree: buffer not in use!"); 1048 entry->slot = i; 1049 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 1050 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 1051 1052 return; 1053 } 1054 1055 /* 1056 * Set media options. 1057 */ 1058 static int 1059 sk_ifmedia_upd(ifp) 1060 struct ifnet *ifp; 1061 { 1062 struct sk_if_softc *sc_if = ifp->if_softc; 1063 struct mii_data *mii; 1064 1065 mii = device_get_softc(sc_if->sk_miibus); 1066 sk_init(sc_if); 1067 mii_mediachg(mii); 1068 1069 return(0); 1070 } 1071 1072 /* 1073 * Report current media status. 1074 */ 1075 static void 1076 sk_ifmedia_sts(ifp, ifmr) 1077 struct ifnet *ifp; 1078 struct ifmediareq *ifmr; 1079 { 1080 struct sk_if_softc *sc_if; 1081 struct mii_data *mii; 1082 1083 sc_if = ifp->if_softc; 1084 mii = device_get_softc(sc_if->sk_miibus); 1085 1086 mii_pollstat(mii); 1087 ifmr->ifm_active = mii->mii_media_active; 1088 ifmr->ifm_status = mii->mii_media_status; 1089 1090 return; 1091 } 1092 1093 static int 1094 sk_ioctl(ifp, command, data) 1095 struct ifnet *ifp; 1096 u_long command; 1097 caddr_t data; 1098 { 1099 struct sk_if_softc *sc_if = ifp->if_softc; 1100 struct sk_softc *sc = sc_if->sk_softc; 1101 struct ifreq *ifr = (struct ifreq *) data; 1102 int error = 0; 1103 struct mii_data *mii; 1104 1105 SK_IF_LOCK(sc_if); 1106 1107 switch(command) { 1108 case SIOCSIFMTU: 1109 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1110 error = EINVAL; 1111 else { 1112 ifp->if_mtu = ifr->ifr_mtu; 1113 sk_init(sc_if); 1114 } 1115 break; 1116 case SIOCSIFFLAGS: 1117 if (ifp->if_flags & IFF_UP) { 1118 if (ifp->if_flags & IFF_RUNNING && 1119 ifp->if_flags & IFF_PROMISC && 1120 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1121 switch(sc->sk_type) { 1122 case SK_GENESIS: 1123 SK_XM_SETBIT_4(sc_if, XM_MODE, 1124 XM_MODE_RX_PROMISC); 1125 break; 1126 case SK_YUKON: 1127 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1128 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1129 break; 1130 } 1131 sk_setmulti(sc_if); 1132 } else if (ifp->if_flags & IFF_RUNNING && 1133 !(ifp->if_flags & IFF_PROMISC) && 1134 sc_if->sk_if_flags & IFF_PROMISC) { 1135 switch(sc->sk_type) { 1136 case SK_GENESIS: 1137 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1138 XM_MODE_RX_PROMISC); 1139 break; 1140 case SK_YUKON: 1141 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1142 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1143 break; 1144 } 1145 sk_setmulti(sc_if); 1146 } else 1147 sk_init(sc_if); 1148 } else { 1149 if (ifp->if_flags & IFF_RUNNING) 1150 sk_stop(sc_if); 1151 } 1152 sc_if->sk_if_flags = ifp->if_flags; 1153 error = 0; 1154 break; 1155 case SIOCADDMULTI: 1156 case SIOCDELMULTI: 1157 sk_setmulti(sc_if); 1158 error = 0; 1159 break; 1160 case SIOCGIFMEDIA: 1161 case SIOCSIFMEDIA: 1162 mii = device_get_softc(sc_if->sk_miibus); 1163 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1164 break; 1165 default: 1166 error = ether_ioctl(ifp, command, data); 1167 break; 1168 } 1169 1170 SK_IF_UNLOCK(sc_if); 1171 1172 return(error); 1173 } 1174 1175 /* 1176 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1177 * IDs against our list and return a device name if we find a match. 1178 */ 1179 static int 1180 skc_probe(dev) 1181 device_t dev; 1182 { 1183 struct sk_softc *sc; 1184 struct sk_type *t = sk_devs; 1185 1186 sc = device_get_softc(dev); 1187 1188 while(t->sk_name != NULL) { 1189 if ((pci_get_vendor(dev) == t->sk_vid) && 1190 (pci_get_device(dev) == t->sk_did)) { 1191 device_set_desc(dev, t->sk_name); 1192 return(0); 1193 } 1194 t++; 1195 } 1196 1197 return(ENXIO); 1198 } 1199 1200 /* 1201 * Force the GEnesis into reset, then bring it out of reset. 1202 */ 1203 static void 1204 sk_reset(sc) 1205 struct sk_softc *sc; 1206 { 1207 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1208 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1209 if (sc->sk_type == SK_YUKON) 1210 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1211 1212 DELAY(1000); 1213 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1214 DELAY(2); 1215 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1216 if (sc->sk_type == SK_YUKON) 1217 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1218 1219 if (sc->sk_type == SK_GENESIS) { 1220 /* Configure packet arbiter */ 1221 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1222 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1223 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1224 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1225 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1226 } 1227 1228 /* Enable RAM interface */ 1229 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1230 1231 /* 1232 * Configure interrupt moderation. The moderation timer 1233 * defers interrupts specified in the interrupt moderation 1234 * timer mask based on the timeout specified in the interrupt 1235 * moderation timer init register. Each bit in the timer 1236 * register represents 18.825ns, so to specify a timeout in 1237 * microseconds, we have to multiply by 54. 1238 */ 1239 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1240 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1241 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1242 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1243 1244 return; 1245 } 1246 1247 static int 1248 sk_probe(dev) 1249 device_t dev; 1250 { 1251 struct sk_softc *sc; 1252 1253 sc = device_get_softc(device_get_parent(dev)); 1254 1255 /* 1256 * Not much to do here. We always know there will be 1257 * at least one XMAC present, and if there are two, 1258 * skc_attach() will create a second device instance 1259 * for us. 1260 */ 1261 switch (sc->sk_type) { 1262 case SK_GENESIS: 1263 device_set_desc(dev, "XaQti Corp. XMAC II"); 1264 break; 1265 case SK_YUKON: 1266 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1267 break; 1268 } 1269 1270 return(0); 1271 } 1272 1273 /* 1274 * Each XMAC chip is attached as a separate logical IP interface. 1275 * Single port cards will have only one logical interface of course. 1276 */ 1277 static int 1278 sk_attach(dev) 1279 device_t dev; 1280 { 1281 struct sk_softc *sc; 1282 struct sk_if_softc *sc_if; 1283 struct ifnet *ifp; 1284 int i, port, error; 1285 1286 if (dev == NULL) 1287 return(EINVAL); 1288 1289 error = 0; 1290 sc_if = device_get_softc(dev); 1291 sc = device_get_softc(device_get_parent(dev)); 1292 SK_LOCK(sc); 1293 port = *(int *)device_get_ivars(dev); 1294 free(device_get_ivars(dev), M_DEVBUF); 1295 device_set_ivars(dev, NULL); 1296 1297 sc_if->sk_dev = dev; 1298 sc_if->sk_unit = device_get_unit(dev); 1299 sc_if->sk_port = port; 1300 sc_if->sk_softc = sc; 1301 sc->sk_if[port] = sc_if; 1302 if (port == SK_PORT_A) 1303 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1304 if (port == SK_PORT_B) 1305 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1306 1307 /* 1308 * Get station address for this interface. Note that 1309 * dual port cards actually come with three station 1310 * addresses: one for each port, plus an extra. The 1311 * extra one is used by the SysKonnect driver software 1312 * as a 'virtual' station address for when both ports 1313 * are operating in failover mode. Currently we don't 1314 * use this extra address. 1315 */ 1316 for (i = 0; i < ETHER_ADDR_LEN; i++) 1317 sc_if->arpcom.ac_enaddr[i] = 1318 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1319 1320 printf("sk%d: Ethernet address: %6D\n", 1321 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":"); 1322 1323 /* 1324 * Set up RAM buffer addresses. The NIC will have a certain 1325 * amount of SRAM on it, somewhere between 512K and 2MB. We 1326 * need to divide this up a) between the transmitter and 1327 * receiver and b) between the two XMACs, if this is a 1328 * dual port NIC. Our algotithm is to divide up the memory 1329 * evenly so that everyone gets a fair share. 1330 */ 1331 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1332 u_int32_t chunk, val; 1333 1334 chunk = sc->sk_ramsize / 2; 1335 val = sc->sk_rboff / sizeof(u_int64_t); 1336 sc_if->sk_rx_ramstart = val; 1337 val += (chunk / sizeof(u_int64_t)); 1338 sc_if->sk_rx_ramend = val - 1; 1339 sc_if->sk_tx_ramstart = val; 1340 val += (chunk / sizeof(u_int64_t)); 1341 sc_if->sk_tx_ramend = val - 1; 1342 } else { 1343 u_int32_t chunk, val; 1344 1345 chunk = sc->sk_ramsize / 4; 1346 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1347 sizeof(u_int64_t); 1348 sc_if->sk_rx_ramstart = val; 1349 val += (chunk / sizeof(u_int64_t)); 1350 sc_if->sk_rx_ramend = val - 1; 1351 sc_if->sk_tx_ramstart = val; 1352 val += (chunk / sizeof(u_int64_t)); 1353 sc_if->sk_tx_ramend = val - 1; 1354 } 1355 1356 /* Read and save PHY type and set PHY address */ 1357 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1358 switch(sc_if->sk_phytype) { 1359 case SK_PHYTYPE_XMAC: 1360 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1361 break; 1362 case SK_PHYTYPE_BCOM: 1363 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1364 break; 1365 case SK_PHYTYPE_MARV_COPPER: 1366 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1367 break; 1368 default: 1369 printf("skc%d: unsupported PHY type: %d\n", 1370 sc->sk_unit, sc_if->sk_phytype); 1371 error = ENODEV; 1372 goto fail; 1373 } 1374 1375 /* Allocate the descriptor queues. */ 1376 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1377 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1378 1379 if (sc_if->sk_rdata == NULL) { 1380 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1381 error = ENOMEM; 1382 goto fail; 1383 } 1384 1385 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1386 1387 /* Try to allocate memory for jumbo buffers. */ 1388 if (sk_alloc_jumbo_mem(sc_if)) { 1389 printf("sk%d: jumbo buffer allocation failed\n", 1390 sc_if->sk_unit); 1391 error = ENOMEM; 1392 goto fail; 1393 } 1394 1395 ifp = &sc_if->arpcom.ac_if; 1396 ifp->if_softc = sc_if; 1397 ifp->if_unit = sc_if->sk_unit; 1398 ifp->if_name = "sk"; 1399 ifp->if_mtu = ETHERMTU; 1400 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1401 ifp->if_ioctl = sk_ioctl; 1402 ifp->if_output = ether_output; 1403 ifp->if_start = sk_start; 1404 ifp->if_watchdog = sk_watchdog; 1405 ifp->if_init = sk_init; 1406 ifp->if_baudrate = 1000000000; 1407 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1408 1409 callout_handle_init(&sc_if->sk_tick_ch); 1410 1411 /* 1412 * Call MI attach routine. 1413 */ 1414 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1415 1416 /* 1417 * Do miibus setup. 1418 */ 1419 switch (sc->sk_type) { 1420 case SK_GENESIS: 1421 sk_init_xmac(sc_if); 1422 break; 1423 case SK_YUKON: 1424 sk_init_yukon(sc_if); 1425 break; 1426 } 1427 1428 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1429 sk_ifmedia_upd, sk_ifmedia_sts)) { 1430 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1431 ether_ifdetach(ifp); 1432 error = ENXIO; 1433 goto fail; 1434 } 1435 1436 fail: 1437 SK_UNLOCK(sc); 1438 if (error) { 1439 /* Access should be ok even though lock has been dropped */ 1440 sc->sk_if[port] = NULL; 1441 sk_detach(dev); 1442 } 1443 1444 return(error); 1445 } 1446 1447 /* 1448 * Attach the interface. Allocate softc structures, do ifmedia 1449 * setup and ethernet/BPF attach. 1450 */ 1451 static int 1452 skc_attach(dev) 1453 device_t dev; 1454 { 1455 struct sk_softc *sc; 1456 int unit, error = 0, rid, *port; 1457 1458 sc = device_get_softc(dev); 1459 unit = device_get_unit(dev); 1460 1461 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1462 MTX_DEF | MTX_RECURSE); 1463 #ifndef BURN_BRIDGES 1464 /* 1465 * Handle power management nonsense. 1466 */ 1467 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1468 u_int32_t iobase, membase, irq; 1469 1470 /* Save important PCI config data. */ 1471 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1472 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1473 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1474 1475 /* Reset the power state. */ 1476 printf("skc%d: chip is in D%d power mode " 1477 "-- setting to D0\n", unit, 1478 pci_get_powerstate(dev)); 1479 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1480 1481 /* Restore PCI config data. */ 1482 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1483 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1484 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1485 } 1486 #endif 1487 /* 1488 * Map control/status registers. 1489 */ 1490 pci_enable_busmaster(dev); 1491 1492 rid = SK_RID; 1493 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid, 1494 0, ~0, 1, RF_ACTIVE); 1495 1496 if (sc->sk_res == NULL) { 1497 printf("sk%d: couldn't map ports/memory\n", unit); 1498 error = ENXIO; 1499 goto fail; 1500 } 1501 1502 sc->sk_btag = rman_get_bustag(sc->sk_res); 1503 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1504 1505 /* Allocate interrupt */ 1506 rid = 0; 1507 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1508 RF_SHAREABLE | RF_ACTIVE); 1509 1510 if (sc->sk_irq == NULL) { 1511 printf("skc%d: couldn't map interrupt\n", unit); 1512 error = ENXIO; 1513 goto fail; 1514 } 1515 1516 /* Set adapter type */ 1517 switch (pci_get_device(dev)) { 1518 case DEVICEID_SK_V1: 1519 sc->sk_type = SK_GENESIS; 1520 break; 1521 case DEVICEID_SK_V2: 1522 case DEVICEID_3COM_3C940: 1523 sc->sk_type = SK_YUKON; 1524 break; 1525 } 1526 1527 /* Reset the adapter. */ 1528 sk_reset(sc); 1529 1530 sc->sk_unit = unit; 1531 1532 /* Read and save vital product data from EEPROM. */ 1533 sk_vpd_read(sc); 1534 1535 if (sc->sk_type == SK_GENESIS) { 1536 /* Read and save RAM size and RAMbuffer offset */ 1537 switch(sk_win_read_1(sc, SK_EPROM0)) { 1538 case SK_RAMSIZE_512K_64: 1539 sc->sk_ramsize = 0x80000; 1540 sc->sk_rboff = SK_RBOFF_0; 1541 break; 1542 case SK_RAMSIZE_1024K_64: 1543 sc->sk_ramsize = 0x100000; 1544 sc->sk_rboff = SK_RBOFF_80000; 1545 break; 1546 case SK_RAMSIZE_1024K_128: 1547 sc->sk_ramsize = 0x100000; 1548 sc->sk_rboff = SK_RBOFF_0; 1549 break; 1550 case SK_RAMSIZE_2048K_128: 1551 sc->sk_ramsize = 0x200000; 1552 sc->sk_rboff = SK_RBOFF_0; 1553 break; 1554 default: 1555 printf("skc%d: unknown ram size: %d\n", 1556 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1557 error = ENXIO; 1558 goto fail; 1559 } 1560 } else { 1561 sc->sk_ramsize = 0x20000; 1562 sc->sk_rboff = SK_RBOFF_0; 1563 } 1564 1565 /* Read and save physical media type */ 1566 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1567 case SK_PMD_1000BASESX: 1568 sc->sk_pmd = IFM_1000_SX; 1569 break; 1570 case SK_PMD_1000BASELX: 1571 sc->sk_pmd = IFM_1000_LX; 1572 break; 1573 case SK_PMD_1000BASECX: 1574 sc->sk_pmd = IFM_1000_CX; 1575 break; 1576 case SK_PMD_1000BASETX: 1577 sc->sk_pmd = IFM_1000_T; 1578 break; 1579 default: 1580 printf("skc%d: unknown media type: 0x%x\n", 1581 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1582 error = ENXIO; 1583 goto fail; 1584 } 1585 1586 /* Announce the product name. */ 1587 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1588 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1589 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1590 *port = SK_PORT_A; 1591 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1592 1593 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1594 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1595 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1596 *port = SK_PORT_B; 1597 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1598 } 1599 1600 /* Turn on the 'driver is loaded' LED. */ 1601 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1602 1603 bus_generic_attach(dev); 1604 1605 /* Hook interrupt last to avoid having to lock softc */ 1606 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1607 sk_intr, sc, &sc->sk_intrhand); 1608 1609 if (error) { 1610 printf("skc%d: couldn't set up irq\n", unit); 1611 goto fail; 1612 } 1613 1614 fail: 1615 if (error) 1616 skc_detach(dev); 1617 1618 return(error); 1619 } 1620 1621 /* 1622 * Shutdown hardware and free up resources. This can be called any 1623 * time after the mutex has been initialized. It is called in both 1624 * the error case in attach and the normal detach case so it needs 1625 * to be careful about only freeing resources that have actually been 1626 * allocated. 1627 */ 1628 static int 1629 sk_detach(dev) 1630 device_t dev; 1631 { 1632 struct sk_if_softc *sc_if; 1633 struct ifnet *ifp; 1634 1635 sc_if = device_get_softc(dev); 1636 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1637 ("sk mutex not initialized in sk_detach")); 1638 SK_IF_LOCK(sc_if); 1639 1640 ifp = &sc_if->arpcom.ac_if; 1641 /* These should only be active if attach_xmac succeeded */ 1642 if (device_is_attached(dev)) { 1643 sk_stop(sc_if); 1644 ether_ifdetach(ifp); 1645 } 1646 if (sc_if->sk_miibus) 1647 device_delete_child(dev, sc_if->sk_miibus); 1648 bus_generic_detach(dev); 1649 if (sc_if->sk_cdata.sk_jumbo_buf) 1650 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1651 if (sc_if->sk_rdata) { 1652 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), 1653 M_DEVBUF); 1654 } 1655 SK_IF_UNLOCK(sc_if); 1656 1657 return(0); 1658 } 1659 1660 static int 1661 skc_detach(dev) 1662 device_t dev; 1663 { 1664 struct sk_softc *sc; 1665 1666 sc = device_get_softc(dev); 1667 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1668 SK_LOCK(sc); 1669 1670 if (device_is_alive(dev)) { 1671 if (sc->sk_devs[SK_PORT_A] != NULL) 1672 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1673 if (sc->sk_devs[SK_PORT_B] != NULL) 1674 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1675 bus_generic_detach(dev); 1676 } 1677 1678 if (sc->sk_intrhand) 1679 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1680 if (sc->sk_irq) 1681 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1682 if (sc->sk_res) 1683 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1684 1685 SK_UNLOCK(sc); 1686 mtx_destroy(&sc->sk_mtx); 1687 1688 return(0); 1689 } 1690 1691 static int 1692 sk_encap(sc_if, m_head, txidx) 1693 struct sk_if_softc *sc_if; 1694 struct mbuf *m_head; 1695 u_int32_t *txidx; 1696 { 1697 struct sk_tx_desc *f = NULL; 1698 struct mbuf *m; 1699 u_int32_t frag, cur, cnt = 0; 1700 1701 m = m_head; 1702 cur = frag = *txidx; 1703 1704 /* 1705 * Start packing the mbufs in this chain into 1706 * the fragment pointers. Stop when we run out 1707 * of fragments or hit the end of the mbuf chain. 1708 */ 1709 for (m = m_head; m != NULL; m = m->m_next) { 1710 if (m->m_len != 0) { 1711 if ((SK_TX_RING_CNT - 1712 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1713 return(ENOBUFS); 1714 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1715 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1716 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1717 if (cnt == 0) 1718 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1719 else 1720 f->sk_ctl |= SK_TXCTL_OWN; 1721 cur = frag; 1722 SK_INC(frag, SK_TX_RING_CNT); 1723 cnt++; 1724 } 1725 } 1726 1727 if (m != NULL) 1728 return(ENOBUFS); 1729 1730 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1731 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1732 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1733 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1734 sc_if->sk_cdata.sk_tx_cnt += cnt; 1735 1736 *txidx = frag; 1737 1738 return(0); 1739 } 1740 1741 static void 1742 sk_start(ifp) 1743 struct ifnet *ifp; 1744 { 1745 struct sk_softc *sc; 1746 struct sk_if_softc *sc_if; 1747 struct mbuf *m_head = NULL; 1748 u_int32_t idx; 1749 1750 sc_if = ifp->if_softc; 1751 sc = sc_if->sk_softc; 1752 1753 SK_IF_LOCK(sc_if); 1754 1755 idx = sc_if->sk_cdata.sk_tx_prod; 1756 1757 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1758 IF_DEQUEUE(&ifp->if_snd, m_head); 1759 if (m_head == NULL) 1760 break; 1761 1762 /* 1763 * Pack the data into the transmit ring. If we 1764 * don't have room, set the OACTIVE flag and wait 1765 * for the NIC to drain the ring. 1766 */ 1767 if (sk_encap(sc_if, m_head, &idx)) { 1768 IF_PREPEND(&ifp->if_snd, m_head); 1769 ifp->if_flags |= IFF_OACTIVE; 1770 break; 1771 } 1772 1773 /* 1774 * If there's a BPF listener, bounce a copy of this frame 1775 * to him. 1776 */ 1777 BPF_MTAP(ifp, m_head); 1778 } 1779 1780 /* Transmit */ 1781 sc_if->sk_cdata.sk_tx_prod = idx; 1782 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1783 1784 /* Set a timeout in case the chip goes out to lunch. */ 1785 ifp->if_timer = 5; 1786 SK_IF_UNLOCK(sc_if); 1787 1788 return; 1789 } 1790 1791 1792 static void 1793 sk_watchdog(ifp) 1794 struct ifnet *ifp; 1795 { 1796 struct sk_if_softc *sc_if; 1797 1798 sc_if = ifp->if_softc; 1799 1800 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1801 sk_init(sc_if); 1802 1803 return; 1804 } 1805 1806 static void 1807 skc_shutdown(dev) 1808 device_t dev; 1809 { 1810 struct sk_softc *sc; 1811 1812 sc = device_get_softc(dev); 1813 SK_LOCK(sc); 1814 1815 /* Turn off the 'driver is loaded' LED. */ 1816 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1817 1818 /* 1819 * Reset the GEnesis controller. Doing this should also 1820 * assert the resets on the attached XMAC(s). 1821 */ 1822 sk_reset(sc); 1823 SK_UNLOCK(sc); 1824 1825 return; 1826 } 1827 1828 static void 1829 sk_rxeof(sc_if) 1830 struct sk_if_softc *sc_if; 1831 { 1832 struct mbuf *m; 1833 struct ifnet *ifp; 1834 struct sk_chain *cur_rx; 1835 int total_len = 0; 1836 int i; 1837 u_int32_t rxstat; 1838 1839 ifp = &sc_if->arpcom.ac_if; 1840 i = sc_if->sk_cdata.sk_rx_prod; 1841 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1842 1843 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1844 1845 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1846 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1847 m = cur_rx->sk_mbuf; 1848 cur_rx->sk_mbuf = NULL; 1849 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1850 SK_INC(i, SK_RX_RING_CNT); 1851 1852 if (rxstat & XM_RXSTAT_ERRFRAME) { 1853 ifp->if_ierrors++; 1854 sk_newbuf(sc_if, cur_rx, m); 1855 continue; 1856 } 1857 1858 /* 1859 * Try to allocate a new jumbo buffer. If that 1860 * fails, copy the packet to mbufs and put the 1861 * jumbo buffer back in the ring so it can be 1862 * re-used. If allocating mbufs fails, then we 1863 * have to drop the packet. 1864 */ 1865 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1866 struct mbuf *m0; 1867 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1868 ifp, NULL); 1869 sk_newbuf(sc_if, cur_rx, m); 1870 if (m0 == NULL) { 1871 printf("sk%d: no receive buffers " 1872 "available -- packet dropped!\n", 1873 sc_if->sk_unit); 1874 ifp->if_ierrors++; 1875 continue; 1876 } 1877 m = m0; 1878 } else { 1879 m->m_pkthdr.rcvif = ifp; 1880 m->m_pkthdr.len = m->m_len = total_len; 1881 } 1882 1883 ifp->if_ipackets++; 1884 (*ifp->if_input)(ifp, m); 1885 } 1886 1887 sc_if->sk_cdata.sk_rx_prod = i; 1888 1889 return; 1890 } 1891 1892 static void 1893 sk_txeof(sc_if) 1894 struct sk_if_softc *sc_if; 1895 { 1896 struct sk_tx_desc *cur_tx = NULL; 1897 struct ifnet *ifp; 1898 u_int32_t idx; 1899 1900 ifp = &sc_if->arpcom.ac_if; 1901 1902 /* 1903 * Go through our tx ring and free mbufs for those 1904 * frames that have been sent. 1905 */ 1906 idx = sc_if->sk_cdata.sk_tx_cons; 1907 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1908 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1909 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1910 break; 1911 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1912 ifp->if_opackets++; 1913 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1914 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1915 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1916 } 1917 sc_if->sk_cdata.sk_tx_cnt--; 1918 SK_INC(idx, SK_TX_RING_CNT); 1919 ifp->if_timer = 0; 1920 } 1921 1922 sc_if->sk_cdata.sk_tx_cons = idx; 1923 1924 if (cur_tx != NULL) 1925 ifp->if_flags &= ~IFF_OACTIVE; 1926 1927 return; 1928 } 1929 1930 static void 1931 sk_tick(xsc_if) 1932 void *xsc_if; 1933 { 1934 struct sk_if_softc *sc_if; 1935 struct mii_data *mii; 1936 struct ifnet *ifp; 1937 int i; 1938 1939 sc_if = xsc_if; 1940 SK_IF_LOCK(sc_if); 1941 ifp = &sc_if->arpcom.ac_if; 1942 mii = device_get_softc(sc_if->sk_miibus); 1943 1944 if (!(ifp->if_flags & IFF_UP)) { 1945 SK_IF_UNLOCK(sc_if); 1946 return; 1947 } 1948 1949 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1950 sk_intr_bcom(sc_if); 1951 SK_IF_UNLOCK(sc_if); 1952 return; 1953 } 1954 1955 /* 1956 * According to SysKonnect, the correct way to verify that 1957 * the link has come back up is to poll bit 0 of the GPIO 1958 * register three times. This pin has the signal from the 1959 * link_sync pin connected to it; if we read the same link 1960 * state 3 times in a row, we know the link is up. 1961 */ 1962 for (i = 0; i < 3; i++) { 1963 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1964 break; 1965 } 1966 1967 if (i != 3) { 1968 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1969 SK_IF_UNLOCK(sc_if); 1970 return; 1971 } 1972 1973 /* Turn the GP0 interrupt back on. */ 1974 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1975 SK_XM_READ_2(sc_if, XM_ISR); 1976 mii_tick(mii); 1977 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 1978 1979 SK_IF_UNLOCK(sc_if); 1980 return; 1981 } 1982 1983 static void 1984 sk_intr_bcom(sc_if) 1985 struct sk_if_softc *sc_if; 1986 { 1987 struct mii_data *mii; 1988 struct ifnet *ifp; 1989 int status; 1990 mii = device_get_softc(sc_if->sk_miibus); 1991 ifp = &sc_if->arpcom.ac_if; 1992 1993 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1994 1995 /* 1996 * Read the PHY interrupt register to make sure 1997 * we clear any pending interrupts. 1998 */ 1999 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2000 2001 if (!(ifp->if_flags & IFF_RUNNING)) { 2002 sk_init_xmac(sc_if); 2003 return; 2004 } 2005 2006 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2007 int lstat; 2008 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2009 BRGPHY_MII_AUXSTS); 2010 2011 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2012 mii_mediachg(mii); 2013 /* Turn off the link LED. */ 2014 SK_IF_WRITE_1(sc_if, 0, 2015 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2016 sc_if->sk_link = 0; 2017 } else if (status & BRGPHY_ISR_LNK_CHG) { 2018 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2019 BRGPHY_MII_IMR, 0xFF00); 2020 mii_tick(mii); 2021 sc_if->sk_link = 1; 2022 /* Turn on the link LED. */ 2023 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2024 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2025 SK_LINKLED_BLINK_OFF); 2026 } else { 2027 mii_tick(mii); 2028 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2029 } 2030 } 2031 2032 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2033 2034 return; 2035 } 2036 2037 static void 2038 sk_intr_xmac(sc_if) 2039 struct sk_if_softc *sc_if; 2040 { 2041 struct sk_softc *sc; 2042 u_int16_t status; 2043 2044 sc = sc_if->sk_softc; 2045 status = SK_XM_READ_2(sc_if, XM_ISR); 2046 2047 /* 2048 * Link has gone down. Start MII tick timeout to 2049 * watch for link resync. 2050 */ 2051 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2052 if (status & XM_ISR_GP0_SET) { 2053 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2054 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2055 } 2056 2057 if (status & XM_ISR_AUTONEG_DONE) { 2058 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2059 } 2060 } 2061 2062 if (status & XM_IMR_TX_UNDERRUN) 2063 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2064 2065 if (status & XM_IMR_RX_OVERRUN) 2066 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2067 2068 status = SK_XM_READ_2(sc_if, XM_ISR); 2069 2070 return; 2071 } 2072 2073 static void 2074 sk_intr_yukon(sc_if) 2075 struct sk_if_softc *sc_if; 2076 { 2077 int status; 2078 2079 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2080 2081 return; 2082 } 2083 2084 static void 2085 sk_intr(xsc) 2086 void *xsc; 2087 { 2088 struct sk_softc *sc = xsc; 2089 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 2090 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2091 u_int32_t status; 2092 2093 SK_LOCK(sc); 2094 2095 sc_if0 = sc->sk_if[SK_PORT_A]; 2096 sc_if1 = sc->sk_if[SK_PORT_B]; 2097 2098 if (sc_if0 != NULL) 2099 ifp0 = &sc_if0->arpcom.ac_if; 2100 if (sc_if1 != NULL) 2101 ifp1 = &sc_if1->arpcom.ac_if; 2102 2103 for (;;) { 2104 status = CSR_READ_4(sc, SK_ISSR); 2105 if (!(status & sc->sk_intrmask)) 2106 break; 2107 2108 /* Handle receive interrupts first. */ 2109 if (status & SK_ISR_RX1_EOF) { 2110 sk_rxeof(sc_if0); 2111 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2112 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2113 } 2114 if (status & SK_ISR_RX2_EOF) { 2115 sk_rxeof(sc_if1); 2116 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2117 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2118 } 2119 2120 /* Then transmit interrupts. */ 2121 if (status & SK_ISR_TX1_S_EOF) { 2122 sk_txeof(sc_if0); 2123 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2124 SK_TXBMU_CLR_IRQ_EOF); 2125 } 2126 if (status & SK_ISR_TX2_S_EOF) { 2127 sk_txeof(sc_if1); 2128 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2129 SK_TXBMU_CLR_IRQ_EOF); 2130 } 2131 2132 /* Then MAC interrupts. */ 2133 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 2134 if (sc->sk_type == SK_GENESIS) 2135 sk_intr_xmac(sc_if0); 2136 else 2137 sk_intr_yukon(sc_if0); 2138 } 2139 2140 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 2141 if (sc->sk_type == SK_GENESIS) 2142 sk_intr_xmac(sc_if1); 2143 else 2144 sk_intr_yukon(sc_if0); 2145 } 2146 2147 if (status & SK_ISR_EXTERNAL_REG) { 2148 if (ifp0 != NULL && 2149 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2150 sk_intr_bcom(sc_if0); 2151 if (ifp1 != NULL && 2152 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2153 sk_intr_bcom(sc_if1); 2154 } 2155 } 2156 2157 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2158 2159 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 2160 sk_start(ifp0); 2161 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 2162 sk_start(ifp1); 2163 2164 SK_UNLOCK(sc); 2165 2166 return; 2167 } 2168 2169 static void 2170 sk_init_xmac(sc_if) 2171 struct sk_if_softc *sc_if; 2172 { 2173 struct sk_softc *sc; 2174 struct ifnet *ifp; 2175 struct sk_bcom_hack bhack[] = { 2176 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2177 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2178 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2179 { 0, 0 } }; 2180 2181 sc = sc_if->sk_softc; 2182 ifp = &sc_if->arpcom.ac_if; 2183 2184 /* Unreset the XMAC. */ 2185 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2186 DELAY(1000); 2187 2188 /* Reset the XMAC's internal state. */ 2189 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2190 2191 /* Save the XMAC II revision */ 2192 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2193 2194 /* 2195 * Perform additional initialization for external PHYs, 2196 * namely for the 1000baseTX cards that use the XMAC's 2197 * GMII mode. 2198 */ 2199 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2200 int i = 0; 2201 u_int32_t val; 2202 2203 /* Take PHY out of reset. */ 2204 val = sk_win_read_4(sc, SK_GPIO); 2205 if (sc_if->sk_port == SK_PORT_A) 2206 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2207 else 2208 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2209 sk_win_write_4(sc, SK_GPIO, val); 2210 2211 /* Enable GMII mode on the XMAC. */ 2212 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2213 2214 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2215 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2216 DELAY(10000); 2217 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2218 BRGPHY_MII_IMR, 0xFFF0); 2219 2220 /* 2221 * Early versions of the BCM5400 apparently have 2222 * a bug that requires them to have their reserved 2223 * registers initialized to some magic values. I don't 2224 * know what the numbers do, I'm just the messenger. 2225 */ 2226 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2227 == 0x6041) { 2228 while(bhack[i].reg) { 2229 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2230 bhack[i].reg, bhack[i].val); 2231 i++; 2232 } 2233 } 2234 } 2235 2236 /* Set station address */ 2237 SK_XM_WRITE_2(sc_if, XM_PAR0, 2238 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2239 SK_XM_WRITE_2(sc_if, XM_PAR1, 2240 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2241 SK_XM_WRITE_2(sc_if, XM_PAR2, 2242 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2243 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2244 2245 if (ifp->if_flags & IFF_PROMISC) { 2246 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2247 } else { 2248 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2249 } 2250 2251 if (ifp->if_flags & IFF_BROADCAST) { 2252 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2253 } else { 2254 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2255 } 2256 2257 /* We don't need the FCS appended to the packet. */ 2258 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2259 2260 /* We want short frames padded to 60 bytes. */ 2261 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2262 2263 /* 2264 * Enable the reception of all error frames. This is is 2265 * a necessary evil due to the design of the XMAC. The 2266 * XMAC's receive FIFO is only 8K in size, however jumbo 2267 * frames can be up to 9000 bytes in length. When bad 2268 * frame filtering is enabled, the XMAC's RX FIFO operates 2269 * in 'store and forward' mode. For this to work, the 2270 * entire frame has to fit into the FIFO, but that means 2271 * that jumbo frames larger than 8192 bytes will be 2272 * truncated. Disabling all bad frame filtering causes 2273 * the RX FIFO to operate in streaming mode, in which 2274 * case the XMAC will start transfering frames out of the 2275 * RX FIFO as soon as the FIFO threshold is reached. 2276 */ 2277 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2278 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2279 XM_MODE_RX_INRANGELEN); 2280 2281 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2282 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2283 else 2284 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2285 2286 /* 2287 * Bump up the transmit threshold. This helps hold off transmit 2288 * underruns when we're blasting traffic from both ports at once. 2289 */ 2290 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2291 2292 /* Set multicast filter */ 2293 sk_setmulti(sc_if); 2294 2295 /* Clear and enable interrupts */ 2296 SK_XM_READ_2(sc_if, XM_ISR); 2297 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2298 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2299 else 2300 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2301 2302 /* Configure MAC arbiter */ 2303 switch(sc_if->sk_xmac_rev) { 2304 case XM_XMAC_REV_B2: 2305 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2306 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2307 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2308 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2309 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2310 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2311 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2312 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2313 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2314 break; 2315 case XM_XMAC_REV_C1: 2316 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2317 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2318 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2319 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2320 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2321 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2322 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2323 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2324 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2325 break; 2326 default: 2327 break; 2328 } 2329 sk_win_write_2(sc, SK_MACARB_CTL, 2330 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2331 2332 sc_if->sk_link = 1; 2333 2334 return; 2335 } 2336 2337 static void sk_init_yukon(sc_if) 2338 struct sk_if_softc *sc_if; 2339 { 2340 u_int32_t phy; 2341 u_int16_t reg; 2342 int i; 2343 2344 /* GMAC and GPHY Reset */ 2345 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2346 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2347 DELAY(1000); 2348 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2349 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2350 DELAY(1000); 2351 2352 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2353 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2354 2355 switch(sc_if->sk_softc->sk_pmd) { 2356 case IFM_1000_SX: 2357 case IFM_1000_LX: 2358 phy |= SK_GPHY_FIBER; 2359 break; 2360 2361 case IFM_1000_CX: 2362 case IFM_1000_T: 2363 phy |= SK_GPHY_COPPER; 2364 break; 2365 } 2366 2367 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2368 DELAY(1000); 2369 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2370 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2371 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2372 2373 /* unused read of the interrupt source register */ 2374 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2375 2376 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2377 2378 /* MIB Counter Clear Mode set */ 2379 reg |= YU_PAR_MIB_CLR; 2380 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2381 2382 /* MIB Counter Clear Mode clear */ 2383 reg &= ~YU_PAR_MIB_CLR; 2384 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2385 2386 /* receive control reg */ 2387 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2388 YU_RCR_CRCR); 2389 2390 /* transmit parameter register */ 2391 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2392 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2393 2394 /* serial mode register */ 2395 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2396 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2397 2398 /* Setup Yukon's address */ 2399 for (i = 0; i < 3; i++) { 2400 /* Write Source Address 1 (unicast filter) */ 2401 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2402 sc_if->arpcom.ac_enaddr[i * 2] | 2403 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2404 } 2405 2406 for (i = 0; i < 3; i++) { 2407 reg = sk_win_read_2(sc_if->sk_softc, 2408 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2409 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2410 } 2411 2412 /* clear all Multicast filter hash registers */ 2413 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 2414 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 2415 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 2416 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 2417 2418 /* enable interrupt mask for counter overflows */ 2419 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2420 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2421 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2422 2423 /* Configure RX MAC FIFO */ 2424 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2425 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2426 2427 /* Configure TX MAC FIFO */ 2428 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2429 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2430 } 2431 2432 /* 2433 * Note that to properly initialize any part of the GEnesis chip, 2434 * you first have to take it out of reset mode. 2435 */ 2436 static void 2437 sk_init(xsc) 2438 void *xsc; 2439 { 2440 struct sk_if_softc *sc_if = xsc; 2441 struct sk_softc *sc; 2442 struct ifnet *ifp; 2443 struct mii_data *mii; 2444 u_int16_t reg; 2445 2446 SK_IF_LOCK(sc_if); 2447 2448 ifp = &sc_if->arpcom.ac_if; 2449 sc = sc_if->sk_softc; 2450 mii = device_get_softc(sc_if->sk_miibus); 2451 2452 /* Cancel pending I/O and free all RX/TX buffers. */ 2453 sk_stop(sc_if); 2454 2455 if (sc->sk_type == SK_GENESIS) { 2456 /* Configure LINK_SYNC LED */ 2457 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2458 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2459 SK_LINKLED_LINKSYNC_ON); 2460 2461 /* Configure RX LED */ 2462 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2463 SK_RXLEDCTL_COUNTER_START); 2464 2465 /* Configure TX LED */ 2466 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2467 SK_TXLEDCTL_COUNTER_START); 2468 } 2469 2470 /* Configure I2C registers */ 2471 2472 /* Configure XMAC(s) */ 2473 switch (sc->sk_type) { 2474 case SK_GENESIS: 2475 sk_init_xmac(sc_if); 2476 break; 2477 case SK_YUKON: 2478 sk_init_yukon(sc_if); 2479 break; 2480 } 2481 mii_mediachg(mii); 2482 2483 if (sc->sk_type == SK_GENESIS) { 2484 /* Configure MAC FIFOs */ 2485 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2486 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2487 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2488 2489 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2490 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2491 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2492 } 2493 2494 /* Configure transmit arbiter(s) */ 2495 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2496 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2497 2498 /* Configure RAMbuffers */ 2499 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2500 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2501 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2502 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2503 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2504 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2505 2506 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2507 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2508 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2509 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2510 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2511 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2512 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2513 2514 /* Configure BMUs */ 2515 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2516 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2517 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2518 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2519 2520 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2521 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2522 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2523 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2524 2525 /* Init descriptors */ 2526 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2527 printf("sk%d: initialization failed: no " 2528 "memory for rx buffers\n", sc_if->sk_unit); 2529 sk_stop(sc_if); 2530 SK_IF_UNLOCK(sc_if); 2531 return; 2532 } 2533 sk_init_tx_ring(sc_if); 2534 2535 /* Configure interrupt handling */ 2536 CSR_READ_4(sc, SK_ISSR); 2537 if (sc_if->sk_port == SK_PORT_A) 2538 sc->sk_intrmask |= SK_INTRS1; 2539 else 2540 sc->sk_intrmask |= SK_INTRS2; 2541 2542 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2543 2544 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2545 2546 /* Start BMUs. */ 2547 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2548 2549 switch(sc->sk_type) { 2550 case SK_GENESIS: 2551 /* Enable XMACs TX and RX state machines */ 2552 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2553 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2554 break; 2555 case SK_YUKON: 2556 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2557 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2558 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2559 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2560 } 2561 2562 ifp->if_flags |= IFF_RUNNING; 2563 ifp->if_flags &= ~IFF_OACTIVE; 2564 2565 SK_IF_UNLOCK(sc_if); 2566 2567 return; 2568 } 2569 2570 static void 2571 sk_stop(sc_if) 2572 struct sk_if_softc *sc_if; 2573 { 2574 int i; 2575 struct sk_softc *sc; 2576 struct ifnet *ifp; 2577 2578 SK_IF_LOCK(sc_if); 2579 sc = sc_if->sk_softc; 2580 ifp = &sc_if->arpcom.ac_if; 2581 2582 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2583 2584 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2585 u_int32_t val; 2586 2587 /* Put PHY back into reset. */ 2588 val = sk_win_read_4(sc, SK_GPIO); 2589 if (sc_if->sk_port == SK_PORT_A) { 2590 val |= SK_GPIO_DIR0; 2591 val &= ~SK_GPIO_DAT0; 2592 } else { 2593 val |= SK_GPIO_DIR2; 2594 val &= ~SK_GPIO_DAT2; 2595 } 2596 sk_win_write_4(sc, SK_GPIO, val); 2597 } 2598 2599 /* Turn off various components of this interface. */ 2600 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2601 switch (sc->sk_type) { 2602 case SK_GENESIS: 2603 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2604 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2605 break; 2606 case SK_YUKON: 2607 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2608 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2609 break; 2610 } 2611 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2612 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2613 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2614 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2615 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2616 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2617 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2618 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2619 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2620 2621 /* Disable interrupts */ 2622 if (sc_if->sk_port == SK_PORT_A) 2623 sc->sk_intrmask &= ~SK_INTRS1; 2624 else 2625 sc->sk_intrmask &= ~SK_INTRS2; 2626 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2627 2628 SK_XM_READ_2(sc_if, XM_ISR); 2629 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2630 2631 /* Free RX and TX mbufs still in the queues. */ 2632 for (i = 0; i < SK_RX_RING_CNT; i++) { 2633 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2634 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2635 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2636 } 2637 } 2638 2639 for (i = 0; i < SK_TX_RING_CNT; i++) { 2640 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2641 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2642 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2643 } 2644 } 2645 2646 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2647 SK_IF_UNLOCK(sc_if); 2648 return; 2649 } 2650